INFINEON TDA5221

Wireless Components
ASK/FSK Single Conversion Receiver
TDA 5221 Version 0.1
Target Specification October 2001
confidential
preliminary
Revision History
Current Version: 0.1. as of 31.10.01
Please note that this is a target specification that is subject to change.
Previous Version: n.a.
Page
(in previous
Version)
Page(s)
(in current
Version)
Subjects (major changes since last revision)
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Edition 10.01
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© Infineon Technologies AG October 2001.
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TDA 5221
preliminary
Product Info
Product Info
General Description
Features
Applications
The IC is a very low power consump- Package
tion single chip FSK/ASK Superheterodyne Receiver (SHR) for the
frequency band 300 to 340 MHz. The
IC offers a high level of integration and
needs only a few external components. The device contains a low noise
amplifier (LNA), a double balanced
mixer, a fully integrated VCO, a PLL
synthesiser, a crystal oscillator, a limiter with RSSI generator, a PLL FSK
demodulator, a data filter, a data comparator (slicer) and a peak detector.
Additionally there is a power down feature to save battery life.
■
Low supply current (Is = 6.4 mA
typ. in FSK mode, Is = 5.6 mA typ.
in ASK mode)
■
Selectable frequency ranges 300320 MHz and 300-340 MHz
■
Supply voltage range 5V ±10%
■
Limiter with RSSI generation,
operating at 10.7MHz
■
Power down mode with very low
supply current (50nA typ.)
■
Selectable reference frequency
■
FSK and ASK demodulation capability
■
2nd order low pass data filter with
external capacitors
■
Fully integrated VCO and PLL
Synthesiser
■
Data slicer with self-adjusting
threshold
■
ASK sensitivity better than
-110 dBm over specified temperature range (- 40 to +105°C)
■
FSK sensitivity better than
-102 dBm over specified temperature range (- 40 to +105°C)
■
Keyless Entry Systems
■
Alarm Systems
■
Remote Control Systems
■
Low Bitrate Communication
Systems
Ordering Information
Type
Ordering Code
Package
TDA 5221
Q67037-A1147
P-TSSOP-28-1
samples available
Wireless Components
Product Info
Target Specification, October 2001
1
Table of Contents
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
i
2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.2
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.4
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
3.1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
3.2
Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3.3
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
3.4
Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
3.4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
3.4.2 Mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
3.4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
3.4.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
3.4.5 Limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
3.4.6 FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
3.4.7 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
3.4.8 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
3.4.9 Peak Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
3.4.10 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
4.1
Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
4.2
Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
4.3
Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
4.4
Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
4.5
Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
4.6
ASK/FSK Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
4.6.1 FSK Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
4.6.2 ASK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
4.7
Principle of the Precharge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
5.1
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
5.1.3 AC/DC Characteristics at TAMB = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
5.1.4 AC/DC Characteristics at TAMB = -40 to 105°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
2
Product Description
Contents of this Chapter
2.1
2.2
2.3
2.4
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TDA 5221
preliminary
Product Description
2.1 Overview
The IC is a very low power consumption single chip FSK/ASK Superheterodyne
Receiver (SHR) for receive frequencies between 300 and 340 MHz. The IC
offers a high level of integration and needs only a few external components. The
device contains a low noise amplifier (LNA), a double balanced mixer, a fully
integrated VCO, a PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a PLL FSK demodulator, a data filter, a data comparator (slicer) and a
peak detector. Additionally there is a power down feature to save battery life.
2.2 Application
■
Keyless Entry Systems
■
Remote Control Systems
■
Alarm Systems
■
Low Bitrate Communication Systems
2.3 Features
Wireless Components
■
Low supply current (Is = 6.4 mA typ.FSK mode, 5.6 mA typ. ASK mode)
■
Supply voltage range 5V ±10%
■
Power down mode with very low supply current (50nA typ.)
■
FSK and ASK demodulation capability
■
Fully integrated VCO and PLL Synthesiser
■
RF input sensitivity ASK -113dBm typ. at 25°C, better than -110dBm over
complete specified operating temperature range (-40 to +105°C)
■
RF input sensitivity FSK -105dBm typ. at 25°C, better than -102dBm over
complete specified operating temperature range (-40 to +105°C)
■
Receive frequency range between 310 and 340 MHz
■
Selectable reference frequency
■
Limiter with RSSI generation, operating at 10.7MHz
■
2nd order low pass data filter with external capacitors
■
Data slicer with self-adjusting threshold
2-2
Target Specification, October 2001
TDA 5221
preliminary
Product Description
2.4 Package Outlines
P_TSSOP_28.EPS
Figure 2-1
Wireless Components
P-TSSOP-28-1 package outlines
2-3
Target Specification, October 2001
3
Functional Description
Contents of this Chapter
3.1
3.2
3.3
3.4
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
TDA 5221
preliminary
Functional Description
3.1 Pin Configuration
CRST1
1
28
CRST2
VCC
2
27
PDW N
LNI
3
26
PDO
TAGC
4
25
DATA
AGND
5
24
3VO UT
LNO
6
23
THRES
VCC
7
22
FFB
MI
8
21
OPP
M IX
9
20
SLN
AGND
10
19
SLP
FSEL
11
18
L IM X
IF O
12
17
L IM
DGND
13
16
SSEL
VDD
14
15
M SEL
TDA 5221
Pin_Configuration_5221.wmf
Figure 3-1
Wireless Components
IC Pin Configuration
3-2
Target Specification, October 2001
TDA 5221
preliminary
Functional Description
3.2 Pin Definition and Function
In the subsequent table the internal circuits connected to the pins of the device
are shown. ESD-protection circuits are omitted to ease reading.
.
Table 3-1 Pin Definition and Function
Pin No.
Symbol
1
CRST1
Equivalent I/O-Schematic
Function
External Crystal Connector 1
4 .1 5 V
1
50uA
2
VCC
5V Supply
3
LNI
LNA Input
57uA
3
500uA
4k
1k
Wireless Components
3-3
Target Specification, October 2001
TDA 5221
preliminary
Functional Description
4
TAGC
AGC Time Constant Control
4 .3V
3u A
4
1k
1.4 uA
1.7V
5
AGND
Analogue Ground Return
6
LNO
LNA Output
5V
1k
6
7
VCC
5V Supply
8
MI
Mixer Input
1.7 V
2k
9
2k
MIX
Complementary Mixer Input
8
9
4 0 0 uA
10
AGND
Wireless Components
Analogue Ground Return
3-4
Target Specification, October 2001
TDA 5221
preliminary
Functional Description
11
FSEL
Frequency Selector
1 .2 V
4 0k
11
12
IFO
10.7 MHz IF Mixer Output
300uA
2 .2 V
60
12
4 .5 k
13
DGND
Digital Ground Return
14
VDD
5V Supply (PLL Counter Circuitry)
15
MSEL
ASK/FSK Modulation Format
Selector
1 .2 V
4 0k
15
16
SSEL
Data-Slicer Reference-Level
Selector
1 .2 V
4 0k
16
Wireless Components
3-5
Target Specification, October 2001
TDA 5221
preliminary
Functional Description
17
LIM
Limiter Input
2 .4 V
15k
17
18
LIMX
Complementary Limiter Input
75uA
330
18
15k
19
SLP
Data Slicer Positive Input
15uA
100
3k
19
8 0 µA
20
SLN
Data Slicer Negative Input
5uA
10k
20
21
OPP
OpAmp Noninverting Input
5uA
20 0
21
Wireless Components
3-6
Target Specification, October 2001
TDA 5221
preliminary
Functional Description
22
FFB
Data Filter Feedback Pin
5u A
10 0k
22
23
THRES
AGC Threshold Input
5uA
10k
23
24
3VOUT
3V Reference Output
24
2 0kΩ
3 .1 V
25
DATA
Data Output
500
25
40k
Wireless Components
3-7
Target Specification, October 2001
TDA 5221
preliminary
Functional Description
26
PDO
Peak Detector Output
26
446k
27
PDWN
Power Down Input
27
220k
220k
28
CRST2
External Crystal Connector 2
4.15 V
28
50 uA
Wireless Components
3-8
Target Specification, October 2001
TDA 5221
preliminary
Functional Description
3.3 Functional Block Diagram
VCC
IF
Filter
MSEL
H=ASK
L=FSK
MI
LNO
6
LNI
RF
3
MIX
8
9
IFO
LIM
12
FFB
LIMX
17
18
OPP
22
15
SLP
21
19
20
Logic
+ CM
LNA
FSK
PLL Demod
+ FSK
- ASK
+
25
DATA
OP
-
TDA 5221
4
SSEL
DATASLICER
+
LIMITER
16
+ CP
-
-
TAGC
SLN
PEAK
DETECTOR
PDO
26
OTA
:2
VCC
VCO
: 128
: 129
Φ
DET
:2
U REF
CRYSTAL
OSC
AGC
Reference
23
THRES
24
3VOUT
14
Bandgap
Reference
Loop
Filter
DGND
13
2,7
5,10
VCC
AGND
11
28
1
27
PDWN
FSEL
Crystal
Functional_diagram_5221.wmf
Figure 3-2
Main Block Diagram
3.4 Functional Blocks
3.4.1
Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The
gain figure is determined by the external matching networks situated ahead of
LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX
(Pins 8 and 9). The noise figure of the LNA is approximately 3dB, the current
consumption is 500µA. The gain can be reduced by approximately 18dB. The
switching point of this AGC action can be determined externally by applying a
threshold voltage at the THRES pin (Pin 23). This voltage is compared internally
with the received signal (RSSI) level generated by the limiter circuitry. In case
that the RSSI level is higher than the threshold voltage the LNA gain is reduced
and vice versa. The threshold voltage can be generated by attaching a voltage
divider between the 3VOUT pin (Pin 24) which provides a temperature stable
3V output generated from the internal bandgap voltage and the THRES pin as
described in Section 4.1. The time constant of the AGC action can be determined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen
along with the appropriate threshold voltage according to the intended operat-
Wireless Components
3-9
Target Specification, October 2001
TDA 5221
preliminary
Functional Description
ing case and interference scenario to be expected during operation. The optimum choice of AGC time constant and the threshold voltage is described in
Section 4.1.
3.4.2
Mixer
The Double Balanced Mixer downconverts the input frequency (RF) in the
range of 310-350MHz to the intermediate frequency (IF) at 10.7MHz with a voltage gain of approximately 21dB by utilising either high- or low-side injection of
the local oscillator signal. In case the mixer is interfaced only single-ended, the
unused mixer input has to be tied to ground via a capacitor. The mixer is followed by a low pass filter with a corner frequency of 20MHz in order to suppress
RF signals to appear at the IF output (IFO pin). The IF output is internally consisting of an emitter follower that has a source impedance of approximately
330Ω=to facilitate interfacing the pin directly to a standard 10.7MHz ceramic filter
without additional matching circuitry.
3.4.3
PLL Synthesizer
The Phase Locked Loop synthesizer consists of a VCO, an asynchronous
divider chain, a phase detector with charge pump and a loop filter and is fully
implemented on-chip. The VCO is including spiral inductors and varactor
diodes. The FSEL pin (Pin11) has to be left open. The tuning range of the VCO
was designed to guarantee over production spread and the specified temperature range a receive frequency range between 300 and 340 MHz depending on
whether high- or low-side injection of the local oscillator is used. The oscillator
signal is fed both to the synthesiser divider chain and to a divider that is dividing
the signal by 2 before it is applied to the downconverting mixer. Local oscillator
high side injection has to be used for receive frequencies between approximately 300 and 320 MHz, low side injection for receive frequencies between
320 and 340MHz - see also Section 4.4..
3.4.4
Crystal Oscillator
The calculation of the value of the necessary quartz load capacitance is shown
in Section 4.3, the quartz frequency calculation is explained in Section 4.4.
3.4.5
Limiter
The Limiter is an AC coupled multistage amplifier with a cumulative gain of
approximately 80 dB that has a bandpass-characteristic centred around
10.7 MHz. It has a typical input impedance of 330 Ω=to allow for easy interfacing
to a 10.7 MHz ceramic IF filter. The limiter circuit also acts as a Receive Signal
Strength Indicator (RSSI) generator which produces a DC voltage that is
Wireless Components
3 - 10
Target Specification, October 2001
TDA 5221
preliminary
Functional Description
directly proportional to the input signal level as can be seen in Figure 4-2. This
signal is used to demodulate ASK-modulated receive signals in the subsequent
baseband circuitry. The RSSI output is applied to the modulation format switch,
to the Peak Detector input and to the AGC circuitry.
In order to demodulate ASK signals the MSEL pin has to be in its ‘High‘-state
as described in the next chapter.
3.4.6
FSK Demodulator
To demodulate frequency shift keyed (FSK) signals a PLL circuit is used that is
contained fully on chip. The Limiter output differential signal is fed to the linear
phase detector as is the output of the 10.7 MHz center frequency VCO. The
demodulator gain is typically 140µV/kHz. The passive loop filter output that is
comprised fully on chip is fed to both the VCO and the modulation format switch
described in more detail below. This signal is representing the demodulated signal with low frequencies applied to the demodulator demodulated to logic ones
and high frequencies demodulated to logic zeroes. However this is only valid in
case the local oscillator is low-side injected to the mixer which is applicable to
receive frequencies above 330MHz (e.g. 345MHz). In case of receive frequencies below 330MHz (e.g.315MHz) high frequencies are demodulated as logical
ones due to a sign inversion in the downconversion mixing process. See also
Section 4.4.
The modulation format switch is actually a switchable amplifier with an AC gain
of 11 that is controlled by the MSEL pin (Pin 15) as shown in the following table.
This gain was chosen to facilitate detection in the subsequent circuits. The DC
gain is 1 in order not to saturate the subsequent Data Filter wih the DC offset
produced by the demodulator in case of large frequency offsets of the IF signal.
The resulting frequency characteristic and details on the principle of operation
of the switch are described in Section 4.6.
Table 3-2 MSEL Pin Operating States
MSEL
Modulation Format
Open
ASK
Shorted to ground
FSK
The demodulator circuit is switched off in case of reception of ASK signals.
3.4.7
Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a
voltage follower and two 100kΩ= on-chip resistors. Along with two external
capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the
capacitor values is described in Section 4.2.
Wireless Components
3 - 11
Target Specification, October 2001
TDA 5221
preliminary
Functional Description
3.4.8
Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows
for a maximum receive data rate of up to 100kBaud. The maximum achievable
data rate also depends on the IF Filter bandwidth and the local oscillator tolerance values. Both inputs are accessible. The output delivers a digital data signal (CMOS-like levels) for subsequent circuits. A self-adjusting slicer-threshold
on pin 20 its generated by a RC-term. In ASK-mode alternatively a scaled value
of the voltage at the PDO-output (approx. 87%) can be used as the slicerthreshold. The data slicer threshold generation alternatives are described in
more detail in Section 4.5.
3.4.9
Peak Detector
The peak detector generates a DC voltage which is proportional to the peak
value of the receive data signal. A capacitor is necessary. The input is connected to the output of the RSSI-output of the Limiter, the output is connected
to the PDO pin (Pin 26). This output can be used as an indicator for the received
signal strength to use in wake-up circuits and as a reference for the data slicer
in ASK mode. Note that the RSSI level is also output in case of FSK mode.
3.4.10
Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage
for the device. A power down mode is available to switch off all subcircuits which
is controlled by the PWDN pin (Pin 27) as shown in the following table. The supply current drawn in this case is typically 50nA.
Table 3-3 PDWN Pin Operating States
PDWN
Operating State
Open or tied to ground
Powerdown Mode
Tied to Vs
Wireless Components
Receiver On
3 - 12
Target Specification, October 2001
4
Applications
Contents of this Chapter
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Choice of LNA Threshold Voltage and Time Constant . . . . . . . . . . . . 4-2
Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
ASK/FSK Datapatch Functional Description. . . . . . . . . . . . . . . . . . . . 4-8
Principle of the Precharge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
TDA 5221
preliminary
Applications
4.1 Choice of LNA Threshold Voltage and Time Constant
In the following figure the internal circuitry of the LNA automatic gain control is
shown.
R1
R2
Uth re s h old
Pins:
23
24
RSSI (0.8 - 2.8V)
20kΩ
OTA
VCC
+3.1 V
Ilo a d
LNA
Gain control
voltage
RSSI > Uth r es h o ld : Ilo a d =4.2µA
RSSI < Uth r es h o ld : Ilo a d = -1.5µA
4
UC
C
Uc :< 2.6V : Gain high
Uc :> 2.6V : Gain low
Uc ma x = VC C - 0.7V
Uc min = 1.67V
LNA_autom.wmf
Figure 4-1
LNA Automatic Gain Control Circuitry
The LNA automatic gain control circuitry consists of an operational transimpedance amplifier that is used to compare the received signal strength signal
(RSSI) generated by the Limiter with an externally provided threshold voltage
Uthres. As shown in the following figure the threshold voltage can have any
value between approximately 0.8 and 2.8V to provide a switching point within
the receive signal dynamic range.
This voltage Uthres is applied to the THRES pin (Pin 23) The threshold voltage
can be generated by attaching a voltage divider between the 3VOUT pin
(Pin 24) which provides a temperature stable 3V output generated from the
internal bandgap voltage and the THRES pin. If the RSSI level generated by the
Limiter is higher than Uthres, the OTA generates a positive current Iload. This
yields a voltage rise on the TAGC pin (Pin 4). Otherwise, the OTA generates a
negative current. These currents do not have the same values in order to
achieve a fast-attack and slow-release action of the AGC and are used to
charge an external capacitor which finally generates the LNA gain control voltage.
Wireless Components
4-2
Target Specification, October 2001
TDA 5221
preliminary
Applications
LNA always
in high gain mode
3
2
RSSI Level Range
UTHRES Voltage Range
2.5
RSSI Level
1.5
1
LNA always
in low gain mode
0.5
0
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
Input Level at LNA Input [dBm]
RSSI-AGC.wmf
Figure 4-2
RSSI Level and Permissive AGC Threshold Levels
The switching point should be chosen according to the intended operating scenario. The determination of the optimum point is described in the accompanying
Application Note, a threshold voltage level of 1.8V is apparently a viable choice.
It should be noted that the output of the 3VOUT pin is capable of driving up to
50µA, but that the THRES pin input current is only in the region of 40nA. As the
current drawn out of the 3VOUT pin is directly related to the receiver power consumption, the power divider resistors should have high impedance values. The
sum of R1 and R2 has to be 600kΩ in order to yield 3V at the 3VOUT pin. R1
can thus be chosen as 240kΩ, R2 as 360kΩ to yield an overall 3VOUT output
current of 5µA1 and a threshold voltage of 1.8V
Note: If the LNA gain shall be kept in either high or low gain mode this has to
be accomplished by tying the THRES pin to a fixed voltage. In order to achieve
high gain mode operation, a voltage higher than 2.8V shall be applied to the
THRES pin, such as a short to the 3VOLT pin. In order to achieve low gain
mode operation a voltage lower than 0.7V shall be applied to the THRES, such
as a short to ground.
As stated above the capacitor connected to the TAGC pin is generating the gain
control voltage of the LNA due to the charging and discharging currents of the
OTA and thus is also responsible for the AGC time constant. As the charging
and discharging currents are not equal two different time constants will result.
The time constant corresponding to the charging process of the capacitor shall
be chosen according to the data rate. According to measurements performed
at Infineon the capacitor value should be greater than 47nF.
1. note the 20kΩ resistor in series with the 3.1V internal voltage source
Wireless Components
4-3
Target Specification, October 2001
TDA 5221
preliminary
Applications
4.2 Data Filter Design
Utilising the on-board voltage follower and the two 100kΩ on-chip resistors a
2nd order Sallen-Key low pass data filter can be constructed by adding 2 external capacitors between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as
depicted in the following figure and described in the following formulas1.
C1
Pins:
C2
22
21
R
R
100k
100k
19
Filter_Design.wmf
Figure 4-3
Data Filter Design
(1)(2)
b C2 = -------------------------4QRΠf 3dB
2Q b
C 1 = ---------------------R2Πf 3dB
with
Q = ------ba
(3)the quality factor of the poles
where
in case of a Bessel filter a = 1.3617, b = 0.618
and thus Q = 0.577
and in case of a Butterworth filtera = 1.414, b = 1
and thus Q = 0.71
Example: Butterworth filter with f3dB = 5kHz and R = 100kΩ:
C1 = 450pF, C2 = 225pF
1. taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999
Wireless Components
4-4
Target Specification, October 2001
TDA 5221
preliminary
Applications
4.3 Quartz Load Capacitance Calculation
The value of the capacitor necessary to achieve that the quartz oscillator is
operating at the intended frequency is determined by the reactive part of the
negative resistance of the oscillator circuit as shown in Section 5.1.3 and by the
quartz specifications given by the quartz manufacturer.
CS
Pin 28
Crystal
Input
impedance
Z1-28
TDA5221
Pin 1
Quartz_load_5221.wmf
Figure 4-4
Determination of Series Capacitance Value for the Quartz Oscillator
Crystal specified with load capacitance
CS =
1
1
+ 2π f X L
Cl
with Cl the load capacitance (refer to the quartz crystal specification).
Example:
10.18 MHz:
CL = 12 pF
XL=870 Ω
CS = 7.2 pF
This value may be obtained by putting two capacitors in series to the quartz,
such as 18pF and 22pF in the 5.1MHz case and 18pF and 12pF in the 10.2MHz
case.
Wireless Components
4-5
Target Specification, October 2001
TDA 5221
preliminary
Applications
4.4 Quartz Frequency Calculation
As described in Section 3.4.3 the operating range of the on-chip VCO is wide
enough to guarantee a receive frequency range between 300 and 340MHz. The
VCO signal is divided by 2 before applied to the mixer . This local oscillator signal can be used to downconvert the RF signals both with high- or low-side injection at the mixer. High-side injection of the local oscillator has to be used for
receive frequencies between 300 and 320 MHz. In this case the local oscillator
frequency is calculated by adding the IF frequency (10.7 MHz) to the RF frequency. In this case the higher frequency of a FSK-modulated signal is
demodulated as a logical one (high).
Low-side injection has to be used for receive frequencies between 320 and
340 MHz. The local oscillator frequency is calculated by subtracting the IF frequency (10.7 MHz) from the RF frequency then. Please note that in this case
sign-inversion occurs and the higher frequency of a FSK-modulated signal is
demodulated as a logical zero (low). The overall division ratios in the PLL are
32 or 32.25 depending on whether the FSEL-pin is left open or tied to ground.
Therefore the quartz frequency may be calculated by using the following formula:
ƒQU = (ƒRF ± 10.7) / r
with
ƒRF
receive frequency
ƒLO
local oscillator (PLL) frequency (ƒRF ± 10.7)
ƒQU
quartz oscillator frequency
r
ratio of local oscillator (PLL) frequency and quartz frequency as
shown in the subsequent table
Table 4-1 PLL Division Ratio Dependence on States of CSEL
FSEL
Ratio r = (fLO/fQU)
High
32
Low
32.25
This yields the following examples:
FSEL is ‘Low‘:
f QU = (318.55MHz+ 10.7MHz) / 32.25 = 10.209375MHz
FSEL is ‘High‘:
f QU = (316 MHz + 10.7 MHz ) / 32 = 10.209375 MHz
Wireless Components
4-6
Target Specification, October 2001
TDA 5221
preliminary
Applications
4.5 Data Slicer Threshold Generation
The threshold of the data slicer can be generated using an external R-C integrator as shown in Figure 4-5. The cut-off frequency of the R-C integrator has
to be lower than the lowest frequency appearing in the data signal. In order to
keep distortion low, the minimum value for R is 20kΩ.
R
C
Pins:
19
data out
25
20
Uthreshold
CM
data
filter
data slicer
Data_slice1.wmf
Figure 4-5
Data Slicer Threshold Generation with External R-C Integrator
In case of ASK operation another possibility for threshold generation is to use
the peak detector in connection with an internal resistive divider and one capacitor as shown in the following figure. The component values are depending on
the coding scheme and the protocol used.
C
data out
Pins:
26
25
peak detector
56k
390k
data slicer
Uthreshold
CP
data
filter
Data_slice2.wmf
Figure 4-6
Wireless Components
Data Slicer Threshold Generation Utilising the Peak Detector
4-7
Target Specification, October 2001
TDA 5221
preliminary
Applications
4.6 ASK/FSK Datapatch Functional Description
The TDA5221 is containing an ASK/FSK switch which can be controlled via
Pin 15 (MSEL). This switch is actually consisting of 2 operational amplifiers that
are having a gain of 1 in case of the ASK amplifier and a gain of 11 in case of
the FSK amplifier in order to achieve an appropriate demodulation gain characteristic. In order to compensate for the DC-offset generated especially in case
of the FSK PLL demodulator there is a feedback connection between the
threshold voltage of the bit slicer comparator (Pin 20) to the negative input of
the FSK switch amplifier.
In ASK-mode alternatively to the voltage at Pin 20 (SLN) a value of approx. 87%
of the peak-detector output-voltage at Pin 26 (PDO) can be used as the slicerreference level. The selection between these modes is controlled by Pin 16
(SSEL). This is shown in the following figure.
MSEL
15
H=ASK
L=FSK
PDO
PEAK
DETECTOR
from RSSI Gen
(ASK signal)
26
R=56k
ASK/FSK Switch
C=100 nF
R=390k
Data Filter
FSK PLL Demodulator
Comp
+ CP
+ CM
H=CP
L=CM
R2=100k
ASK
+ FSK
-
v=1
AC
0.18 mV/kHz
R1=100k
+
25
DATA Out
R3=300k
1
DC
typ. 2 V
1.5 V......2.5 V
R4=30k
ASK mode: v=1
FSK mode: v=11
22
21
FFB
19
OOP
C1
C2
20
SLP
16
SLN
SSEL
R
C
ask_fsk_datapath.WMF
Figure 4-7
Wireless Components
ASK/FSK mode datapath
4-8
Target Specification, October 2001
TDA 5221
preliminary
Applications
4.6.1
FSK Mode
The FSK datapath has a bandpass characterisitc due to the feedback shown
above (highpass) and the data filter (lowpass). The lower cutoff frequency f2 is
determined by the external RC-combination. The upper cutoff frequency f3 is
determined by the data filter bandwidth.
The demodulation gain of the FSK PLL demodulator is 140µV/kHz. This gain is
increased by the gain v of the FSK switch, which is 11. Therefore the resulting
dynamic gain of this circuit is 1.5mV/kHz within the bandpass. The gain for the
DC content of FSK signal remains at 140µV/kHz. The cutoff frequencies of the
bandpass have to be chosen such that the spectrum of the data signal is influenced in an acceptable amount.
In case that the user data is containing long sequences of logical zeroes the
effect of the drift-off of the bit slicer threshold voltage can be lowered if the offset
voltage inherent at the negative input of the slicer comparator (Pin20) is used.
The comparator has no hysteresis built in.
This offset voltage is generated by the bias current of the negative input of the
comparator (i.e. 20nA) running over the external resistor R. This voltage raises
the voltage appearing at pin 20 (e.g. 1mV with R = 100kΩ). In order to obtain
benefit of this asymmetrical offset for the demodulation of long zeros the lower
of the two FSK frequencies should be chosen in the transmitter as the zerosymbol frequency.
In the following figure the shape of the above mentioned bandpass is shown.
gain (pin19)
v
v-3dB
20dB/dec
-40dB/dec
3dB
0dB
f
DC
f1
f2
0.18mV/kHz
f3
2mV/kHz
frequenzgang.WMF
Figure 4-8
Frequency characterstic in case of FSK mode
The cutoff frequencies are calculated with the following formulas:
f1 =
Wireless Components
4-9
1
R ⋅ 330kΩ
⋅C
2π
R + 330kΩ
Target Specification, October 2001
TDA 5221
preliminary
Applications
f 2 = v ⋅ f1 = 11 ⋅ f1
f 3 = f 3dB
f3 is the 3dB cutoff frequency of the data filter - see Section 4.2.
Example:
R = 100kΩ,=C = 47nF
This leads tof1 = 44Hz and f2 = 485Hz
4.6.2
ASK Mode
In case the receiver is operated in ASK mode the datapath frequency charactersitic is dominated by the data filter alone, thus it is lowpass shaped.The cutoff
frequency is determined by the external capacitors C12 and C14 and the internal 100k resistors as described in Section 4.2
0dB
-3dB
-40dB/dec
f
f3dB
freq_ask.WMF
Figure 4-9
Wireless Components
Frequency charcteristic in case of ASK mode
4 - 10
Target Specification, October 2001
TDA 5221
preliminary
Applications
4.7 Principle of the Precharge Circuit
In case the data slicer threshold shall be generated with an external RC network
as described in Section 4.5 it is necessary to use large values for the capacitor
C attached to the SLN pin (pin 20) in order to achieve long time constants. This
results also from the fact that the choice of the value for R connected between
the SLP and SLN pins (pins 19 and 20) is limited by the 330kΩ resistor appearing in parallel to R as can be seen in Figure 4-7. Apart from this a resistor value
of 100kΩ leads to a voltage offset of 1mv at the comparator input as described
in Section 4.6.1. The resulting startup time constant τ1 can be calculated with:
τ1 = (R // 330kΩ) · C
In case R is chosen to be 100kΩ and C is chosen as 47nF this leads to
τ1 = (100kΩ // 330kΩ) · 47nF = 77kΩ · 47nF = 3.6ms
When the device is turned on this time constant dominates the time necessary
for the device to be able to demodulate data properly. In the powerdown mode
the capacitor is only discharged by leakage currents.
In order to reduce the turn-on time in the presence of large values of C a precharge circuit was included in the TDA5221 as shown in the following figure.
C2
R1+R2=600k
R1
R2
C
R
Uth r es h o ld
24
20
23
Uc>Us
Uc<Us
19
Uc
I load
Data Filter
ASK/FSK Switch
-
U2
0 / 240uA
+
Us
OTA
+
-
U2<2.4V : I=240uA
U2>2.4V : I=0
20k
+3.1V
+2.4V
precharge.WMF
Figure 4-10
Wireless Components
Principle of the precharge circuit
4 - 11
Target Specification, October 2001
TDA 5221
preliminary
Applications
This circuit charges the capacitor C with an inrush current Iload of typically
220µA for a duration of T2 until the voltage Uc appearing on the capacitor is
equal to the voltage Us at the input of the data filter. This voltage is limited to
2.5V. As soon as these voltages are equal or the duration T2 is exceeded the
precharge circuit is disabled.
τ2 is the time constant of the charging process of C which can be calculated as
τ2 ≈=20kΩ · C2
as the sum of R1 and R2 is sufficiently large and thus can be neglected. T2 can
then be calculated according to the following formula:
æ
ö
ç
1
≈ τ 2 ⋅1 . 6
T 2 = τ 2 ln ç
ç 1 − 2 . 4V
ç
3V
è
The voltage transient during the charging of C2 is shown in the following figure:
U2
3V
2.4V
2
T2
e-fkt1.WMF
Figure 4-11
Voltage appearing on C2 during precharging process
The voltage appearing on the capacitor C connected to pin 20 is shown in the
following figure. It can be seen that due to the fact that it is charged by a constant current source it exhibits is a linear increase in voltage which is limited to
USmax = 2.5V which is also the approximate operating point of the data filter
input. The time constant appearing in this case can be denoted as T3, which
can be calculated with
USmax ⋅ C
2,5V
T3 = ----------------------- = ----------------- ⋅ C
220µA
220µA
Wireless Components
4 - 12
Target Specification, October 2001
TDA 5221
preliminary
Applications
Uc
Us
T3
e-Fkt2.WMF
Figure 4-12
Voltage transient on capacitor C attached to pin 20
As an example the choice of C2 = 22nF and C = 47nF yields
τ2 = 0.44ms
T2 = 0.71ms
T3 = 0.53ms
This means that in this case the inrush current could flow for a duration of
0.64ms but stops already after 0.49ms when the USmax limit has been reached.
T3 should always be chosen to be shorter than T2.
It has to be noted finally that during the turn-on duration T2 the overall device
power consumption is increased by the 220µA needed to charge C.
The precharge circuit may be disabled if C2 is not equipped. This yields a T2
close to zero. Note that the sum of R4 and R5 has to be 600kΩ in order to produce 3V at the THRES pin as this voltage is internally used also as the reference for the FSK demodulator.
Wireless Components
4 - 13
Target Specification, October 2001
5
Reference
Contents of this Chapter
5.1
Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
TDA 5221
preliminary
Reference
5.1 Electrical Data
5.1.1
Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even
momentarily and individually, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-40°C ... + 105°C
#
Parameter
Symbol
Limit Values
min
max
Unit
1
Supply Voltage
Vs
-0.3
5.5
V
2
Junction Temperature
Tj
-40
+150
°C
3
Storage Temperature
Ts
-40
+125
°C
4
Thermal Resistance
RthJA
114
K/W
5
ESD integrity, all pins excl. Pins 1,3, 6, 28
ESD integrity Pins 1,3,6,28
VESD
+2
+1.5
kV
kV
Wireless Components
5-2
Remarks
HBM
according to
MIL STD
883D,
method
3015.7
Target Specification, October 2001
TDA 5221
preliminary
Reference
5.1.2
Operating Range
Within the operational range the IC operates as explained in the circuit description. The AC/DC characteristic limits are not guaranteed. Currents flowing into
the device are denoted as positive currents and v.v.
Supply voltage: VCC = 4.5V .. 5.5V
Table 5-2 Operating Range, Ambient temperature TAMB= -40°C ... + 105°C
#
Parameter
1
Supply Current
2
Receiver Input Level
ASK
FSK, frequ. dev. ± 50kHz
Symbol
Limit Values
Unit
Test Conditions
fRF = 315MHz, FSK Mode
fRF = 315MHz, ASK Mode
min
max
ISF
ISA
t.b.d.
t.b.d.
t.b.d.
t.b.d.
mA
mA
RFin
-110
-102
-13
-13
dBm
dBm
3
LNI Input Frequency
fRF
300
340
MHz
4
MI/X Input Frequency
fMI
300
340
MHz
5
3dB IF Frequency Range
ASK
FSK
fIF -3dB
5
10.4
23
11
MHz
6
Powerdown Mode On
PWDNON
0
0.8
V
7
Powerdown Mode Off
PWDNOFF
2
VS
V
8
Gain Control Voltage,
LNA high gain state
VTHRES
2.8
VS
V
9
Gain Control Voltage,
LNA low gain state
VTHRES
0
0.7
V
@ source impedance 50Ω,
BER 2E-3, average power
level, Manchester encoded
datarate 4kBit, 280kHz IF
Bandwidth
L
Item
■
■
■ This value is guaranteed by design.
Wireless Components
5-3
Target Specification, October 2001
TDA 5221
preliminary
Reference
5.1.3
AC/DC Characteristics at TAMB = 25°C
AC/DC characteristics involve the spread of values guaranteed within the specified voltage and ambient temperature range. Typical characteristics are the
median of the production. Currents flowing into the device are denoted as positive currents and vice versa.
The device performance parameters marked with ■ were measured on an
Infineon evaluation board as described in Section 5.2.
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V
Parameter
Symbol
Limit Values
min
Unit
Test Conditions
typ
max
50
t.b.d.
nA
Pin 27 (PDWN)
open or tied to 0 V
L
Item
Supply
Supply Current
1
Supply current,
standby mode
2
Supply current, device
operating in FSK mode
ISF
t.b.d.
6.4
t.b.d.
mA
Pin 11 (FSEL)
open, Pin 15
(MSEL) tied to GND
3
Supply current, device
operating in ASK mode
ISA
t.b.d.
5.6
t.b.d.
mA
Pin 11 (FSEL)
open, Pin 15
(MSEL) open
dBm
Manchester
encoded datarate
4kBit, 280kHz IF
Bandwidth
IS PDWN
LNA
Signal Input LNI (PIN 3), VTHRES > 2.8V, high gain mode
1
2
Average Power Level
at BER = 2E-3
(Sensitivity)
RFin
-113
Average Power Level
at BER = 2E-3
(Sensitivity) FSK
RFin
-105
dBm
Manchester enc.
datarate 4kBit,
280kHz IF Bandw.,
± 50kHz pk. dev.
■
■
■
3
Input impedance,
fRF = 315 MHz
S11 LNA
4
Input level @ 1dB C.P.
fRF=315 MHz
P1dBLNA
-14
dBm
5
Input 3rd order intercept
point fRF = 315 MHz
IIP3LNA
-10
dBm
6
LO signal feedthrough
at antenna port
LOLNI
-119
dBm
0.895 / -25.5 deg
■
fin = 315 & 317MHz
■
■
Signal Output LNO (PIN 6), VTHRES > 2.8V, high gain mode
1
Gain fRF = 315 MHz
S21 LNA
1.577 / 150.3 deg
■
2
Output impedance,
fRF = 315 MHz
S22 LNA
0.897 / -10.3 deg
■
Wireless Components
5-4
Target Specification, October 2001
TDA 5221
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
min
typ
Unit
Test Conditions
L
Item
max
3
Voltage Gain Antenna
to MI fRF = 315 MHz
GAntMI
21
dB
4
Noise Figure
NFLNA
2
dB
■
excluding matching
network loss - see
Appendix
■
Signal Input LNI, VTHRES = GND, low gain mode
■
1
Input impedance,
fRF = 315 MHz
S11 LNA
0.918 / -25.2 deg
2
Input level @ 1dB C. P.
fRF = 315 MHz
P1dBLNA
-7
dBm
matched input
■
3
Input 3rd order intercept
point fRF = 315 MHz
IIP3LNA
-13
dBm
fin = 315 & 317MHz
■
Signal Output LNO, VTHRES = GND, low gain mode
1
Gain fRF = 315 MHz
S21 LNA
0.193 / 153.7 deg
■
2
Output impedance,
fRF = 315 MHz
S22 LNA
0.907 / -10.5 deg
■
3
Voltage Gain Antenna
to MI fRF = 315 MHz
GAntMI
2
■
dB
Signal 3VOUT (PIN 24)
1
Output voltage
V3VOUT
2.9
3.1
3.3
V
3VOUT Pin open
2
Current out
I3VOUT
-3
-5
-10
µA
see Section 4.1
see Section 4.1
Signal THRES (PIN 23)
1
Input Voltage range
VTHRES
0
VS
V
2
LNA low gain mode
VTHRES
0
0.3
V
3
LNA high gain mode
VTHRES
3.3
VS
V
4
Current in
ITHRES_in
5
or shorted to VCC
nA
Signal TAGC (PIN 4)
1
Current out,
LNA low gain state
ITAGC_out
-3.6
-4.2
-5
µA
RSSI > VTHRES
2
Current in,
LNA high gain state
ITAGC_in
1
1.6
2.2
µA
RSSI < VTHRES
MIXER
Signal Input MI/MIX (PINS 8/9)
1
Input impedance,
fRF = 315 MHz
S11 MIX
2
Input 3rd order intercept
point
IIP3MIX
Wireless Components
■
0.954 / -10.9 deg
-25
5-5
dBm
■
Target Specification, October 2001
TDA 5221
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
min
typ
Unit
Test Conditions
L
Item
max
Signal Output IFO (PIN 12)
1
Output impedance
ZIFO
330
Ω
■
2
Conversion Voltage
Gain fRF = 315 MHz
GMIX
21
dB
■
3
Noise Figure, SSB
(~DSB NF+3dB)
NFMIX
13
dB
■
4
RF to IF isolation
ARF-IF
46
dB
■
396
Ω
■
80
dB
LIMITER
Signal Input LIM/X (PINS 17/18)
1
Input Impedance
ZLIM
264
2
RSSI dynamic range
DRRSSI
60
3
RSSI linearity
LINRSSI
4
Operating frequency
(3dB points)
fLIM
330
dB
■
23
MHz
■
100
kHz
■
±1
5
10.7
DATA FILTER
1
Useable bandwidth
2
RSSI Level at Data Filter Output SLP,
RFIN=-103dBm
RSSIlow
0.3
1
V
LNA in high gain
mode
3
RSSI Level at Data Filter Output SLP,
RFIN=-30dBm
RSSIhigh
1.8
3
V
LNA in high gain
mode
100
kBps
0.1
V
BWBB FILT
SLICER
Signal Output DATA (PIN 25)
1
Maximum Datarate
DRmax
2
LOW output voltage
VSLIC_L
0
3
HIGH output voltage
VSLIC_H
VS1.3V
VS-1V
VS0.7V
V
IPCH_SLN
-100
-220
-300
µA
NRZ, 20pF capacitive loading
■
Slicer, Negative Input (PIN 20)
1
Precharge Current Out
Wireless Components
5-6
see Section 4.7
Target Specification, October 2001
TDA 5221
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
Unit
min
typ
max
Iload
-600
-950
-1300
µA
R
t.b.d.
446
t.b.d.
kΩ
11
MHz
Test Conditions
L
Item
PEAK DETECTOR
Signal Output PDO (PIN 26)
1
Load current
2
Internal resistive load
CRYSTAL OSCILLATOR
Signals CRSTL1, CRISTL 2, (PINS 1/28)
1
Operating frequency
2
Input Impedance
@ ~10MHz
3
Serial Capacity
@ ~10MHz
fCRSTL
t.b.d.
Z1-28
-700 +
j 865
Ω
CS10=C1
7.2
pF
fundamental mode,
series resonance
■
ASK/FSK Signal Switch
Signal MSEL (PIN 15)
1
ASK Mode
VMSEL
1.4
4
V
or open
2
FSK Mode
VMSEL
0
0.2
V
or tied to ground
3
Input Bias Current
MSEL
IMSEL
t.b.d.
-11
t.b.d.
µA
MSEL tied to GND
FSK DEMODULATOR
1
Demodulation Gain
GFMDEM
85
140
225
µV/
kHz
2
Useable IF Bandwidth
BWIFPLL
10.2
10.7
11.2
MHz
POWER DOWN MODE
Signal PDWN (PIN 27)
1
Powerdown Mode On
PWDNON
0
0.8
V
2
Powerdown Mode Off
PWDNOff
2.8
VS
V
3
Input bias current
PDWN
4
Start-up Time until valid
IF signal is detected
IPDWN
19
TSU
µA
1
ms
Power On Mode
PLL DIVIDER
Signal FSEL (PIN 11)
1
Overal divison ratio 32
VFSEL
1.4
4
V
or open
2
Overal division ratio
32.25
VFSEL
0
0.2
V
or tied to GND
3
Input bias current FSEL
IFSEL
t.b.d.
t.b.d.
µA
FSEL tied to GND
Wireless Components
-11
5-7
Target Specification, October 2001
TDA 5221
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
min
typ
Unit
Test Conditions
L
Item
max
DATA-SLICER REFERENCE-LEVEL
Signal SSEL (PIN 16), ASK-Mode
1
Slicer-Reference is
voltage at Pin 20 (SLN)
VSSEL
1.4
4
V
2
Slicer-Reference is
approx. 87% of the voltage at Pin 26 (PDO)
VSSEL
0
0.2
V
3
Input bias current
SSEL
ISSEL
-3
-7
µA
-5
or open
SSEL tied to GND
■ Measured only in lab.
Wireless Components
5-8
Target Specification, October 2001
TDA 5221
preliminary
Reference
5.1.4
AC/DC Characteristics at TAMB = -40 to 105°C
Currents flowing into the device are denoted as positive currents and vice
versa.
Table 5-4 AC/DC Characteristics with TAMB= -40°C ... + 105°C, VVCC = 4.5 ... 5.5 V
Parameter
Symbol
Limit Values
min
Unit
Test Conditions
typ
max
50
t.b.d.
nA
Pin 27 (PDWN)
open or tied to 0 V
L
Item
Supply
Supply Current
1
Supply current,
standby mode
2
Supply current, device
operating in FSK mode
ISF
t.b.d.
6.4
t.b.d.
mA
Pin 11 (FSEL) tied
to GND, Pin 15
(MSEL) tied to GND
3
Supply current, device
operating in ASK mode
ISA
t.b.d.
5.6
t.b.d.
mA
Pin 11 (FSEL)
open, Pin 15
(MSEL) open
IS PDWN
Signal 3VOUT (PIN 24)
1
Output voltage
V3VOUT
2.9
3.1
3.3
V
3VOUT Pin open
2
Current out
I3VOUT
-3
-5
-10
µA
see Section 4.1
see Section 4.1
Signal THRES (PIN 23)
1
Input Voltage range
VTHRES
0
VS-1V
V
2
LNA low gain mode
VTHRES
0
0.3
V
3
LNA high gain mode
VTHRES
3
VS
V
4
Current in
ITHRES_in
5
or shorted to Pin 24
nA
Signal TAGC (PIN 4)
1
Current out,
LNA low gain state
ITAGC_out
-1
-4.2
-8
µA
RSSI > VTHRES
2
Current in, LNA high
gain state
VTAGC_in
0.5
1.5
5
µA
RSSI < VTHRES
MIXER
1
GMIX
Conversion Voltage
Gain fRF = 315 MHz
+19
dB
LIMITER
Signal Input LIM/X (PINS 17/18)
1
RSSI dynamic range
DRRSSI
60
80
dB
2
RSSI Level at Data Filter Output SLP,
RFIN= -103dBm
RSSIlow
0.3
1
V
LNA in high gain
mode
3
RSSI Level at Data Filter Output SLP,
RFIN= -30dBm
RSSIhigh
1.8
3
V
LNA in high gain
mode
Wireless Components
5-9
Target Specification, October 2001
TDA 5221
preliminary
Reference
Table 5-4 AC/DC Characteristics with TAMB= -40°C ... + 105°C, VVCC = 4.5 ... 5.5 V
Parameter
Symbol
Limit Values
min
typ
Unit
Test Conditions
L
100
kBps
NRZ, 20pF capacitive loading
■
0.1
V
Item
max
DATA FILTER
Slicer, Signal Output DATA (PIN 25)
1
Maximum Datarate
DRmax
2
LOW output voltage
VSLIC_L
0
3
HIGH output voltage
VSLIC_H
VS1.5V
VS-1V
VS0.5V
V
IPCH_SLN
-100
-220
-300
µA
Iload
-400
-850
-1400
µA
R
t.b.d
446
t.b.d.
kΩ
Slicer, Negative Input (PIN 20)
1
Precharge Current Out
see Section 4.7
PEAK DETECTOR
Signal Output PDO (PIN 26)
1
Load current
2
Internal resistive load
CRYSTAL OSCILLATOR
Signals CRSTL1, CRSTL 2, (PINS 1/28)
1
Operating frequency
fCRSTL
t.b.d.
11
MHz
fundamental mode,
series resonance
ASK/FSK Signal Switch
Signal MSEL (PIN 15)
1
ASK Mode
VMSEL
1.4
4
V
2
FSK Mode
VMSEL
0
0.2
V
3
Input bias current MSEL
IMSEL
t.b.d.
-11
t.b.d.
µA
or open
MSEL tied to GND
FSK DEMODULATOR
1
Demodulation Gain
GFMDEM
105
140
245
µV/
kHz
2
Useable IF Bandwidth
BWIFPLL
10.4
10.7
11
MHz
POWER DOWN MODE
Signal PDWN (PIN 27)
1
Powerdown Mode On
PWDNON
0
0.8
V
2
Powerdown Mode Off
PWDNOff
2.8
VS
V
3
Start-up Time until valid
signal is detected at IF
1
ms
TSU
PLL DIVIDER
Signal FSEL (PIN 11)
1
Overal divison ratio 32
VFSEL
1.4
4
V
or open
2
Overal division ratio
32.25
VFSEL
0
0.2
V
or tied to GND
3
Input bias current FSEL
IFSEL
t.b.d.
t.b.d.
µA
FSEL tied to GND
Wireless Components
-11
5 - 10
Target Specification, October 2001
TDA 5221
preliminary
Reference
DATA-SLICER REFERENCE-LEVEL
Signal SSEL (PIN 16), ASK-Mode
1
Slicer-Reference is voltage at Pin 20 (SLN)
VSSEL
1.4
4
V
2
Slicer-Reference is
approx. 87% of the voltage at Pin 26 (PDO)
VSSEL
0
0.2
V
3
Input bias current
SSEL
ISSEL
-3
-7
µA
Wireless Components
-5
5 - 11
or open
SSEL tied to GND
Target Specification, October 2001