RICHTEK RT8862

RT8862
Advanced 4/3/2/1-Phase PWM Controller with Embedded
Drivers for CPU Core Power Supply
General Description
Features
The RT8862 is an advanced 4/3/2/1-phase synchronous
buck controller with 2 integrated MOSFET drivers for Intel
VR11/VR10 and AMD K8/K8_M2 CPUs power application.
RT8862 adopts state-of-the-art dynamic phase control
capability. That achieves high efficiency over wide load
range. It uses differential inductor DCR current sense to
achieve phase current balance and active voltage
positioning. Other features include adjustable operating
frequency, adjustable soft start, power good indication,
external error-amp compensation, over voltage protection,
over current protection and enable/shutdown for various
application. RT8862 comes to a small footprint with
WQFN-48L 7x7 package.
z
z
z
z
z
z
z
z
z
z
z
z
z
Ordering Information
z
RT8862
z
Package Type
QW : WQFN-48L 7x7 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
z
z
Support Dynamic Phase Control
12V Power Supply Voltage
4/3/2/1-Phase Power Conversion
2 Embedded MOSFET Drivers
Internal Regulated 5V Output
VID table for INTEL VR11.1/VR10.x and AMD K8/
K8_M2 CPUs
Continuous Differential Inductor DCR Current Sense
Adjustable Soft Start
Adjustable Frequency (300kHz typ.)
Power Good Indication
Adjustable Over Current Protection
Over Voltage Protection
VRHOT Sensing with External Thermistor
IMON Output Current Indication
Power State Indicator (PSI)
Small 48-Lead WQFN Package
RoHS Compliant and Halogen Free
Pin Configurations
Note :
(TOP VIEW)
`
PS
PSI
VIDSEL
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
EN/VTT
Richtek products are :
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
Applications
z
z
Desktop CPU Core Power
Low Voltage, High Current DC/ DC Converter
48 47 46 45 44 43 42 41 40 39 38 37
FBRTN
QR1
QR2
SS/EN
COMP
FB
OFS
RT
ADJ
IMAX
IMAXPSI
IMONFB
1
36
2
35
3
34
4
33
5
32
6
7
31
GND
30
8
29
9
28
10
27
49
26
11
25
12
PWRGD
BOOT1
UGATE1
PHASE1
LGATE1
VCC12
LGATE2
PHASE2
UGATE2
BOOT2
PWM3
PWM4
IMON
ISP4
ISN4
ISN3
ISP3
ISP2
ISN2
ISN1
ISP1
VRHOT
TSEN
VCC5
13 14 15 16 17 18 19 20 21 22 23 24
WQFN-48L 7x7
DS8862-01 April 2011
www.richtek.com
1
www.richtek.com
2
L4
L3
12V
12V
5V
VCC5/VTT
PWM
GND
VCC
PWM
GND
VCC
LGATE
RT9619
PHASE
UGATE
BOOT
RT9619
LGATE
PHASE
UGATE
BOOT
5V
12V
12V
NTC2
5V
TSEN
RT
VCC5
OFS
IMAX
IMAXPSI
PWM4
14
ISP4
15 ISN4
25
2 QR1
17 ISP3
16 ISN3
26 PWM3
48 PS
46
VIDSEL
10
11
24
7
8
12 IMONFB
13
IMON
9 ADJ
23
VRHOT
22
VRHOT
EN/VTT
QR2 3
GND Exposed Pad (49)
VCC12 31
FBRTN 1
SS/EN 4
COMP 5
FB 6
ISP2 18
19
ISN2
PHASE2 29
LGATE2 30
UGATE2 28
ISP1 21
ISN1 20
38 to 45
VID[7:0]
37
EN/VTT
47
PSI
PWRGD 36
BOOT2 27
PHASE1 33
32
LGATE1
BOOT1 35
UGATE1 34
RT8862
12V
V IN
V IN
L2
L1
NTC1
LOAD
V CC_SNS
V SS_SNS
VOUT
RT8862
Typical Application Circuit
DS8862-01 April 2011
RT8862
Table 1. VR11.1 VID Code Table
VID7 VID6 VID5 VID4 VID3 VID 2 VID1 VID0 Voltage
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
0
0
0
0
0
0
0
0
OFF
0
0
1
0
0
0
1
1
1.39375
0
0
0
0
0
0
0
1
OFF
0
0
1
0
0
1
0
0
1.38750
0
0
0
0
0
0
1
0
1.60000
0
0
1
0
0
1
0
1
1.38125
0
0
0
0
0
0
1
1
1.59375
0
0
1
0
0
1
1
0
1.37500
0
0
0
0
0
1
0
0
1.58750
0
0
1
0
0
1
1
1
1.36875
0
0
0
0
0
1
0
1
1.58125
0
0
1
0
1
0
0
0
1.36250
0
0
0
0
0
1
1
0
1.57500
0
0
1
0
1
0
0
1
1.35625
0
0
0
0
0
1
1
1
1.56875
0
0
1
0
1
0
1
0
1.35000
0
0
0
0
1
0
0
0
1.56250
0
0
1
0
1
0
1
1
1.34375
0
0
0
0
1
0
0
1
1.55625
0
0
1
0
1
1
0
0
1.33750
0
0
0
0
1
0
1
0
1.55000
0
0
1
0
1
1
0
1
1.33125
0
0
0
0
1
0
1
1
1.54375
0
0
1
0
1
1
1
0
1.32500
0
0
0
0
1
1
0
0
1.53750
0
0
1
0
1
1
1
1
1.31875
0
0
0
0
1
1
0
1
1.53125
0
0
1
1
0
0
0
0
1.31250
0
0
0
0
1
1
1
0
1.52500
0
0
1
1
0
0
0
1
1.30625
0
0
0
0
1
1
1
1
1.51875
0
0
1
1
0
0
1
0
1.30000
0
0
0
1
0
0
0
0
1.51250
0
0
1
1
0
0
1
1
1.29375
0
0
0
1
0
0
0
1
1.50625
0
0
1
1
0
1
0
0
1.28750
0
0
0
1
0
0
1
0
1.50000
0
0
1
1
0
1
0
1
1.28125
0
0
0
1
0
0
1
1
1.49375
0
0
1
1
0
1
1
0
1.27500
0
0
0
1
0
1
0
0
1.48750
0
0
1
1
0
1
1
1
1.26875
0
0
0
1
0
1
0
1
1.48125
0
0
1
1
1
0
0
0
1.26250
0
0
0
1
0
1
1
0
1.47500
0
0
1
1
1
0
0
1
1.25625
0
0
0
1
0
1
1
1
1.46875
0
0
1
1
1
0
1
0
1.25000
0
0
0
1
1
0
0
0
1.46250
0
0
1
1
1
0
1
1
1.24375
0
0
0
1
1
0
0
1
1.45625
0
0
1
1
1
1
0
0
1.23750
0
0
0
1
1
0
1
0
1.45000
0
0
1
1
1
1
0
1
1.23125
0
0
0
1
1
0
1
1
1.44375
0
0
1
1
1
1
1
0
1.22500
0
0
0
1
1
1
0
0
1.43750
0
0
1
1
1
1
1
1
1.21875
0
0
0
1
1
1
0
1
1.43125
0
1
0
0
0
0
0
0
1.21250
0
0
0
1
1
1
1
0
1.42500
0
1
0
0
0
0
0
1
1.20625
0
0
0
1
1
1
1
1
1.41875
0
1
0
0
0
0
1
0
1.20000
0
0
1
0
0
0
0
0
1.41250
0
1
0
0
0
0
1
1
1.19375
0
0
1
0
0
0
0
1
1.40625
0
1
0
0
0
1
0
0
1.18750
0
0
1
0
0
0
1
0
1.40000
0
1
0
0
0
1
0
1
1.18125
To be continued
DS8862-01 April 2011
www.richtek.com
3
RT8862
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
0
1
0
0
0
1
1
0
1.17500
0
1
1
0
1
0
1
0
0.95000
0
1
0
0
0
1
1
1
1.16875
0
1
1
0
1
0
1
1
0.94375
0
1
0
0
1
0
0
0
1.16250
0
1
1
0
1
1
0
0
0.93750
0
1
0
0
1
0
0
1
1.15625
0
1
1
0
1
1
0
1
0.93125
0
1
0
0
1
0
1
0
1.15000
0
1
1
0
1
1
1
0
0.92500
0
1
0
0
1
0
1
1
1.14375
0
1
1
0
1
1
1
1
0.91875
0
1
0
0
1
1
0
0
1.13750
0
1
1
1
0
0
0
0
0.91250
0
1
0
0
1
1
0
1
1.13125
0
1
1
1
0
0
0
1
0.90625
0
1
0
0
1
1
1
0
1.12500
0
1
1
1
0
0
1
0
0.90000
0
1
0
0
1
1
1
1
1.11875
0
1
1
1
0
0
1
1
0.89375
0
1
0
1
0
0
0
0
1.11250
0
1
1
1
0
1
0
0
0.88750
0
1
0
1
0
0
0
1
1.10625
0
1
1
1
0
1
0
1
0.88125
0
1
0
1
0
0
1
0
1.10000
0
1
1
1
0
1
1
0
0.87500
0
1
0
1
0
0
1
1
1.09375
0
1
1
1
0
1
1
1
0.86875
0
1
0
1
0
1
0
0
1.08750
0
1
1
1
1
0
0
0
0.86250
0
1
0
1
0
1
0
1
1.08125
0
1
1
1
1
0
0
1
0.85625
0
1
0
1
0
1
1
0
1.07500
0
1
1
1
1
0
1
0
0.85000
0
1
0
1
0
1
1
1
1.06875
0
1
1
1
1
0
1
1
0.84375
0
1
0
1
1
0
0
0
1.06250
0
1
1
1
1
1
0
0
0.83750
0
1
0
1
1
0
0
1
1.05625
0
1
1
1
1
1
0
1
0.83125
0
1
0
1
1
0
1
0
1.05000
0
1
1
1
1
1
1
0
0.82500
0
1
0
1
1
0
1
1
1.04375
0
1
1
1
1
1
1
1
0.81875
0
1
0
1
1
1
0
0
1.03750
1
0
0
0
0
0
0
0
0.81250
0
1
0
1
1
1
0
1
1.03125
1
0
0
0
0
0
0
1
0.80625
0
1
0
1
1
1
1
0
1.02500
1
0
0
0
0
0
1
0
0.80000
0
1
0
1
1
1
1
1
1.01875
1
0
0
0
0
0
1
1
0.79375
0
1
1
0
0
0
0
0
1.01250
1
0
0
0
0
1
0
0
0.78750
0
1
1
0
0
0
0
1
1.00625
1
0
0
0
0
1
0
1
0.78125
0
1
1
0
0
0
1
0
1.00000
1
0
0
0
0
1
1
0
0.77500
0
1
1
0
0
0
1
1
0.99375
1
0
0
0
0
1
1
1
0.76875
0
1
1
0
0
1
0
0
0.98750
1
0
0
0
1
0
0
0
0.76250
0
1
1
0
0
1
0
1
0.98125
1
0
0
0
1
0
0
1
0.75625
0
1
1
0
0
1
1
0
0.97500
1
0
0
0
1
0
1
0
0.75000
0
1
1
0
0
1
1
1
0.96875
1
0
0
0
1
0
1
1
0.74375
0
1
1
0
1
0
0
0
0.96250
1
0
0
0
1
1
0
0
0.73750
0
1
1
0
1
0
0
1
0.95625
1
0
0
0
1
1
0
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4
1 0.73125
To be continued
DS8862-01 April 2011
RT8862
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
1
0
0
0
1
1
1
0
0.72500
1
0
1
1
0
0
1
0
0.50000
1
0
0
0
1
1
1
1
0.71875
1
1
1
1
1
1
1
0
OFF
1
0
0
1
0
0
0
0
0.71250
1
1
1
1
1
1
1
1
OFF
1
0
0
1
0
0
0
1
0.70625
1
0
0
1
0
0
1
0
0.70000
1
0
0
1
0
0
1
1
0.69375
1
0
0
1
0
1
0
0
0.68750
1
0
0
1
0
1
0
1
0.68125
1
0
0
1
0
1
1
0
0.67500
1
0
0
1
0
1
1
1
0.66875
1
0
0
1
1
0
0
0
0.66250
1
0
0
1
1
0
0
1
0.65625
1
0
0
1
1
0
1
0
0.65000
1
0
0
1
1
0
1
1
0.64375
1
0
0
1
1
1
0
0
0.63750
1
0
0
1
1
1
0
1
0.63125
1
0
0
1
1
1
1
0
0.62500
1
0
0
1
1
1
1
1
0.61875
1
0
1
0
0
0
0
0
0.61250
1
0
1
0
0
0
0
1
0.60625
1
0
1
0
0
0
1
0
0.60000
1
0
1
0
0
0
1
1
0.59375
1
0
1
0
0
1
0
0
0.58750
1
0
1
0
0
1
0
1
0.58125
1
0
1
0
0
1
1
0
0.57500
1
0
1
0
0
1
1
1
0.56875
1
0
1
0
1
0
0
0
0.56250
1
0
1
0
1
0
0
1
0.55625
1
0
1
0
1
0
1
0
0.55000
1
0
1
0
1
0
1
1
0.54375
1
0
1
0
1
1
0
0
0.53750
1
0
1
0
1
1
0
1
0.53125
1
0
1
0
1
1
1
0
0.52500
1
0
1
0
1
1
1
1
0.51875
1
0
1
1
0
0
0
0
0.51250
1
0
1
1
0
0
0
1
0.50625
DS8862-01 April 2011
www.richtek.com
5
RT8862
Table 2. Output Voltage Program (VRD10.x + VID6)
Pin Nam e
Nominal Output Voltage DACOUT
VID4
VID3
VID2
VID1
VID0
VID5
VID6
0
1
0
1
0
1
1
1.60000V
0
1
0
1
0
1
0
1.59375V
0
1
0
1
1
0
1
1.58750V
0
1
0
1
1
0
0
1.58125V
0
1
0
1
1
1
1
1.57500V
0
1
0
1
1
1
0
1.56875V
0
1
1
0
0
0
1
1.56250V
0
1
1
0
0
0
0
1.55625V
0
1
1
0
0
1
1
1.55000V
0
1
1
0
0
1
0
1.54375V
0
1
1
0
1
0
1
1.53750V
0
1
1
0
1
0
0
1.53125V
0
1
1
0
1
1
1
1.52500V
0
1
1
0
1
1
0
1.51875V
0
1
1
1
0
0
1
1.51250V
0
1
1
1
0
0
0
1.50625V
0
1
1
1
0
1
1
1.50000V
0
1
1
1
0
1
0
1.49375V
0
1
1
1
1
0
1
1.48750V
0
1
1
1
1
0
0
1.48125V
0
1
1
1
1
1
1
1.47500V
0
1
1
1
1
1
0
1.46875V
1
0
0
0
0
0
1
1.46250V
1
0
0
0
0
0
0
1.45625V
1
0
0
0
0
1
1
1.45000V
1
0
0
0
0
1
0
1.44375V
1
0
0
0
1
0
1
1.43750V
1
0
0
0
1
0
0
1.43125V
1
0
0
0
1
1
1
1.42500V
1
0
0
0
1
1
0
1.41875V
1
0
0
1
0
0
1
1.41250V
1
0
0
1
0
0
0
1.40625V
1
0
0
1
0
1
1
1.40000V
1
0
0
1
0
1
0
1.39375V
1
0
0
1
1
0
1
1.38750V
1
0
0
1
1
0
0
1.38125V
1
0
0
1
1
1
1
1.37500V
1
0
0
1
1
1
0
1.36875V
1
0
1
0
0
0
1
1.36250V
To be continued
www.richtek.com
6
DS8862-01 April 2011
RT8862
Pin Name
Nominal Output Voltage D ACOUT
VID4
VID3
VID2
VID1
VID0
VID5
VID6
1
0
1
0
0
0
0
1.35625V
1
0
1
0
0
1
1
1.35000V
1
0
1
0
0
1
0
1.34375V
1
0
1
0
1
0
1
1.33750V
1
0
1
0
1
0
0
1.33125V
1
0
1
0
1
1
1
1.32500V
1
0
1
0
1
1
0
1.31875V
1
0
1
1
0
0
1
1.31250V
1
0
1
1
0
0
0
1.30625V
1
0
1
1
0
1
1
1.30000V
1
0
1
1
0
1
0
1.29375V
1
0
1
1
1
0
1
1.28750V
1
0
1
1
1
0
0
1.28125V
1
0
1
1
1
1
1
1.27500V
1
0
1
1
1
1
0
1.26875V
1
1
0
0
0
0
1
1.26250V
1
1
0
0
0
0
0
1.25625V
1
1
0
0
0
1
1
1.25000V
1
1
0
0
0
1
0
1.24375V
1
1
0
0
1
0
1
1.23750V
1
1
0
0
1
0
0
1.23125V
1
1
0
0
1
1
1
1.22500V
1
1
0
0
1
1
0
1.21875V
1
1
0
1
0
0
1
1.21250V
1
1
0
1
0
0
0
1.20625V
1
1
0
1
0
1
1
1.20000V
1
1
0
1
0
1
0
1.19375V
1
1
0
1
1
0
1
1.18750V
1
1
0
1
1
0
0
1.18125V
1
1
0
1
1
1
1
1.17500V
1
1
0
1
1
1
0
1.16875V
1
1
1
0
0
0
1
1.16250V
1
1
1
0
0
0
0
1,15625V
1
1
1
0
0
1
1
1.15000V
1
1
1
0
0
1
0
1.14375V
1
1
1
0
1
0
1
1.13750V
1
1
1
0
1
0
0
1.13125V
1
1
1
0
1
1
1
1.12500V
1
1
1
0
1
1
0
1.11875V
To be continued
DS8862-01 April 2011
www.richtek.com
7
RT8862
Pin Name
Nominal Output Voltage D AC OUT
VID4
VID3
VID2
VID1
VID0
VID5
VID6
1
1
1
1
0
0
1
1.11250V
1
1
1
1
0
0
0
1.10625V
1
1
1
1
0
1
1
1.10000V
1
1
1
1
0
1
0
1.09375V
1
1
1
1
1
0
1
OFF
1
1
1
1
1
0
0
OFF
1
1
1
1
1
1
1
OFF
1
1
1
1
1
1
0
OFF
0
0
0
0
0
0
1
1.08750V
0
0
0
0
0
0
0
1.08125V
0
0
0
0
0
1
1
1.07500V
0
0
0
0
0
1
0
1.06875V
0
0
0
0
1
0
1
1.06250V
0
0
0
0
1
0
0
1.05625V
0
0
0
0
1
1
1
1.05000V
0
0
0
0
1
1
0
1.04375V
0
0
0
1
0
0
1
1.03750V
0
0
0
1
0
0
0
1.03125V
0
0
0
1
0
1
1
1.02500V
0
0
0
1
0
1
0
1.01875V
0
0
0
1
1
0
1
1.01250V
0
0
0
1
1
0
0
1.00625V
0
0
0
1
1
1
1
1.00000V
0
0
0
1
1
1
0
0.99375V
0
0
1
0
0
0
1
0.98750V
0
0
1
0
0
0
0
0.98125V
0
0
1
0
0
1
1
0.97500V
0
0
1
0
0
1
0
0.96875V
0
0
1
0
1
0
1
0.96250V
0
0
1
0
1
0
0
0.95625V
0
0
1
0
1
1
1
0.95000V
0
0
1
0
1
1
0
0.94375V
0
0
1
1
0
0
1
0.93750V
0
0
1
1
0
0
0
0.93125V
0
0
1
1
0
1
1
0.92500V
0
0
1
1
0
1
0
0.91875V
0
0
1
1
1
0
1
0.91250V
0
0
1
1
1
0
0
0.90625V
0
0
1
1
1
1
1
0.90000V
To be continued
www.richtek.com
8
DS8862-01 April 2011
RT8862
Pin Name
Nominal Output Voltage DACOUT
VID 4
VID3
VID2
VID1
VID0
VID5
VID6
0
0
1
1
1
1
0
0.89375V
0
1
0
0
0
0
1
0.88750V
0
1
0
0
0
0
0
0.88125V
0
1
0
0
0
1
1
0.87500V
0
1
0
0
0
1
0
0.86875V
0
1
0
0
1
0
1
0.86250V
0
1
0
0
1
0
0
0.85625V
0
1
0
0
1
1
1
0.85000V
0
1
0
0
1
1
0
0.84375V
0
1
0
1
0
0
1
0.83750V
0
1
0
1
0
0
0
0.83125V
DS8862-01 April 2011
www.richtek.com
9
RT8862
Table 3. Output Voltage Program (K8)
VID4
VID3
VID2
VID1
VID0
Nominal Output Voltage D ACOUT
0
0
0
0
0
1.550
0
0
0
0
1
1.525
0
0
0
1
0
1.500
0
0
0
1
1
1.475
0
0
1
0
0
1.450
0
0
1
0
1
1.425
0
0
1
1
0
1.400
0
0
1
1
1
1.375
0
1
0
0
0
1.350
0
1
0
0
1
1.325
0
1
0
1
0
1.200
0
1
0
1
1
1.275
0
1
1
0
0
1.250
0
1
1
0
1
1.225
0
1
1
1
0
1.200
0
1
1
1
1
1.175
1
0
0
0
0
1.150
1
0
0
0
1
1.125
1
0
0
1
0
1.100
1
0
0
1
1
1.075
1
0
1
0
0
1.050
1
0
1
0
1
1.025
1
0
1
1
0
1.000
1
0
1
1
1
0.975
1
1
0
0
0
0.950
1
1
0
0
1
0.925
1
1
0
1
0
0.900
1
1
0
1
1
0.875
1
1
1
0
0
0.850
1
1
1
0
1
0.825
1
1
1
1
0
0.800
1
1
1
1
1
Shutdown
Note: (1) 0 : Connected to GND
(2) 1 : Open
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10
DS8862-01 April 2011
RT8862
Table 4. Output Voltage Program (K8_M2)
Pin Name
Nominal Output Voltage DACOUT
VID5
VID4
VID3
VID2
VID1
VID0
0
0
0
0
0
0
1.5500
0
0
0
0
0
1
1.5250
0
0
0
0
1
0
1.5000
0
0
0
0
1
1
1.4750
0
0
0
1
0
0
1.4500
0
0
0
1
0
1
1.4250
0
0
0
1
1
0
1.4000
0
0
0
1
1
1
1.3750
0
0
1
0
0
0
1.3500
0
0
1
0
0
1
1.3250
0
0
1
0
1
0
1.3000
0
0
1
0
1
1
1.2750
0
0
1
1
0
0
1.2500
0
0
1
1
0
1
1.2250
0
0
1
1
1
0
1.2000
0
0
1
1
1
1
1.1750
0
1
0
0
0
0
1.1500
0
1
0
0
0
1
1.1250
0
1
0
0
1
0
1.1000
0
1
0
0
1
1
1.0750
0
1
0
1
0
0
1.0500
0
1
0
1
0
1
1.0250
0
1
0
1
1
0
1.0000
0
1
0
1
1
1
0.9750
0
1
1
0
0
0
0.9500
0
1
1
0
0
1
0.9250
0
1
1
0
1
0
0.9000
0
1
1
0
1
1
0.8750
0
1
1
1
0
0
0.8500
0
1
1
1
0
1
0.8250
0
1
1
1
1
0
0.8000
0
1
1
1
1
1
0.7750
1
0
0
0
0
0
0.7625
1
0
0
0
0
1
0.7500
To be continued
DS8862-01 April 2011
www.richtek.com
11
RT8862
Pin Name
Nominal Output Voltage DACOUT
VID5
VID4
VID3
VID2
VID1
VID0
1
0
0
0
1
0
0.7375
1
0
0
0
1
1
0.7250
1
0
0
1
0
0
0.7125
1
0
0
1
0
1
0.7000
1
0
0
1
1
0
0.6875
1
0
0
1
1
1
0.6750
1
0
1
0
0
0
0.6625
1
0
1
0
0
1
0.6500
1
0
1
0
1
0
0.6375
1
0
1
0
1
1
0.6250
1
0
1
1
0
0
0.6125
1
0
1
1
0
1
0.6000
1
0
1
1
1
0
0.5875
1
0
1
1
1
1
0.5750
1
1
0
0
0
0
0.5625
1
1
0
0
0
1
0.5500
1
1
0
0
1
0
0.5375
1
1
0
0
1
1
0.5250
1
1
0
1
0
0
0.5125
1
1
0
1
0
1
0.5000
1
1
0
1
1
0
0.4875
1
1
0
1
1
1
0.4750
1
1
1
0
0
0
0.4625
1
1
1
0
0
1
0.4500
1
1
1
0
1
0
0.4375
1
1
1
0
1
1
0.4250
1
1
1
1
0
0
0.4125
1
1
1
1
0
1
0.4000
1
1
1
1
1
0
0.3875
1
1
1
1
1
1
0.3750
Note: (1) 0 : Connected to GND
(2) 1 : Open
(3) The voltage above are load independent for desktop and server platforms. For mobile platforms the voltage above
correspond to zero load current.
www.richtek.com
12
DS8862-01 April 2011
RT8862
Functional Pin Description
Pin No.
1
Pin Name
FBRTN
Pin Function
Negative Remote Sense Pin of Output Voltage.
2
QR1
Quick Response Setting Pins for Load Transition.
3
QR2
4
SS/EN
Quick Response Setting Pins for Load Transition.
Connect this pin to GND by a capacitor to adjust soft start time.
Pull this pin to GND to disable controller.
5
COMP
Output of the Error-Amplifier and Input of the PWM Comparator.
6
FB
7
OFS
8
9
RT
ADJ
10
IMAX
11
12
IMAXPSI
IMONFB
Inverting Input of the Error-Amplifier.
Connect this pin to GND or 5V by a resistor to set no-load offset
voltage.
Connect this Pin to GND by a Resistor to Adjust Frequency.
Connect this Pin to GND by a Resistor to Set Load Line.
Negative Input of OCP Comparator. (Positive input of OCP
comparator is ADJ).
OCP Setting in Power Saving Mode.
Current Monitor Gain/Offset Adjustment.
13
IMON
Current Monitor Output.
14, 17, 18, 21
ISP4, ISP3, ISP2, ISP1 Positive Current Sense Pin of phase 1, 2, 3 and 4.
15, 16, 19, 20
ISN4, ISN3, ISN2, ISN1 Negative Current Sense Pin of phase 1, 2, 3 and 4.
22
23
VRHOT
TSEN
Temperature Monitor Output.
Temperature Sense Input.
24
VCC5
5V LDO Output for System Power Supply.
25, 26
PWM4, PWM3
PWM Output for Phase 4 and Phase 3.
27, 35
BOOT2, BOOT1
Bootstrap Supply for Phase 2 and Phase 1.
28, 34
29, 33
UGATE2, UGATE1
PHASE2, PHASE1
Upper Gate Driver for Phase 2 and Phase 1.
Switching Node of Phase 2 and Phase 1.
30, 32
LGATE2, LGATE1
Lower Gate Driver for Phase 2 and Phase 1.
31
VCC12
IC Power Supply. Connect to 12V.
36
PWRGD
Power Good Indicator.
VTT Voltage Detector Input.
Voltage Identification Input for DAC.
47
EN/VTT
VID7 to VID0
PSI
48
PS
Dynamic Phase Control Threshold Input.
46
VIDSEL
VID DAC Selection Pin.
GND
The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
37
38 to 45
49
(Exposed pad)
VID Table Selection
VIDSEL VID [7]
Table
VTT
X
VR11
GND
X
VR10.x
VCC5
VTT
K8
VCC5
GND
K8_M2
DS8862-01 April 2011
Power Status Indicator II.
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13
RT8862
Function Block Diagram
VCC12
Modulator
Waveform
Generator
RT
5V
Regulator
Power-On
Reset
POR
VCC5
IMON
COMP
FB
EA
+
IOFSP
OFS
PS
Dynamic Phase
Control
BOOT1
IOFSN
Offset
MOSFET
Driver
+
+
OV
-
UGATE1
PHASE1
LGATE1
OE4
PSI
+
150mV
BOOT2
+
-
Transient
Response
Enhancement
QR1/QR2
OE3
MOSFET
Driver
UGATE2
PHASE2
LGATE2
PWM3
+
-
OV
OC
VIDOFF
POR
OE2
Soft Start
and
Fault
Logic
SS/EN
EN/VTT
+
PWM4
+
-
OE1
+
-
I_SEN2
+
FBRTN
VID
Table
Generator
-
+
VIDSEL
VID7 to VID0
-
-
I_SEN3
+
+
-
OC
-
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14
+
IMONFB
GND
CH1
Current
SENSE
CH2
Current
SENSE
ISP1
ISN1
ISP2
ISN2
AVG
ADJ
IMAX/
IMAXPSI
I_SEN1
+
850mV
Load Current
Monitor
Temperature
Monitor
IMON
TSEN
I_SEN4
CH3
Current
SENSE
CH4
Current
SENSE
ISP3
ISN3
ISP4
ISN4
VRHOT
DS8862-01 April 2011
RT8862
Absolute Maximum Ratings
z
z
z
z
z
z
z
z
z
z
z
z
(Note 1)
Supply Input Voltage ------------------------------------------------------------------------------BOOTx to PHASEx -------------------------------------------------------------------------------PHASEx to GND
DC -----------------------------------------------------------------------------------------------------< 20ns ------------------------------------------------------------------------------------------------UGATEx to GND -----------------------------------------------------------------------------------< 20ns ------------------------------------------------------------------------------------------------LGATEx to GND ------------------------------------------------------------------------------------< 20ns ------------------------------------------------------------------------------------------------Others Pins -----------------------------------------------------------------------------------------Input/Output Voltage ------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
WQFN−48L 7x7 ------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
WQFN−48L 7x7, θJA ------------------------------------------------------------------------------WQFN−48L 7x7, θJC ------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Mode) -----------------------------------------------------------------------MM (Machine Mode) -------------------------------------------------------------------------------
Recommended Operating Conditions
z
z
z
−0.3V to 15V
−0.3V to 15V
−2V to 15V
−5V to 30V
(VPHASE − 0.3V) to (VBOOT + 0.3V)
(VPHASE − 5V) to (VBOOT + 5V)
(GND − 0.3V) to (VCC + 0.3V)
(GND− 5V) to (VCC + 5V)
− 0.3V to 6.5V
−0.3V to (VCC5 + 0.3V)
2.941W
34°C/W
7°C/W
150°C
260°C
2kV
200V
(Note 4)
Supply Voltage, VCC12 ---------------------------------------------------------------------------------------- 12V ± 10%
Junction Temperature Range ---------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ---------------------------------------------------------------------------------- 0°C to 70°C
Electrical Characteristics
(VCC12 = 12V, VGND = 0V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
10.8
12
13.2
V
--
6
--
mA
4.75
5.0
5.25
V
10
--
--
mA
9.2
9.6
10
V
--
0.9
--
V
VCC12 Supply Input
VCC12 Supply Voltage
VCC12
VCC12 Supply Current
ICC
VCC5 Power
VCC5 Supply Voltage
VCC5
VCC5 Output Sourcing
IVCC5
I LOAD = 10mA
(Note 6)
Power On Reset
VCC12 Rising Threshold
VVCC12TH
VCC12 Rising
VCC12 Hysteresis
VVCC12HY VCC12 Falling
VCC5 Rising Threshold
VVCC5TH
4.4
4.6
4.8
V
VCC5 Hysteresis
VVCC5HY
--
0.4
--
V
To be continued
DS8862-01 April 2011
www.richtek.com
15
RT8862
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
EN/VTT
EN/VTT Rising Threshold
V ENVTT
EN/VTT Rising
0.8
0.85
0.9
V
Enable Hysteresis
V ENVTTHY
EN/VTT Falling
--
100
--
mV
1V to 1.6V
−0.5
--
0.5
%
0.8V to 1V
−5
--
5
mV
0.5V to 0.8V
−8
--
8
mV
Reference Voltage accuracy
DAC Accuracy
Error Amplifier
DC Gain
A DC
No Load
--
80
--
dB
Gain-Bandwidth
GBW
CLOAD = 10pF
--
10
--
MHz
Slew Rate
Output voltage range
SR
V COMP
CLOAD = 10pF
10
0.5
--
-3.6
V/μs
V
Max Current
IEA_S LEW
Slew
300
--
--
μA
PWRGD Low Voltage
V PGOOD
IPWRGD = 4mA
--
--
0.4
V
Soft-Start Delay
TD1
--
2
--
ms
VBOOT Duration
TD3
--
0.8
--
ms
PWRGD Delay
TD5
Measured the time form VBOOT change
to PWRGD = 1
--
1.6
--
ms
Max Current
IGMMAX
V CSP = 1.3V
Sink Current from CSN
100
--
--
μA
Input Offset Voltage
V OSCS
−2
0
2
mV
Running Frequency
fOSC
RRT = 40kΩ
270
300
330
kHz
RT Pin Voltage
V RT
RRT = 40kΩ
0.76
0.8
0.84
V
Ramp Slope
V RAMP
RRT = 40kΩ
--
22
--
%/V
Soft Start Current
ISS1
Slew
12
16
20
μA
VID Change Current
ISS2
Slew
120
160
200
μA
--
1
--
Ω
--
1
--
Ω
Power Sequence
Current Sense Amplifier
Soft Start
Gate Driver
BOOT − PHASE = 8V
250mA Source Current
BOOT − PHASE = 8V
250mA Sink Current
UGATE Drive Source
RUGATEsr
UGATE Drive Sink
RUGATEsk
LGATE Drive Source
RLGATEsr
V LGATE = 8V
--
1
--
Ω
LGATE Drive Sink
RLGATEsk
250mA Sink Current
--
0.8
--
Ω
Over-Voltage Threshold
V OVP
Sweep FB Voltage, V FB − VEAP
125
150
175
mV
Over-Current Threshold
V OCP
Sweep IMAX Voltage, V IMAX − V ADJ
−10
0
10
mV
Protection
To be continued
www.richtek.com
16
DS8862-01 April 2011
RT8862
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
--
15
--
ns
--
10
--
ns
--
15
--
ns
--
10
--
ns
86.4
96
105.6
μA
VID7 to VID0 Rising,
VIDSEL Rising
--
1/2VTT +
12.5mV
--
V
VID7 to VID0 Hysteresis
VID7 to 0_Hy VID7 to VID0 Falling
--
25
--
mV
PSI Rising Threshold
VPSI
--
1/2VTT +
12.5mV
--
V
Dynamic Characteristic
UGATE Rise Time
trUGATE
UGATE Fall Time
t fUGATE
LGATE Rise Time
t rLGATE
LGATE Fall Time
t fLGATE
Current Sourcing from PS
Ips
pin to Set Vps2
Ciss = 3000p
When Vps2 Is Needed by Control
Circuit
Input Threshold
VID7 to VID0,
VID7 to 0,
VIDSEL Rising Threshold VIDSEL
PSI Rising
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of
JEDEC 51-7 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. The maximum output voltage of power monitor will be restricted by EN/VTT pin input voltage.
Note 6. Test condition : RT8862 normal operating, an extra static DC current load 10mA applying at VCC5 pin.
DS8862-01 April 2011
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17
RT8862
Typical Operating Characteristics
Power On from EN/VTT
VOUT
(1V/Div)
Power Off from EN/VTT
VOUT
(1V/Div)
EN/VTT
(1V/Div)
EN/VTT
(1V/Div)
PWRGD
(1V/Div)
PWRGD
(1V/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
VID = 1.4V, ILOAD = 5A
Time (1ms/Div)
Time (400μs/Div)
Dynamic VID Up
Dynamic VID Down
VOUT
(500mV/Div)
VOUT
(500mV/Div)
VID1
(1V/Div)
VID1
(1V/Div)
Time (100μs/Div)
Time (100μs/Div)
Load Transient Response
Load Transient Response
1.3V ->
100A
35A
1.3V ->
ILOAD
VID = 1.4V, fLoad = 200Hz, ILOAD = 35A to 100A
Time (100μs/Div)
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18
VID from 1.4V down to 0.8V, ILOAD = 85A
VOUT
(20mV/Div)
VOUT
(20mV/Div)
VID from 0.8V up to 1.4V, ILOAD = 85A
ILOAD
VID = 1.4V, ILOAD = 5A
100A
35A
VID = 1.4V, fLoad = 200Hz, ILOAD = 100A to 35A
Time (100μs/Div)
DS8862-01 April 2011
RT8862
Over Current Protection
Over Voltage Protection
VOUT
(1V/Div)
PWRGD
(1V/Div)
FB
(1V/Div)
PWRGD
(1V/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
ILOAD
(100A/Div)
LGATE
(10V/Div)
Time (200μs/Div)
Time (40μs/Div)
Thermal Monitoring
Current Monitor Output Voltage (V)
Current Monitor Output Voltage vs. Load Current
1.0
0.8
TSEN
(2V/Div)
0.6
VRHOT
(1V/Div)
0.4
0.2
TSEN from 0V sweep to 5V, ILOAD = 0A
0.0
0
22
44
66
88
110
Time (500μs/Div)
Load Current (A)
DS8862-01 April 2011
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19
RT8862
Application Information
Power Ready Detection
During start-up, the RT8862 will detect VCC12, VCC5 and
VTT. When VCC12 > 9.6V, VCC5 > 4.6V and VTT > 0.85V,
POR will go high. POR (Power On Reset) is the internal
signal to indicate all powers are ready to let the RT8862
and the companioned MOSFET drivers work properly.
When POR = L, the RT8862 will try to turn off both high
side and low side MOSFETs.
VCC12
9.6V
VCC5
+
+
4.6V
V TT
+
0.85V
1000
600
400
0
0
40
80
120
160
200
240
280
RRT (k
ohm)
(kΩ)
Figure 2. RRT vs Phase Switching Frequency
CMP
POR
CMP
800
200
CMP
-
Frequency vs. RRT
1200
Frequency (kHz)
The RT8862 is a 4/3/2/1-phase synchronous buck DC/DC
converter with 2 embedded MOSFET drivers. The internal
VID DAC is designed to interface with the Intel VR11.x/
10.x and AMD K8/K8_M2 compatible CPUs.
POR : Power On Reset
-
Soft Start
Output current of OPSS (ISS) is limited and variant
V DAC
OPSS
+
-
SSQ
Figure 1. Circuit for Power Ready Detection
SS
Phase Detection
The number of operational phases is determined by the
internal circuitry that monitors the ISNn voltages during
start up. Normally, the RT8862 operates as a 4-phase
PWM controller. Pull ISN4 and ISP4 to VCC5 programs
3-phase operation. Pull ISN3 and ISP3 to VCC5 programs
2-phase operation. The RT8862 detects the voltage of
ISN4 and ISN3 POR rising edge. At the rising edge, the
RT8862 detects whether the voltage of ISN4 and ISN3 are
higher than “VCC5 − 1V” respectively to decide how many
phases should be active. Phase detection is only active
during start up. When POR = H, the number of operational
phases is determined and latched. The unused PWM pins
can be connected either to 5V, GND or left floating.
C SS
EAP
(ErrorAmp positive input)
+ADJ
R ADJ
NTC
Figure 4. Circuit for Soft Start and Dynamic VID
The VOUT start-up time is set by a capacitor from the SS
pin to GND. In power_on_reset state (POR = L), the SS
pin is held at GND. After power_on_reset stae (POR = H)
and an extra delay of 1600μs, VSS and VSSQ begin to rise
till VSSQ = VBOOT. When VSSQ = VBOOT, the RT8862 stays
in this state for 800μs, waiting for valid VID code sent by
CPU. After receiving valid VID code, VOUT continues
ramping up or down to the voltage specified by VID code.
Before PWRGD = H, output current of OPSS (ISS) is
limited to μA (ISS1). When PWRGD = H, ISS is limited to
80μA (ISS2). The soft start waveform is shown in Figure 5.
Phase Switching Frequency
The phase switching frequency of the RT8862 is set by
an external resistor connected from the RT pin to GND.
The frequency follows the graph in Figure 2.
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20
DS8862-01 April 2011
RT8862
Output Voltage Differential Sensing
V TT
0.85V
VCC12
VCC5
9.6V
The RT8862 uses differential sensing by a high gain low
offset Error Amplifier. The CPU voltage is sensed between
4.6V
the FB and FBRTN pins. A resistor (RFB) connects FB pin
V DAC
SS
SSQ
V BOOT
SS
SSQ
T1
PWRGD
T2
T3
T4
and the positive remote sense pin of the CPU (VCCP).
FBRTN pin connects to the negative remote sense pin of
CPU (VCCN) directly. The Error Amplifier compares EAP
(= VDAC −VADJ) with the VFB to regulate the output voltage.
T5
No Load Offset
Figure 5. Soft Start Waveforms
VOUT will trace VEAP which is equal to “VSSQ − VADJ”.
VADJ is a small voltage signal which is proportional to
IOUT. This voltage is used to generate loadline and will be
described later. T1 is the delay time from power_on_reset
state to the beginning of VOUT rising.
T1 = 1600μs + 0.6V x CSS / ISS1
(1)
T2 is the soft start time from VOUT = 0 to VOUT = VBOOT.
T2 = VBOOT x CSS / ISS1
(2)
T3 is the dwelling time for VOUT = VBOOT. T3 = 800us.
T4 is the soft start time from VOUT = VBOOT to VOUT = VDAC.
T4 ~= |VDAC - VBOOT| x CSS/ISS1
(3)
T5 is the power good delay time, T5 ~= 1600μs.
Dynamic VID
The RT8862 can accept VID input changing while the
controller is running. This allows the output voltage (VOUT)
to change while the DC/DC converter is running and
supplying current to the load. This is commonly referred
to as VID on-the-fly (OTF). A VID OTF can occur under
either light or heavy load conditions. The CPU changes
the VID inputs in multiple steps from the start code to the
finish code. This change can be positive or negative.
Theoretically, VOUT should follow VDAC which is a staircase
waveform. In RT8862, as mentioned in soft start session,
VDAC slew rate is limited by ISS2/CSS when PWRGD = H.
This slew rate limiter works as a low pass filter of VDAC
and makes the bandwidth of VDAC waveform finite. By
smoothening VDAC staircase waveform, VOUT will no longer
overshoot or undershoot. On the other hand, CSS will
increase the settling time of VOUT during VID OTF. In most
cases, 1nF to 30nF ceramic capacitor is suitable for CSS.
DS8862-01 April 2011
In Figure 6, IOFSN or IOFSP are used to generate no-load
offset. Either IOFSN or IOFSP is active during normal operation.
It should be noted that users can only enable one polarity
of no-load offset. Do not connect OFS pin to GND and to
VCC5 at the same time. Connect a resistor from OFS pin
to GND to activate IOFSN. IOFSN flows through RADJ from
ADJ pin to GND. In this case, negative no-load offset voltage
(VOFSN) is generated.
VOFSN = IOFSN x RADJ = 0.8 x RADJ/ROFS
(4)
Connect a resistor from OFS pin to VCC5 to activate IOFSP.
IOFSP flows through RFB from the VCCP to FB pin. In this
case, positive no-load offset voltage (VOFSP) is generated.
When OFS pin is connected to VCC5 through a resistor,
the positive no-load offset can be calculated as :
VOFSP = IOFSP × RFB = 6.4 ×
RFB
ROFS
(5)
The RT8862 provides wide range no-load positive offset
for over-clocking applications. The IOFSP capability can
supply from 30μA to 640μA, which means in Equation
(5), ROFS can range from 240kΩ to 10kΩ. Other resistances
of ROFS exceeding this range can also provide no-load
positive offset but cannot be guaranteed by Equation (5).
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21
RT8862
C2
C FB
R FB
VCCP
(Positive remote
sense pin of CPU)
(Negative remote
sense pin of CPU)
VCCN
L/DCR = RS x CS
C1
R1
FB
+EAP
EA
+
COMP
-
FBRTN
Then the output current of CSA will follow the equation
below :
IX = [IL x DCR − VOFS-CSA + 235n x (RCSP − RCSN)]
IOFSP
+
V DAC
(6)
IOFSN
R ADJ
ADJ
Figure 6. Circuit for VOUT Differential Sensing and No
Load Offset
/RCSN
(7)
235nA is typical value of CSA input offset current.
VOFS-CSA is the input offset voltage of CSA. VOFS-CSA of
RT8862 is smaller than +/- 1mV. Usually, “VOFS-CSA +
235n x (RCSP − RCSN)” is negligible except at very light
load and the equation can be simplified as the equation
below :
IX = IL x DCR/RCSN
(8)
Loadline
Load Transient Quick Response
The RT8862 utilizes a new quick response feature to supply
heavy load current demand during instantaneous load
application transient. The RT8862 detects load transient
and reacts via VOUT pin. When VOUT drops during load
application transient,the quick response comparator will
send asserted signals to turn on high side MOSFETs and
turn off low side MOSFETs. The QR signal will turn on all
phase's high side MOSFETs while turning off low side
MOSFETs also. Therefore, the influence of total quick
response function of RT8862 is adjustable, and the
magnitude of quick response is flexible via fine-tuning the
resistor connected to QR1 or QR2 pin.
ΣIX[n] is a PTC (Positive Temperature Coefficient) current,
an NTC (Negative Temperature Coefficient) resistor is
needed to connect ADJ pin to GND. If the NTC resistor is
properly selected to compensate the temperature
coefficient of IX[n], the voltage on ADJ pin will be
proportional to IOUT without temperature effect. In the
RT8862, the positive input of Error Amplifier is “VDAC −
VADJ”. VOUT will follow “VDAC − VADJ”, too. Thus, the
output voltage decreasing linearly with IOUT is obtained.
The loadline is defined as
LL(loadline) = ΔVOUT/ΔIOUT = ΔVADJ/ΔIOUT
= 0.5 x DCR x RADJ/RCSN
IOUT
(9)
Briefly, the resistance of RADJ sets the resistance of
loadline. The temperature coefficient of RADJ compensates
the temperature effect of loadline.
V OUT
QR
Current Balance
Figure 7
Output Current Sensing
The RT8862 provides low input offset current-sense
amplifier (CSA) to monitor the output current of every
phase. Output current of CSA (IX[n]) is used for phase
current balance and active voltage position. In this inductor
current sensing topology, RS and CS must be set according
to the equation below :
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22
Output current of CSA is summed and averaged in the
RT8862. Then 0.5Σ(IX[n]) is sent to ADJ pin. Because
In Figure 8, IX[n] is the current signal which is proportional
to current flowing through phase n. In Figure 9, the current
error signals IERRn (= IX[n] − AVG(IX[n])) are used to raise
or lower the internal sawtooth waveforms (RAMP[1] to
RAMP[n]) which are compared with Error Amplifier output
(COMP) to generate PWM signal. The raised sawtooth
waveform will decrease the PWM duty of the corresponding
phase while the lowered will increase. Eventually, current
flowing through each phase will be balanced.
DS8862-01 April 2011
RT8862
CSA: Current Sense Amplifier
V OFS_CSA
IX
ISP
+
235nA
DCR
RS
CS
I1
I2
R ISP
IOUT , total
+
-
ISN
-
235nA
L
Constant ratio
R ISN
I1
I2
Figure 8. Circuit for Phase Current Sensing
IOUT , total
COMP
Constant difference
RAMP[1]
Interleaved
RAMP[n]
+
-
+
CMP
-
BUF
PWM[1]
Over Current Protection (OCP)
IERR[1] x RCB
+
-
Figure 10. Phase Current vs. Total Current
+
CMP
-
BUF
PWM[n]
IERR[n] x RCB
Figure 9. Circuit for Phase Current Balance
RT8862 provides single phase OCP and multi-phase OCP
according to the operation condition. In Figure 11, single
phase OCP (IMAXPSI) and multi-phase OCP (IMAX)
thresholds can be set by external resistors :
R2 + R3
R1 + R2 + R3
R3
VIMAXPSI = VCC5 ×
R1 + R2 + R3
VIMAX = VCC5 ×
Adjusting Phase Current
If phase current is not balanced due to asymmetric PCB
layout of power stage, external resistors can be adjusted
to correct current imbalance. Figure 10 shows two types
of current imbalance, constant ratio type and constant
difference type.
If the initial current distribution is constant ratio type,
according to Equation (8), reduce RCSN[1] can reduce IL[1]
and improve current balance. If the initial current distribution
is constant difference type, according to Equation (7),
increase RCSP[1] can reduce IL[1] and improve current
balance.
DS8862-01 April 2011
(10)
(11)
Once VADJ is larger than the negative input of CP
comparator, OCP will be triggered and latched, and RT8862
will turn off both high side and low side MOSFETs of all
phases. A 20us delay after OCP detection is used to
prevent false trigger.
Over Voltage Protectiom (OVP)
The over voltage protection monitors the output voltage
via the FB pin. Once VFB exceeds “VEAP + 150mV”, OVP
is triggered and latched. RT8862 will try to turn on low
side MOSFET and turn off high side MOSFET to protect
CPU. A 20us delay is used in OVP detection circuit to
prevent false trigger.
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23
RT8862
V CC5
VCC5
0.28 x V CC5
R1
R1
TSEN
IMAX
-
R2
IMAXPSI
+
-
S
Q
VRHOT
R
0.33 x V CC5
R3
Figure 13. Thermal Monitoring
ADJ
Power State Indicator (PSI)
Figure 11. Over Current Protection
Output Current Monitoring (IMON)
The RT8862 senses load current and output a voltage
signal to indicate the instantaneous load current status.
Since the sensed total current is injected into the resistors
connected to ADJ pin, ADJ voltage than is used for IMON
function as shown in Figure 12. Through the resistor
network R1, R2 and R3, IMON voltage will be proportional
to ADJ pin voltage according to the Equation :
VIMON =
+
R NTC
OCP
+
R3
× VADJ − R3 × VTT
R1 // R2 // R3
R1
(12)
VCC5/VTT
ADJ
IMONFB
+
-
R3
R1
VTT
R2
IMON
Figure 12. Output Current Monitoring
Thermal Monitoring (VRHOT)
The RT8862 provides thermal monitoring function via
sensing TSEN pin voltage. Through the voltage divider R1
and RNTC, the voltage of TSEN is typically set to be higher
than 0.33 x VCC5 when ambient temperature is lower than
VRHOT assertion target. When ambient temperature rises,
TSEN voltage will fall, and VRHOT signal will be set to
high if TSEN voltage drops below 0.28 x V CC5 .
Accordingly, VRHOT will be reset to low once TSEN
voltage rises above 0.33 x VCC5. Correctly choose the
resistance of R1 and RNTC can assert and de-assert VRHOT
accurately at target ambient temperature.
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24
The RT8862 supports PSI# function for VR11.1 CPUs and
platform users. The RT8862 will monitor PSI pin input
voltage to change the operating state. When PSI is high
(higher than 1/2 VTT + 12.5mV), the RT8862 operates as
a full-phase interleaving PWM controller and all phases
are active. When input voltage is low (lower than VTT +
12.5mV), the RT8862 will change to single phase operation
mode and only phase 1 is active. Since phase 2 includes
embedded driver, the RT8862 will automatically disable
phase 2 by forcing UGATE2 and LGATE2 into high
impedance state when input voltage is low. The RT8862
will also disable phase 3 and phase 4 by sending
continuous tri-state signals (~2.5V) from PWM3 and
PWM4 to external drivers when input voltage is low.
Therefore, 2 external drivers which support tri-state
shutdown should be used if PSI function is considered,
and the RT9619 is recommended to be the external drivers
for VR11.1 compatibility.
During PSI asserted period, e.g., input voltage is low, if
the RT8862 receives dynamic VID change command, the
RT8862 will enter interleaving mode operation and all
phases will be activated. PSI command will be ignored
during dynamic VID operation, and PSI will be blanked for
about 100us after dynamic VID change is completed.
Dynamic Phase Control
RT8862 has the ability of automatically control phase
numbers according to the total load current. This feature
optimizes system efficiency over a wide load range.
Connect a resistive voltage divider to PS pin to define the
two thresholds, VPS1 and VPS2, for the dynamic phase
control. Because the IMON pin voltage (VIMON) represents
the total current, the controller compares PS pin voltage
(VPS1 and VPS2) with VIMON to decide the number of
operating phase. See Table 1 for the dynamic phase control
mechanism.
DS8862-01 April 2011
RT8862
Table 1
For example, if VPS2 is designed as 1V and the hysteresis
Operating phases
Max.
Max.
Max.
phase=4 phase=3 phase=2
4-phase
3-phase
2-phase
< VIMON < VIMON
operation operation operation
3-phase
2-phase
2-phase
< VIMON > VIMON
operation operation operation
2-phase
1-phase
1-phase
> VIMON > VIMON
operation operation operation
is 0.25V, the down phase operation can only take place
when VIMON is continuously lower than 0.75V for 6.82ms
(if switching frequency is 300kHz).
V PS1
V PS2
Note that ,if RT8862 received a QR command it will change
to maximum phase interleaving operation. Howerve,if PSI
signal assert, the RT8862 will down to single phase
operation directly, although VIMON is higher than VPS .
If Max. Phase number = 3, it means phase 4 is disabled
by pulling ISN4 to 5V before power up. If Max. phase
number = 2, it means phase 4 and phase 3 are disabled
by pulling ISN4 and ISN3 to 5V before power up.
Setting Dynamic Phase Control Threshold (VPS1,
VPS2)
The IMON pin voltage of RT8862 is clamped below VCC5.
Users can get more design flexibility to implement auto
phase control feature by higher IMON voltage. Note that
the linearity of IMON can be guaranteed when VIMON <
2.5V. A 1μF bypass capacitor connected to a clean ground
is necessary at IMON pin.
divider R1 and R2. But VPS2 is defined by IPS, R1 and R2
altogether. The calculation is listed in Figure 14.
Further more, the RT8862 utilizes true interleaving during
auto phase shedding process. i.e. 4-phase : 90°, 3-phase
: 120°, and 2-phase : 180°. By doing so, ripple uniformity
is guaranteed in steady state.
VPS1 and VPS2 can be set by the PS pin resistors.
In Figure 14, VPS1 is defined only by the resistive voltage
To decide the value of R1 and R2,, one must choose the
target threshold current for auto down phase, calculate
VPS1 and VPS2, and then use the equations in Figure 14 to
calculate R1 and R2.. The calculation is very easy. An
example is provided as follows :
A bypass capacitor is recommended at PS pin. But the
capacitor must be smaller than 200pF to keep the circuit
in normal function.
R1
5α
R1
=
,α=
R1+R2
1+α
R2
R1
=5x
+ IPS x (R1//R2)
R1+R2
R1R2
= VPS1 + IPS x
R1+R2
IPSR1
= VPS1 +
α+1
IPSR1
- VPS1 =
α+1
VPS1 = 5 x
Dynamic Phase Control Principles
The RT8862 change to higher number of phase operation
when VIMON is higher than VPS1 or VPS2. No hysteresis and
extra delay exists during an up phase decision.
However, hysteresis (VHYS) and delay exist during a down
phase decision. RT8862 triggers a timer when VIMON is
lower than (VPS1- VHYS) or (VPS2-VHYS), and persisted a
certain amount of time, the controller goes to lower phase
number operation.
The timer is designed as long as 2047 switching cycles.
Therefore, if the switching frequency is chosen at 300kHz,
the timer is about 2047x(1/300kHz) = 6.82ms.
The V HYS value is always proportional to V PS. i.e.
6
VHYS =k x VPS. Where k =
when 2 phases operation
20
down to 1 phase, and k = 4 for all other cases.
20
When quick response is triggered, the RT8862 goes back
to full-phase operation immediately.
VCC
5V
IPS
VPS2
R2
PS Pin
R1
RT8862
VPS2
Figure 14. VPS1 and VPS2 Setting and Equations
Design example :
1. Derive VIMAX vs. total current relationship :
Assume we have a platform with VIMAX = 1V represents
maximum current = 100A, so 10mV represents 1A can be
drived.
2. To set first threshold to 32A,
VPS1 = 0.01 x 32 = 0.32 (V) , VPS1 =
5α
⇒ α = 0.068
1+α
3. To set second threshold to 48A,
VPS2 = 0.01× 48 = 0.48 (V), VPS2 − VPS1 = 0.16 (V)
=
IPS × R1 96μ A × R1
=
⇒ R1 = 1.78kΩ
α+1
α+1
4. R2 = R1/α = 26.176kΩ
DS8862-01 April 2011
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25
RT8862
C2
Loop Compensation
The RT8862 is a synchronous Buck converter with two
control loops : voltage loop and current balance loop. Since
the function of the current balance loop is to maintain the
current balance between each active phase, its influence
to converter stability will be negligible compared with the
voltage feedback loop. Therefore, to compensate the
voltage loop will be the main task to maintain converter
stability.
The converter duty-to-output transfer function Gd is :
Gd =
1+
S
R L
C
+
(13)
S2
⎛ 1 ⎞
⎜
⎟
⎝ LC ⎠
2
(15)
Where A denotes as compensation gain. To compensate
a typical voltage mode buck converter, there are two
ordinary compensation schemes, well known as type-II
compensator and type-III compensator. The choice of using
type-II or type-III compensator will be up to platform
designers, and the main concern will be the position of
the capacitor ESR zero and mid-frequency to highfrequency gain boost. Typically, the ESR zero of output
capacitor will tend to stabilize the effect of output LC double
poles, hence the positon of the output capacitor ESR zero
in frequency domain may influence the design of voltage
loop compensation. If FZERO,ESR is <1/2FCO where FCO
denotes cross-over frequency, type-II compensation will
be sufficient for voltage stability. If FZERO,ESR is > 1/2FCO
(or higher gain and phase margin is required at midfrequency to high-frequency), then type-III compensation
may be a better solution for voltage loop compensation.
A typical type-II compensation network is shown in
Figure 15.
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26
EA
+
Figure 15. Type-II Compensation
R1 can be determined independently from DC
considerations. Normally choose R1 that the current
passing by will be around 1mA. Therefore,
VREF
1mA
(16)
Then determine R2 by the boosted gain of loop gain at
(14)
Where VOUT is the output voltage of the converter, R is
the loading resistance, L and C are the output inductance
and capacitance, and VP is the peak-to-peak voltage of
ramp applied at modulator input. The overall loop gain after
compensation can be described as :
Loop Gain = T = Gd x Fm x A
C1
+ V REF
-
R1 =
and the modulator gain of the converter is :
Fm = 1
VP
R1
crossover :
R2 = R1×
VP
2
VIN(MAX)
⎛ FZERO, ESR ⎞
FCO
×⎜
×
⎟
F
F
LC
ZERO, ESR
⎝
⎠
(17)
Where VIN(MAX) is the max input voltage of power stage,
VP is the peak-to-peak voltage of ramp applied at modulator
input, FZERO,ESR is the frequency of output capacitor ESR
zero, and FLC is the frequency of output LC :
FZERO, ESR =
FLC =
1
2π × RESR × C
(18)
1
2π × LC
(19)
After determining the phase margin at crossover
frequency, the position of zero and pole produced by
type-II compensation network, FZ and FP, can then be
determined. The bode plot of type-II compensation is
shown in Figure15, where
Gain (dB)
VIN
R2
FZ
FP
Frequency (Hz)
Figure 16. Bode Plot of Type-II Compensation
DS8862-01 April 2011
RT8862
1
2π × R2 × C1
1
FP =
2π × R2 × (C1 // C2)
FZ =
(20)
(21)
FZ can be determined by the following Equation :
⎞ − tan-1 ⎛ FZ ⎞ ≥ 90D
⎟
⎜F ⎟
⎠
⎝ CO ⎠
⎛
⎞
FCO
+P.M. − tan-1 ⎜
⎟
F
ZERO,
ESR
⎝
⎠
F
F
tan-1 ⎛⎜ CO ⎞⎟ − tan-1 ⎛⎜ Z ⎞⎟ ≥ P.M. + 45 D
2
⎝ FZ ⎠
⎝ FCO ⎠
and
F
tan-1 ⎛⎜ CO
⎝ FZ
(22)
By properly choosing FZ to fit equation (22), C1 can then
be determined by :
1
C1 =
2π × R2 × FZ
(23)
and C2 can be determined by :
C2 =
C2
C3
R2
R1
(26)
R2 can be determined by the following Equation :
2
F
F
× ⎛ CO ⎞ × Z
VIN(MAX) ⎜⎝ FLC ⎟⎠ FCO
VP
(27)
Other component values of the Type-III compensation can
then be calculated as :
1
2π × R2 × FZ
1
C2 =
C1 =
2π × R2 × FP − 1
C1
1
C3 =
2π × R1× FZ
1
R3 =
2π × C3 × FP
(28)
(29)
(30)
(31)
C1
EA
+
+ V REF
-
Figure 17. Type-III Compensation
F P = F P1 = F P2
Gain (dB)
FCO 2
FZ
(25)
FZ and FP can be determined by choosing proper FCO to
FZ ratio to meet Equation (25). Again, R1 can be determined
by the Equation (16).
(24)
A typical type-III compensation contains two zeros and
two poles where the extra one zero and one pole compared
with type-II compensation are added for stabilizing the
system when ESR zero is relatively far from LC double
poles in frequency domain. Figure16. and Figure.17 shows
the typical circuit and bode plot of the type-III compensation.
F Z = F Z1 = F Z2
Frequency (Hz)
Figure 18. Bode Plot of the Type-III Compensation
DS8862-01 April 2011
FP =
R2 = R1×
1
F2CO
− 1
2π × R2 ×
FZ
C1
R3
In typical application, the FZ2 and FP2 are usually
designed closed FZ1 and FP1 respectively so, the following
equation can be derived, after determining desired phase
margin, according to the following Equation :
Thermal Considerations
For continuous operation, do not exceed absolute
maximum operation junction temperature. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
PD(MAX) = ( TJ(MAX) − TA ) / θJA
Where T J(MAX) is the maximum operation junction
temperature, TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT8862, The maximum junction temperature is 125°C.
The junction to ambient thermal resistance θJA is layout
dependent. For WQFN-48L 7x7 packages, the thermal
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27
RT8862
resistance θJA is 34°C/W on the standard JEDEC 51-7
four layers thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by following
formula :
PD(MAX) = (125°C − 25°C) / (34°C/W) = 2.941W for
WQFN-48L 7x7
close to high side MOSFETs, and boot to phase damping
resistors have to be close to high side MOSFETs and
phase planes. Also keep the traces of these snubbers
circuits as short as possible.
`
The area of VIN plane (power stage 12V VIN) and VOUT
plane (output bulk capacitors and inductors connection
plane) have to be as wide as possible. Long traces or
thin bars must be avoided in these planes. The plane
trace width must be wide enough to carry large input/
output current (40mil/A).
`
The following traces have to be wide and short : UGATE,
LGATE, BOOT, PHASE, and VCC12. Make sure the
width of these traces are wide enough to carry large
driving current(at least 40mil).
`
The voltage feedback loop contains two traces, VCC
and VSS, which are Kelvin sensed from CPU socket or
output capacitors. These two traces are suggested above
10mil width and put away from high (di/dt) switching
elements such as high side MOSFETs, low side
MOSFETs, phase plane etc. The circuit elements of
voltage feedback loop, such as feedback loop short
resistors and voltage loop compensation RCs, have to
be kept near the RT8862 and also away from switching
elements.
`
The current sense mechanism of the RT8862 is fully
differential Kelvin sense. Therefore, the current sense
loops of the RT8862 contain two traces : the positive
traces(ISP1 to ISP4) come from the positive node of
output inductors(the node connecting phase plane) and
the negative traces (ISN1 to ISN4) come from the
negative node of output inductors(the node connecting
output plane).
The maximum power dissipation depends on operating
ambient temperature for fixed T J(MAX) and thermal
Maximum Power Dissipation (W)
resistance θJA. For RT8862 package, the Figure 19 of
derating curves allows the designer to see the effect of
rising ambient temperature on the maximum power
dissipation allowed.
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Four Layers PCB
WQFN-48L 7x7
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 19. Derating Curves for RT8862 Packages
Layout Considerations
For best performance of the RT8862, the following
guidelines must be strictly followed :
`
Input bulk capacitors and MLCCs have to be put near
high side MOSFETs. The connection plane of input
capacitors and high side MOSFETs then can be kept as
square as possible.
`
The shape of phase planes (the connection plane
between high side MOSFETs, low side MOSFETs and
output inductors) have to be as square as possible. Long
traces, thin bars or separated islands must be avoided
in phase planes.
`
Keep snubber circuits or damping elements near its
objects. Phase RC snubbers have to be close to low
side MOSFETs, UGATE damping resistors have to be
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28
DO NOT connect the current sense traces from phase
plane or output plane. Only connect these traces from
both sides of output inductors can achieve the goal of
precise Kelvin sense. The current sense feedback loops
have to be routed away from switching elements, and
the current sense RC elements have to be put near
their respective ISN or ISP pins of the RT8862 and also
away from noise switching elements. At lease 10 mil
width is suggested for current sense feedback loops.
DS8862-01 April 2011
RT8862
Outline Dimension
2
1
2
1
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.200
0.300
0.008
0.012
D
6.950
7.050
0.274
0.278
D2
5.050
5.250
0.199
0.207
E
6.950
7.050
0.274
0.278
E2
5.050
5.250
0.199
0.207
e
L
0.500
0.350
0.020
0.450
0.014
0.018
W-Type 48L QFN 7x7 Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
DS8862-01 April 2011
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29