IS62WV2568ALL IS62WV2568BLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES • High-speed access time: 45ns, 55ns, 70ns • CMOS low power operation – 36 mW (typical) operating – 9 µW (typical) CMOS standby • TTL compatible interface levels JANUARY 2013 DESCRIPTION The ISSI IS62WV2568ALL / IS62WV2568BLL are high- speed, 2M bit static RAMs organized as 256K words by 8 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is LOW (deselected) , the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. • Single power supply – 1.65V--2.2V Vcc (62WV2568ALL) – 2.5V--3.6V Vcc (62WV2568BLL) • Fully static operation: no clock or refresh required • Three state outputs • Industrial temperature available Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62WV2568ALL and IS62WV2568BLL are packaged in the JEDEC standard 32-pin TSOP (TYPE I), sTSOP (TYPE I), and 36-pin mini BGA. • Lead-free available FUNCTIONAL BLOCK DIAGRAM A0-A17 DECODER 256K x 8 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VCC GND I/O0-I/O7 CS2 CS1 OE CONTROL CIRCUIT WE Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1 Rev. I 1/10/13 IS62WV2568ALL, IS62WV2568BLL PIN DESCRIPTIONS A0-A17 Address Inputs CS1 Chip Enable 1 Input CS2 Chip Enable 2 Input OE Output Enable Input WE Write Enable Input I/O0-I/O7Input/Output NC No Connection Vcc Power GND Ground PIN CONFIGURATION 36-pin mini BGA (B) (6mm x 8mm) 1 2 2 3 4 5 32-pin TSOP (TYPE I), sTSOP (TYPE I) 6 A A0 A1 CS2 A3 A6 A8 B I/O4 A2 WE A4 A7 I/O0 C I/O5 NC A5 D GND Vcc E Vcc GND F I/O6 G I/O7 H A9 I/O1 NC A17 I/O2 OE CS1 A16 A15 I/O3 A10 A11 A12 A13 A14 A11 A9 A8 A13 WE CS2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 Integrated Silicon Solution, Inc. — www.issi.com Rev. I 1/10/13 IS62WV2568ALL, IS62WV2568BLL ABSOLUTE MAXIMUM RATINGS(1) Symbol Vterm Tstg Pt Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation Value –0.2 to Vcc+0.3 –65 to +150 1.0 Unit V °C W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE (Vcc) Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C IS62WV2568ALL 1.65V - 2.2V 1.65V - 2.2V IS62WV2568BLL 2.5V - 3.6V 2.5V - 3.6V DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Vcc Voh Output HIGH Voltage Ioh = -0.1 mA 1.65-2.2V Ioh = -1 mA 2.5-3.6V Vol Output LOW Voltage Iol = 0.1 mA 1.65-2.2V Iol = 2.1 mA 2.5-3.6V Vih Input HIGH Voltage 1.65-2.2V 2.5-3.6V (1) Vil Input LOW Voltage 1.65-2.2V 2.5-3.6V Ili Input Leakage GND ≤ Vin ≤ Vcc Ilo Output Leakage GND ≤ Vout ≤ Vcc, Outputs Disabled Min. Max. Unit 1.4 — V 2.2 — V — 0.2 V — 0.4 V 1.4 Vcc + 0.2 V 2.2 Vcc + 0.3 V –0.2 0.4 V –0.2 0.6 V –11µA –1 1 µA Notes: 1. Undershoot: -1.0V for pulse width less than 10ns. Not 100% tested. 2. Overshoot: Vdd + 1.0V for pulse width less than 10ns. Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com3 Rev. I 1/10/13 IS62WV2568ALL, IS62WV2568BLL CAPACITANCE(1) Symbol Cin Cout Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 8 10 Unit pF pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter 62WV2568ALL (Unit) 62WV2568BLL (Unit) 0.4V to Vcc-0.2V 5 ns Vref 0.4V to Vcc-0.3V 5ns Vref See Figures 1 and 2 See Figures 1 and 2 Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load R1(Ω) R2(Ω) Vref Vtm 1.65-2.2V 3070 3150 0.9V 1.8V 2.5V - 3.6V 3070 3150 1.5V 2.8V AC TEST LOADS R1 R1 VTM VTM OUTPUT OUTPUT 30 pF Including jig and scope Figure 1 4 5 pF Including jig and scope R2 R2 Figure 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. I 1/10/13 IS62WV2568ALL, IS62WV2568BLL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) 62WV2568ALL (1.65V - 2.2V) Symbol Parameter Test Conditions Max. Unit 70ns Icc Vcc Dynamic Operating Vcc = Max., Com. 15 mA Supply Current Iout = 0 mA, f = fmax Ind. 15 Icc1 Operating Supply Vcc = Max., Com. 3 mA Current Iout = 0 mA, f = 0 Ind. 3 Isb1 TTL Standby Current Vcc = Max., Com. 0.3 mA (TTL Inputs) Vin = Vih or Vil Ind. 0.3 CS1 = Vih , CS2 = Vil, f = 1 MHz Isb2 CMOS Standby Current (CMOS Inputs) Vcc = Max., Com. CS1 ≥ Vcc – 0.2V, Ind. CS2 ≤ 0.2V, Vin ≥ Vcc – 0.2V, or Vin ≤ 0.2V, f = 0 5 µA 10 Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) 62WV2568BLL (2.5V - 3.6V) Symbol Parameter Test Conditions Max.Max.Max. Unit 45ns55ns70ns Icc Vcc Dynamic Operating Vcc = Max., Com. 35 30 25 mA Supply Current Iout = 0 mA, f = fmax Ind. 40 35 30 Isb1 TTL Standby Current Vcc = Max., Com. 0.3 0.3 0.3 mA (TTL Inputs) Vin = Vih or Vil Ind.0.3 0.3 0.3 CS1 = Vih , CS2 = Vil, f = 1 MHz Isb2 CMOS Standby Current (CMOS Inputs) Vcc = Max., Com. CS1 ≥ Vcc – 0.2V, Ind. CS2 ≤ 0.2V, Vin ≥ Vcc – 0.2V, or Vin ≤ 0.2V, f = 0 10 10 10 10 10 10 µA Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. Integrated Silicon Solution, Inc. — www.issi.com Rev. I 1/10/13 5 IS62WV2568ALL, IS62WV2568BLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) 45ns 55ns 70ns Symbol Parameter Min. Max. Min. Max. Min. Max Unit trc Read Cycle Time 45 — 55 — 70 — ns taa Address Access Time — 45 — 55 — 70 ns toha Output Hold Time 10 — 10 — 10 — ns tacs1/tacs2 CS1/CS2 Access Time — 45 — 55 — 70 ns tdoe OE Access Time — 20 — 25 — 35 ns thzoe(2) OE to High-Z Output — 15 — 20 — 25 ns tlzoe(2) OE to Low-Z Output 5 — 5 — 5 — ns thzcs1/thzcs2(2) CS1/CS2 to High-Z Output 0 15 0 20 0 25 ns tlzcs1/tlzcs2 CS1/CS2 to Low-Z Output 10 — 10 — 10 — ns (2) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4 to 1.4V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = Vil, CS2 = WE = Vih) tRC ADDRESS tAA tOHA DOUT 6 PREVIOUS DATA VALID tOHA DATA VALID Integrated Silicon Solution, Inc. — www.issi.com Rev. I 1/10/13 IS62WV2568ALL, IS62WV2568BLL AC WAVEFORMS READ CYCLE NO. 2(1,3)(CS1, CS2, OE Controlled) tRC ADDRESS tAA tOHA OE tDOE CS1 tHZOE tLZOE tACS1/tACS2 CS2 DOUT tLZCS1/ tLZCS2 HIGH-Z tHZCS DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1= Vil. CS2=WE=Vih. 3. Address is valid prior to or coincident with CS1 LOW and CS2 HIGH transition. Integrated Silicon Solution, Inc. — www.issi.com Rev. I 1/10/13 7 IS62WV2568ALL, IS62WV2568BLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) 45ns Symbol Parameter twc 55ns 70ns Min. Max. Min. Max. Min. Max Unit Write Cycle Time 45 — 55 — 70 — ns tscs1/tscs2 CS1/CS2 to Write End 35 — 45 — 60 — ns taw Address Setup Time to Write End 35 — 45 — 60 — ns tha Address Hold from Write End 0 — 0 — 0 — ns tsa Addrress Setup Time 0 — 0 — 0 — ns tpwe WE Pulse Width 35 — 40 — 50 — ns tsd Data Setup to Write End 20 — 25 — 30 — ns thd Data Hold from Write End 0 — 0 — 0 — ns thzwe WE LOW to High-Z Output — 20 — 20 — 20 ns tlzwe WE HIGH to Low-Z Output 5 — 5 — 5 — ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW) tWC ADDRESS tHA tSCS1 CS1 tSCS2 CS2 tAW tPWE WE tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN 8 tHD DATA-IN VALID Integrated Silicon Solution, Inc. — www.issi.com Rev. I 1/10/13 IS62WV2568ALL, IS62WV2568BLL AC WAVEFORMS WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 CS2 tAW tPWE WE tSA DOUT tHZWE tLZWE HIGH-Z DATA UNDEFINED tSD DIN tHD DATA-IN VALID WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 CS2 tAW tPWE WE tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN tHD DATA-IN VALID Integrated Silicon Solution, Inc. — www.issi.com9 Rev. I 1/10/13 IS62WV2568ALL, IS62WV2568BLL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Vdr Idr tsdr trdr Parameter Vcc for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform Vcc = 1.0V, CS1 ≥ Vcc – 0.2V See Data Retention Waveform See Data Retention Waveform Min. Max. Unit 1.0 3.6 V — 10 µA 0 — ns trc — ns DATA RETENTION WAVEFORM (CS1 Controlled) Data Retention Mode tSDR 3.0V 2.2V tRDR VCC VDR CS1 ≥ VCC CS1 GND - 0.2V DATA RETENTION WAVEFORM (CS2 Controlled) Data Retention Mode 3.0 VCC CS2 2.2V tSDR tRDR VDR 0.4V CS2 ≤ 0.2V GND 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. I 1/10/13 IS62WV2568ALL, IS62WV2568BLL ORDERING INFORMATION IS62WV2568ALL (1.65V - 2.2V) Commercial Range: 0°C to +70°C Speed (ns) 70 Order Part No. IS62WV2568ALL-70T Package TSOP, TYPE I, Industrial Range: –40°C to +85°C Speed (ns) 70 70 70 70 Order Part No. IS62WV2568ALL-70TI IS62WV2568ALL-70TLI IS62WV2568ALL-70BI IS62WV2568ALL-70BLI Package TSOP, TYPE I TSOP, TYPE I, Lead-free mini BGA (6mm x 8mm) mini BGA (6mm x 8mm), Lead-free 70 70 IS62WV2568ALL-70HI IS62WV2568ALL-70HLI sTSOP, TYPE I sTSOP, TYPE I, Lead-free IS62WV2568BLL (2.5V - 3.6V) Commercial Range: 0°C to +70°C Speed (ns) 70 70 70 Order Part No.Package IS62WV2568BLL-70T TSOP, TYPE I IS62WV2568BLL-70B mini BGA (6mm x 8mm) IS62WV2568BLL-70H sTSOP, TYPE I Industrial Range: –40°C to +85°C Speed (ns) 45 45 45 55 55 55 55 55 55 70 70 70 Order Part No. IS62WV2568BLL-45TLI IS62WV2568BLL-45BLI IS62WV2568BLL-45HLI IS62WV2568BLL-55TI IS62WV2568BLL-55TLI IS62WV2568BLL-55BI IS62WV2568BLL-55BLI IS62WV2568BLL-55HI IS62WV2568BLL-55HLI IS62WV2568BLL-70TI IS62WV2568BLL-70BI IS62WV2568BLL-70HI Package TSOP, TYPE I, Lead-free mini BGA (6mm x 8mm), Lead-free sTSOP, TYPE I TSOP, TYPE I TSOP, TYPE I, Lead-free mini BGA (6mm x 8mm) mini BGA (6mm x 8mm), Lead-free sTSOP, TYPE I sTSOP, TYPE I, Lead-free TSOP, TYPE I mini BGA (6mm x 8mm) sTSOP, TYPE I Integrated Silicon Solution, Inc. — www.issi.com11 Rev. I 1/10/13 IS62WV2568ALL, IS62WV2568BLL 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. I 1/10/13 IS62WV2568ALL, IS62WV2568BLL Integrated Silicon Solution, Inc. — www.issi.com13 Rev. I 1/10/13 14 Package Outline 08/12/2008 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : IS62WV2568ALL, IS62WV2568BLL Integrated Silicon Solution, Inc. — www.issi.com Rev. I 1/10/13