IS62WV25616ALL IS62WV25616BLL

IS62WV25616ALL
IS62WV25616BLL
256K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC SRAM
FEATURES
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•
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AUGUST 2014
DESCRIPTION
The ISSI IS62WV25616ALL/IS62WV25616BLL are high-
High-speed access time: 55ns, 70ns
CMOS low power operation
36 mW (typical) operating
9 µW (typical) CMOS standby
TTL compatible interface levels
Single power supply 1.65V--2.2V Vdd (IS62WV25616ALL)
2.5V--3.6V Vdd (IS62WV25616BLL)
Fully static operation: no clock or refresh
required
Three state outputs
Data control for upper and lower bytes
Industrial temperature available
Lead-free available
speed, low power, 4M bit SRAMs organized as 256K words
by 16 bits. It is fabricated using ISSI's high-performance
CMOS technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-performance
and low power consumption devices.
When CS1 is HIGH (deselected) or when CS1 is low and
both LB and UB are HIGH, the device assumes a standby
mode at which the power dissipation can be reduced down
with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs.The active LOW Write Enable (WE)
controls both writing and reading of the memory. A data byte
allows Upper Byte (UB) and Lower Byte (LB) access.
The IS62WV25616ALL/IS62WV25616BLL are packaged
in the JEDEC standard 44-Pin TSOP (TYPE II) and 48-pin
mini BGA (6mmx8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 16
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
CS1
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev. F
08/25/2014
IS62WV25616ALL, IS62WV25616BLL
PIN CONFIGURATIONS
48- ball mini BGA (6mm x 8mm)
(Package Code B)
44-Pin mini TSOP (Type II)
(Package Code T)
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
NC
B
I/O8
UB
A3
A4
CSI
I/O0
C
I/O9
I/O10
A5
A6
I/O1
I/O2
D
GND
I/O11
A17
A7
I/O3
VDD
E
VDD
I/O12
NC
A16
I/O4
GND
F
I/O14
I/O13
A14
A15
I/O5
I/O6
G
I/O15
NC
A12
A13
WE
I/O7
H
NC
A8
A9
A10
A11
NC
A4
A3
A2
A1
A0
CS1
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A17
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
CS2
A8
A9
A10
A11
A17
44-Pin mini TSOP (Type II)
2 Chip Enable Option
(Package Code T2)
PIN DESCRIPTIONS
A0-A17 I/O0-I/O15
CS1, CS2
OE WE LB
UB
NC
Vdd
GND
2
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
Power
Ground
A4
A3
A2
A1
A0
CS1
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
08/25/2014
IS62WV25616ALL, IS62WV25616BLL
TRUTH TABLE
I/O PIN
Mode
WE CS1 OE
LBUB
I/O0-I/O7 I/O8-I/O15Vdd Current
Not Selected
X
H
X
X
X
High-Z
High-Z
Isb1, Isb2
X
X
X
H
H
High-Z
High-Z
Isb1, Isb2
Output Disabled
H
L
H
L
X
High-Z
High-Z
Icc
H
L
H
X
L
High-Z
High-Z
Icc
Read
H
L
L
L
H
Dout
High-Z
Icc
H
L
L
H
L
High-Z
Dout
HLLLLDoutDout
Write
L
L
X
L
H
Din
High-Z
Icc
L
L
X
H
L
High-Z
Din
LL
XLLDinDin
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vterm
Vdd
Tstg
Pt
Parameter
Terminal Voltage with Respect to GND
Vdd Related to GND
Storage Temperature
Power Dissipation
Value
Unit
–0.2 to Vdd+0.3V
–0.2 to Vdd+0.3V
–65 to +150
°C
1.0
W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
OPERATING RANGE (Vdd)
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
IS62WV25616ALL
1.65V - 2.2V
1.65V - 2.2V
IS62WV25616BLL
2.5V-3.6V
2.5V-3.6V
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Vdd
Min.
Max.Unit
Voh
Output HIGH Voltage
Ioh = -0.1 mA
1.65-2.2V
1.4
—
V
Ioh = -1 mA
2.5-3.6V
2.2
—
V
Vol
Output LOW Voltage
Iol = 0.1 mA
1.65-2.2V
—
0.2
V
Iol = 2.1 mA
2.5-3.6V
—
0.4
V
Vih
Input HIGH Voltage
1.65-2.2V
1.4
Vdd + 0.2
V
2.5-3.6V2.2
Vdd + 0.3
V
(1)
Vil Input LOW Voltage
1.65-2.2V
–0.2
0.4
V
2.5-3.6V
–0.2
0.8
V
Ili
Input Leakage
GND ≤ Vin ≤ Vdd
–1
1µA
Ilo
Output Leakage
GND ≤ Vout ≤ Vdd, Outputs Disabled
–1
1
µA
Notes: 1. Vil (min.) = –1.0V for pulse width less than 10 ns.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3
Rev. F
08/25/2014
IS62WV25616ALL, IS62WV25616BLL
IS62WV25616ALL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions Max.
70
Icc
Vdd Dynamic Operating Vdd = Max.,
Com.
25
Supply Current
Iout = 0 mA, f = fmax
Ind.30
Icc1
Operating Supply
Vdd = Max., CS1 = 0.2V
Com.
10
Current
WE = Vdd-0.2V
Ind.10
f=1mhz
Isb1
TTL Standby Current
Vdd = Max.,
Com. 0.35
(TTL Inputs)
Vin = Vih or Vil
Ind.0.35
CS1 = Vih , f = 1 MHz
OR
Unit
mA
mA
mA
ULB Control
Isb2
CMOS Standby
Current (CMOS Inputs)
Vdd = Max., Vin = Vih or Vil
CS1 = Vil, f = 0, UB = Vih, LB = Vih
Vdd = Max., Com.
15
µA
CS1 ≥ Vdd – 0.2V,
Ind.
15
Vin ≥ Vdd – 0.2V, or
Vin ≤ 0.2V, f = 0
OR
ULB Control
Vdd = Max., CS1 = Vil,
Vin ≤ 0.2V, f = 0; UB / LB = Vdd – 0.2V
IS62WV25616BLL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions
Max. Max.
55
70
Icc
Vdd Dynamic Operating Vdd = Max.,
Com.
40
35
Supply Current
Iout = 0 mA, f = fmax
Ind. 45 40
Icc1
Operating Supply
Vdd = Max., CS1 = 0.2V Com.
15
15
Current
WE = Vdd-0.2V
Ind. 15 15
f=1mhz
Isb1
TTL Standby Current
Vdd = Max.,
Com.
0.35
0.35
(TTL Inputs)
Vin = Vih or Vil
Ind. 0.350.35
CS1 = Vih, f = 1 MHz
OR
Unit
mA
mA
mA
ULB Control
Isb2
CMOS Standby
Current (CMOS Inputs)
Vdd = Max., Vin = Vih or Vil
CS1 = Vil, f = 0, UB = Vih, LB = Vih
Vdd = Max., Com.
15
15
µA
CS1 ≥ Vdd – 0.2V,
Ind.
15
15
Vin ≥ Vdd – 0.2V, ortyp.(1)
3
Vin ≤ 0.2V, f = 0
OR
ULB Control
Vdd = Max., CS1 = Vil,
Vin ≤ 0.2V, f = 0; UB / LB = Vdd – 0.2V
Note:
1. Typical values are measured at Vdd = 3.0V, Ta = 25oC. Not 100% tested.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
08/25/2014
IS62WV25616ALL, IS62WV25616BLL
CAPACITANCE(1)
Symbol
Cin
Cout
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.
8
10
Unit
pF
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
IS62WV25616ALL
(Unit)
0.4V to Vdd-0.2V
5 ns
IS62WV25616BLL
(Unit)
0.4V to Vdd-0.3V
5ns
Vref
Vref
See Figures 1 and 2
See Figures 1 and 2
IS62WV25616ALL IS62WV25616BLL
1.65V-2.2V 2.5V - 3.6V
R1(Ω)
3070
3070
R2(Ω)
31503150
Vref
0.9V
1.5V
Vtm1.8V
2.8V
AC TEST LOADS
R1
R1
VTM
VTM
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
Figure 1
5 pF
Including
jig and
scope
R2
R2
Figure 2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5
Rev. F
08/25/2014
IS62WV25616ALL, IS62WV25616BLL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
trc
taa
toha
tacs1
tdoe
thzoe(2)
tlzoe(2)
thzcs1
tlzcs1
tba
thzb
tlzb
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CS1 Access Time
OE Access Time
OE to High-Z Output
OE to Low-Z Output
CS1 to High-Z Output
CS1 to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
55 ns
Min.Max.
55
—
—
55
10
—
—
55
—
25
—
20
5
—
0
20
10
—
—
55
0
0
20
—
70 ns
Min.Max.
70
—
—
70
10
—
—
70
—
35
—
25
5
—
0
25
10
—
—
70
0
0
25
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to
Vdd-0.2V/Vdd-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
08/25/2014
IS62WV25616ALL, IS62WV25616BLL
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = Vil, WE = Vih, UB or LB = Vil)
tRC
ADDRESS
tAA
tOHA
tOHA
DOUT
DATA VALID
PREVIOUS DATA VALID
READ CYCLE NO. 2(1,3)(CS1, OE, AND UB/LB Controlled)
tRC
ADDRESS
tAA
tOHA
OE
tDOE
CS1
tHZOE
tLZOE
tACE1
tLZCE1
tHZCS1
LB, UB
tLZB
DOUT
tBA
HIGH-Z
tHZB
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1, UB, or LB = Vil. WE=Vih.
3. Address is valid prior to or coincident with CS1 LOW transition.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F
08/25/2014
7
IS62WV25616ALL, IS62WV25616BLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
55 ns
70 ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
twc
Write Cycle Time
55
—
70
—
ns
tscs1
CS1 to Write End
45
—
60
—
ns
taw
Address Setup Time to Write End 45
—
60
—
ns
tha
Address Hold from Write End
0
—
0
—
ns
tsa
Address Setup Time
0
—
0
—
ns
tpwb
LB, UB Valid to End of Write
45
—
60
—
ns
tpwe
WE Pulse Width
40
—
50
—
ns
tsd
Data Setup to Write End
25
—
30
—
ns
thd
Data Hold from Write End
0
—
0
—
­ns
thzwe(3) WE LOW to High-Z Output
—
20
—
20
ns
(3)
tlzwe WE HIGH to Low-Z Output
5
—
5
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to
Vdd-0.2V/Vdd-0.3V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CS1 LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one
can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
08/25/2014
IS62WV25616ALL, IS62WV25616BLL
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW)
tWC
ADDRESS
tHA
tSCS1
CS1
tAW
tPWE
WE
tPWB
LB, UB
tSA
DOUT
tHZWE
tLZWE
HIGH-Z
DATA UNDEFINED
tSD
DIN
tHD
DATA-IN VALID
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 and WE inputs and at
least one of the LB and UB inputs being in the LOW state.
2. WRITE = (CS1) [ (LB) = (UB) ] (WE).
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCS1
CS1
tAW
t PWE
WE
LB, UB
tSA
DOUT
DATA UNDEFINED
tHZWE
tLZWE
HIGH-Z
tSD
DIN
tHD
DATA-IN VALID
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9
Rev. F
08/25/2014
IS62WV25616ALL, IS62WV25616BLL
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCS1
CS1
tAW
t PWE
WE
LB, UB
tSA
DOUT
tHZWE
DATA UNDEFINED
tLZWE
HIGH-Z
tSD
DIN
tHD
DATA-IN VALID
WRITE CYCLE NO. 4 (UB/LB Controlled)
t WC
ADDRESS
t WC
ADDRESS 1
ADDRESS 2
OE
t SA
CS1
LOW
t HA
t SA
WE
UB, LB
t HA
t PBW
t PBW
WORD 1
WORD 2
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t HD
t SD
DIN
DATAIN
VALID
t HD
t SD
DATAIN
VALID
UB_CSWR4.eps
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
08/25/2014
IS62WV25616ALL, IS62WV25616BLL
DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter
VdrVdd for Data Retention
Idr
Data Retention Current
tsdr
Data Retention Setup Time
trdr
Recovery Time
Test Condition
See Data Retention Waveform
Vdd = 1.2V, CS1 ≥ Vdd – 0.2V
See Data Retention Waveform
See Data Retention Waveform
Min. Max.
Unit
1.2
3.6
V
—
15
µA
0
—
ns
trc— ns
DATA RETENTION WAVEFORM (CS1 Controlled)
tSDR
Data Retention Mode
tRDR
VDD
VDR
CS1
GND
CS1 ≥ VDD - 0.2V
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 11
Rev. F
08/25/2014
IS62WV25616ALL, IS62WV25616BLL
ORDERING INFORMATION
IS62WV25616ALL (1.65V-2.2V)
Commercial Range: 0°C to +70°C
Speed (ns)
70 Order Part No.
IS62WV25616ALL-70T
Package
TSOP
Industrial Range: –40°C to +85°C
Speed (ns)
70 70 70 Order Part No.
IS62WV25616ALL-70TI
IS62WV25616ALL-70BI
IS62WV25616ALL-70BLI
Package
TSOP
mini BGA (6mmx8mm) mini BGA (6mmx8mm), Lead-free
IS62WV25616BLL (2.5V - 3.6V)
Commercial Range: 0°C to +70°C
Speed (ns)
55 70 Order Part No.
IS62WV25616BLL-55T
IS62WV25616BLL-70T
Package
TSOP
TSOP
Industrial Range: –40°C to +85°C
Speed (ns)
55 55 55 55 55 12
Order Part No.
IS62WV25616BLL-55TI
IS62WV25616BLL-55TLI
IS62WV25616BLL-55T2LI
IS62WV25616BLL-55BI
IS62WV25616BLL-55BLI
Package
TSOP
TSOP, Lead-free
TSOP, Lead-free, 2 CS Option
mini BGA (6mmx8mm)
mini BGA (6mmx8mm), Lead-free
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
08/25/2014
Rev. F
08/25/2014
Θ
Package Outline
06/04/2008
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION.
1. CONTROLLING DIMENSION : MM
NOTE :
Θ
IS62WV25616ALL, IS62WV25616BLL
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 13
14
08/12/2008
Package Outline
1. CONTROLLING DIMENSION : MM .
2. Reference document : JEDEC MO-207
NOTE :
IS62WV25616ALL, IS62WV25616BLL
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
08/25/2014