IS61WV2568EDBLL IS64WV2568EDBLL 256K x 8 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH ECC DECEMBER 2011 DESCRIPTION The ISSI IS61/64WV2568EDBLL is a high-speed, FEATURES • High-speed access time: 8, 10 ns • Low Active Power: 85 mW (typical) • Low Standby Power: 7 mW (typical) CMOS standby • Single power supply — Vdd 2.4V to 3.6V (10 ns) — Vdd 3.3V ± 10% (8 ns) • Fully static operation: no clock or refresh required • Three state outputs • Industrial and Automotive temperature support • Lead-free available • Error Detection and Error Correction 2,097,152-bit static RAMs organized as 262,144 words by 8 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61/64WV2568EDBLL is packaged in the JEDEC standard 44-pin TSOP-II, 36-pin SOJ and 36-pin Mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM A0-A17 Memory Array (256Kx8) Decoder 8 8 IO0-7 I/O Data Circuit /CE /OE /WE Control Circuit 8 ECC Array (256Kx4) 4 12 ECC Column I/O Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/08/2011 1 IS61/64WV2568EDBLL PIN CONFIGURATION 44-Pin TSOP (Type II) 36 mini BGA 1 2 3 4 5 6 A A0 A1 NC A3 A6 A8 B I/O4 A2 WE A4 A7 I/O0 C I/O5 NC A5 D GND E VDD F I/O6 G I/O7 H A9 I/O1 VDD GND I/O2 NC A17 OE CE A16 A15 I/O3 A10 A11 A12 A13 A14 NC NC A0 A1 A2 A3 A4 CE I/O0 I/O1 VDD GND I/O2 I/O3 WE A5 A6 A7 A8 A9 NC NC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NC NC NC A17 A16 A15 A14 OE I/O7 I/O6 GND VDD I/O5 I/O4 A13 A12 A11 A10 NC NC NC NC 36-Pin SOJ PIN DESCRIPTIONS A0-A17 CE OE WE I/O0-I/O7 Vdd GND NC 2 Address Inputs Chip Enable Input Output Enable Input Write Enable Input Bidirectional Ports Power Ground No Connection A0 1 36 NC A1 2 35 A17 A2 3 34 A16 A3 4 33 A15 A4 5 32 A14 CE 6 31 OE I/O0 7 30 I/O7 I/O1 8 29 I/O6 VDD 9 28 GND GND 10 27 VDD I/O2 11 26 I/O5 I/O3 12 25 I/O4 WE 13 24 A13 A5 14 23 A12 A6 15 22 A11 A7 16 21 A10 A8 17 20 NC A9 18 19 NC Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/08/2011 IS61/64WV2568EDBLL ABSOLUTE MAXIMUM RATINGS(1) Symbol Vterm Vdd Tstg Pt Parameter Terminal Voltage with Respect to GND Vdd Relates to GND Storage Temperature Power Dissipation Value –0.5 to Vdd + 0.5 –0.3 to 4.0 –65 to +150 1.0 1 Unit V V °C W 2 Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 4 CAPACITANCE(1,2) Symbol Cin CI/O Parameter Input Capacitance Input/Output Capacitance Conditions Max. Unit Vin = 0V Vout = 0V 6 8 pF pF 5 Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. 6 ERROR DETECTION AND ERROR CORRECTION • • • • 7 Independent ECC with hamming code for each byte Detect and correct one bit error per byte Better reliability than parity code schemes which can only detect an error but not correct an error Backward Compatible: Drop in replacement to current in industry standard devices (without ECC) 8 TRUTH TABLE Mode CE Not Selected H (Power-down) Output DisabledL Read L Write L 9 WE OE I/O Operation Vdd Current X X High-Z Isb1, Isb2 H H L H L X 10 Icc Icc Icc High-Z Dout Din 11 OPERATING RANGE (Vdd)1 Range Ambient Temperature Industrial –40°C to +85°C Automotive (A1) –40°C to +85°C Automotive (A3) –40°C to +125°C IS61WV2568EDBLL Vdd (8, 10ns) 2.4V-3.6V (10ns) 3.3V ± 10% (8ns) — — IS64WV2568EDBLL Vdd (10ns) — 12 2.4V-3.6V 2.4V-3.6V Note: 1. Contact [email protected] for 1.8V option Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/08/2011 3 IS61/64WV2568EDBLL DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 3.3V + 10% Symbol Voh Vol Vih Vil Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions Vdd = Min., Ioh = –4.0 mA Vdd = Min., Iol = 8.0 mA GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 2.4 — 2 –0.3 –1 –1 Max. — 0.4 Vdd + 0.3 0.8 1 1 Unit V V V V µA µA Max. — 0.4 Vdd + 0.3 0.8 1 1 Unit V V V V µA µA Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 2.4V-3.6V Symbol Voh Vol Vih Vil Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions Vdd = Min., Ioh = –1.0 mA Vdd = Min., Iol = 1.0 mA GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 1.8 — 2.0 –0.3 –1 –1 Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 -10 -20 Symbol Parameter Test ConditionsMin. Max. Min. Max. Min. Max. Icc Vdd Dynamic Operating Vdd = Max., Com. — 40 — 30 — 25 Supply Current Iout = 0 mA, f = fmax Ind. — 45 — 35 — 30 Auto. — — — 50 — 45 21 typ.(2) 21 Icc1 Operating Vdd = Max., Com. — 20 — 20 — 20 Supply Current Iout = 0 mA, f = 0 Ind. — 25 — 25 — 25 Auto. — — — 40 — 40 Isb1 TTL Standby Current Vdd = Max., Com. — 10 — 10 — 10 (TTL Inputs) Vin = Vih or Vil Ind. — 15 — 15 — 15 CE ≥ Vih, f = 0 Auto. — — — 30 — 30 Isb2 CMOS Standby Vdd = Max., Com. — 5 — 5 — 5 Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Ind. — 6 — 6 — 6 Vin ≥ Vdd – 0.2V, or Auto. — — — 15 — 15 Vin ≤ 0.2V, f = 0 typ.(2) 1.5 1.5 Unit mA mA mA mA Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/08/2011 IS61/64WV2568EDBLL AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level (VRef) Output Load 1 Unit (2.4V-3.6V) 0.4V to Vdd-0.3V 1V/ ns Vdd/2 2 See Figures 1 and 2 3 AC TEST LOADS 4 319 Ω ZO = 50Ω 3.3V 50Ω 1.5V OUTPUT 30 pF Including jig and scope Figure 1. OUTPUT 5 353 Ω 5 pF Including jig and scope 6 Figure 2. 7 READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -8 -10 -20 Symbol Parameter Min.Max. Min.Max. Min.Max. trc Read Cycle Time 8 — 10 — 20 — taa Address Access Time — 8 — 10 — 20 toha Output Hold Time 2.0 — 2.0 — 2.5 — tace CE Access Time — 8 — 10 — 20 OE Access Time — 4.5 — 4.5 — 8 tdoe thzoe(2) OE to High-Z Output — 3 — 4 — 8 (2) tlzoe OE to Low-Z Output 0 — 0 — 0 — thzce(2 CE to High-Z Output 0 3 0 4 0 8 tlzce(2) CE to Low-Z Output 3 — 3 — 3 — tpu Power Up Time 0 — 0 — 0 — tpd Power Down Time — 8 — 10 — 20 8 Unit ns ns ns ns ns ns ns ns ns ns ns 9 10 11 Notes: 1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1). 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/08/2011 12 5 IS61/64WV2568EDBLL AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = Vil) t RC ADDRESS t AA t OHA DOUT t OHA DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) (CE and OE Controlled) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE t LZCE DOUT t ACE HIGH-Z t HZCE DATA VALID CE_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = Vil. 3. Address is valid prior to or coincident with CE LOW transitions. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/08/2011 IS61/64WV2568EDBLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -8 -10 -20 Symbol Parameter Min.Max. Min.Max. Min. Max. twc Write Cycle Time 8 — 10 — 20 — tsce CE to Write End 6.5 — 8 — 12 — taw Address Setup Time 6.5 — 8 — 12 — to Write End tha Address Hold from Write End 0 — 0 — 0 — tsa Address Setup Time 0 — 0 — 0 — tpwe1 WE Pulse Width 6.5 — 8 — 12 — tpwe2 WE Pulse Width (OE = LOW) 8.0 — 10 — 17 — tsd Data Setup to Write End 5 — 6 — 9 — thd Data Hold from Write End 0 — 0 — 0 — thzwe(2) WE LOW to High-Z Output — 3.5 — 5 — 9 tlzwe(2) WE HIGH to Low-Z Output 2 — 2 — 2 — 1 Unit ns ns ns 2 3 ns ns ns ns ns ns ns ns 4 5 Notes: 1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1). 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development 6 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/08/2011 7 IS61/64WV2568EDBLL AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE_WR1.eps 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/08/2011 IS61/64WV2568EDBLL WRITE CYCLE NO. 2(1,2) (WE Controlled: OE is HIGH During Write Cycle) t WC ADDRESS 1 VALID ADDRESS t HA 2 OE CE 3 LOW t AW t PWE1 WE t SA DOUT t HZWE 4 t LZWE HIGH-Z DATA UNDEFINED t SD 5 t HD DATAIN VALID DIN CE_WR2.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE > Vih. 6 7 WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) 8 t WC ADDRESS VALID ADDRESS OE LOW CE LOW 9 t HA t AW 10 t PWE2 11 WE t SA DOUT t HZWE DATA UNDEFINED t LZWE HIGH-Z t SD DIN 12 t HD DATAIN VALID CE_WR3.eps Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/08/2011 9 IS61/64WV2568EDBLL HIGH SPEED DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V) Symbol Parameter Test Condition Vdr Vdd for Data Retention See Data Retention Waveform Idr Data Retention Current Vdd = 2.0V, CE ≥ Vdd – 0.2V tsdr Data Retention Setup Time See Data Retention Waveform trdr Recovery Time See Data Retention Waveform Note 1: Typical values are measured at Vdd = Vdr(min), Ta = 25 C and not 100% tested. Options Com. Ind. Auto. Min. 2.0 — — 0 trc Typ.(1) — 0.5 — — — Max. 3.6 5 6 15 — — Unit V mA ns ns o DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode tRDR VDD VDR CE GND 10 CE ≥ VDD - 0.2V Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/08/2011 IS61/64WV2568EDBLL ORDERING INFORMATION 1 Industrial Range: -40°C to +85°C peed (ns) S 8 Order Part No. IS61WV2568EDBLL-8BLI IS61WV2568EDBLL-8TLI IS61WV2568EDBLL-8KLI Package 36 mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Lead-free 400-mil Plastic SOJ, Lead-free 2 3 Industrial Range: -40°C to +85°C peed (ns) S 10 Order Part No. IS61WV2568EDBLL-10BI IS61WV2568EDBLL-10BLI IS61WV2568EDBLL-10TI IS61WV2568EDBLL-10TLI IS61WV2568EDBLL-10KLI Package 36 mini BGA (6mm x 8mm) 36 mini BGA (6mm x 8mm), Lead-free TSOP (Type II) TSOP (Type II), Lead-free 400-mil Plastic SOJ, Lead-free 4 5 Automotive (A1) Range: -40°C to +85°C peed (ns) S 10 Order Part No. IS64WV2568EDBLL-10BA1 IS64WV2568EDBLL-10BLA1 IS64WV2568EDBLL-10CTA1 IS64WV2568EDBLL-10CTLA1 IS64WV2568EDBLL-10KLA1 Package 36 mini BGA (6mm x 8mm) 36 mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Copper Leadframe TSOP (Type II), Lead-free, Copper Leadframe 400-mil Plastic SOJ, Lead-free 6 7 8 Automotive (A3) Range: -40°C to +125°C peed (ns) S 10 Order Part No. IS64WV2568EDBLL-10BA3 IS64WV2568EDBLL-10BLA3 IS64WV2568EDBLL-10CTA3 IS64WV2568EDBLL-10CTLA3 IS64WV2568EDBLL-10KLA3 Package 36 mini BGA (6mm x 8mm) 36 mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Copper Leadframe TSOP (Type II), Lead-free, Copper Leadframe 400-mil Plastic SOJ, Lead-free 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/08/2011 11 12 Θ Package Outline 06/04/2008 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. 1. CONTROLLING DIMENSION : MM NOTE : Θ IS61/64WV2568EDBLL Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/08/2011 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/08/2011 4. Formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test. 5. Reference document : JEDEC SPEC MS-027. 3. Dimension b2 does not include dambar protrusion/intrusion. 2. Dimension D and E1 do not include mold protrusion . 1. Controlling dimension : mm NOTE : 12/20/2007 IS61/64WV2568EDBLL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Package Outline 08/12/2008 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : IS61/64WV2568EDBLL Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/08/2011