IS62WV1288ALL IS62WV1288BLL, IS65WV1288BLL 128K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES • High-speed access time: 45ns, 55ns, 70ns • CMOS low power operation: 30 mW (typical) operating 15 µW (typical) CMOS standby • TTL compatible interface levels DECEMBER 2008 DESCRIPTION The ISSI IS62WV1288ALL / IS62/65WV1288BLL are high-speed, 1M bit static RAMs organized as 128K words by 8 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is low (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. • Single power supply: 1.65V--2.2V Vdd (62WV1288ALL) 2.5V--3.6V Vdd (62WV1288BLL/ 65WV1288BLL) • Fully static operation: no clock or refresh required • Three state outputs • Automotive and Industrial temperatures available Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62WV1288ALL and IS62/65WV1288BLL are packaged in the JEDEC standard 32-pin TSOP (TYPEI), sTSOP (TYPEI), SOP, and 36-pin mini BGA. • Lead-free available FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K x 8 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 CS2 CS1 OE CONTROL CIRCUIT WE Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 11/12/08 1 IS62WV1288ALL, IS62WV1288BLL, IS65WV1288BLL PIN CONFIGURATION 36-pin mini BGA (B) (6mm x 8mm) 1 2 3 4 5 A0 A1 CS2 A3 A6 A8 B I/O4 A2 WE A4 A7 I/O0 C I/O5 NC A5 D GND VDD E VDD GND F I/O6 G I/O7 H A9 A0-A16 CS1 CS2 OE WE I/O0-I/O7 NC Vdd GND 2 6 A I/O1 I/O2 NC NC OE CS1 A16 A15 I/O3 A10 A11 A12 A13 A14 PIN DESCRIPTIONS Address Inputs Chip Enable 1 Input Chip Enable 2 Input Output Enable Input Write Enable Input Input/Output No Connection Power Ground 32-pin TSOP (TYPE I) (T), 32-pin sTSOP (TYPE I) (H) A11 A9 A8 A13 WE CS2 A15 VDD NC A16 A14 A12 A7 A6 A5 A4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 32-pin SOP (Q) NC 1 32 VDD A16 2 31 A15 A14 3 30 CS2 A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CS1 A0 12 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O2 15 18 I/O4 GND 16 17 I/O3 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 11/12/08 IS62WV1288ALL, IS62WV1288BLL, IS65WV1288BLL ABSOLUTE MAXIMUM RATINGS(1) Symbol Vterm Vdd Tstg Pt Parameter Terminal Voltage with Respect to GND Vdd Related to GND Storage Temperature Power Dissipation Value –0.2 to Vdd+0.3 –0.2 to +3.8 –65 to +150 1.0 Unit V V °C W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE (Vdd) Range Commercial Industrial/A1 Automotive Ambient Temperature 0°C to +70°C –40°C to +85°C –40°C to +125°C IS62WV1288ALL 1.65V - 2.2V 1.65V - 2.2V IS62/65WV1288BLL 2.5V - 3.6V 2.5V - 3.6V 2.5V - 3.6V DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Vdd Voh Output HIGH Voltage Ioh = -0.1 mA 1.65-2.2V Ioh = -1 mA 2.5-3.6V Vol Output LOW Voltage Iol = 0.1 mA 1.65-2.2V Iol = 2.1 mA 2.5-3.6V Vih(2) Input HIGH Voltage 1.65-2.2V 2.5-3.6V (1) Vil Input LOW Voltage 1.65-2.2V 2.5-3.6V Ili Input Leakage GND ≤ Vin ≤ Vdd Ilo Output Leakage GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 1.4 2.2 — — 1.4 2.2 –0.2 –0.2 –1 –1 Max. — — 0.2 0.4 Vdd + 0.2 Vdd + 0.3 0.4 0.6 1 1 Unit V V V V V V V V µA µA Notes: 1. Undershoot: –1.0V for pulse width less than 10 ns. Not 100% tested. 2. Overshoot: Vdd + 1.0V for pulse width less than 10 ns. Not 100% tested. TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE X X H H L CS1 H X L L L CS2 X L H H H OE X X H L X I/O Operation Vdd Current High-Z Isb1, Isb2 High-Z Isb1, Isb2 High-Z Icc Dout Icc Din Icc Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 11/12/08 3 IS62WV1288ALL, IS62WV1288BLL, IS65WV1288BLL CAPACITANCE(1) Symbol Cin Cout Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 8 10 Unit pF pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter 62WV1288ALL 62/65WV1288BLL (Unit) (Unit) Input Pulse Level 0.4V to Vdd-0.2V 0.4V to Vdd-0.3V Input Rise and Fall Times Input and Output Timing and Reference Level Output Load R1(Ω) R2(Ω) Vref Vtm 1.65V - 2.2V 3070 3150 0.9V 1.8V 5 ns Vref 5ns Vref See Figures 1 and 2 See Figures 1 and 2 2.5V - 3.6V 3070 3150 1.5V 2.8V AC TEST LOADS R1 R1 VTM VTM OUTPUT OUTPUT 30 pF Including jig and scope Figure 1 4 5 pF Including jig and scope R2 R2 Figure 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 11/12/08 IS62WV1288ALL, IS62WV1288BLL, IS65WV1288BLL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) 1.65V - 2.2V Symbol Parameter Test Conditions Icc Vdd Dynamic Operating Vdd = Max., Com. Supply Current Iout = 0 mA, f = fmax Ind. typ.(2) Icc1 Operating Supply Vdd = Max., Com. Current Iout = 0 mA, f = 0 Ind. Isb1 TTL Standby Current Vdd = Max., Com. (TTL Inputs) Vin = Vih or Vil Ind. CS1 = Vih , CS2 = Vil, f = 1 MHz Isb2 CMOS Standby Current (CMOS Inputs) Vdd = Max., CS1 ≥ Vdd – 0.2V, CS2 ≤ 0.2V, Vin ≥ Vdd – 0.2V, or Vin ≤ 0.2V, f = 0 Com. Ind. typ.(2) Max. Unit 70 ns 8 mA 8 5 5 mA 5 0.8 mA 0.8 10 µA 10 5 Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd=1.8V, Ta=25oC. Not 100% tested. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) 2.5V - 3.6V Symbol Parameter Test Conditions Max. Max. Unit 45ns 55 ns Icc Vdd Dynamic Operating Vdd = Max., Com. 17 15 mA Supply Current Iout = 0 mA, f = fmax Ind./A1 17 15 A3 35 typ.(2) 12 10 Operating Supply Vdd = Max., Com. 5 5 mA Icc1 Current Iout = 0 mA, f = 0 Ind./A1 5 5 A3 7 Isb1 TTL Standby Current Vdd = Max., Com. 0.8 0.8 mA (TTL Inputs) Vin = Vih or Vil Ind./A1 0.8 0.8 CS1 = Vih , CS2 = Vil, A3 3 f = 1 MHz Isb2 CMOS Standby Current (CMOS Inputs) Vdd = Max., CS1 ≥ Vdd – 0.2V, CS2 ≤ 0.2V, Vin ≥ Vdd – 0.2V, or Vin ≤ 0.2V, f = 0 Com. Ind./A1 A3 typ.(2) 10 10 5 10 10 75 5 µA Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd=3.0V, Ta=25oC. Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 11/12/08 5 IS62WV1288ALL, IS62WV1288BLL, IS65WV1288BLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol trc taa toha tacs1/tacs2 tdoe thzoe(2) tlzoe(2) thzcs1/thzcs2(2) tlzcs1/tlzcs2(2) Parameter Read Cycle Time Address Access Time Output Hold Time CS1/CS2 Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CS1/CS2 to High-Z Output CS1/CS2 to Low-Z Output 45 ns Min. Max. 45 — — 45 10 — — 45 — 20 0 15 5 — 0 15 5 — 55 ns Min. Max. 55 — — 55 10 — — 55 — 25 0 20 5 — 0 20 10 — 70 ns Min. Max. 70 — — 70 10 — — 70 — 35 0 25 5 — 0 25 10 — Unit ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to Vdd-0.2V/Vdd-0.3V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = Vil, CS2 = WE = Vih) tRC ADDRESS tAA tOHA DOUT 6 PREVIOUS DATA VALID tOHA DATA VALID Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 11/12/08 IS62WV1288ALL, IS62WV1288BLL, IS65WV1288BLL AC WAVEFORMS READ CYCLE NO. 2(1,3) (CS1, CS2, OE Controlled) tRC ADDRESS tAA tOHA OE tDOE CS1 tHZOE tLZOE tACS1/tACS2 CS2 DOUT tLZCS1/ tLZCS2 HIGH-Z tHZCS DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1= Vil. CS2=WE=Vih. 3. Address is valid prior to or coincident with CS1 LOW and CS2 HIGH transition. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 11/12/08 7 IS62WV1288ALL, IS62WV1288BLL, IS65WV1288BLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol twc tscs1/tscs2 taw tha tsa tpwe tsd thd thzwe(3) tlzwe(3) Parameter Write Cycle Time CS1/CS2 to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output 45 ns Min. Max. 45 — 35 — 35 — 0 — 0 — 35 — 20 — 0 — — 20 5 — 55 ns Min. Max. 55 — 45 — 45 — 0 — 0 — 40 — 25 — 0 — — 20 5 — 70 ns Min. Max. 70 — 60 — 60 — 0 — 0 — 50 — 30 — 0 — — 20 5 — Unit ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to Vdd-0.2V/Vdd-0.3V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW) tWC ADDRESS tHA tSCS1 CS1 tSCS2 CS2 tAW tPWE WE tSA DOUT tHZWE DATA UNDEFINED tLZWE HIGH-Z tSD DIN 8 tHD DATA-IN VALID Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 11/12/08 IS62WV1288ALL, IS62WV1288BLL, IS65WV1288BLL AC WAVEFORMS WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 CS2 tAW tPWE WE tSA DOUT tHZWE tLZWE HIGH-Z DATA UNDEFINED tSD DIN tHD DATA-IN VALID WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 CS2 tAW tPWE WE tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 11/12/08 tHD DATA-IN VALID 9 IS62WV1288ALL, IS62WV1288BLL, IS65WV1288BLL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Vdr Idr tsdr trdr Parameter Vdd for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition Min. See Data Retention Waveform 1.2 Vdd = 1.2V, CS1 ≥ Vdd – 0.2V Com. — Ind./A1 — A3 — See Data Retention Waveform 0 See Data Retention Waveform trc Max. 3.6 5 10 75 — — Unit V µA ns ns DATA RETENTION WAVEFORM (CS1 Controlled) Data Retention Mode tSDR tRDR VDD VDR CS1 ≥ VDD - 0.2V CS1 GND DATA RETENTION WAVEFORM (CS2 Controlled) Data Retention Mode VDD CS2 tSDR tRDR VDR CS2 ≤ 0.2V GND 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 11/12/08 IS62WV1288ALL, IS62WV1288BLL, IS65WV1288BLL ORDERING INFORMATION IS62WV1288ALL (1.65V - 2.2V) Industrial Range: -40°C to +85°C Speed (ns) 70 Order Part No. IS62WV1288ALL-70BI IS62WV1288ALL-70HI Package mini BGA (6mm x 8mm) sTSOP, TYPE I IS62WV1288BLL (2.5v-3.6V) Industrial Range: -40°C to +85°C Speed (ns) 45 55 Order Part No. IS62WV1288BLL-45TI IS62WV1288BLL-45BI IS62WV1288BLL-45HI IS62WV1288BLL-45HLI IS62WV1288BLL-45QI IS62WV1288BLL-55TI IS62WV1288BLL-55TLI IS62WV1288BLL-55BI IS62WV1288BLL-55HI IS62WV1288BLL-55HLI IS62WV1288BLL-55QI IS62WV1288BLL-55QLI Package TSOP, TYPE I mini BGA (6mm x 8mm) sTSOP, TYPE I sTSOP, TYPE I, Lead-free SOP TSOP, TYPE I TSOP, TYPE I, Lead-free mini BGA (6mm x 8mm) sTSOP, TYPE I sTSOP, TYPE I, Lead-free SOP SOP, Lead-free IS65WV1288BLL (2.5v-3.6V) A1 Range: -40°C to +85°C Speed (ns) 55 Order Part No. IS65WV1288BLL-55HLA1 IS65WV1288BLL-55TLA1 Package sTSOP, TYPE I, Lead-free TSOP, TYPE I, Lead-free A3 Range: -40°C to +125°C Speed (ns) 55 Order Part No. IS65WV1288BLL-55HLA3 Package sTSOP, TYPE I, Lead-free Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 11/12/08 11 PACKAGING INFORMATION 450-mil Plastic SOP Package Code: Q (32-pin) N E1 1 D SEATING PLANE A S B e MILLIMETERS Symbol No. Leads A A1 B C D E E1 e L α S E Min. INCHES Max. Min. Max. 32 — 3.00 0.10 — 0.36 0.51 0.15 0.30 20.14 20.75 13.87 14.38 11.18 11.43 1.27 BSC 0.58 0.99 0° 10° — 0.86 L A1 — 0.118 0.004 — 0.014 0.020 0.006 0.012 0.793 0.817 0.546 0.566 0.440 0.450 0.050 BSC 0.023 0.039 0° 10° — 0.034 α C Notes: 1. Controlling dimension: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/13/03 PACKAGING INFORMATION Plastic STSOP - 32 pins Package Code: H (Type I) A2 A A1 1 N E b e D1 S SEATING PLANE D L Plastic STSOP (H - Type I) Millimeters Inches Symbol Min Max Min Max Ref. Std. N 32 A — 1.25 — 0.049 A1 0.05 — 0.002 — A2 0.95 1.05 0.037 0.041 b 0.17 0.23 0.007 0.009 C 0.14 0.16 0.0055 0.0063 D 13.20 13.60 0.520 0.535 D1 11.70 11.90 0.461 0.469 E 7.90 8.10 0.311 0.319 e 0.50 BSC 0.020 BSC L 0.30 0.70 0.012 0.028 S 0.28 Typ. 0.011 Typ. α 0° 5° 0° 5° Integrated Silicon Solution, Inc. PK13197H32 Rev. B 04/21/03 α C Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. PACKAGING INFORMATION Mini Ball Grid Array Package Code: B (36-pin) Top View Bottom View φ b (36x) 1 2 3 4 5 6 6 A 4 3 2 1 A e B B C C D D 5 D D1 E E F F G G H H e E E1 Notes: 1. Controlling dimensions are in millimeters. A2 A A1 SEATING PLANE mBGA - 6mm x 8mm mBGA - 8mm x 10mm MILLIMETERS INCHES MILLIMETER INCHES Sym. Min. Typ. Max. Min. Typ. Max. Sym. Min. Typ. Max. Min. Typ. Max. N0. Leads 36 36 N0. Leads 36 36 A — — 1.20 — — 0.047 A — — 1.20 — — 0.047 A1 0.24 — 0.30 0.009 — 0.012 A1 0.24 — 0.30 0.009 — 0.012 A2 0.60 — — 0.024 — — A2 0.60 — — 0.024 — — D 7.90 8.00 8.10 D 9.90 10.00 10.10 D1 E 5.25BSC 5.90 6.00 0.311 0.315 0.319 0.207BSC 6.10 D1 0.232 0.236 0.240 E 5.25BSC 7.90 0.390 0.394 0.398 .207BSC 8.00 8.10 0.311 0.315 0.319 E1 3.75BSC 0.148BSC E1 3.75BSC 0.148BSC e 0.75BSC 0.030BSC e 0.75BSC 0.030BSC 0.012 0.014 0.016 b b 0.30 0.35 0.40 0.30 0.35 0.40 0.012 0.014 0.016 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 01/15/03 PACKAGING INFORMATION Plastic TSOP-Type I Package Code: T (32-pin) 1 E H N D SEATING PLANE A S B e MILLIMETERS Symbol No. Leads A A1 B C D E H e L α S Min. A1 INCHES Max. Min. Max. 32 — 1.20 0.05 0.25 0.17 0.23 0.12 0.17 7.90 8.10 18.30 18.50 19.80 20.20 0.50 BSC 0.40 0.60 0° 8° 0.25 REF — 0.047 0.002 0.010 0.007 0.009 0.005 0.007 0.311 0.319 0.720 0.728 0.780 0.795 0.020 BSC 0.016 0.024 0° 8° 0.010 REF L α C Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/13/03