HD74HC279 Octal D-type Flip-Flops (with Clear) REJ03D0605–0200 (Previous ADE-205-483) Rev.2.00 Jan 31, 2006 Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established. And when both inputs are low, output is high, but this high level are uncontinuance, if either of input goes high. Features • • • • • • High Speed Operation: tpd (S to Q) = 10 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C) Ordering Information Part Name Package Type HD74HC279FPEL SOP-16 pin (JEITA) Package Code (Previous Code) PRSP0016DH-B (FP-16DAV) Package Abbreviation FP PRSP0016DG-A RP (FP-16DNV) Note: Please consult the sales office for the above package availability. HD74HC279RPEL SOP-16 pin (JEDEC) Taping Abbreviation (Quantity) EL (2,000 pcs/reel) EL (2,500 pcs/reel) Function Table Inputs S* H L R H H Output Q Q0 H H L L L L H*1 2 H : L : Q0 : Notes: High level Low level The level of Q respectively, before the indicated steady-state input conditions were established. 1. It is unpredictable, if S or R goes High. 2. As to latches which has two S inputs. H: Both of S inputs are high. L: Either or both of S inputs are low. Rev.2.00 Jan 31, 2006 page 1 of 5 HD74HC279 Pin Arrangement 1R 1 16 VCC 1S1 2 15 4S 1S2 3 14 4R 1Q 4 13 4Q 2R 5 12 3S2 2S 6 11 3S1 2Q 7 10 3R GND 8 9 3Q (Top view) Logic Diagram R S1 Q S2 R Q S Absolute Maximum Ratings Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC VIN, VOUT IIK, IOK IO ICC or IGND PT Tstg Ratings –0.5 to 7.0 –0.5 to VCC +0.5 ±20 ±25 ±50 500 –65 to +150 Unit V V mA mA mA mW °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Rev.2.00 Jan 31, 2006 page 2 of 5 HD74HC279 Recommended Operating Conditions Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time*1 Symbol VCC VIN, VOUT Ta tr, tf Ratings 2 to 6 0 to VCC –40 to 85 0 to 1000 0 to 500 0 to 400 Unit V V °C ns Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Electrical Characteristics Item Input voltage Output voltage Symbol VCC (V) Ta = 25°C Typ Max — — — — — — Ta = –40 to+85°C Unit Min Max 1.5 — V 3.15 — 4.2 — VIH 2.0 4.5 6.0 Min 1.5 3.15 4.2 VIL 2.0 4.5 6.0 — — — — — — 0.5 1.35 1.8 — — — 0.5 1.35 1.8 V VOH 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 1.9 4.4 5.9 4.18 5.68 — — — — — — — 2.0 4.5 6.0 — — 0.0 0.0 0.0 — — — — — — — — — 0.1 0.1 0.1 0.26 0.26 ±0.1 2.0 1.9 4.4 5.9 4.13 5.63 — — — — — — — — — — — — 0.1 0.1 0.1 0.33 0.33 ±1.0 20 V VOL Input current Iin Quiescent supply current ICC V Test Conditions Vin = VIH or VIL IOH = –20 µA Vin = VIH or VIL IOH = –4 mA IOH = –5.2 mA IOL = 20 µA IOL = 4 mA IOL = 5.2 mA µA Vin = VCC or GND µA Vin = VCC or GND, Iout = 0 µA Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Propagation delay time Symbol VCC (V) Min Ta = 25°C Typ Max tPLH tPHL 2.0 4.5 6.0 — — — — 10 — 130 26 22 tPHL 2.0 4.5 6.0 2.0 4.5 6.0 — — — — — — — 12 — — 5 — — — 5 Output rise/fall time tTLH tTHL Input capacitance Cin Rev.2.00 Jan 31, 2006 page 3 of 5 Ta = –40 to +85°C Unit Test Conditions Min Max ns S to Q — 165 — — 33 28 120 24 20 75 15 13 — — — — — — 150 30 26 95 19 16 10 — 10 ns ns pF R to Q HD74HC279 Test Circuit Measurement point CL* Note: CL includes the probe and fig capacitance. Waveforms • Waveform tr tf VCC 90% 50% 90% S 50% 10% 10% 0V tr tf 90% R 50% 10% 10% tPHL VOH 90% 50% 10% tTHL 50% 10% 50% tTLH Note : 1. Input pulse : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns Rev.2.00 Jan 31, 2006 page 4 of 5 0V tPHL tPLH 90% Q VCC 90% VOL HD74HC279 Package Dimensions JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV MASS[Typ.] 0.24g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 16 9 *2 c HE E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 *3 e Nom D 10.06 E 5.50 Max 10.5 A2 8 Z Dimension in Millimeters Min bp x A1 M 0.00 0.10 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 A L1 0.20 2.20 bp b1 c A c θ A1 y 1 θ 0° HE 7.50 e L Detail F 1.27 x 0.12 y 0.15 0.80 Z L L JEITA Package Code P-SOP16-3.95x9.9-1.27 RENESAS Code PRSP0016DG-A *1 Previous Code FP-16DNV 0.50 0.70 0.90 1.15 1 MASS[Typ.] 0.15g D NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 16 8° 9 c *2 Index mark HE E bp Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) Dimension in Millimeters Min Nom Max D 9.90 10.30 E 3.95 A2 8 1 Z e *3 bp x A1 0.10 0.14 0.34 0.40 0.46 0.15 0.20 0.25 6.10 6.20 A M L1 0.25 1.75 bp b1 c A c A1 θ L y Detail F 1 θ 0° HE 5.80 e 1.27 x 0.25 y 0.15 0.635 Z L L Rev.2.00 Jan 31, 2006 page 5 of 5 8° 0.40 1 0.60 1.08 1.27 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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