IS61(64)LF12832A IS64VF12832A IS61(64)LF12836A IS61(64)VF12836A IS61(64)LF25618A IS61(64)VF25618A 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEBRUARY 2014 FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • Power Supply LF: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% VF: Vdd 2.5V -5% +10%, Vddq 2.5V -5% +10% • JEDEC 100-Pin QFP, 119-pin BGA, and 165-pin BGA packages • Automotive temperature available • Lead-free available DESCRIPTION The ISSI IS61(64)LF12832A, IS64VF12832A, IS61(64) LF/VF12836A and IS61(64)LF/VF25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61(64)LF12832A is organized as 131,072 words by 32 bits. The IS61(64)LF/ VF12836A is organized as 131,072 words by 36 bits. The IS61(64)LF/VF25618A is organized as 262,144 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable (BWE) input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol tkq tkc Parameter Clock Access Time Cycle Time Frequency -6.5 6.5 7.5 133 -7.5 7.5 8.5 117 Units ns ns MHz Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.1 Rev. G1 2/11/2014 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A BLOCK DIAGRAM MODE Q0 CLK CLK A0 BINARY COUNTER ADSC ADSP A Q1 CE ADV A1 A0' A1' 128Kx32; 128Kx36; 256Kx18 MEMORY ARRAY CLR 17/18 D Q 15/16 17/18 ADDRESS REGISTER CE CLK 32, 36, or 18 D GW BWE BW(a-d) x18: a,b x32/x36: a-d 32, 36, or 18 Q DQ(a-d) BYTE WRITE REGISTERS CLK CE 2/4/8 Q CE2 D CE2 ENABLE REGISTER INPUT REGISTERS CLK 32, 36, or 18 DQa - DQd OE CE CLK ZZ POWER DOWN OE 2 Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A 165-pin BGA 119-pin BGA 165-Ball, 13x15 mm BGA 119-Ball, 14x22 mm BGA Bottom view Bottom View Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 3 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A 119 BGA PACKAGE PIN CONFIGURATION 128K x 36 (TOP VIEW) A B C D E F G H J K L M N P R T U 1 2 3 4 5 6 VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ A CE2 A DQPc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQPd A NC NC A A A Vss Vss Vss BWc Vss NC Vss BWd Vss Vss Vss MODE A NC ADSP ADSC VDD NC CE OE ADV GW VDD CLK NC BWE A1* A0* VDD A NC A A A Vss Vss Vss BWb Vss NC Vss BWa Vss Vss Vss NC A NC A CE2 A DQPb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQPa A NC NC 7 VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A Pin Name Address Inputs A0, A1 Synchronous Burst Address Inputs ADV Synchronous Burst Address Advance ADSP Address Status Processor ADSC GW Address Status Controller Global Write Enable Symbol OE Pin Name Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection NC No Connect DQa-DQd Data Inputs/Outputs DQPa-Pd Output Power Supply CLK Synchronous Clock CE, CE2, CE2 Synchronous Chip Select Vdd Power Supply Vddq Output Power Supply BWx (x=a-d) Synchronous Byte Write Controls Vss Ground BWE Byte Write Enable 4 Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A 119 BGA PACKAGE PIN CONFIGURATION 256Kx18 (TOP VIEW) A B C D E F G H J K L M N P R T U 1 2 3 4 5 6 7 VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC NC VDDQ A CE2 A NC DQb NC DQb NC VDD DQb NC DQb NC DQPb A A NC A A A Vss Vss Vss BWb Vss NC Vss Vss Vss Vss Vss MODE A NC ADSP ADSC VDD NC CE OE ADV GW VDD CLK NC BWE A1* A0* VDD NC NC A A A Vss Vss Vss Vss Vss NC Vss BWa Vss Vss Vss NC A NC A CE2 A DQPa NC DQa NC DQa VDD NC DQa NC DQa NC A A NC VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A Pin Name Address Inputs A0, A1 Synchronous Burst Address Inputs ADV Synchronous Burst Address Advance ADSP Address Status Processor ADSC GW Address Status Controller Global Write Enable CLK CE, CE2, CE2 Synchronous Clock Synchronous Chip Select BWx (x=a,b) Synchronous Byte Write Controls BWE Byte Write Enable Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 Symbol OE Pin Name Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection NC No Connect DQa-DQb Data Inputs/Outputs DQPa-Pb Output Power Supply Vdd Power Supply Vddq Output Power Supply Vss Ground 5 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A 165 BGA PACKAGE PIN CONFIGURATION 128K x 36 (TOP VIEW) A B C D E F G H J K L M N P R 1 NC NC DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd NC MODE 2 A A NC DQc DQc DQc DQc NC DQd DQd DQd DQd NC NC NC 3 CE CE2 Vddq Vddq Vddq Vddq Vddq NC Vddq Vddq Vddq Vddq Vddq A A 4 BWc BWd Vss Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vss A A 5 BWb BWa Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC 6 CE2 CLK Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC A1* A0* 7 BWE GW Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC 8 ADSC OE Vss Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vss A A 9 ADV ADSP Vddq Vddq Vddq Vddq Vddq NC Vddq Vddq Vddq Vddq Vddq A A 10 A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A 11 NC NC DQPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DQPa NC A Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A Pin Name Address Inputs A0, A1 Synchronous Burst Address Inputs ADV Synchronous Burst Address Advance ADSP Address Status Processor ADSC GW Address Status Controller Global Write Enable CLK CE, CE2, CE2 Synchronous Clock Synchronous Chip Select BWx (x=a,b,c,d) Synchronous Byte Write Controls 6 Symbol Pin Name BWE Byte Write Enable OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection NC DQx DQPx Vdd Vddq No Connect Data Inputs/Outputs Data Inputs/Outputs 3.3V/2.5V Power Supply Isolated Output Power Supply 3.3V/2.5V Vss Ground Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A 165 BGA PACKAGE PIN CONFIGURATION 256K x 18 (TOP VIEW) A B C D E F G H J K L M N P R 1 NC NC NC NC NC NC NC NC DQb DQb DQb DQb DQPb NC MODE 2 A A NC DQb DQb DQb DQb NC NC NC NC NC NC NC NC 3 CE CE2 Vddq Vddq Vddq Vddq Vddq NC Vddq Vddq Vddq Vddq Vddq A A 4 BWb NC Vss Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vss A A 5 NC BWa Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC 6 CE2 CLK Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC A1* A0* 7 BWE GW Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC 8 ADSC OE Vss Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vss A A 9 ADV ADSP Vddq Vddq Vddq Vddq Vddq NC Vddq Vddq Vddq Vddq Vddq A A 10 A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A 11 A NC DQPa DQa DQa DQa DQa ZZ NC NC NC NC NC NC A Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A Pin Name Address Inputs Symbol A0, A1 Synchronous Burst Address Inputs ADV Synchronous Burst Address Advance ADSP Address Status Processor ADSC GW Address Status Controller Global Write Enable CLK CE, CE2, CE2 Synchronous Clock Synchronous Chip Select BWx (x=a,b) Synchronous Byte Write Controls Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 Pin Name BWE Byte Write Enable OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection NC DQx DQPx Vdd Vddq No Connect Data Inputs/Outputs Data Inputs/Outputs 3.3V/2.5V Power Supply Isolated Output Power Supply 3.3V/2.5V Vss Ground 7 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A PIN CONFIGURATION 100-Pin QFP (128K x 36) DQPc DQPb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQPa NC DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa NC MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A CE CE2 BWd BWc BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE CE2 BWd BWc BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-Pin QFP (128K x 32) (3 Chip-Enable option) (3 Chip-Enable option) PIN DESCRIPTIONS A0, A1 A Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs ADSC Synchronous Controller Address Status ADSP Synchronous Processor Address Status ADV Synchronous Burst Address Advance BWa-BWd Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable CLK 8 DQa-DQd Synchronous Data Input/Output DQPa-DQPd Parity Data Input/Output GW MODE Synchronous Global Write Enable Burst Sequence Mode Selection OE Output Enable Vdd 3.3V/2.5V Power Supply Vddq Isolated Output Buffer Supply: 3.3V/2.5V Ground Snooze Enable Vss ZZ Synchronous Clock Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A PIN CONFIGURATION A A CE CE2 NC NC BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-Pin QFP (256K x 18) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC (3 Chip-Enable Option) PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. A Synchronous Address Inputs Synchronous Controller Address Status ADSC ADSP Synchronous Processor Address Status ADV Synchronous Burst Address Advance BWa-BWb Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable CLK Synchronous Clock DQa-DQb Synchronous Data Input/Output Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 DQPa-DQPb Parity Data I/O; DQPa is parity for DQa1-8; DQPb is parity for DQb1-8 GW MODE Synchronous Global Write Enable Burst Sequence Mode Selection OE Vdd Vddq Vss ZZ Output Enable 3.3V/2.5V Power Supply Isolated Output Buffer Supply: 3.3V/2.5V Ground Snooze Enable 9 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A TRUTH TABLE(1-8) OPERATIONADDRESS CE CE2 CE2ZZ ADSP ADSC ADV WRITE OE Deselect Cycle, Power-Down None H X X L X L X X X Deselect Cycle, Power-Down None L X L L L X X X X Deselect Cycle, Power-Down None L H X L L X X X X Deselect Cycle, Power-Down None L X L L H L X X X Deselect Cycle, Power-Down None L H X L H L X X X Snooze Mode, Power-Down None X X X H X X X X X Read Cycle, Begin Burst External L L H L L X X X L Read Cycle, Begin Burst External L L H L L X X X H Write Cycle, Begin Burst External L L H L H L X L X Read Cycle, Begin Burst External L L H L H L X H L Read Cycle, Begin Burst External L L H L H L X H H Read Cycle, Continue Burst Next X X X L H H L H L Read Cycle, Continue Burst Next X X X L H H L H H Read Cycle, Continue Burst Next H X X L X H L H L Read Cycle, Continue Burst Next H X X L X H L H H Write Cycle, Continue Burst Next X X X L H H L L X Write Cycle, Continue Burst Next H X X L X H L L X Read Cycle, Suspend Burst Current X X X L H H H H L Read Cycle, Suspend Burst Current X X X L H H H H H Read Cycle, Suspend Burst Current H X X L X H H H L Read Cycle, Suspend Burst Current H X X L X H H H H Write Cycle, Suspend Burst Current X X X L H H H L X Write Cycle, Suspend Burst Current H X X L X H H L X CLKDQ L-H High-Z L-H High-Z L-H High-Z L-H High-Z L-H High-Z X High-Z L-H Q L-H High-Z L-H D L-H Q L-H High-Z L-H Q L-H High-Z L-H Q L-H High-Z L-H D L-H D L-H Q L-H High-Z L-H Q L-H High-Z L-H D L-H D NOTE: 1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. 2.For WRITE, L means one or more byte write enable signals (BWa-d) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH. 3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version. 4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification. PARTIAL TRUTH TABLE Function Read Read Write Byte 1 Write All Bytes Write All Bytes 10 GW BWEBWaBWbBWcBWd HHXXXX HLHHHH H L L H H H H L L L L L L X X X X X Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or No Connect) External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A1 A0 A1 A0 A1 A0 A1 A0 00011011 01001110 10110001 11100100 LINEAR BURST ADDRESS TABLE (MODE = Vss) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) SymbolParameter Tstg Storage Temperature Pd Power Dissipation Iout Output Current (per I/O) Vin, Vout Voltage Relative to Vss for I/O Pins Vin Voltage Relative to Vss for for Address and Control Inputs Vdd Voltage on Vdd Supply Relative to Vss Value Unit –55 to +150 °C 1.6 W 100 mA –0.5 to Vddq + 0.5 V –0.5 to Vdd + 0.5 V –0.5 to 4.6 V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. Integrated Silicon Solution, Inc.11 Rev. G1 2/11/2014 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A OPERATING RANGE (IS61/64LFxxxxx) Range Commercial Industrial Automotive Ambient Temperature 0°C to +70°C -40°C to +85°C -40°C to +125°C Vdd 3.3V ± 5% 3.3V ± 5% 3.3V ± 5% Vddq 3.3V/2.5V ± 5% 3.3V/2.5V ± 5% 3.3V/2.5V ± 5% Vdd 2.5V -5% +10% 2.5V -5% +10% 2.5V -5% +10% Vddq 2.5V -5% +10% 2.5V -5% +10% 2.5V -5% +10% OPERATING RANGE (IS61/64VFxxxxx) Range Commercial Industrial Automotive Ambient Temperature 0°C to +70°C -40°C to +85°C -40°C to +125°C DC ELECTRICAL CHARACTERISTICS (Over Operating Range) 3.3V2.5V Symbol Parameter Test Conditions Min.Max. Min.Max. Voh Output HIGH Voltage Ioh = –4.0 mA (3.3V) 2.4— 2.0— Ioh = –1.0 mA (2.5V) Vol Output LOW Voltage Iol = 8.0 mA (3.3V) —0.4 —0.4 Iol = 1.0 mA (2.5V) Vih Input HIGH Voltage (1) 2.0 Vdd + 0.3 1.7 Vdd + 0.3 Vil Input LOW Voltage(1) –0.3 0.8 –0.3 0.7 (1) Ili Input Leakage Current Vss ≤ Vin ≤ Vdd –5 5 –5 5 Ilo Output Leakage Current Vss ≤ Vout ≤ Vddq, OE = Vih –5 5 –5 5 Unit V V V V µA µA Note: 1.Vill(min) = -2.0V AC (pulse width < tkc/ 2). Guaranteed by design. Vihh(max) = Vdd + 1.5V AC (pulse width < tkc/ 2). Guaranteed by design. 12 Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Icc AC Operating Supply Current Isb Standby Current TTL Input Isbi Standby Current CMOS Input Isb2 Sleep Mode Test Conditions Temp. range Device Selected, Com. OE = Vih, ZZ ≤ Vil, Ind. All Inputs ≤ 0.2V or ≥ Vdd – 0.2V, Auto. Cycle Time ≥ tkc min.typ.(2) Device Deselected, Com. Vdd = Max., Ind. All Inputs ≤ Vil or ≥ Vih, Auto. ZZ ≤ Vil, f = Max. Device Deselected, Com. Vdd = Max., Ind. Auto. Vin ≤ Vss + 0.2V or ≥Vdd – 0.2V f = 0 typ. ZZ>Vih Com. Ind. Auto. typ. 6.5 7.5 MAX MAX x18 x32/x36 x18 x32/x36 175 175 155 155 180 180 160 160 190 190 175 175 120 110 90 90 90 90 100 100 100 100 120 120 120 120 70 75 90 40 30 35 45 25 70 70 70 75 75 75 90 90 90 40 30 30 30 35 35 35 45 45 45 25 Unit mA mA mA mA Note: 1. MODE pin has an internal pullup and should be tied to Vdd or Vss. It exhibits ±100 µA maximum leakage current when tied to ≤ Vss + 0.2V or ≥ Vdd – 0.2V. 2. Typical values are measured at Vdd = 3.3V, Ta = 25oC and not 100% tested. CAPACITANCE(1,2) SymbolParameter Cin Input Capacitance Cout Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max.Unit 6pF 8pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 13 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 AC TEST LOADS 317 Ω 3.3V ZO = 50Ω OUTPUT 50Ω 1.5V Figure 1 14 OUTPUT 5 pF Including jig and scope 351 Ω Figure 2 Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT 1,667 Ω +2.5V ZO = 50Ω OUTPUT OUTPUT 50Ω 5 pF Including jig and scope 1,538 Ω 1.25V Figure 3 Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 Figure 4 15 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol fmax tkc tkh tkl tkq tkqx(2) tkqlz(2,3) tkqhz(2,3) toeq toeqx(2) toelz(2,3) toehz(2,3) tas tss tws tces tavs tds tah twh tsh tceh tavh tdh tpds tpus Notes: Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Read/Write Setup Time Chip Enable Setup Time Address Advance Setup Time Data Setup Time Address Hold Time Write Hold Time Address Status Hold Time Chip Enable Hold Time Address Advance Hold Time Data Hold Time ZZ High to Power Down ZZ Low to Power Down 6.5 Min. Max. — 133 7.5 — 2.2 — 2.2 — — 6.5 2.5 — 2.5 — — 3.8 — 3.2 2.5 — 0 — — 3.5 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — — 2 — 2 7.5 Min.Max. — 117 8.5 — 2.5 — 2.5 — — 7.5 2.5 — 2.5 — — 4.0 — 3.4 2.5 — 0 — — 3.5 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — — 2 — 2 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. 16 Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A READ/WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP tSS tSH ADSC ADV tAS Address tAH RD1 WR1 tWS tWH tWS tWH RD2 RD3 GW BWE tWS tWH WR1 BWd-BWa tCES tCEH tCES tCEH tCES tCEH CE Masks ADSP CE CE2 and CE2 only sampled with ADSP or ADSC CE2 Unselected with CE2 CE2 tOEHZ OE tKQ tOEQX DATAOUT High-Z 2c 2d tKQHZ tKQHZ 1a High-Z tDS Single Read Flow-through Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 2b tKQX tKQX tKQX tKQ DATAIN 2a 1a tKQLZ tKQ tDH Single Write Burst Read Unselected 17 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE1 inactive ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS tAVH ADV tAS Address tAH WR1 WR2 tWS tWH tWS tWH tWS tWH WR3 GW BWE BWd-BWa WR1 tCES tCEH tCES tCEH tCES tCEH tWS tWH WR2 WR3 CE1 Masks ADSP CE Unselected with CE2 CE2 and CE3 only sampled with ADSP or ADSC CE2 CE2 OE DATAOUT High-Z tDS DATAIN High-Z Single Write 18 tDH 1a BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d Burst Write 3a Write Unselected Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A SNOOZE MODE ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Isb2 Current during SNOOZE MODE ZZ ≥ Vih tpds ZZ active to input ignored tpus ZZ inactive to input sampled tzzi ZZ active to SNOOZE current trzzi ZZ inactive to exit SNOOZE current Min. — — 2 — 0 Max. 60 2 — 2 — Unit mA cycle cycle cycle ns SNOOZE MODE TIMING CLK tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z Don't Care Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 19 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ORDERING INFORMATION (Vdd = 3.3V/Vddq = 2.5V/3.3V) Commercial Range: 0°C to +70°C Configuration 128Kx32 128Kx32 128Kx36 128Kx36 256Kx18 256Kx18 20 Access Time 6.5 7.5 6.5 7.5 6.5 7.5 Order Part Number IS61LF12832A-6.5TQ IS61LF12832A-6.5B2 IS61LF12832A-6.5B3 IS61LF12832A-7.5TQ IS61LF12832A-7.5B2 IS61LF12832A-7.5B3 IS61LF12836A-6.5TQ IS61LF12836A-6.5B2 IS61LF12836A-6.5B3 IS61LF12836A-7.5TQ IS61LF12836A-7.5B2 IS61LF12836A-7.5B3 IS61LF25618A-6.5TQ IS61LF25618A-6.5TQL IS61LF25618A-6.5B2 IS61LF25618A-6.5B3 IS61LF25618A-7.5TQ IS61LF25618A-7.5B2 IS61LF25618A-7.5B3 Package 100 QFP 119 BGA 165 BGA 100 QFP 119 BGA 165 BGA 100 QFP 119 BGA 165 BGA 100 QFP 119 BGA 165 BGA 100 QFP 100 QFP, Lead-free 119 BGA 165 BGA 100 QFP 119 BGA 165 BGA Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ORDERING INFORMATION (Vdd = 3.3V/Vddq = 2.5V/3.3V) Industrial Range: -40°C to +85°C Configuration 128Kx32 128Kx32 128Kx36 128Kx36 256Kx18 256Kx18 Access Time 6.5 7.5 6.5 7.5 6.5 7.5 Order Part Number IS61LF12832A-6.5TQI IS61LF12832A-6.5B2I IS61LF12832A-6.5B3I IS61LF12832A-7.5TQI IS61LF12832A-7.5TQLI IS61LF12832A-7.5B2I IS61LF12832A-7.5B3I IS61LF12836A-6.5TQI IS61LF12836A-6.5TQLI IS61LF12836A-6.5B2I IS61LF12836A-6.5B3I IS61LF12836A-7.5TQI IS61LF12836A-7.5TQLI IS61LF12836A-7.5B2I IS61LF12836A-7.5B3I IS61LF25618A-6.5TQI IS61LF25618A-6.5B2I IS61LF25618A-6.5B3I IS61LF25618A-7.5TQI IS61LF25618A-7.5TQLI IS61LF25618A-7.5B2I IS61LF25618A-7.5B3I Package 100 QFP 119 BGA 165 BGA 100 QFP 100 QFP, Lead-free 119 BGA 165 BGA 100 QFP 100 QFP, Lead-free 119 BGA 165 BGA 100 QFP 100 QFP, Lead-free 119 BGA 165 BGA 100 QFP 119 BGA 165 BGA 100 QFP 100 QFP, Lead-free 119 BGA 165 BGA Order Part Number IS64LF12832A-7.5TQA3 IS64LF12832A-7.5TQLA3 IS64LF12836A-7.5TQA3 IS64LF12836A-7.5B3LA3 IS64LF25618A-7.5TQA3 Package 100 QFP 100 QFP, Lead-free 100 QFP 165 BGA, Lead-free 100 QFP Automotive Range: -40°C to +125°C Configuration 128Kx32 128Kx36 256Kx18 Access Time 7.5 7.5 7.5 Integrated Silicon Solution, Inc.21 Rev. G1 2/11/2014 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ORDERING INFORMATION (Vdd = 2.5V /Vddq = 2.5V) Commercial Range: 0°C to +70°C Configuration 128Kx36 128Kx36 256Kx18 256Kx18 Access Time 6.5 7.5 6.5 7.5 Order Part NumberPackage IS61VF12836A-6.5TQ 100 QFP IS61VF12836A-6.5B2 119 BGA IS61VF12836A-6.5B3 165 BGA IS61VF12836A-7.5TQ 100 QFP IS61VF12836A-7.5B2 119 BGA IS61VF12836A-7.5B3 165 BGA IS61VF25618A-6.5TQ 100 QFP IS61VF25618A-6.5B2 119 BGA IS61VF25618A-6.5B3 165 BGA IS61VF25618A-7.5TQ 100 QFP IS61VF25618A-7.5B2 119 BGA IS61VF25618A-7.5B3 165 BGA Industrial Range: -40°C to +85°C Configuration 128Kx36 128Kx36 256Kx18 256Kx18 Access Time 6.5 7.5 6.5 7.5 Order Part NumberPackage IS61VF12836A-6.5TQI 100 QFP IS61VF12836A-6.5B2I 119 BGA IS61VF12836A-6.5B3I 165 BGA IS61VF12836A-7.5TQI 100 QFP IS61VF12836A-7.5B2I 119 BGA IS61VF12836A-7.5B3I 165 BGA IS61VF25618A-6.5TQI 100 QFP IS61VF25618A-6.5B2I 119 BGA IS61VF25618A-6.5B3I 165 BGA IS61VF25618A-7.5TQI 100 QFP IS61VF25618A-7.5B2I 119 BGA IS61VF25618A-7.5B3I 165 BGA Automotive Range: -40°C to +125°C Configuration 128Kx32 128Kx36 256Kx18 22 Access Time 7.5 7.5 7.5 Order Part NumberPackage IS64VF12832A-7.5TQLA3 100 QFP, Lead-free IS64VF12836A-7.5TQA3 100 QFP IS64VF25618A-7.5TQA3 100 QFP Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 23 24 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MS-028 NOTE : Package Outline 10/02/2008 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 Integrated Silicon Solution, Inc. Rev. G1 2/11/2014 Package Outline 1. CONTROLLING DIMENSION : MM . NOTE : 08/28/2008 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A 25