LF4430 30-Mbit Video Memory / FIFO DEVICES INCORPORATED Preliminary Datasheet FRAME MEMORY Features 30Mbit (31,046,400 bit) memory density 150MHz Max clock rate Independent Read and Write ports: • Supports simultaneous read/write operations Selectable Memory Organization: • 3,880,800 x 8-bit • 3,104,640 x 10-bit • 2,587,200 x 12-bit • 1,940,400 x 16-bit • 1,552,320 x 20-bit • 1,293,600 x 24-bit Operating Modes: • Single-channel FIFO w/ Asynchronous I/O • Dual independent FIFOs w/ Asynchronous I/O Flexible Pointer Manipulation • Write/Read address pointer Clear/Set • Write/Read address pointers can be overridden in real-time using external 24bit address port • TRS detection for auto-clearing of Write pointer • Write/Read memory access Enable/Disable • Input enable control (Write Masking) for freeze frame control Selectable Core VDD = 1.8V, 2.5V, 3.3V Selectable I/O VDD = 1.8V, 2.5V, 3.3V 172 ball LBGA package (15 x 15 mm) Depth expansion is supported for Multi-frame HDTV, Multiframe SDTV, and other formats: • Seamless address space is maintained with up to 6 cascaded devices Near-Full/Empty Flags With Programmable Thresholds Collide Flag alerts User of W/R pointer crossings I2C Serial Microprocessor Interface Output Enable Control (Data Skipping) JTAG Boundary Scan - IEEE 1149.1 Applications Frame buffer for common HD formats (720p, 1080i, 1080p) HDTV / SDTV Frame Synchronization HDTV Display Buffer Time Base Correction (TBC) Freeze-Frame Buffer Picture-in-Picture (PIP) Buffer Frame Rate Conversion Security Camera Systems Field-Based or Frame-Based Comb Filtering HD Video Capture & Editing Systems Deep Data Buffering Image Manipulation (Rotation, Zoom) Test Pattern Generation Motion Detection or Frame-to-Frame Correlation LOGIC Devices Incorporated www.logicdevices.com 1 High Performance Memory Product November 12, 2007 LPB.4430 A LF4430 30-Mbit Video Memory / FIFO DEVICES INCORPORATED Preliminary Datasheet FRAME MEMORY LF4430 Overview Memory Organization Addressing Flexibility Simple Configuration The LF4430 is a 31,046,400-bit FIFO memory device configurable in a wide range of memory organizations from 8bit x 3,880,800 to 24bit x 1,293,600. An all-purpose HD frame store solution, the device supports all common SD/HD video formats/resolutions and data rates in a single chip. Independent (asynchronous) clock domains on the device’s data I/O ports enable synchronization and rate matching. Since reads are non-destructive, a given data value written into the memory core may be read as many times as desired. Applications requiring additional depth may cascade devices for depth expansion or may find the LOGIC Devices 60Mbit FIFO (LF4460) more suitable. In addition to providing memory organization flexibility, the LF4430 simplifies memory addressing tasks. Timing reference signals (TRS) on an incoming video signal can be detected and used to provide an autoclear on the Write pointer/address for simplified frame-sync applications. Write or Read pointers can be forced (in real-time) to any location within the entire address space using the external 24bit address port. Full-time Write or Read address manipulation using the external address port enables such applications as image rotation, Region-of-Interest extraction, or Picture-in-Picture (PIP). The device is configured by simply tying off static control pins. If a more complex memory implementation is required, access to application specific functions/features are provided through 8bit configuration words programmed via a standard I2C serial interface. Simple MODE and WIDTH control pins select the memory organization. I/O width is selected by the W[1:0] control pin that selects between 8, 10, and 12bit I/O. Combinations of Width and Mode selections allow buffering of 8bit to 24bit data in single or dual-independent FIFO channels. LF4430 Functional Block Diagram ADDR[23:0] 24 ADDRESS OVERRIDE CONTROL RDWRB WEN WIEN WRITE CONTROL WCLR WSET D[23:0] READ ADDRESS & CONTROL WRITE ADDRESS & CONTROL WCLK MODE MEMORY ARRAY I2C RSET OE 24 FLAGS Q[23:0] PF0 COLLIDE0 PE0 JTAG 2 7 MODE RDWR WIDTH SDA SCL CHIP_ADDR6-0 LOGIC Devices Incorporated READ CONTROL 1,293,600 x 24-bit 1,552,320 x 20-bit 1,940,400 x 16-bit 2,587,200 x 12-bit 3,104,640 x 10-bit 3,880,800 x 8-bit 24 RCLK REN RCLR TDI TDO TMS TCK High Performance Memory Product www.logicdevices.com 2 November 12, 2007 LPB.4430 A