LSI/CSI UL ® A3800 LS7366 LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405 PRELIMINARY 32-BIT QUADRATURE COUNTER WITH SERIAL INTERFACE GENERAL FEATURES: • Operating voltage: 3.0V to 5.5V (VDD-VSS) • 5V count frequency: 38MHz • 3V count frequency: 20MHz • 32-bit counter (CNTR). • 32-bit data register (DTR) and comparator. • 32-bit output register (OTR). • Two 8-bit mode registers (MDR0, MDR1) for programmable functional modes. • 8-bit instruction register (IR). • 8-bit status register (STR). • Latched Interrupt output on Carry or Borrow or Compare or Index. • Index driven counter load, output register load or counter reset. • Internal quadrature clock decoder and filter. • x1, x2 or x4 mode of quadrature counting. • Non-quadrature up/down counting. • Modulo-N, Non-recycle, Range-limit or Free-running modes of counting • 8-bit, 16-bit, 24-bit and 32-bit programmable configuration • Asynchronous (SCI) and synchronous (SPI) serial interface • LS7366 (DIP), LS7366-S (SOIC) LS7366SCI (DIP), LS7366SCI-S (SOIC) LS7366SPI (DIP), LS7366SPI-S (SOIC) SERIAL I/O FEATURES: SCI (Serial Communication Interface): • Standard NRZ (mark/space) format. • Idle line detect. • Internal or external baud-rate clock. • Pin-selectable baud-rates. • Addressable chip-select. SPI/MICROWIRE (Serial Peripheral Interface): • Standard 4-wire connection: MOSI, MISO, SS/ and SCK. • Slave mode only. GENERAL DESCRIPTION: LS7366 is a 32-bit CMOS counter, with direct interface for quadrature clocks from incremental encoders. It also interfaces with the index signals from incremental encoders to perform variety of marker functions. For communications with microprocessors or microcontrollers, it provides two types of serial hardware protocols: a 2-wire SCI bus or a 4-wire SPI/MICROWIRE bus. August 2001 PIN ASSIGNMENTS TOP VIEW fBR0 1 24 V DD fBRi 2 23 NC BR0 3 22 fCKO BR1 4 21 fCKi BR2 5 20 NC AD0 6 19 EN_SCI/ AD1 7 18 A CNT_EN 8 17 B SS/ LS7366 16 INDEX SCK 10 9 15 FLAG/ TXD/MISO 11 14 Vss RXD/MOSI 12 13 OE fBR0 1 18 V DD f BRi 2 17 f CKO BR0 3 16 f CKi BR1 4 15 A BR2 5 14 B AD0 6 13 INDEX AD1 7 12 FLAG/ TXD 8 11 Vss RXD 9 10 OE LS7366SCI N/C 1 14 V DD 2 13 fCKO CNT_EN 3 12 fCKi 11 A 10 B MISO 6 9 INDEX MOSI 7 8 FLAG/ Vss SS/ 4 SCLK 5 LS7366SPI Figure 1 7366-072401-1 CNT_EN SPI/Microwire Mode: In this mode, the four standard bus I/Os are SS/, SCK, MISO and MOSI. The data transfer between a microcontroller and a slave LS7366 is synchronous. The synchronization is done by the SCK clocks supplied by the microcontroller. Each transmission is organized in blocks of 1 to 5 bytes of data. A transmission cycle is intitiated by a high to low transition of the SS/ input. The first byte received in a transmission cycle is always an instruction byte, whereas the second through the fifth bytes are always interpreted as data bytes. A transmission cycle is terminated with the low to high transition of the SS/ input. Received bytes are shifted in at the MOSI input, MSB first, with the leading edges (high transition) of the SCK clocks. Output data are shifted out on the MISO output, MSB first, with the trailing edges (low transition) of the SCK clocks. Read and write commands cannot be combined. For example, when the device is shifting out read data on the MISO output, it ignores the MOSI input, even though the SS/ input is active. SS/ must be terminated and reasserted before the device will accept a new command. SCI Mode: In this mode the two standard bus I/Os are RXD and TXD. The data transfer between a microcontroller and a LS7366 is asynchronous and is controlled by separate but matched internal baud-rate clocks of the microcontroller and the LS7366. A receive cycle is initiated by a high to low transition at the RXD input constituting the “start bit” following a continuous high for a duration equivalent to 10 bits of data transmission, called idle state. Each receive cycle consists of 1 to 5 blocks, each block consisting of 10 bits in the following sequence: 1 start bit, 8 data bits and 1 stop bit. The first block received in a receive cycle always contains an instruction byte, whereas the second through the fifth blocks always contain data bytes. A receive cycle is terminated when the RXD input goes into the idle state. The logic states of the individual bits are determined as follows: A bit field is divided into four slots. Following the detection of a start bit high to low transition at the RXD input, the logic level at this input is sampled for three successive bit-field slots. If all three samples result in a logic 0, it is accepted as a valid start bit and sampling for the next bit is initiated; otherwise the process is aborted and the system waits for a new start bit transition. If a valid start bit is received, the successive bits are resolved similarly by 3-sample votes. If all three samples agree, then the bit is accepted, otherwise the receiver error (RE) bit in the status register (STR) is set and the device goes into the “sleep” state ignoring all incoming data. The device goes back into the awake state only when it detects an idle state again. 7366-072401-2 In a multi-slave network, individual LS7366 devices are addressed by means of a 2-bit address field embedded in the instruction byte. Following an idle cycle every slave unit in the network is in the awake state. A LS7366 device in the awake state examines the instruction byte for an address match by comparing the received 2-bit address field with its locally hardwired 2-bit address lines, AD0 and AD1. If the two addresses match, the device remains in the awake state and continues accepting all the data blocks following the instruction block. If the two addresses fail to match, the device goes into a sleep state, and ignores all the data blocks following the instruction block. The device goes back into the awake state only when it detects an idle state again. When a device is in the awake state, it accepts all properly constructed sequential bytes from the master and automatically resolves the instruction/data identity of each byte by resolving the context in which it was received. For example, if an instruction requires one byte of data, following the reception of that one byte of data, the next byte is automatically interpreteted as an instruction. The counter can be configured to operate as 1, 2, 3 or 4-byte counter. When configured as an n-byte counter, the CNTR, DTR and OTR are all configured as n-byte registers, where n = 1 or 2 or 3 or 4. The content of the instruction/data identity is automatically adjusted to match the n-byte configuration. For example, if the counter is configured as a 2-byte counter, the instruction “write to DTR” expects 2 data bytes following the instruction byte. If the counter is configured as a 3-byte counter, the same instruction will expect 3 bytes of data following the instruction byte. It is extremely important that an instruction byte is appended with the correct number of data bytes when more than one instruction is chained together without intervening idle states. Otherwise a data byte could be interpreted as an instruction byte by the device. Once a device is made awake, it ignores the address field of all subsequent instructions and accepts all transmissions from the controller without verifying the address fields. The process is terminated with the device being put into the sleep state when one of the following occurs: 1. The device encounters an unresolved bit state with the error (RE) bit set. 2. The device encounters a missing stop bit 3. The device encounters an idle state An exception to the above “awake state” rule is when the LS7366 is in the transmit mode. Following the transmission (in response to a READ command) the device must be addressed with the correct address in the manner devices are addressed following an idle state. Aside from read/write communications between the controller and a single LS7366 device, there is another type of communication called “global poll” in which the controller interrogates every device in the loop with a single command for the status of their FLAG registers. In response, every device whose FLAG is set inserts a “0" in the address mapped bit field of a synchronous joint transmission sent to the controller. A global poll must be preceded and followed by an idle state. In the SCI mode, the LS7366 can operate in half-duplex mode only. During data transmit in response to a READ command from the controller, the RXD input is disabled from receiving any transmissions. The counter can be programmed to operate in a number of different modes, with the operating characteristics being written into the two mode registers MDR0 and MDR1. Hardware I/Os are provided for event driven operations, such as processor interrupt and index related functions. I/O Pins: The LS7366 is available in a 24-pin package. The 24-pin package can be used in both SPI and SCI modes. Alternatively, a 14-pin package for the SPI mode alone and an 18-pin package for the SCI mode alone are also available. (See Figure 1). Following is a description of all the input/output pins. A, B (2-pins) Inputs. A and B quadrature clock outputs from incremental encoders are directly applied to the A and B inputs of the LS7366. These clocks are ideally 90 degrees out-ofphase signals. A and B inputs are validated by on-chip digital filters and then decoded for up/down direction and count clocks. In non-quadrature mode, A serves as the count input and B serves as the direction input (B = high enables up count, B = low enables down count). In non-quadrature mode, the A and B inputs are not filtered internally, and are instantaneous in nature. INDEX (1-pin) Input. The INDEX is a programmable input that can be driven directly by the Index output of an incremental encoder. It can be programmed via the MDR to function as one of the following: LCNTR (load CNTR with data from DTR), RCNTR (reset CNTR), or LOTR (load OTR with data from CNTR). Alternatively, the INDEX input can be masked out for "no functionality". In quadrature mode, the INDEX input is validated with the filter clock in order to synchronize with the quadrature inputs A and B. To be valid, the INDEX signal in quadrature mode must overlap the condition in which both A and B are low or both A and B are high. In non-quadrature mode, however, the INDEX input is instantaneous in nature and totally independent of A and B. 7366-072301-3 fBRi, fBR0 (2-pins) Input, Output. A crystal is connected between these pins for the internal oscillator. The oscillator serves as the basic frequency for the baud-rate generator. An external clock, such as the system clock, can also drive the fBRi pin if the oscillator is not used. fCKi, fCK0 (2-pins) Input, Output. A crystal connected between these 2 pins generates the basic clock for filtering the A,B and INDEX inputs in the quadrature count mode. The frequency at the fCKi input is either divided by 2 (if MDR0 <B7> = 1) or divided by 1 (if MDR0 <B7> = 0) for the filter circuit. For proper filtering of the A, B and the Index inputs the following condition must be satisfied: ff ≥ 4fQA Where ff is the internal filter clock frequency derived from the fCKi in accordance with the status of MDR0 <B7> and fQA is the maximum frequency of Clock A in quadrature mode. In non-quadrature count mode, fCKi is not used and should be tied off to any stable logic state. SS/ (1-pin) In the SPI mode, a high to low transition at the SS/ (Slave Select) input selects the LS7366 for serial bi-directional data transfer; a low to high transition disables serial data transfer and brings the MISO output to high impedance state. This allows for the accommodation of multiple slave units on the serial I/O. SS/ is not used in the SCI mode. BR0, BR1 and BR2 (3-pins) Inputs. These three baud-rate select pins provide 8selections of baud-rates in the SCI mode of transmission. In the SPI mode these inputs are irrelevant, and should be tied back to any stable logic states. In the SCI mode, the crystal oscillator frequency or the clock frequency at the fBRi pin is divided down by 16 to produce the basic internal baud-rate clock. The following table represents the standard baud rates derived from a crystal frequency of 3.6864MHz. BR2 BR1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 BR0 0 1 0 1 0 1 0 1 fc = 3.6864 MHz 230.4k Baud 115.2k Baud 57.6k Baud 38.4k Baud 19.2k Baud 9.6k Baud 4.8k Baud 2.4k Baud Division Factor 1 2 4 6 12 24 48 96 CNT_EN (1-pin) Input. Counting is enabled when CNT_EN input is high; counting is disabled when this input is low. There is an internal pull-up resistor on this input. FLAG/ (1-pin) Output. The FLAG is a programmable output to function as one or all of the following: Latched output on Carry (CNTR overflow) or Borrow (CNTR underflow) or Compare (CNTR = DTR) or Index or data receive error (RE) in SCI mode. It is an open drain output, which can be wire-ORed in a multi-slave configuration forming a single processor interrupt line. When the wire-ORed flag is asserted, the processor identifies the asserting device by means of a global poll. In response to a global poll every slave device inserts its individual flag status in an address specific bit location of a shared transmit data frame. The flag output gets cleared following a global poll. AD0, AD1 (2-pins) Inputs. In the SCI mode these inputs are used to assign the device address. The inputs are intended to be configured by local connections in one of 4 possible addresses. Following an idle state, the first byte received from the processor is a command byte, which contains a 2-bit address field. If the received address matches the local hardwired address, the device accepts the received data and all subsequent transmissions without any further address verification until another idle cycle is detected. If the received address fails to match the local address, the device goes into the sleep state and ignores the transmission and all subsequent transmissions until another idle cycle is detected. The address inputs are not used in the SPI mode. EN_SCI/ (1-pin) Input. When low, SCI mode is selected. When high SPI mode is selected. MOSI (RXD) (1-pin) Input. Serial output data from the host processor is shifted into the LS7366 at this input in both SPI and SCI modes. MISO (TXD) (1-pin) Output. Serial output data from the LS7366 is shifted out on the MISO (Master In Slave Out) pin in both SPI and SCI modes. The MISO output goes into high impedance state when SS/ input is at logic high, providing multiple slave-unit serial outputs to be wire-ORed. OE (1-pin) Output. In SCI mode OE is used to enable/disable IEEE standard line drivers driven by the TXD output. Whenever the LS7366 is addressed, as described above in MISO (TXD), the OE goes to logic high to enable any drivers connected to the TXD output. The OE output of an unaddressed LS7366 goes low, disabling its associated driver. 7366-072301-4 SCK (1-pin) Input. In SPI mode, the SCK input serves as the shift clock input for transmitting data in and out of LS7366 on the MOSI and the MISO pins, respectively. Since the LS7366 can operate only in the slave mode, the SCK signal is provided by the host processor as a means for synchronizing the serial transmission between itself and the slave LS7366. In SCI mode, the SCK input is not used. REGISTERS: The following is a list of LS7366 internal registers: DTR. The DTR is a software configurable 8, 16, 24 or 32bit input data register which can be written into directly from MOSI, the serial input. The DTR data can be transferred into the 32-bit counter (CNTR) under program control or by hardware index signal. The DTR can be cleared to zero by software control. In certain count modes, such as modulo-n and range-limit, DTR holds the data for "n" and the count range, respectively. In compare operations, whereby compare flag is set, the DTR is compared with the CNTR. CNTR. The CNTR is a software configurable 8, 16, 24 or 32-bit up/down counter which counts the up/down pulses resulting from the quadrature clocks applied at the A and B inputs, or alternatively, in non-quadrature mode, pulses applied at the A input. The CNTR can be loaded from the DTR. In turn, the CNTR can be transferred to the 32-bit output register (OTR). The CNTR can also be cleared to zero. OTR. The OTR is a software configuration 8, 16, 24 or 32-bit register which can be read back on the MISO output. Since instantaneous CNTR value is often needed to be read while the CNTR continues to count, the OTR serves as a convenient dump site for instantaneous CNTR data which can then be read without interfering with the counting process. STR. The STR is an 8-bit status register which stores count related status information. CY 7 CY: BW: CMP: IDX: CEN: BW 6 CMP 5 IDX 4 CEN 3 PLS 2 U/D 1 RE 0 Carry (CNTR overflow) latch Borrow (CNTR underflow) latch Compare (CNTR = DTR) latch Index latch Count enable status: 0: counting disabled, 1: counting enabled PLS: Power loss indicator latch; set upon power up U/D: Count direction indicator: 0: count down, 1: count up RE: Receiver error latch, set by ambiguous state of a received bit or a missing stop bit MDR0. The MDR0 (Mode Register 0) is an 8-bit read/write register that sets up the operating mode for the LS7366. The MDR0 is written into by executing the "write-to-MDR0" instruction via the instruction register. Upon power up MDR0 is cleared to zero. The following is a breakdown of the MDR bits: B7 B6 B5 B4 B3 B2 B1 B0 B1 B0 = 00: non-quadrature count mode. (A = clock, B = direction). = 01: x1 quadrature count mode (one count per quadrature cycle). = 10: x2 quadrature count mode (two counts per quadrature cycle). = 11: x4 quadrature count mode (four counts per quadrature cycle). B3 B2 = 00: free-running count mode. = 01: single-cycle count mode (counter disabled with carry or borrow, re-enabled with reset or load). = 10: range-limit count mode (up and down count-ranges are limited between DTR and zero, respectively; counting freezes at these limits but resumes when direction reverses). = 11: modulo-n count mode (input count clock frequency is divided by a factor of (n+1), where n = DTR, in both up and down directions). B5 B4 = 00: disable index. = 01: configure index as the "load CNTR" input (transfers DTR to CNTR). = 10: configure index as the "reset CNTR" input (clears CNTR to 0). = 11: configure index as the "load OTR" input (transfers CNTR to OTR). B6 = 0: = 1: B7 = 0: = 1: Negative index input Positive index input Filter clock division factor = 1 Filter clock division factor = 2 MDR1. The MDR1 (Mode Register 1) is an 8-bit read/write register which is appended to MDR0 for additional modes. Upon power-up MDR1 is cleared to zero. B7 B1 B0 = 00: = 01: = 10: = 11: B2 = 0: = 1: B3 = 0: = 1: B4 = 0: = 1: B5 = 0: = 1: B6 = 0: = 1: B7 = 0: = 1: 7366-072401-6 B6 B5 B4 B3 4-byte counter mode 3-byte counter mode 2-byte counter mode. 1-byte counter mode Enable counting Disable counting NOP FLAG on RE (B0 of STR) NOP FLAG on IDX (B4 of STR) NOP FLAG on CMP (B5 of STR) NOP FLAG on BW (B6 of STR) NOP FLAG on CY (B7 of STR) B2 B1 B0 +V AD1 AD1 AD0 AD0 AD1 EN SCI/ EN SCI/ LS7366 RXD TXD FLAG RXD TXD FLAG AD0 EN SCI/ EN SCI/ LS7366 AD1 AD0 LS7366 LS7366 RXD TXD FLAG RXD TXD FLAG +V +V TXD RXD INTERRUPT MPU FIGURE 2. MULTI-SLAVE CONFIGURATION IN SCI MODE +V AD0 AD1 EN SCI/ TXD DI RXD RO OE DE LS7366 A MAX481 B +V +V AD0 AD1 TXD RXD EN SCI/ DI RO OE DE LS7366 A MAX481 B +V +V AD0 AD1 EN SCI/ LS7366 TXD DI RXD RO OE DE A MAX481 B FIGURE 3. MULTI-SLAVE SCI WITH LINE DRIVERS 7366-072301-7 RS-485 RS-422 IR. The IR is an 8-bit register that fetches instruction bytes from the received data stream and executes them to perform such functions as setting up the operating mode for the chip (load the MDR) and data transfer among the various registers. B7 B6 B5 B4 B3 B2 B1 B0 B1 B0 = device address in SCI mode; irrelevant in SPI mode B2 = 0: single device addressing; in SCI mode, device is selected when B1 B0=AD1 AD0; in SPI mode B2 is irrelevant, device is selected when SS/=0 = 1: global poll; in SCI mode, every device sends its FLAG status by inserting a "1" for non-asserted flag and a "0" for asserted flag in an address mapped bit location of a shared transmission byte. In SPI mode, global poll is not recognized. B5 B4 B3 = 000: Select none = 001: Select MDR0 = 010: Select MDR1 = 011: Select DTR = 100: Select CNTR = 101: Select OTR = 110: Select STR = 111: Select none B7 B6 = 00: CLR register = 01: RD register = 10: WR register = 11: LOAD register The actions of the four functions, CLR, RD, WR and LOAD are elaborated in Table 1. Number of Bytes OP Code 1 CLR 2 to 5 RD 2 to 5 1 7366-072401-5 WR LOAD TABLE 1 Register MDR0 MRD1 DTR CNTR OTR STR MDR0 MDR1 DTR CNTR OTR STR MDR0 MDR1 DTR CNTR OTR STR MDR0 MDR1 DTR CNTR OTR STR Operation Clear MDR0 to zero Clear MDR1 to zero None Clear CNTR to zero None Clear STR to zero Output MDR0 serially on TXD (MISO) Output MDR1 serially on TXD (MISO) None Transfer CNTR to OTR, then output OTR serially on TXD (MISO) Output OTR serially on TXD (MISO) Output STR serially on TXD (MISO) Write serial data at RXD (MOSI) into MDR0 Write serial data at RXD (MOSI) into MDR1 Write serial data at RXD (MOSI) into DTR None None None None None None Transfer DTR to CNTR in “parallel” Transfer CNTR to OTR in “parallel” None Transient Characteristics. (TA = -25˚C to +80˚C, VDD = 3.0 to 5.5V) Parameter Symbol Min. Value Max.Value Unit Remarks fBRI High Pulse Width fBRI Low Pulse Width fBRI Frequency Baud rate SCK High Pulse Width SCK Low Pulse Width SS/ Set Up Time SS/ Hold Time tCH tCL tCSL tCSH 30 30 100 100 100 100 16 921.6 - ns ns MHz kBaud ns ns ns ns - Quadrature Mode fCKI High Pulse Width fCKI Pulse Width fCKI Frequency Effective Filter Clock fF Period t1 t2 fFCK t3 12 12 25 40 - ns ns MHz ns Effective Filter Clock fF frequency Quadrature Separation Quadrature Clock Pulse Width Quadrature Clock frequency Quadrature Clock to Count Delay x1/x2/x4 Count Clock Pulse Width Index Input Pulse Width Index Set Up Time Index Hold Time fF t4 t5 fQA, fQB tQ1 tQ2 tid tis tih 26 52 4t3 12 32 - 40 9.6 5t3 5 5 MHz ns ns MHz ns ns ns ns t3 = t1+t2, MDR0 <7> = 0 t3 = 2(t1+t2), MDR0 <7> = 1 fF = 1/ t3 t4 > t3 t5 ≥ 2t3 fQA = fQB < 1/4t3 tQ2 = (t3)/2 tid > t4 - Non-Quadrature Mode Clock A - High Pulse Width Clock A - Low Pulse Width Direction Input B Set-up Time Clock Frequency (non-Mod-N) t6 t7 tDS fA 12 12 12 - 40 ns ns ns MHz fA = ( 1/ (t6 + t7) ) - UP DOWN A B x1 CLOCK tQ1 x2 CLOCK tQ2 Note : x1, x2 and x4 clocks are internal count clocks derived from A and B. FIGURE 4. QUADRATURE CLOCK 7366-072400-9 ABSOLUTE MAXIMUM RATINGS: (All voltages referenced to Vss) Parameter Symbol DC Supply Voltage VDD Voltage VIN Operating Temperature TA Storage Temperature TSTG Values +7.0 Vss - 0.3 to VDD + 0.3 -25 to +80 -65 to +150 Unit V V oC oC DC Electrical Characteristics. (TA = -25˚C to +80°C) Parameter Supply Voltage Supply Current Min. 3.0 300 700 TYP 400 800 Max. 5.5 450 950 VCH VCH VCL VCL 0.7 1.3 2.1 3.5 0.9 1.5 2.3 3.7 - V V V V VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD = 5.0V All other inputs, Logic High VAH VAH - 1.9 3.2 2.1 3.5 V V VDD = 3.0V VDD = 5.0V All other inputs, Logic Low VAL VAL 0.5 1.0 0.7 1.2 - V V VDD = 3.0V VDD = 5.0V IIEL IIEL - 3.0 10.0 5.0 15.0 µA µA VAL = 0.7V, VDD = 3.0V VAL = 1.2V, VDD = 5.0V CNT_EN High IIEH IIEH - 1.0 4.0 3.0 6.0 µA µA VAH = 1.9V, VDD = 3.0V VAH = 3.2V, VDD = 5.0V All other inputs, High or Low - - 0 0 µA IOFL IOFL - -1.3 -3.2 0 -2.0 -4.0 0 - mA mA mA VOUT = 0.5V, VDD = 3.0V VOUT = 0.5V, VDD = 5.0V Open Drain Output fCKO Sink IOCL IOCL -1.3 -3.2 -2.0 -4.0 - mA mA VOUT = 0.5V, VDD = 3.0V VOUT = 0.5V, VDD = 5.0V fCKO Source IOCH IOCH 1.3 3.2 2.0 4.0 - mA mA VOUT = 2.5V, VDD = 3.0V VOUT = 4.5V, VDD = 5.0V fBRO Sink IOBL IOBL -1.0 -2.5 -1.6 -3.2 - mA mA VOUT = 0.5V, VDD = 3.0V VOUT = 0.5V, VDD = 5.0V fBRO Source IOBH IOBH 1.0 2.5 1.6 3.2 - mA mA VOUT = 2.5V, VDD = 3.0V VOUT = 4.5V, VDD = 5.0V IOTL IOTL IOTH -1.8 -4.2 0 -2.8 -5.5 0 - mA mA mA VOUT = 0.5V, VDD = 3.0V VOUT = 0.5V, VDD = 5.0V Open Drain Output IOML IOML -1.5 -3.8 -2.4 -4.8 - mA mA VOUT = 0.5V, VDD = 3.0V VOUT = 0.5V, VDD = 5.0V IOMH IOMH 1.5 3.8 2.4 4.8 - mA mA VOUT = 0.5V, VDD = 3.0V VOUT = 0.5V, VDD = 5.0V Input Voltages fCKi, fBRi, Logic high fCKi, fBRi, Logic Low Input Currents: CNT_EN Low Output Currents: FLAG Sink FLAG Source TXD/MISO in SCI mode: Sink Source TXD/MISO in SPI mode: Sink Source 7366-072301-8 Symbol VDD IDD IDD Unit V µA µA Remarks VDD = 3.0V VDD = 5.0V - SPI COMMUNICATION FORMAT Figure 5A exemplifies a Write to MDR1 followed by Read from MDR1 operation. Figure 5B exemplifies a Read CNTR (in 2-byte configuration) followed by CLR STR operation. START OF NEW COMMAND tCSL tCSH SS/ SCK WR MDR1 MOSI BIT # 7 6 5 4 RD DATA 3 X X X 2 1 0 MDR1 D7 D6 D5 D4 D3 D2 D1 D0 X 7 6 5 4 3 2 1 0 7 6 5 4 3 X X X RANDOM DATA 2 1 0 RANDOM DATA MISO D7 D6 D5 D4 D3 D2 D1 D0 RANDOM DATA BIT # 7 6 5 4 3 2 1 0 X X X FIGURE 5A. WR MDR1 - RD MDR1 tCSI SS/ SCK RD CLR CNTR MOSI BIT # 7 6 5 4 3 X X X 2 1 0 7 BYTE 1 BIT # 7 6 5 4 3 6 5 4 3 2 1 0 BYTE 0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 RANDOM DATA MISO STR RANDOM DATA 2 1 FIGURE 5B. 0 7 6 5 4 3 2 1 RANDOM DATA 0 RD CNTR - CLR STR SCI COMMUNICATION FORMAT Figure 6A exemplifies a Write to MDR1, followed by a Read from MDR1 operated on the same device (address 3) Figure 6B illustrates the same operation but in multislave connection switching from one addressed device to another between commands. Note the necessary idle state between commands when switching from one device to another. Figure 6C illustrates a read CNTR (2-byte configuration) followed by a clear STR operation. RXD IDLE A=3 MDR1 A0 A1 D0 D1 D2 STOP STRT TXD DATA WR STOP STRT MDR1 A=3 D6 D7 RD A0 A1 STOP STRT STRT (@ ADRS = 3) D0 D1 STOP D6 D7 FIGURE 6A. WR MDR1 @ ADRS = 3, RD MDR1 @ ADRS = 3 IDLE A=3 MDR1 DATA WR IDLE RXD A0 A1 D0 D1 D2 STOP STRT A=1 MDR1 RD D6 D7 STOP STRT STRT STOP STOP TXD D0 D1 (@ ADRS = 1) FIGURE 6B. WR MDR1 @ ADRS = 3, RD MDR1 @ ADRS =1 IDLE RXD CNTR A0 A1 STR A0 A1 START START BYTE 0 TXD D0 D1 D6 D7 STOP FIGURE 6C. RD CNTR, CLR STR 7366-072301-10 STRT IDLE RD BYTE 0 D0 D1 D6 D7 STOP D6 D7 CLR RXD IDLE X X STRT X X X X X X X X STOP GLOBAL 0 if FLAG/ = 0 TXD (ADRS = 0) 0 if FLAG/ = 0 TXD (ADRS = 1) 0 if FLAG/ = 0 TXD (ADRS = 2) 0 if FLAG/ = 0 TXD (ADRS = 3) FIGURE 7. GLOBAL POLL IN SCI A tDS tDS B UP/DN (internal) DOWN DOWN UP UP Figure 8. A (Count Clock) and B (Direction) in Non-Quadrature Mode t1 f CKi t2 t3 f f (Note 4) t3 (MDR0 <7> = 0) f f (Note 4) t5 (MDR0 <7> = 1) A B INDEX t4 t5 t4 t4 t ih t is Note 1 t4 t is t ih Note 2 t id Note 1. Positive index coincident with both A and B high. Note 2. Positive index coincident with both A and B low. Note 3. The index logic level in the above examples are inverted for negative index. Note 4. fF is the internal effective filter clock FIGURE 9. fCKi, A ,B and INDEX 7366-072501-11 fBRi fBR0 BR0 BR1 V+ ADRS MTCH BAUD RATE BR2 SCK (8) CLOCK CONTROL SPI_XMIT/ V+ I0 SHIFT REG I0 DATA CONTROL EN_SC/ TXD/MIS0 (8) (8) RXD/MOSI EN_DTR SPI_XMIT/ DTR (32) POR OE BUFFER SS/ A B EN_CNTR CNTR (32) FILTER MODE CONTROL /2 FLAG LOGIC LOAD MUX V+ fCKo FLAG/ EN_OTR OTR (32) INDEX fCKi CMPR EN_MDR0 MDR0 FLAGS (8) MDR0<7> CNT_EN EN_MDR1 WR MDR1 (2) AD0 (8) POR POR AD1 CMPR EN_STR FLAG MASK STR RD V DD Vss POR GEN (8) CLR (V+) EN_DTR ADRS MTCH (V-) FLAGS EN_CNTR EN_OTR IR (5) FIGURE 10. LS7366 BLOCK DIAGRAM EN_MDR0 LOAD CLR RD WR EN_MDR1 EN_STR