PRELIMINARY TECHNICAL DATA Isolated Half-Bridge Driver with Integrated Isolated High-Side Supply ADuM6132 FEATURES GENERAL DESCRIPTION Integrated Isolated High Side Supply 250mW Isolated DC/DC converter 200mA Output Sink Current, 200mA Output Source Current High common-mode transient immunity: > 25 kV/μs High temperature operation: 105°C Wide body SOIC 16-lead package Safety and regulatory approvals (pending) UL recognition 3750 V rms for 1 minute per UL 1577 CSA component acceptance notice #5A CSA/IEC 60950-1, 400 VRMS VDE certificate of conformity DIN V VDE 0884-10 (VDE V 0884-10):2006-12 VIORM = 560 V peak The ADuM61321 is an isolated half-bridge gate driver that employs Analog Devices’ iCoupler® technology to provide an isolated highside driver with an integrated 300 mW high-side supply. This supply, provided by an internal isolated DC/DC converter powers not only the ADuM6132’s high-side output but also any external buffer circuitry that would commonly be used with the ADuM6132. This eliminates the cost, space, and performance APPLICATIONS MOSFET/IGBT Gate Drive Motor Drives Solar Panel Inverters Power Supplies difficulties associated with external supply configurations such as a bootstrap circuitry. The architecture isolates the high side channel and high side power from the control and low side interface circuitry. Care has been taken to ensure close matching between the high and low side driver timing characteristics, reduces the need for dead time margin. In comparison to gate drivers employing high voltage level translation methodologies, the ADuM6132 offers the benefit of true, galvanic isolation. The differential voltage between high and low side channels can be as high as 1131V in some configurations (see Table 7). 1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075 329. Other patents pending. FUNCTIONAL BLOCK DIAGRAM Figure 1. ADuM6132 Functional Block Diagram Rev. PrG March 19, 2008 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2008 Analog Devices, Inc. All rights reserved. ADuM6132 PRELIMINARY TECHNICAL DATA SPECIFICATIONS ELECTRICAL CHARACTERISTICS All voltages are relative to their respective ground. 4.5 ≤ VDD = VDDL ≤ 5.5 V, 12.5 ≤ VDDB ≤ 17.0 V, VDDA = VISO. All min/max specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD = VDDL = 5.0V, VDDB = 15 V, VDDA = VISO. Table 1. Parameter DC SPECIFICATIONS Isolated Power Supply Input Current, Quiescent Input Current, Loaded Maximum Output Current1 Output Voltage Logic Supply Input Current Output Supplies, Channel A or Channel B2 Supply Current, Quiescent Supply Current, fIN=20kHz Supply Current, fIN=100kHz Supply Current, fIN=1000kHz Logic Inputs, Channel A or Channel B Input Current Logic High Input Voltage Logic Low Input Voltage Outputs, Channel A or Channel B Channel A High Level Output Voltage Channel B High Level Output Voltage Low Level Output Voltages High Level Output Current, Peak3 Low Level Output Current, Peak3 Undervoltage Lockout, VDDA or VDDB Supply Positive going threshold Negative going threshold Hysteresis Undervoltage Lockout, VDDL Supply Positive going threshold Negative going threshold Hysteresis SWITCHING SPECIFICATIONS Minimum Pulse Width4 Maximum Switching Frequency5 Propagation Delay6 Change versus temperature Pulse-Width Distortion, |tPLH−tPHL| Channel-to-Channel Matching, Rising or Falling Matching Edge Polarity7 Channel-to-Channel Matching, Rising vs. Falling Opposite Edge Polarity8 Part-to-Part Matching9 Output Rise Time (10%−90%) Output Fall Time (10%−90%) Symbol Min Typ Max Unit Test Conditions 250 350 IISO=0, DC signal inputs IISO = IISO(max,) 12.5 < VISO < 17.0 0 < IISO < 22 15 17 mA mA mA V IDDL 1.8 3.0 mA IDDA(Q), IDDB(Q) IDDA(20), IDDB(20) IDDA(100), IDDB(100) IDDA(1000), IDDB(1000) 1.0 1.1 1.3 4.5 2 2.1 2.3 5.5 mA mA mA mA 0.01 10 μA V V 0 ≤ VIA, VIB ≤ 5.5V 0.1 V V V mA mA IOAH = -1 mA IOBH = -1 mA IOAL, IOBL = +1 mA 12.3 11.2 1.2 V V V 4.2 3.7 V V V 50 CL = 200 pF CL = 200 pF CL = 200 pF IDD(Q) IDD IISO(max) VISO 22 12.5 IIA, IIB VIAH, VIBH VIAL, VIBL −10 0.7 xVDDL VOAH VOBH VOAL,VOBL IOAH, IOBH IOAL, IOBL VDDA –0.1 VDDB –0.1 200 200 VDDAUV+, VDDBUV+ VDDAUV-, VDDBUVVDDBUVH, VDDBUVH 11.0 10.0 0.8 VDDLUV+ VDDLUVVDDLUVH 3.5 3.0 0.3 PW fIN tPHL, tPLH 1000 40 0.3 x VDDL 11.7 10.7 1.0 CL = 200 pF CL = 200 pF CL = 200 pF PWD tM2 10 20 ns KHz ns ps/° C ns ns tM1 20 ns CL = 200 pF tR tF 60 15 15 ns ns ns CL = 200 pF CL = 200 pF CL = 200 pF Rev. PrG| Page 2 of 12 60 100 100 CL = 200 pF CL = 200 pF ADuM6132 PRELIMINARY TECHNICAL DATA 1 The maximum output current is the maximum isolated supply current that the ADuM6132 can provide. This current supports external loads as well as the needs of the ADuM6132 Channel A output circuitry. This is achieved via external connection of VISO to VDDA and GNDISO to GNDA (Figure 3). The net current available to power external loads is the ADuM6132 output current IISO less the Channel A supply current IDDA. 2 IDDA is supplied by the output of the integrated isolated dc/dc power as described in Footnote 1 above. IDDB is supplied by external power connection to VDDB pin. See Figure 3. 3 Duration less than 1 second. Average output current must conform to the limit shown under the Absolute Maximum Ratings. 4 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. Operation below the minimum pulse width is not recommended. 5 The maximum switching frequency is the maximum signal frequency at which the specified timing parameters are guaranteed. Operation beyond the maximum frequency is not recommended since high switching rates can cause droop in the output supply voltage. 6 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 7 “Channel-to-channel matching, rising or falling matching edge polarity” is the magnitude of the propagation delay difference between two channels of the same part when both inputs are either both rising or falling edges. The loads on each channel are equal. 8 “Channel-to-channel matching, rising vs. falling opposite edge polarity” is the magnitude of the propagation delay difference between two channels of the same part when one input is a rising edge and one input is a falling edge. The loads on each channel are equal. 9 Part-to-part matching is the magnitude of the propagation delay difference between the same channels of two different parts. This includes rising vs. rising, falling vs. falling, or rising vs. falling edges. The supply voltages, temperatures, and loads of each part are equal. Rev. PrG| Page 3 of 12 ADuM6132 PRELIMINARY TECHNICAL DATA PACKAGE CHARACTERISTICS Table 2. Parameter Resistance (Input Side- High Side Output)1 Capacitance (Input to High Side Output)1 Input Capacitance IC Junction-to-Ambient Thermal Resistance 1 Symbol RI-O CI-O CI θJA Min Typ 1012 2.0 4.0 45 Max Unit Ω pF pF °C/W Test Conditions 4-layer PC board The device is considered a two-terminal device: Pins 1-8 are shorted together, and Pins 9-16 are shorted together. REGULATORY INFORMATION The ADuM6132 will be approved by the organizations listed in Table 3. Table 3. UL (pending) Recognized under 1577 component recognition program1 Double/reinforced insulation, 3750 V rms isolation voltage File E214100 1 2 CSA (Pending) Approved under CSA Component Acceptance Notice #5A Basic insulation per CSA 60950-1-03 and IEC 60950-1, 800 V rms (1131 V peak) maximum working voltage Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms maximum working voltage VDE (Pending) Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122 Reinforced insulation, 560 V peak Complies with DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01, DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000, DIN V VDE 0884-10 (VDE V 0884-10):2006-12 File 2471900-4880-0001 File 205078 In accordance with UL1577, each ADuM6132 is proof tested by applying an insulation test voltage ≥ 4500 V rms for 1 second (current leakage detection limit = 10 μA). In accordance with DIN V VDE V 0884-10, each ADuM6132 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 4. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group L(I01) Value 3750 8.0 min Unit V rms mm Conditions 1 minute duration Measured from input terminals to output terminals, shortest distance through air L(I02) 8.0 min mm Measured from input terminals to output terminals, shortest distance path along body 0.017 min mm Insulation distance through insulation >175 V DIN IEC 112/VDE 0303 Part 1 CTI IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Rev. PrG| Page 4 of 12 ADuM6132 PRELIMINARY TECHNICAL DATA DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS The ADuM6132 is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The * marking on the package denotes DIN V VDE V 0884-10 approval. Table 5. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree (DIN VDE 0110, Table 1) Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Safety-Limiting Values Case Temperature Side 1 Current Side 2 Current Insulation Resistance at TS Conditions VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC Symbol Characteristic Unit VIORM VPR I to IV I to III I to II 40/105/21 2 560 1050 V peak V peak 896 672 V peak V peak VTR 6000 V peak TS IS1 IS2 RS 150 265 335 >109 °C mA mA Ω VPR VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 sec Maximum value allowed in the event of a failure; see VIO = 500 V RECOMMENDED OPERATING CONDITIONS Table 6. Parameter Operating Temperature Input Supply Voltage1 Channel B Supply Voltage1 Input Signal Rise and Fall Times Common-Mode Transient Immunity, Input-to-Output 1 Symbol TA VDD VDDB Min −40 4.5 12.5 −50 All voltages are relative to their respective ground. Rev. PrG| Page 5 of 12 Max +105 5.5 17 1 +50 Unit °C V V ms kV/μs ADuM6132 PRELIMINARY TECHNICAL DATA ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Storage Temperature Ambient Operating Temperature Input Supply Voltage1 Channel B Supply Voltage1 Input Voltage1 Output Voltage1 Symbol TST TA Min −55 −40 Max +150 +105 Unit °C °C VDD VDDB −0.5 −0.5 +7.0 +27 V V VIA, VIB VOA, VOB −0.5 −0.5 V V Output DC Current Common-Mode Transients2 IOA, IOB −100 −100 VDDI + 0.5 VISO + 0.5, VDDB + 0.5 +100 +100 1 2 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Ambient temperature = 25°C, unless otherwise noted. mA kV/μs ESD CAUTION All voltages are relative to their respective ground. Refers to common-mode transients across any insulation barrier. Commonmode transients exceeding the Absolute Maximum Ratings can cause latchup or permanent damage. Table 7. Maximum Continuous Working Voltage1 Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform Basic Insulation DC Voltage Basic Insulation Constraint 50-year minimum lifetime 1131 Unit V peak V peak V peak 1131 V peak Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details 600 Safe Operating VDD1 Current (mA) 1 Max 565 500 400 300 200 100 0 0 50 100 150 200 Am bient Tem pearture (°C) Figure 2 Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2 Rev. PrG| Page 6 of 12 ADuM6132 PRELIMINARY TECHNICAL DATA PIN CONFIGURATIONS AND PIN FUNCTION DESCRIPTIONS Figure 3. ADuM6132 Pin Configuration Table 8. ADuM6132 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 Mnemonic VDD GND VDDL VIA VIB VOB VDDB 8 9 10 11 12 13 14 15 16 GND GNDISO NC NC VOA VDDA GNDA GNDISO VISO Function Input supply voltage for isolated power supply, 4.5V to 5.5V Ground reference for isolated power supply input and logic inputs Input supply voltage for logic, 4.5V to 5.5V Logic input A Logic input B Output B (non-isolated). Output B supply voltage input (non-isolated), 12.5V to 17V Ground reference for isolated power supply input and logic inputs Ground reference for isolated power supply output No Connect No Connect Output A (isolated) Output A supply voltage input, must be connected externally to VISO (pin16) Output A ground reference, must be connected externally to GNDISO (pin 15) Ground reference for isolated power supply output Isolated power supply voltage output Table 9. ADuM6132 Truth Table (Positive Logic) VIA Input L L H H X VIB Input L H L H X VDDL State VDDB State Powered Powered Powered Powered Powered VOA Output L L H H L VOB Output L H L H L Powered Powered Powered Powered Unpowered X X Powered Unpowered L L Notes VOA returns to input state within 1 μs of VDD power restoration. Rev. PrG| Page 7 of 12 ADuM6132 PRELIMINARY TECHNICAL DATA Figure 3. Typical Application Circuit APPLICATION INFORMATION PC BOARD LAYOUT TYPICAL APPLICATION USAGE The architecture of the ADuM6132 is ideal for motor drive and inverter applications where the low side channels are common to the controller. This arrangement requires only two isolation regions in a package. All of the isolated signals and Isolated power are grouped on one side of the package so full package creepage and clearance are maintained. The low side drive as well as the control signals share a common reference and are also grouped together. In order to maximize the efficacy of external bypass capacitors, the isoPower DC/DC converter is not internally tied to the data channels, and should be treated as a completely independent subsystem, except for a UVLO function (see Undervoltage lockout). This means that power must be applied to VDD to operate the DC/DC converter. Power must also be applied to VDDL and VDDB to operate the data input and the channel B driver output. On the secondary side, the power generated at the VISO pin must be applied as an input power supply to the VDDA pin. GNDISO and GNDA must be connected together. The ADuM6132 is intended for driving low gate capacitance transistors (200 pF typically). Most high voltage applications involve larger transistors than this. To accommodate these applications, users can implement a buffer configuration with the ADuM6132 as shown in Figure 3. In many cases, this buffer configuration is the least expensive option to drive high capacitance devices and provides the greatest amount of design flexibility. The precise buffer/high voltage transistor combination can be selected to fit the needs of the application. The ADuM6132 digital isolator with integrated 250mW isoPower DC/DC converter requires no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins (Figure 4). The power supply section of the ADuM6132 uses a very high oscillator frequency to efficiently pass power through its chip scale transformers. In addition, the normal operation of the data section of the iCoupler introduces switching transients on the power supply pins. Bypass capacitors are required for several operating frequencies. Noise suppression requires a low ESR high frequency capacitor, ripple suppression and proper regulation require a large value capacitor in parallel, see Table 10. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Supply VDD VDDB VDDL VDDA VISO Pins 1,2 7,8 2,3 13,14 15,16 Bypass Capacitors 0.1μF, 10μF 0.1μF 0.1μF 0.1μF 0.1μF, 10μF Table 10 Recommended Bypass Capacitors In applications involving high common-mode transients, care should be taken to ensure that board capacitive coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the device’s Absolute Maximum Ratings, specified in Error! Reference source not found. leading to latch-up and/or permanent damage. Figure 4. Recommended Printed Circuit Board Layout The ADuM6132 is a power device that dissipates about 1W of power when fully loaded and running at maximum speed. Since it is not possible to apply a heat sink to an isolation device, the device primarily depends on heat dissipation into the PCB through the GND pins. If the device will be used at high ambient temperatures, care should be taken to provide a thermal path from the GND pins to the PCB ground plane. Rev. PrG| Page 8 of 12 ADuM6132 PRELIMINARY TECHNICAL DATA The board layout in Figure 4 shows enlarged pads for pins 8 and 9. Multiple vias should be implemented from the pad to the ground plane. This will significantly reduce the temperatures inside of the chip. The dimensions of the expanded pads are left to discretion of the designer and the available board space. THERMAL ANALYSIS The ADuM6132 parts consist of several internal die, attached to two lead frame paddles. For the purposes of thermal analysis it is treated as a thermal unit with the highest junction temperature reflected in the θJA from Error! Reference source not found. The value of θJA is based on measurements taken with the part mounted on a JEDEC standard 4 layer board with fine width traces and still air. Under normal operating conditions the ADuM6132 will operate at full load across the full temperature range without derating the output current. However, following the recommendations in the PC Board Layout section will decrease the thermal resistance to the PCB allowing increased thermal margin it high ambient temperatures. Table 11. Undervoltage Lockout Functionality Table User-provided supplies VDDB VDDL Supply Supply H H VISOpowered supply VDDA Supply H H H L X L X L X X UNDERVOLTAGE LOCKOUT The ADuM6132 has undervoltage lockout (UVLO) circuits on the VDDL, VDDA, and VDDB supplies. For each supply its respective UVLO circuit monitors the supply voltage and takes a predetermined action based on whether the supply voltage is above or below a given threshold. These thresholds are specified in Table 1. Notes: L: denotes supply voltage < undervoltage lockout threshold H: denotes supply voltage > undervoltage lockout threshold X: denotes supply voltage level is irrelevant When all three supplies are above their respective UVLO thresholds the ADuM6132 operates normally. The internal DC/DC converter is active and both outputs operate as determined by their respective input logic signals. If either of the user-provided supplies is below its UVLO threshold, the ADuM6132 is put into a disabled mode. In this mode the internal DC/DC converter is turned off and both outputs are driven low. The VOB output is driven low by either the VDDL or VDDB UVLO circuit (whichever is below its threshold). The VOA output is driven low as the internal DC/DC converter is turned off. The VISO supply voltage is drops to zero. Since VDDA is connected to VISO, it also is brought down to zero. Once VDDA is below its UVLO threshold VOA is driven low by the VDDA UVLO circuit. PROPAGATION DELAY-RELATED PARAMETERS Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output may differ from the propagation delay to a logic high. INPUT (VIX) 50% tPLH tPHL OUTPUT (VOX) 50% 03786-018 In the recommended configuration of Figure 3 only two independent supplies are controlled by the user: VDDB and VDDL/VDD (VDDL=VDD in Figure 3). VDDA is supplied by the internal DC/DC converter via the VISO=VDDA external connection. Nevertheless, the VDDA UVLO functionality is included in the below table so that the user has an understanding of the VOA output behavior as the internal DC/DC converter powers on and off. Resultant Effect Normal operation. Internal DC/DC converter active. VOA/VOB output logic states match VIA/VIB input logic states. Internal DC/DC converter active but VISO belpow UVLO threshold. VOA output driven low. VOB output operates normally. Internal DC/DC converter turned off (VISO = 0). VOA output driven low. VOB output drive low. Internal DC/DC converter turned off (VISO = 0). VOA output driven low. VOB output drive low. Figure 5. Propagation Delay Parameters Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how Rev. PrG| Page 9 of 12 ADuM6132 PRELIMINARY TECHNICAL DATA MAGNETIC FIELD IMMUNITY The ADuM6132 is extremely immune to external magnetic fields. The limitation on the ADuM6132’s magnetic field immunity is set by the condition in which induced voltage in the transformer’s receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (−dβ / dt )∑ Π rn2 ; n = 1, 2, ...N where: 1000 β is the magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). 10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1 1k 10k 100k 1M 10M 100M MAGNETIC FIELD FREQUENCY (Hz) 100 MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss) 100 0.01 Given the geometry of the receiving coil in the ADuM6132 and an imposed requirement that the induced voltage is at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 6. 10 Figure 7. Maximum Allowable Current for Various Current-to-ADuM6132 Spacings Note that at combinations of strong magnetic fields and high frequencies, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the threshold of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility. INSULATION LIFETIME All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation depends on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices conducts an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM5230. 1 0.1 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M 06401-010 0.01 0.001 1k DISTANCE = 1m 06401-011 Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM6132 component. The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM6132 transformers. Figure 7 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown in Figure 7, the ADuM6132 is extremely immune and can be affected only by extremely large currents operated at high frequency and very close to the component. For the 1 MHz example, one would have to place a 0.5 kA current 5 mm away from the ADuM6132 to affect the component’s operation. MAXIMUM ALLOWABLE CURRENT (kA) accurately the input signal’s timing is preserved. Figure 6. Maximum Allowable External Magnetic Flux Density For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (with the worst-case polarity), it reduces the received pulse from > 1.0 V to 0.75 V. Note that this is still well above the 0.5 V sensing threshold of the decoder. Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. Table 7 summarizes the peak voltages for 50 years of service life for a bipolar ac operating condition and the maximum Analog Devices recommended working voltages. In many cases, the approved working voltage is higher than the 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. The insulation lifetime of the ADuM6132 depends on the Rev. PrG| Page 10 of 12 ADuM6132 PRELIMINARY TECHNICAL DATA RATED PEAK VOLTAGE 06920-014 voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 8, Figure 9, and Figure 10 illustrate these different isolation voltage waveforms. 0V Figure 8. Bipolar AC Waveform Rev. PrG| Page 11 of 12 06920-015 In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 7 can be applied while maintaining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage cases. Any cross insulation voltage waveform that does not conform to Figure 9 or Figure 10 should be treated as a bipolar ac waveform and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 7. Note that the voltage presented in Figure 9 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V. RATED PEAK VOLTAGE 0V Figure 9. Unipolar AC Waveform RATED PEAK VOLTAGE 06920-016 Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the maximum working voltage recommended by Analog Devices. 0V Figure 10. DC Waveform ADuM6132 PRELIMINARY TECHNICAL DATA OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 10.65 (0.4193) 10.00 (0.3937) 8 1 1.27 (0.0500) BSC 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 0.75 (0.0295) × 45° 0.25 (0.0098) 8° 0.33 (0.0130) 0° 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 6. 16-Lead Standard Small Outline Package [SOIC]— Wide Body (RW-16). Dimensions shown in millimeters (inches) ORDERING GUIDE Model ADuM6132ARWZ1 ADuM6132ARWZ-RL1 1 No. of Channels 2 2 Output Peak Current (A) 0.2 0.2 Output Voltage (V) 15 15 Temperature Range −40°C to +105°C −40°C to +105°C Z = Pb-free part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07393-0-3/08(PrG) Rev. PrG| Page 12 of 12 Package Description 16-Lead SOIC_W 16-Lead SOIC_W, 13-inch Tape and Reel Option (1, 000 Units) Package Option RW-16 RW-16