Low Noise, Matched Dual Monolithic Transistor MAT12 Preliminary Technical Data FEATURES PIN CONFIGURATION Low offset voltage (VOS): 50 μV max Very Low Voltage Noise: 1nV/√Hz max @ 100Hz High Gain (hFE): 500 min at IC = 1mA 300 min at IC = 1μA Excellent Log Conformance: rBE = 0.3 Ω Low Offset Voltage Drift: 0.1 μV/ºC max High Gain Bandwidth Product: 200MHz Note: Substrate is connected to case on TO-78 package. Substrate is normally connected to the most negative circuit potential, but can be floated GENERAL DESCRIPTION The design of the MAT12 series of NPN dual monolithic transistors is optimized for very low noise, low drift and low rBE. Exceptional characteristics of the MAT12 include offset voltage of 50 µV max and high current gain (hFE) which is maintained over a wide range of collector current. Device performance is specified over the full temperature range as well as at 25°C. Input protection diodes are provided across the emitter-base junctions to prevent degradation of the device characteristics due to reverse-biased emitter current. The substrate is clamped to the most negative emitter by the parasitic isolation junction created by the protection diodes. This results in complete isolation between the transistors. The MAT12 is ideal for applications where low noise is a priority. The MAT12 can be used as an input stage to make an amplifier with noise voltage of less than 1.0 nV/√Hz at 100 Hz. Other applications, such as log/antilog circuits, may use the excellent logging conformity of the MAT12. Typical bulk resistance is only 0.3 Ω to 0.4 Ω. The MAT12 electrical characteristics approach those of an ideal transistor when operated over a collector current range of 1µA to 10 mA. Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. MAT12 Preliminary Technical Data SPECIFICATIONS ELECTRICAL CHARACTERISTICS; VCB = 15V VCB = 15 V, IO = 10μA, TA = 25°C, unless otherwise specified. Table 1. Parameter Current Gain Symbol Conditions Min Typ hFE IC = 1mA (note 1) -25ºC≤TA≤+85ºC IC = 100μA -25ºC≤TA≤+85ºC IC = 10μA -25ºC≤TA≤+85ºC IC = 1μA -25ºC≤TA≤+85ºC 500 325 500 275 400 225 300 200 605 Max Unit 590 550 485 Current Gain Match ΔhFE 10μA ≤ IC ≤ 1mA (note 2) 0.5 2 % Noise Voltage Density eN IC = 1mA, VCB = 0 (note 3) f O= 10Hz f O= 100Hz f O= 1kHz f O= 10kHz 1.6 0.9 0.85 0.85 2 1 1 1 nV/√Hz nV/√Hz nV/√Hz nV/√Hz Offset Voltage VOS VCB = 0, 1μA ≤ IC ≤ 1mA -25ºC≤TA≤+85ºC 10 50 70 μV uV Offset Voltage Change vs. VCB ΔVOS/ΔVCB 0 ≤ VCB ≤ VMAX (note 4) 1μA ≤ IC ≤ 1mA (note 5) 10 25 μV Offset Voltage Change vs. IC ΔVOS/ΔIC 1μA ≤ IC ≤ 1mA (note 5), VCB=0 5 25 μV Offset Voltage Drift ΔVOS/ΔT -25ºC≤TA≤+85ºC -25ºC≤TA≤+85ºC, VOS trimmed to zero 0.08 0.03 0.3 0.3 μV/ ºC μV/ ºC Breakdown Voltage BVCEO V 40 Gain-Bandwidth Product Collector-Base Leakage Current fT ICBO IC = 100mA, VCE = 10V VCB=VMAX -25ºC≤TA≤+85ºC 200 25 2 Collector-Collector Leakage Current ICC VCC=VMAX (notes 6,7) -25ºC≤TA≤+85ºC 35 3 200 pA nA Collector-Emitter Leakage Current ICES VBE=0 (notes 6,7) -25ºC≤TA≤+85ºC 35 3 200 pA nA Rev. PrA | Page 2 of 4 200 MHz pA nA Preliminary Technical Data MAT12 Input Bias Current IB IC = 10μA -25ºC≤TA≤+85ºC 25 45 nA nA Input Offset Current IOS IC = 10μA -25ºC≤TA≤+85ºC 0.6 8 nA nA Input Offset Current Drift ΔIOS/ΔT IC=10μA (note 6) -25ºC≤TA≤+85ºC 40 90 pA/ºC Offset Current Change vs. VCB ΔIOS/ΔVCB 0 ≤ VCB ≤ VMAX (note 4) 30 70 pA/V Collector Saturation Voltage Output Capacitance Bulk Resistance Collector-Collector Capacitance VCE(SAT) COB rBE CCC IC = 1mA, IB=100μA VCB=15V, IE=0 10μA≤IC≤10mA (note6) VCC = 0 0.05 23 0.3 35 0.1 V pF Ω pF Notes: 1. 2. 3. 4. 5. 6. 7. 0.5 Current gain is guaranteed with Collector-Base Voltage (VCB) swept from 0 to VMAX at the indicated collector currents. Current Gain Match (ΔhFE) defined as: ΔhFE = (100(ΔIB)( hFE min)/IC) Noise Voltage Density is guaranteed, but not 100% tested This is the maximum change in VOS as VCB is swept from 0V to 40V. Measured at IC=10μA and guaranteed by design over the specified range of IC Guaranteed by Design ICC and ICES are verified by measurement of ICBO Rev. PrA | Page 3 of 4 MAT12 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Parameter Collector-Base Voltage (BVCBO) Collector-Emitter Voltage (BVCEO) Collector-Collector Voltage (BVCC) Emitter-Emitter Voltage (BVEE) Collector Current (IC) Emitter Current (IE) Rating 40 V 40V 40V 40V 20 mA 20 mA Storage Temperature Range H Packages Operating Temperature Range Junction Temperature Range RM, CP Packages Lead Temperature (Soldering, 60 sec) −65°C to +150°C −25°C to +85°C −65°C to +150°C 300°C 1 Table 3. Thermal Resistance Package Type TO-78 (H) ESD CAUTION Differential input voltage is limited to 5 V or the supply voltage, whichever is less. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR09044-0-4/10(PrA) Rev. PrA | Page 4 of 4 θJA TBD θJC TBD Unit ºC/W