MX25L6473F

MX25L6473F
MX25L6473F
3V, 64M-BIT [x 1/x 2/x 4]
CMOS MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
Key Features
• Multi I/O Support - Single I/O, Dual I/O and Quad I/O
• Auto Erase and Auto Program Algorithms
• Program Suspend/Resume & Erase Suspend/Resume
• Permanently fixed QE bit, QE=1; and 4 I/O mode is enabled
P/N: PM2212
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REV. 1.1, DEC. 19, 2014
MX25L6473F
Contents
1. FEATURES......................................................................................................................................................... 4
2. GENERAL DESCRIPTION................................................................................................................................ 6
3. PIN CONFIGURATION....................................................................................................................................... 7
4. PIN DESCRIPTION............................................................................................................................................. 7
5. BLOCK DIAGRAM.............................................................................................................................................. 8
6. DATA PROTECTION........................................................................................................................................... 9
Table 1. Protected Area Sizes...............................................................................................................10
Table 2. 8K-bit Secured OTP Definition................................................................................................ 11
7. MEMORY ORGANIZATION.............................................................................................................................. 12
Table 3. Memory Organization..............................................................................................................12
8. DEVICE OPERATION....................................................................................................................................... 13
9. COMMAND DESCRIPTION.............................................................................................................................. 14
Table 4. Command Sets........................................................................................................................14
9-1. Write Enable (WREN)...........................................................................................................................17
9-2. Write Disable (WRDI)............................................................................................................................18
9-3. Read Identification (RDID)....................................................................................................................19
9-4. Read Status Register (RDSR)..............................................................................................................20
9-5. Read Configuration Register (RDCR)...................................................................................................21
9-6. Write Status Register (WRSR)..............................................................................................................24
Table 5. Protection Modes.....................................................................................................................25
9-7. Read Data Bytes (READ).....................................................................................................................27
9-8. Read Data Bytes at Higher Speed (FAST_READ)...............................................................................28
9-9. Dual Read Mode (DREAD)...................................................................................................................29
9-10. 2 x I/O Read Mode (2READ)................................................................................................................30
9-11. Quad Read Mode (QREAD).................................................................................................................31
9-12. 4 x I/O Read Mode (4READ)................................................................................................................32
9-13. Performance Enhance Mode................................................................................................................34
9-14. Performance Enhance Mode Reset......................................................................................................35
9-15. Burst Read............................................................................................................................................36
9-16. Sector Erase (SE).................................................................................................................................37
9-17. Block Erase (BE)..................................................................................................................................38
9-18. Block Erase (BE32K)............................................................................................................................39
9-19. Chip Erase (CE)....................................................................................................................................40
9-20. Page Program (PP)..............................................................................................................................41
9-21. 4 x I/O Page Program (4PP).................................................................................................................42
9-22. Deep Power-down (DP)........................................................................................................................45
9-23. Release from Deep Power-down (RDP), Read Electronic Signature (RES)........................................46
9-24. Read Electronic Manufacturer ID & Device ID (REMS)........................................................................48
Table 6. ID Definitions ..........................................................................................................................49
9-25. Enter Secured OTP (ENSO).................................................................................................................49
9-26. Exit Secured OTP (EXSO)....................................................................................................................49
9-27. Read Security Register (RDSCUR)......................................................................................................50
Table 7. Security Register Definition.....................................................................................................51
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MX25L6473F
9-28. Write Security Register (WRSCUR)......................................................................................................52
9-29. Program Suspend and Erase Suspend................................................................................................53
Table 8. Readable Area of Memory While a Program or Erase Operation is Suspended.....................53
Table 9. Acceptable Commands During Program/Erase Suspend after tPSL/tESL..............................53
Table 10. Acceptable Commands During Suspend (tPSL/tESL not required).......................................54
9-30. Program Resume and Erase Resume..................................................................................................55
9-31. No Operation (NOP).............................................................................................................................56
9-32. Software Reset (Reset-Enable (RSTEN) and Reset (RST))................................................................56
9-33. Read SFDP Mode (RDSFDP)...............................................................................................................57
Table 11. Signature and Parameter Identification Data Values ............................................................58
Table 12. Parameter Table (0): JEDEC Flash Parameter Tables..........................................................59
Table 13. Parameter Table (1): Macronix Flash Parameter Tables.......................................................61
10. POWER-ON STATE........................................................................................................................................ 63
11. Electrical Specifications............................................................................................................................... 64
11-1. Absolute Maximum Ratings..................................................................................................................64
11-2. Capacitance TA = 25°C, f = 1.0 MHz....................................................................................................64
Table 14. DC Characteristics.................................................................................................................66
Table 15. AC Characteristics.................................................................................................................67
12. TIMING ANALYSIS......................................................................................................................................... 69
13. OPERATING CONDITIONS............................................................................................................................ 70
Table 16. Power-Up/Down Voltage and Timing.....................................................................................72
13-1. Initial Delivery State..............................................................................................................................72
14. ERASE AND PROGRAMMING PERFORMANCE......................................................................................... 73
15. DATA RETENTION......................................................................................................................................... 73
16. LATCH-UP CHARACTERISTICS................................................................................................................... 73
17. ORDERING INFORMATION........................................................................................................................... 74
18. PART NAME DESCRIPTION.......................................................................................................................... 75
19. PACKAGE INFORMATION............................................................................................................................. 76
20. REVISION HISTORY ...................................................................................................................................... 78
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REV. 1.1, DEC. 19, 2014
MX25L6473F
64M-BIT [x 1 / x 2 / x 4] CMOS MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
1. FEATURES
GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and Mode 3
• 67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two I/O read mode) structure or 16,777,216 x 4 bits (four I/O mode) structure
• 2048 Equal Sectors with 4K bytes each
- Any Sector can be erased individually
• 256 Equal Blocks with 32K bytes each
- Any Block can be erased individually
• 128 Equal Blocks with 64K bytes each
- Any Block can be erased individually
• Power Supply Operation
- 2.65 ~ 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Permanently fixed QE bit, QE=1 and 4 I/O mode is enabled
PERFORMANCE
• High Performance
VCC = 2.65~3.6V
- Normal read
- 50MHz
- Fast read
- FAST_READ, DREAD, QREAD: 133MHz with 8 dummy cycles
- 2READ: 80MHz with 4 dummy cycle, 133MHz with 8 dummy cycle
- 4READ: 80MHz with 6 dummy cycle, 133MHz with 10 dummy cycle
- Configurable dummy cycle number for 2READ and 4READ operation
- 8/16/32/64 byte Wrap-Around Burst Read Mode
• Low Power Consumption
• Typical 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- BP0-BP3 block group protect
• Additional 8K-bit bit security OTP
- Features unique identifier
- Factory locked identifiable, and customer lockable
• Auto Erase and Auto Program Algorithms
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times
the program pulse width (Any page to be programmed should have page in the erased state first.)
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MX25L6473F
• Status Register Feature
• Command Reset
• Program/Erase Suspend
• Program/Erase Resume
• Electronic Identification
- JEDEC 1-byte Manufacturer ID and 2-byte Device ID
- RES command for 1-byte Device ID
• Support Serial Flash Discoverable Parameters (SFDP) mode
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O mode or Serial Data Input/Output for 4 x I/O mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O mode or Serial Data Input/Output for 4 x I/O mode
• SIO2
- Serial data Input/Output for 4 x I/O mode
• SIO3
- Serial data Input/Output for 4 x I/O mode
• PACKAGE
- 8-pin SOP (200mil)
- 8-WSON (6x5mm)
- All devices are RoHS Compliant and Halogen-free
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MX25L6473F
2. GENERAL DESCRIPTION
MX25L6473F is 64Mb bits Serial Flash memory, which is configured as 8,388,608 x 8 internally. When it is in
four I/O mode, the structure becomes 16,777,216 bits x 4. When it is in two I/O mode, the structure becomes
33,554,432 bits x 2.
MX25L6473F features a serial peripheral interface and software protocol allowing operation on a simple 3-wire
bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a
serial data output (SO). Serial access to the device is enabled by CS# input.
MX25L6473F, MXSMIO® (Serial Multi I/O) flash memory, provides sequential read operation on the whole chip
and multi-I/O features.
When it is in quad I/O mode, the SI pin, SO pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/
dummy bits input and data Input/Output.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis. Erase command is executed on 4K-byte sector, 32K-byte/64K-byte block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status
read command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode.
The MX25L6473F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
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MX25L6473F
3. PIN CONFIGURATION
4. PIN DESCRIPTION
SYMBOL
DESCRIPTION
CS#
Chip Select
Serial Data Input (for 1xI/O)/ Serial Data
SI/SIO0 Input & Output (for 2xI/O mode and 4xI/
O mode)
Serial Data Output (for 1xI/O)/Serial
SO/SIO1 Data Input & Output (for 2xI/O mode
and 4xI/O mode)
SCLK
Clock Input
Serial Data Input & Output (for 4xI/O
SIO2
mode)
8-PIN SOP (200mil)
CS#
SO/SIO1
SIO2
GND
1
2
3
4
8
7
6
5
VCC
SIO3
SCLK
SI/SIO0
8-WSON (6x5mm)
CS#
SO/SIO1
SIO2
GND
P/N: PM2212
1
2
3
4
8
7
6
5
VCC
SIO3
SCLK
SI/SIO0
7
SIO3
Serial data Input/Output for 4 x I/O
mode
VCC
GND
NC
+ 3.0V Power Supply
Ground
No Connection
REV. 1.1, DEC. 19, 2014
MX25L6473F
5. BLOCK DIAGRAM
X-Decoder
Address
Generator
Memory Array
Page Buffer
SI/SIO0
Data
Register
Y-Decoder
SRAM
Buffer
Sense
Amplifier
CS#
SIO2
SIO3
SCLK
Mode
Logic
State
Machine
Clock Generator
Output
Buffer
SO/SIO1
P/N: PM2212
HV
Generator
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MX25L6473F
6. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC
power-up and power-down or from system noise.
•
Valid command length checking: The command length will be checked whether it is at byte base and
completed on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data.
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic
Signature command (RES).
I. Block lock protection
- The Software Protected Mode (SPM) uses (TB, BP3, BP2, BP1, BP0) bits to allow part of memory to be
protected as read only. The protected area definition is shown as table of "Table 1. Protected Area Sizes", the
protected areas are more flexible which may protect various areas by setting value of TB, BP0-BP3 bits.
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MX25L6473F
Table 1. Protected Area Sizes
Protected Area Sizes (T/B bit = 0)
Status bit
BP3
BP2
BP1
BP0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Protected Area Sizes (T/B bit = 1)
Status bit
BP3
BP2
BP1
BP0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Protect Level
64Mb
0 (none)
1 (1block, block 127th)
2 (2blocks, block 126th-127th)
3 (4blocks, block 124th-127th)
4 (8blocks, block 120th-127th)
5 (16blocks, block 112th-127th)
6 (32blocks, block 96th-127th)
7 (64blocks, block 64th-127th)
8 (128blocks, protect all)
9 (128blocks, protect all)
10 (128blocks, protect all)
11 (128blocks, protect all)
12 (128blocks, protect all)
13 (128blocks, protect all)
14 (128blocks, protect all)
15 (128blocks, protect all)
Protect Level
64Mb
0 (none)
1 (1block, block 0th)
2 (2blocks, block 0th-1st)
3 (4blocks, block 0th-3rd)
4 (8blocks, block 0th-7th)
5 (16blocks, block 0th-15th)
6 (32blocks, block 0th-31st)
7 (64blocks, block 0th-63rd)
8 (128blocks, protect all)
9 (128blocks, protect all)
10 (128blocks, protect all)
11 (128blocks, protect all)
12 (128blocks, protect all)
13 (128blocks, protect all)
14 (128blocks, protect all)
15 (128blocks, protect all)
Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1,
BP0) are 0.
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MX25L6473F
II. Additional 8K-bit secured OTP for unique identifier: to provide 8K-bit One-Time Program area for setting
device unique serial number - Which may be set by factory or system maker.
The 8K-bit secured OTP area is composed of two rows of 4K-bit. Customer could lock the first 4K-bit OTP
area and factory could lock the other.
- Security register bit 0 indicates whether the 2nd 4K-bit is locked by factory or not.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR (write security register)
command to set customer lock-down bit1 as "1". Please refer to table of "Table 7. Security Register Definition"
for security register bit definition and table of "Table 2. 8K-bit Secured OTP Definition" for address range
definition.
- To program 8K-bit secured OTP by entering secured OTP mode (with ENSO command), and going through
normal program procedure, and then exiting secured OTP mode by writing EXSO command.
Note: Once lock-down whatever by factory or customer, the corresponding secured area cannot be changed
any more. While in 8K-bit Secured OTP mode, array access is not allowed.
Table 2. 8K-bit Secured OTP Definition
P/N: PM2212
Address range
Size
Lock-down
xxx000~xxx1FF
4096-bit
Determined by Customer
xxx200~xxx3FF
4096-bit
Determined by Factory
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MX25L6473F
7. MEMORY ORGANIZATION
Table 3. Memory Organization
125
250
…
…
…
…
7EFFFFh
…
7F0FFFh
7EF000h
…
7F0000h
2031
7E8000h
7E8FFFh
7E7000h
7E7FFFh
…
2024
2023
7E0000h
7E0FFFh
7DF000h
7DFFFFh
…
2016
2015
2008
7D8000h
7D8FFFh
2007
7D7000h
7D7FFFh
…
251
2032
…
252
7F8FFFh
7F7FFFh
…
126
7F8000h
7F7000h
…
253
7FFFFFh
2039
…
254
Address Range
7FF000h
2040
…
127
…
255
…
2047
…
Sector (4K-byte)
…
Block(64K-byte) Block(32K-byte)
∼
0
0
…
…
…
…
…
01FFFFh
018FFFh
017000h
017FFFh
…
018000h
23
…
24
010000h
010FFFh
15
00F000h
00FFFFh
…
16
8
008000h
008FFFh
7
007000h
007FFFh
0
P/N: PM2212
…
…
020FFFh
01F000h
…
020000h
31
12
000000h
…
1
32
…
2
028FFFh
027FFFh
…
1
028000h
027000h
…
3
02FFFFh
39
…
4
02F000h
40
…
2
…
47
5
000FFFh
REV. 1.1, DEC. 19, 2014
MX25L6473F
8. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended
operation.
2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode
until next CS# falling edge. In standby mode, SO pin of the device is High-Z.
3. When correct command is inputted to this device, it enters active mode and remains in active mode until next
CS# rising edge.
4. For standard single data rate serial mode, input data is latched on the rising edge of Serial Clock(SCLK) and
data is shifted out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as "Figure 1.
Serial Modes Supported (for Normal Serial mode)".
5. For the following instructions: RDCR, RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, 4READ,
QREAD, 2READ, DREAD, RES, and REMS the shifted-in instruction sequence is followed by a data-out
sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN,
WRDI, WRSR, SE, BE, BE32K, CE, PP, 4PP, Suspend, Resume, NOP, RSTEN, RST, ENSO, EXSO, and
WRSCUR, the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and
not executed.
6. While a Write Status Register, Program or Erase operation is in progress, access to the memory array is
neglected and will not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported (for Normal Serial mode)
CPOL
CPHA
shift in
(Serial mode 0)
0
0
SCLK
(Serial mode 3)
1
1
SCLK
SI
shift out
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while
not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial
mode is supported.
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MX25L6473F
9. COMMAND DESCRIPTION
Table 4. Command Sets
Read Commands
I/O
1
1
2
2
4
4
Command
READ
(normal read)
03 (hex)
FAST READ
(fast read
data)
0B (hex)
2READ
(2 x I/O read
command)
BB (hex)
DREAD
(1I / 2O read
command)
3B (hex)
4READ
(4 x I/O read
command)
EB (hex)
QREAD
(1I/4O read
command)
6B (hex)
1st byte
2nd byte
ADD1(8)
ADD1(8)
ADD1
ADD1
ADD1(2)
ADD1(8)
3rd byte
ADD2(8)
ADD2(8)
ADD2
ADD2
ADD2(2)
ADD2(8)
4th byte
ADD3(8)
ADD3(8)
ADD3
ADD3
ADD3(2)
ADD3(8)
5th byte
Action
n bytes read
out until CS#
goes high
Dummy(8)
Dummy*
Dummy(8)
Dummy*
n bytes read n bytes read n bytes read
Quad I/O
read with
out until CS# out by 2 x I/O out by Dual
goes high until CS# goes Output until
configurable
high
CS# goes high dummy cycles
Dummy(8)
Note: *Dummy cycle number will be different, depending on the bit6 (DC) setting of Configuration Register.
Please refer to "Configuration Register" Table.
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MX25L6473F
Other Commands
Command
1st byte
2nd byte
3rd byte
4th byte
Action
Command
1st byte
2nd byte
3rd byte
4th byte
Action
Command
1st byte
2nd byte
3rd byte
4th byte
Action
P/N: PM2212
WRSR
(write status/
4PP (quad
SE
configuration page program) (sector erase)
register)
06 (hex)
04 (hex)
05 (hex)
15 (hex)
01 (hex)
38 (hex)
20 (hex)
Values
ADD1
ADD1
Values
ADD2
ADD2
ADD3
ADD3
sets the (WEL) resets the to read out the to read out the to write new quad input to to erase the
selected
write enable
(WEL) write values of the values of the values of the program the
sector
latch bit
enable latch status register configuration configuration/ selected page
bit
register
status register
RDCR (read
WREN
WRDI
RDSR (read
configuration
(write enable) (write disable) status register)
register)
BE 32K
(block erase
32KB)
BE
(block erase
64KB)
CE
(chip erase)
PP
(page
program)
RDP (Release
DP (Deep
from deep
power down)
power down)
52 (hex)
D8 (hex)
60 or C7 (hex)
02 (hex)
B9 (hex)
ADD1
ADD1
ADD1
ADD2
ADD2
ADD2
ADD3
ADD3
ADD3
to erase the
to erase the to erase whole to program the enters deep
chip
selected page power down
selected 32KB selected 64KB
block
mode
block
PGM/ERS
Resume
(Resumes
Program/
Erase)
7A/30 (hex)
RDID
RES (read
(read identificelectronic ID)
ation)
9F (hex)
to continue
outputs
performing the
JEDEC
suspended
ID: 1-byte
program/erase Manufacturer
sequence
ID & 2-byte
Device ID
AB (hex)
release from program/erase
deep power
operation is
down mode
interrupted
by suspend
command
REMS (read
WRSCUR
electronic
ENSO (enter
EXSO (exit
(write security
manufacturer secured OTP) secured OTP)
register)
& device ID)
AB (hex)
90 (hex)
B1 (hex)
C1 (hex)
x
x
x
x
x
ADD
output the
to enter the
to exit the
to read out
1-byte Device Manufacturer 8K-bit secured 8K-bit secured
OTP mode
ID
ID & Device ID OTP mode
15
PGM/ERS
Suspend
(Suspends
Program/
Erase)
75/B0 (hex)
2F (hex)
to set the
lockdown
bit as
"1" (once
lockdown,
cannot
be update)
REV. 1.1, DEC. 19, 2014
MX25L6473F
Command
(byte)
RDSCUR (read
security register)
RSTEN
(Reset Enable)
RST
(Reset Memory)
1st byte
2nd byte
3rd byte
4th byte
5th byte
2B (hex)
66 (hex)
99 (hex)
to read value of
security register
RDSFDP
5A (hex)
ADD1(8)
ADD2(8)
ADD3(8)
Dummy(8)
Read SFDP
mode
SBL (Set Burst
Length)
C0/ 77 (hex)
NOP
(No
Operation)
00 (hex)
to set Burst
length
Action
Note 1: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the
hidden mode.
Note 2: Before executing RST command, RSTEN command must be executed. If there is any other command to interfere,
the reset operation will be disabled.
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MX25L6473F
9-1.
Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP,
4PP, SE, BE, BE32K, CE, and WRSR which are intended to change the device content, should be set every time
after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes
high.
The SIO[3:1] are don't care.
Figure 2. Write Enable (WREN) Sequence (Command 06)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
06h
High-Z
SO
P/N: PM2212
17
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-2.
Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high.
The WEL bit is reset by following situations:
- Power-up
- WRDI command completion
- WRSR command completion
- PP command completion
- 4PP command completion
- SE command completion
- BE32K command completion
- BE command completion
- CE command completion
- PGM/ERS Suspend command completion
- Softreset command completion
- WRSCUR command completion
Figure 3. Write Disable (WRDI) Sequence (Command 04)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
04h
High-Z
SO
P/N: PM2212
18
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-3.
Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The
Macronix Manufacturer ID and Device ID are listed as table of "Table 6. ID Definitions".
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data
out on SO→ to end RDID operation can use CS# to high at any time during data out.
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the
cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby
stage.
Figure 4. Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
Command
SI
9Fh
Manufacturer Identification
SO
High-Z
7
6
5
MSB
P/N: PM2212
3
2
1
Device Identification
0 15 14 13
3
2
1
0
MSB
19
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-4.
Read Status Register (RDSR)
The RDSR instruction is for reading Status Register. The Read Status Register can be read at any time (even
in program/erase/write status register condition) and continuously. It is recommended to check the Write in
Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is
in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register
data out on SO.
The SIO[3:1] are don't care.
Figure 5. Read Status Register (RDSR) Sequence (Command 05)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
05h
SI
SO
High-Z
Status Register Out
7
6
5
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
P/N: PM2212
4
Status Register Out
20
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-5.
Read Configuration Register (RDCR)
The RDCR instruction is for reading Configuration Register Bits. The Read Configuration Register can be read
at any time (even in program/erase/write configuration register condition). It is recommended to check the Write
in Progress (WIP) bit before sending a new instruction when a program, erase, or write configuration register
operation is in progress.
The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configuration
Register data out on SO.
The SIO[3:1] are don't care.
Figure 6. Read Configuration Register (RDCR) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Mode 0
command
15h
SI
SO
High-Z
Configuration register Out
7
6
5
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
P/N: PM2212
4
Configuration register Out
21
REV. 1.1, DEC. 19, 2014
MX25L6473F
Status Register
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/
write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write
status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/
write status register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write
enable latch. When WEL bit sets to "1", which means the internal write enable latch is set, the device can accept
program/erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable
latch; the device will not accept program/erase/write status register instruction. The program/erase command will
be ignored and will reset WEL bit if it is applied to a protected memory area. To ensure both WIP bit & WEL bit are
both set to 0 and available for next program/erase/operations, WIP bit needs to be confirm to be 0 before polling
WEL bit. After WIP bit confirmed, WEL bit needs to be confirm to be 0.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected
area (as defined in "Table 1. Protected Area Sizes") of the device to against the program/erase instruction
without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the
Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to
against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase (CE) instructions (only if all
Block Protect bits set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default.
Which is un-protected.
QE bit. The Quad Enable (QE) bit, an OTP bit, which is permanently set to "1". The flash always performs Quad
I/O mode.
Status Register
bit7
bit6
Reserved
QE
(Quad
Enable)
Reserved
1= Quad
Enable
Reserved
OTP bit
bit5
BP3
(level of
protected
block)
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
(note 1)
(note 1)
(note 1)
(note 1)
Non-volatile Non-volatile Non-volatile Non-volatile
bit
bit
bit
bit
bit1
bit0
WEL
WIP
(write enable
(write in
latch)
progress bit)
1=write
1=write
enable
operation
0=not write 0=not in write
enable
operation
volatile bit
volatile bit
Note 1: see the "Table 1. Protected Area Sizes".
P/N: PM2212
22
REV. 1.1, DEC. 19, 2014
MX25L6473F
Configuration Register
The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured
after the CR bit is set.
ODS bit
The output driver strength ODS bit are volatile bits, which indicate the output driver level of the device. The
Output Driver Strength is defaulted=1 when delivered from factory. To write the ODS bit requires the Write Status
Register (WRSR) instruction to be executed.
TB bit
The Top/Bottom (TB) bit is a OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect area by BP
bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as “0”, which
means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory device.
To write the TB bit requires the Write Status Register (WRSR) instruction to be executed.
Configuration Register
bit7
bit6
DC
Reserved
(Dummy
Cycle)
bit5
bit4
Reserved
Reserved
x
2READ/
4READ
Dummy
Cycle
x
x
x
volatile
x
x
bit3
TB
(top/bottom
selected)
0=Top area
protect
1=Bottom
area protect
(Default=0)
OTP
bit2
bit1
bit0
Reserved
Reserved
ODS
x
x
0,Output driver
strength=1
1,Output driver
strength=1/4
(Default=0)
x
x
volatile
Note: See "Dummy Cycle and Frequency Table", with "Don't Care" on other Reserved Configuration Registers.
Dummy Cycle and Frequency Table
2READ
4READ
P/N: PM2212
DC
Numbers of Dummy
Cycles
0 (default)
4
1
8
0 (default)
6
1
10
Freq. (MHz)
80 @ 2.65V ≦ VCC < 3V
104 @ VCC ≧ 3V
133
80 @ 2.65V ≦ VCC < 3V
104 @ VCC ≧ 3V
133
23
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-6.
Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before
sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write
Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2,
BP1, BP0) bits to define the protected area of memory (as shown in "Table 1. Protected Area Sizes").
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status
Register data on SI→ CS# goes high.
Figure 7. Write Status Register (WRSR) Sequence (Command 01)
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Mode 0
SI
SO
P/N: PM2212
command
01h
High-Z
Status
Register In
7
6
5
4
3
2
Configuration
Register In
1
0 15 14 13 12 11 10 9
8
MSB
24
REV. 1.1, DEC. 19, 2014
MX25L6473F
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The
Write in Progress (WIP) bit still can be checked out during the Write Status Register cycle is in progress. The
WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write
Enable Latch (WEL) bit is reset.
Table 5. Protection Modes
Mode
Software protection
mode (SPM)
Status register condition
Memory
Status register can be written
in (WEL bit is set to "1") and
the BP0-BP3
bits can be changed
The protected area cannot
be programmed or erased.
Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0, TB) bits of the Status Register, as
shown in "Table 1. Protected Area Sizes".
Software Protected Mode (SPM):
- The WREN instruction may set the WEL bit and can change the values of BP3, BP2, BP1, BP0. The
protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM).
P/N: PM2212
25
REV. 1.1, DEC. 19, 2014
MX25L6473F
Figure 8. WRSR flow
start
WREN command
RDSR command
WEL=1?
No
Yes
WRSR command
Write status register data
RDSR command
WIP=0?
No
Yes
RDSR command
Read WEL=0, BP[3:0],
QE data
Verify OK?
No
Yes
WRSR successfully
P/N: PM2212
WRSR fail
26
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-7.
Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out
on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The
address is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest
address has been reached.
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→3-byte address
on SI →data out on SO→ to end READ operation can use CS# to high at any time during data out.
Figure 9. Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
SI
03
24 ADD Cycles
A23 A22 A21
A3 A2 A1 A0
MSB
SO
Data Out 1
High-Z
D7 D6 D5 D4 D3 D2 D1 D0 D7
MSB
P/N: PM2212
Data Out 2
27
MSB
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-8.
Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be
at any location. The address is automatically increased to the next higher address after each byte data is shifted
out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to
0 when the highest address has been reached.
Read on SPI Mode The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ
instruction code→ 3-byte address on SI→1-dummy byte (default) address on SI→ data out on SO→ to end
FAST_READ operation can use CS# to high at any time during data out. (Please refer to "Figure 10. Read at
Higher Speed (FAST_READ) Sequence (Command 0B)")
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 10. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
0Bh
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
4
3
2
1
0
7
MSB
MSB
P/N: PM2212
5
28
6
5
4
3
2
1
0
7
MSB
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-9.
Dual Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fT. The first address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once
writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 3-byte address
on SI → 8-bit dummy cycle → data out interleave on SIO1 & SIO0 → to end DREAD operation can use CS# to
high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 11. Dual Read Mode Sequence (Command 3B)
CS#
0
1
2
3
4
5
6
7
8
…
Command
SI/SIO0
SO/SIO1
P/N: PM2212
30 31 32
9
SCLK
3B
…
24 ADD Cycle
A23 A22
…
High Impedance
39 40 41 42 43 44 45
A1 A0
8 dummy
cycle
Data Out
1
Data Out
2
D6 D4 D2 D0 D6 D4
D7 D5 D3 D1 D7 D5
29
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-10.
2 x I/O Read Mode (2READ)
The 2READ instruction enables Double Transfer Rate of Serial Flash in read mode. The address is latched on
rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at
a maximum frequency fT. The first address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once
writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address
interleave on SIO1 & SIO0→ 4 dummy cycles(default) on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→
to end 2READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 12. 2 x I/O Read Mode Sequence (Command BB)
CS#
0
1
2
3
4
5
6
7
8
SCLK
…
Command
SI/SIO0
SO/SIO1
18 19 20 21 22 23 24 25 26 27 28 29
9
BB(hex)
High Impedance
12 ADD Cycle
Configurable
Dummy cycles
Data Out
1
Data Out
2
A22 A20
…
A2 A0 P2 P0
D6 D4 D2 D0 D6 D4
A23 A21
…
A3 A1 P3 P1
D7 D5 D3 D1 D7 D5
Note: SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the first two dummy cycles. In other words, P2=P0 or
P3=P1 is necessary.
P/N: PM2212
30
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-11.
Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fQ. The first address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
QREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once
writing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte address
on SI → 8-bit dummy cycle → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD operation can
use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 13. Quad Read Mode Sequence (Command 6B)
CS#
0
1
2
3
4
5
6
7
8
…
Command
SI/SIO0
SO/SIO1
SIO2
SIO3
P/N: PM2212
29 30 31 32 33
9
SCLK
6B
…
24 ADD Cycles
A23 A22
High Impedance
…
38 39 40 41 42
A2 A1 A0
8 dummy cycles
Data Data
Out 1 Out 2
Data
Out 3
D4 D0 D4 D0 D4
D5 D1 D5 D1 D5
High Impedance
D6 D2 D6 D2 D6
High Impedance
D7 D3 D7 D3 D7
31
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-12.
4 x I/O Read Mode (4READ)
The 4READ instruction enables quad throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fQ. The first address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once
writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit.
4 x I/O Read on SPI Mode (4READ) The sequence of issuing 4READ instruction is: CS# goes low→ sending
4READ instruction→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→2+4 dummy cycles (default) →data
out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during
data out. (Please refer to figure below)
Figure 14. 4 x I/O Read Mode Sequence (Command EB)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
8 Bit Instruction
SI/SIO0
SO/SIO1
SIO2
SIO3
6 Address cycles
Configurable
Dummy cycles
(Note 3)
Performance
enhance
indicator (Note 1 & 2)
Data Output
address
bit20, bit16..bit0
P4 P0
data
bit4, bit0, bit4....
High Impedance
address
bit21, bit17..bit1
P5 P1
data
bit5 bit1, bit5....
High Impedance
address
bit22, bit18..bit2
P6 P2
data
bit6 bit2, bit6....
High Impedance
address
bit23, bit19..bit3
P7 P3
data
bit7 bit3, bit7....
EBh
Notes:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
3. The Configurable Dummy Cycle is set by Configuration Register Bit. Please see "Dummy Cycle and
Frequency Table"
P/N: PM2212
32
REV. 1.1, DEC. 19, 2014
MX25L6473F
Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low→ sending
4READ instruction→ 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling
bit P[7:0]→ 4 dummy cycles → data out until CS# goes high → CS# goes low (reduce 4READ instruction) →
24-bit random access address (Please refer to "Figure 15. 4 x I/O Read Enhance Performance Mode Sequence
(Command EB) (SPI Mode)" ).
In the performance-enhancing mode (Notes of "Figure 15. 4 x I/O Read Enhance Performance Mode Sequence
(Command EB) (SPI Mode)"), P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can
make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0];
likewise P[7:0]=FFh, 00h, AAh or 55h. These commands will reset the performance enhance mode. And
afterwards CS# is raised and then lowered, the system then will return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
P/N: PM2212
33
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-13.
Performance Enhance Mode
The device could waive the command cycle bits if the two cycle bits after address cycle toggles. (Please note
"Figure 15. 4 x I/O Read Enhance Performance Mode Sequence (Command EB) (SPI Mode)")
Performance enhance mode is supported for 4READ mode.
“EBh” commands support enhance mode.
After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low
of the first clock as address instead of command cycle.
To exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. Or issue
”FFh” data cycles to exit enhance mode.
Figure 15. 4 x I/O Read Enhance Performance Mode Sequence (Command EB) (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
8 Bit Instruction
SIO2
SIO3
Configurable
Dummy cycles
(Note 2)
Performance
enhance
indicator (Note1)
Data Output
address
bit20, bit16..bit0
P4 P0
data
bit4, bit0, bit4....
High Impedance
address
bit21, bit17..bit1
P5 P1
data
bit5 bit1, bit5....
High Impedance
address
bit22, bit18..bit2
P6 P2
data
bit6 bit2, bit6....
High Impedance
address
bit23, bit19..bit3
P7 P3
data
bit7 bit3, bit7....
EBh
SI/SIO0
SO/SIO1
6 Address cycles
CS#
n+1
...........
n+7 ...... n+9
........... n+13
...........
SCLK
6 Address cycles
Configurable
Dummy cycles
(Note 2)
Performance
enhance
indicator (Note1)
Data Output
SI/SIO0
address
bit20, bit16..bit0
P4 P0
data
bit4, bit0, bit4....
SO/SIO1
address
bit21, bit17..bit1
P5 P1
data
bit5 bit1, bit5....
SIO2
address
bit22, bit18..bit2
P6 P2
data
bit6 bit2, bit6....
SIO3
address
bit23, bit19..bit3
P7 P3
data
bit7 bit3, bit7....
Notes:
1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F, if not using
performance enhance recommend to keep 1 or 0 in performance enhance indicator.
Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF
2. The Configurable Dummy Cycle is set by Configuration Register Bit. Please see "Dummy Cycle and
Frequency Table"
P/N: PM2212
34
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-14.
Performance Enhance Mode Reset
To conduct the Performance Enhance Mode Reset operation in SPI mode, FFh data cycle, 8 clocks, should be
issued in 1I/O sequence.
If the system controller is being Reset during operation, the flash device will return to the standard SPI operation.
The SIO[3:1] are don't care.
Figure 16. Performance Enhance Mode Reset for Fast Read Quad I/O
Mode Bit Reset
for Quad I/O
CS#
Mode 3
SCLK
P/N: PM2212
０ 1
2
3
4
5
Mode ０
6
7
Mode 3
Mode ０
SIO0
FFh
SIO1
Don’t Care
SIO2
Don’t Care
SIO3
Don’t Care
35
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-15.
Burst Read
To set the Burst length, following command operation is required
Issuing command: “C0h” or “77h” in the first Byte (8-clocks), following 4 clocks defining wrap around enable with “0h”
and disable with“1h”.
Next 4 clocks is to define wrap around depth. Definition as following table:
Data
00h
01h
02h
03h
1xh
Wrap Around
Yes
Yes
Yes
Yes
No
Wrap Depth
8-byte
16-byte
32-byte
64-byte
X
The wrap around unit is defined within the wrap-around depth specified region. For example, if it is set to 32byte wrap depth, then address above A5 will be kept, it will read wrap around within A[22:5] specified page. To
exit wrap around, it is required to issue another “C0h” or “77h” command in which data=‘1xh”. Otherwise, wrap
around status will be retained until power down or reset command. To change wrap around depth, it is requried
to issue another “C0h” or “77h” command in which data=“0xh”. SPI “EBh” support wrap around feature after wrap
around enable. The Device ID default without Burst read.
SPI Mode
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
D7
D6
10
11
12
13
14
15
SCLK
Mode 0
SIO
P/N: PM2212
C0h or 77h
36
D5
D4
D3
D2
D1
D0
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-16.
Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used
for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Sector Erase (SE). Any address of the sector (see "Table 3. Memory Organization" ) is a
valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest
eighth of address byte has been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI
→CS# goes high.
The SIO[3:1] are don't care.
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the tSE
timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
sector is protected by BP3~0, the array data will be protected (no change) and the WEL bit still be reset.
Figure 17. Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
24 Bit Address
Command
SI
23 22
20h
2
1
0
MSB
P/N: PM2212
37
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-17.
Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write
Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see "Table 3. Memory
Organization") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte
boundary (the least significant bit of address byte has been latched-in); otherwise, the instruction will be rejected
and not executed.
The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code → 3-byte address on
SI → CS# goes high.
The SIO[3:1] are don't care.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE
timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
block is protected by BP3~0, the array data will be protected (no change) and the WEL bit still be reset.
Figure 18. Block Erase (BE) Sequence (Command D8)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24 Bit Address
23 22
D8h
2
1
0
MSB
P/N: PM2212
38
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-18.
Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (see "Table 3. Memory
Organization" ) is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte
boundary (the least significant bit of address byte has been latched-in); otherwise, the instruction will be rejected
and not executed.
The sequence of issuing BE32K instruction is: CS# goes low → sending BE32K instruction code → 3-byte
address on SI → CS# goes high.
The SIO[3:1] are don't care.
The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during
the tBE32K timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is
cleared. If the block is protected by BP3~0, the array data will be protected (no change) and the WEL bit still be
reset.
Figure 19. Block Erase 32KB (BE32K) Sequence (Command 52)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24 Bit Address
23 22
52h
2
1
0
MSB
P/N: PM2212
39
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-19.
Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN)
instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The
CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low → sending CE instruction code → CS# goes high.
The SIO[3:1] are don't care.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE
timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
chip is protected the Chip Erase (CE) instruction will not be executed, but WEL will be reset.
Figure 20. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
P/N: PM2212
60h or C7h
40
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-20.
Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device
programs only the last 256 data bytes sent to the device. The last address byte (the 8 least significant address
bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that
exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently
selected page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the
requested page and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256,
the data will be programmed at the requested address of the page. There will be no effort on the other data bytes
of the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on
SI→ at least 1-byte on data on SI→ CS# goes high.
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary (the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be
executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during
the tPP timing, and clearse when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is
cleared. If the page is protected by BP3~0, the array data will be protected (no change) and the WEL bit will still
be reset.
The SIO[3:1] are don't care.
Figure 21. Page Program (PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
1
0
7
6
5
3
2
1
0
2079
2
2078
3
2077
23 22 21
02h
SI
Data Byte 1
2076
24-Bit Address
2075
Command
4
1
0
MSB
MSB
2074
2073
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
CS#
SCLK
Data Byte 2
SI
7
6
MSB
P/N: PM2212
5
4
3
2
Data Byte 3
1
0
7
6
5
MSB
4
3
2
Data Byte 256
1
0
7
6
5
4
3
2
MSB
41
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-21.
4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must be executed to set the Write Enable Latch (WEL) bit. The Quad Page Programming takes
four pins: SIO0, SIO1, SIO2, and SIO3, which can raise programmer performance and the effectiveness of
application of lower clock less than f4PP. For system with faster clock, the Quad page program cannot provide
more performance, because the required internal page program time is far more than the time data flows in.
Therefore, we suggest that while executing this command (especially during sending data), user can slow the
clock speed down to f4PP below. The other function descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high.
If the page is protected by BP3~0, the array data will be protected (no change) and the WEL bit will still be reset.
Figure 22. 4 x I/O Page Program (4PP) Sequence (Command 38)
CS#
0
1
2
3
4
5
6
7
8
SCLK
…
Command
6 ADD cycles
Data
Byte 256
Data Data
Byte 1 Byte 2
A20 A16 A12 A8 A4 A0 D4 D0 D4 D0
…
D4 D0
SO/SIO1
A21 A17 A13 A9 A5 A1 D5 D1 D5 D1
…
D5 D1
SIO2
A22 A18 A14 A10 A6 A2 D6 D2 D6 D2
…
D6 D2
SIO3
A23 A19 A15 A11 A7 A3 D7 D3 D7 D3
…
D7 D3
SI/SIO0
P/N: PM2212
524 525
9 10 11 12 13 14 15 16 17
38
42
REV. 1.1, DEC. 19, 2014
MX25L6473F
The Program/Erase function instruction function flow is as follows:
Figure 23. Program/Erase Flow(1) with read array data
Start
WREN command
RDSR command*
No
WEL=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
Read array data
(same address of PGM/ERS)
Verify OK?
No
Yes
Program/erase fail
Program/erase successfully
Program/erase
another block?
No
Yes
*
* Issue RDSR to check BP[3:0].
Program/erase completed
P/N: PM2212
43
REV. 1.1, DEC. 19, 2014
MX25L6473F
Figure 24. Program/Erase Flow(2) without read array data
Start
WREN command
RDSR command*
No
WEL=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
RDSCUR command
Yes
P_FAIL/E_FAIL=1?
No
Program/erase fail
Program/erase successfully
Program/erase
Yes
another block?
* Issue RDSR to check BP[3:0].
No
Program/erase completed
P/N: PM2212
44
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-22.
Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device to minimum power consumption (the standby
current is reduced from ISB1 to ISB2.) The Deep Power-down mode requires the Deep Power-down (DP)
instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase
instructions are ignored. When CS# goes high, the device is in standby mode, not deep power-down mode.
The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high.
The SIO[3:1] are don't care when during this mode.
Once the DP instruction is set, all instructions will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When
Power-down, the deep power-down mode automatically stops, and when power-up, the device automatically is
in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of
instruction code has been latched-in); otherwise, the instruction will not be executed. As soon as Chip Select (CS#)
goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to
ISB2.
Figure 25. Deep Power-down (DP) Sequence (Command B9)
CS#
0
1
2
3
4
5
6
7
tDP
SCLK
Command
SI
B9h
Stand-by Mode
P/N: PM2212
45
Deep Power-down Mode
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-23.
Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When
Chip Select (CS#) is driven High, the device is put in the standby Power mode. If the device was not previously in
the Deep Power-down mode, the transition to the standby Power mode is immediate. If the device was previously
in the Deep Power-down mode, though, the transition to the standby Power mode is delayed by tRES2, and Chip
Select (CS#) must remain High for at least tRES2(max), as specified in "Table 15. AC Characteristics". Once in
the standby mode, the device waits to be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 6.
ID Definitions". This is not the same as RDID instruction. It is not recommended to use for new design. For new
design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to
be executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current
program/erase/write cycles in progress.
The SIO[3:1] are don't care in this mode.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs
repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not
previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was
previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must
remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can
receive, decode, and execute instruction.
The RDP instruction is for releasing from Deep Power-down Mode.
Figure 26. Read Electronic Signature (RES) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
SI
ABh
tRES2
3 Dummy Bytes
23 22 21
3
2
1
0
MSB
SO
Electronic Signature Out
High-Z
7
6
5
4
3
2
1
0
MSB
Deep Power-down Mode
P/N: PM2212
46
Stand-by Mode
REV. 1.1, DEC. 19, 2014
MX25L6473F
Figure 27. Release from Deep Power-down (RDP) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
tRES1
7
SCLK
Mode 0
Command
SI
SO
ABh
High-Z
Deep Power-down Mode
P/N: PM2212
47
Stand-by Mode
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-24.
Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both
the JEDEC assigned manufacturer ID and the specific device ID.
The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is
initiated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one
bytes address (A7~A0). After which, the Manufacturer ID for Macronix (C2h) and the Device ID are shifted out
on the falling edge of SCLK with most significant bit (MSB) first. The Device ID values are listed in "Table 6. ID
Definitions". If the one-byte address is initially set to 01h, then the device ID will be read first and then followed
by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the
other. The instruction is completed by driving CS# high.
Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence
CS#
SCLK
Mode 3
0
1
2
Mode 0
3
4
5
6
7
8
Command
SI
9 10
2 Dummy Bytes
15 14 13
90h
3
2
1
0
High-Z
SO
CS#
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
ADD (1)
SI
7
6
5
4
3
2
1
0
Manufacturer ID
SO
7
6
MSB
5
4
3
2
1
Device ID
0
7
6
5
4
3
2
MSB
1
0
7
MSB
Note:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.
P/N: PM2212
48
REV. 1.1, DEC. 19, 2014
MX25L6473F
Table 6. ID Definitions
Command Type
RDID
Manufactory ID
C2
RES
REMS
9-25.
Manufactory ID
C2
MX25L6473F
Memory type
20
Electronic ID
16
Device ID
16
Memory density
17
Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 8K-bit Secured OTP mode. While the device is in 8K-bit
Secured OTP mode, array access is not available. The additional 8K-bit Secured OTP is independent from main
array, and may be used to store unique serial number for system identifier. After entering the Secured OTP
mode, follow standard read or program procedure to read out the data or update data.
The Secured OTP data cannot be updated again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
The SIO[3:1] are don't care.
Please note that WRSR/WRSCUR/CE/BE/SE/BE32K commands are not acceptable during the access of secure
OTP region, once Security OTP is locked down, only read related commands are valid.
9-26.
Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 8K-bit Secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
The SIO[3:1] are don't care.
P/N: PM2212
49
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-27.
Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→ sending RDSCUR instruction → Security
Register data out on SO→ CS# goes high.
The SIO[3:1] are don't care.
Figure 29. Read Security Register (RDSCUR) Sequence (Command 2B)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
2B
SI
SO
High-Z
Security Register Out
7
6
5
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
P/N: PM2212
4
Security Register Out
50
REV. 1.1, DEC. 19, 2014
MX25L6473F
The definition of the Security Register is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before exfactory or not. When it is "0", it indicates non-factory lock; "1" indicates factory- lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for
customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 1st 4K-bit
Secured OTP area cannot be updated any more.
Program Suspend Status bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation.
Users may use PSB to identify the state of flash memory. After the flash memory is suspended by Program
Suspend command, PSB is set to "1". PSB is cleared to "0" after program operation resumes.
Erase Suspend Status bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users
may use ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend
command, ESB is set to "1". ESB is cleared to "0" after erase operation resumes.
Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. If the program
operation fails on a protected memory region, this bit will also be set. This bit can be the failure indication of
one or more program operations. This fail flag bit will be cleared automatically after the next successful program
operation.
Erase Fail Flag bit. While an erase failure happened, the Erase Fail Flag bit would be set. If the erase operation
fails on a protected memory region, this bit will also be set. This bit can be the failure indication of one or more
erase operations. This fail flag bit will be cleared automatically after the next successful erase operation.
Table 7. Security Register Definition
bit7
Reserved
bit6
bit5
E_FAIL
P_FAIL
0=normal
Erase
succeed
0=normal
Program
succeed
1=indicate
Erase failed
(default=0)
1=indicate
Program
failed
(default=0)
non-volatile
bit
volatile bit
volatile bit
Reserved
Read Only
Read Only
Reserved
P/N: PM2212
bit4
bit3
bit2
Reserved
Erase
Suspend
status
Program
Suspend
status
Reserved
volatile bit
bit1
bit0
Secured OTP
LDSO
Indicator bit
(lock-down
(2nd 4K-bit
1st 4K-bit
Secured OTP) Secured OTP)
0 = not
0=Program
lockdown
is not
0 = nonfactory
1 = lock-down
suspended
lock
(cannot
1 = factory
program/
1=Erase is 1=Program
lock
erase
suspended is suspended
OTP)
(default=0) (default=0)
0=Erase
is not
suspended
volatile bit
volatile bit non-volatile bit non-volatile bit
Read Only
Read Only
51
OTP
Read Only
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-28.
Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the
WREN instruction is required before sending WRSCUR instruction. The WRSCUR instruction may change the
values of bit1 (LDSO bit) for customer to lock-down the 1st 4K-bit Secured OTP area. Once the LDSO bit is set
to "1", the 1st 4K-bit Secured OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes
high.
The SIO[3:1] are don't care.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
Figure 30. Write Security Register (WRSCUR) Sequence (Command 2F) (SPI mode)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
SO
P/N: PM2212
2F
High-Z
52
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-29. Program Suspend and Erase Suspend
The Suspend instruction interrupts a Page Program, Sector Erase, or Block Erase operation to allow access to
the memory array. After the program or erase operation has entered the suspended state, the memory array can
be read except for the page being programmed or the sector or block being erased ("Table 8. Readable Area of
Memory While a Program or Erase Operation is Suspended").
Table 8. Readable Area of Memory While a Program or Erase Operation is Suspended
Suspended Operation
Readable Region of Memory Array
Page Program
All but the Page being programmed
Sector Erase (4KB)
All but the 4KB Sector being erased
Block Erase (32KB)
All but the 32KB Block being erased
Block Erase (64KB)
All but the 64KB Block being erased
When the serial flash receives the Suspend instruction, there is a latency of tPSL or tESL ("Figure 31. Suspend to
Read Latency") before the Write Enable Latch (WEL) bit clears to “0” and the PSB or ESB sets to “1”, after which
the device is ready to accept one of the commands listed in "Table 9. Acceptable Commands During Program/
Erase Suspend after tPSL/tESL" (e.g. FAST READ). Refer to "Table 15. AC Characteristics" for tPSL and tESL
timings. "Table 10. Acceptable Commands During Suspend (tPSL/tESL not required)" lists the commands for
which the tPSL and tESL latencies do not apply. For example, RDSR, RDSCUR, RSTEN, and RST can be
issued at any time after the Suspend instruction.
Security Register bit 2 (PSB) and bit 3 (ESB) can be read to check the suspend status. The PSB (Program
Suspend Bit) sets to “1” when a program operation is suspended. The ESB (Erase Suspend Bit) sets to “1”
when an erase operation is suspended. The PSB or ESB clears to “0” when the program or erase operation is
resumed.
Table 9. Acceptable Commands During Program/Erase Suspend after tPSL/tESL
Command Name
Command Code
READ
03h
FAST READ
0Bh
DREAD
3Bh
QREAD
6Bh
2READ
BBh
4READ
EBh
RDSFDP
5Ah
RDID
9Fh
REMS
90h
ENSO
B1h
EXSO
C1h
WREN
06h
RESUME
7Ah or 30h
PP
02h
4PP
38h
P/N: PM2212
Suspend Type
Program Suspend
Erase Suspend
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
53
REV. 1.1, DEC. 19, 2014
MX25L6473F
Table 10. Acceptable Commands During Suspend (tPSL/tESL not required)
Command Name
Command Code
WRDI
04h
RDSR
05h
RDCR
15h
RDSCUR
2Bh
RES
ABh
RSTEN
66h
RST
99h
NOP
00h
Suspend Type
Program Suspend
Erase Suspend
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Figure 31. Suspend to Read Latency
CS#
Suspend Command
tPSL / tESL
Read Command
tPSL: Program Latency
tESL: Erase Latency
Figure 32. Resume to Suspend Latency
CS#
Resume Command
tPRS / tERS
Suspend
Command
tPRS: Program Resume to another Suspend
tERS: Erase Resume to another Suspend
P/N: PM2212
54
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-29-1. Erase Suspend to Program
The “Erase Suspend to Program” feature allows Page Programming while an erase operation is suspended.
Page Programming is permitted in any unprotected memory except within the sector of a suspended Sector
Erase operation or within the block of a suspended Block Erase operation. The Write Enable (WREN) instruction
must be issued before any Page Program instruction.
A Page Program operation initiated within a suspended erase cannot itself be suspended and must be allowed
to finish before the suspended erase can be resumed. The Status Register can be polled to determine the status
of the Page Program operation. The WEL and WIP bits of the Status Register will remain “1” while the Page
Program operation is in progress and will both clear to “0” when the Page Program operation completes.
Figure 33. Suspend to Program Latency
CS#
Suspend Command
tPSL / tESL
Program Command
tPSL: Program Latency
tESL: Erase Latency
9-30.
Program Resume and Erase Resume
The Resume instruction resumes a suspended Page Program, Sector Erase, or Block Erase operation. Before
issuing the Resume instruction to restart a suspended erase operation, make sure that there is no Page Program
operation in progress.
Immediately after the serial flash receives the Resume instruction, the WEL and WIP bits are set to “1” and the
PSB or ESB is cleared to “0”. The program or erase operation will continue until finished ("Figure 34. Resume to
Read Latency") or until another Suspend instruction is received. A resume-to-suspend latency of tPRS or tERS
must be observed before issuing another Suspend instruction ("Figure 32. Resume to Suspend Latency").
Please note that the Resume instruction will be ignored if the serial flash is in “Performance Enhance Mode”.
Make sure the serial flash is not in “Performance Enhance Mode” before issuing the Resume instruction.
Figure 34. Resume to Read Latency
CS#
P/N: PM2212
Resume Command
tSE/tBE/tBE32K/tPP
Read Command
55
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-31.
No Operation (NOP)
The "No Operation" command is only able to terminate the Reset Enable (RSTEN) command and will not affect
any other command.
9-32.
Software Reset (Reset-Enable (RSTEN) and Reset (RST))
The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST)
command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which
makes the device return to the default status as power on.
To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the
Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable
will be invalid.
If the Reset command is executed during program or erase operation, the operation will be disabled, the data
under processing could be damaged or lost.
The reset time is different depending on the last operation. Longer latency time is required to recover from a
program operation than from other operations.
Figure 35. Software Reset Recovery
Stand-by Mode
CS#
66
99
tRCR
tRCP
tRCE
Mode
P/N: PM2212
56
REV. 1.1, DEC. 19, 2014
MX25L6473F
9-33.
Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the
functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These
parameter tables can be interrogated by host system software to enable adjustments needed to accommodate
divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC
Standard, JESD68 on CFI.
The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3
address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation
can use CS# to high at any time during data out.
SFDP is a JEDEC Standard, JESD216.
Figure 36. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
5Ah
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
MSB
P/N: PM2212
57
5
4
3
2
1
0
7
MSB
6
5
4
3
2
1
0
7
MSB
REV. 1.1, DEC. 19, 2014
MX25L6473F
Table 11. Signature and Parameter Identification Data Values
SFDP Table below is for MX25L6473FM2I-08G and MX25L6473FZNI-08G
Description
SFDP Signature
Comment
Fixed: 50444653h
Add (h) DW Add Data (h/b) Data
(Byte)
(Bit)
(Note1)
(h)
00h
07:00
53h
53h
01h
15:08
46h
46h
02h
23:16
44h
44h
03h
31:24
50h
50h
SFDP Minor Revision Number
Start from 00h
04h
07:00
00h
00h
SFDP Major Revision Number
Start from 01h
This number is 0-based. Therefore,
0 indicates 1 parameter header.
05h
15:08
01h
01h
06h
23:16
01h
01h
07h
31:24
FFh
FFh
00h: it indicates a JEDEC specified
header.
08h
07:00
00h
00h
Start from 00h
09h
15:08
00h
00h
Start from 01h
0Ah
23:16
01h
01h
How many DWORDs in the
Parameter table
0Bh
31:24
09h
09h
0Ch
07:00
30h
30h
0Dh
15:08
00h
00h
0Eh
23:16
00h
00h
0Fh
31:24
FFh
FFh
it indicates Macronix manufacturer
ID
10h
07:00
C2h
C2h
Start from 00h
11h
15:08
00h
00h
Start from 01h
12h
23:16
01h
01h
How many DWORDs in the
Parameter table
13h
31:24
04h
04h
14h
07:00
60h
60h
15h
15:08
00h
00h
16h
23:16
00h
00h
17h
31:24
FFh
FFh
Number of Parameter Headers
Unused
ID number (JEDEC)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
First address of JEDEC Flash
Parameter table
Unused
ID number
(Macronix manufacturer ID)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
First address of Macronix Flash
Parameter table
Unused
P/N: PM2212
58
REV. 1.1, DEC. 19, 2014
MX25L6473F
Table 12. Parameter Table (0): JEDEC Flash Parameter Tables
SFDP Table below is for MX25L6473FM2I-08G and MX25L6473FZNI-08G
Description
Comment
Block/Sector Erase sizes
00: Reserved, 01: 4KB erase,
10: Reserved,
11: not support 4KB erase
Write Granularity
0: 1Byte, 1: 64Byte or larger
Write Enable Instruction Required 0: not required
1: required 00h to be written to the
for Writing to Volatile Status
status register
Registers
Add (h) DW Add Data (h/b)
(Byte)
(Bit)
(Note1)
01b
02
1b
03
0b
30h
0: use 50h opcode,
1: use 06h opcode
Write Enable Opcode Select for
Note: If target flash status register is
Writing to Volatile Status Registers
nonvolatile, then bits 3 and 4 must
be set to 00b.
Contains 111b and can never be
Unused
changed
4KB Erase Opcode
01:00
31h
Data
(h)
E5h
04
0b
07:05
111b
15:08
20h
16
1b
18:17
00b
19
0b
20
1b
20h
(1-1-2) Fast Read (Note2)
0=not support 1=support
Address Bytes Number used in
addressing flash array
Double Transfer Rate (DTR)
Clocking
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
(1-2-2) Fast Read
0=not support 1=support
(1-4-4) Fast Read
0=not support 1=support
21
1b
(1-1-4) Fast Read
0=not support 1=support
22
1b
23
1b
33h
31:24
FFh
37h:34h
31:00
03FF FFFFh
0=not support 1=support
32h
Unused
Unused
Flash Memory Density
(1-4-4) Fast Read Number of Wait
states (Note3)
(1-4-4) Fast Read Number of
Mode Bits (Note4)
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8
Mode Bits:
000b: Not supported; 010b: 2 bits
(1-4-4) Fast Read Opcode
(1-1-4) Fast Read Number of Wait
states
(1-1-4) Fast Read Number of
Mode Bits
39h
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8
Mode Bits:
000b: Not supported; 010b: 2 bits
(1-1-4) Fast Read Opcode
P/N: PM2212
38h
3Ah
3Bh
59
04:00
0 0100b
07:05
010b
15:08
EBh
20:16
0 1000b
23:21
000b
31:24
6Bh
F1h
FFh
44h
EBh
08h
6Bh
REV. 1.1, DEC. 19, 2014
MX25L6473F
SFDP Table below is for MX25L6473FM2I-08G and MX25L6473FZNI-08G
Description
Comment
(1-1-2) Fast Read Number of Wait
states
(1-1-2) Fast Read Number of
Mode Bits
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8
Mode Bits:
000b: Not supported; 010b: 2 bits
(1-1-2) Fast Read Opcode
(1-2-2) Fast Read Number of Wait
states
(1-2-2) Fast Read Number of
Mode Bits
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8
Mode Bits:
000b: Not supported; 010b: 2 bits
3Eh
3Fh
0=not support 1=support
Unused
(4-4-4) Fast Read
3Ch
3Dh
(1-2-2) Fast Read Opcode
(2-2-2) Fast Read
Add (h) DW Add Data (h/b)
(Byte)
(Bit)
(Note1)
0=not support 1=support
40h
Unused
04:00
0 1000b
07:05
000b
15:08
3Bh
20:16
0 0100b
23:21
000b
31:24
BBh
00
0b
03:01
111b
04
0b
07:05
111b
Data
(h)
08h
3Bh
04h
BBh
EEh
Unused
43h:41h
31:08
FFh
FFh
Unused
45h:44h
15:00
FFh
FFh
20:16
0 0000b
23:21
000b
47h
31:24
FFh
FFh
49h:48h
15:00
FFh
FFh
20:16
0 0000b
23:21
000b
4Bh
31:24
FFh
FFh
4Ch
07:00
0Ch
0Ch
4Dh
15:08
20h
20h
4Eh
23:16
0Fh
0Fh
4Fh
31:24
52h
52h
50h
07:00
10h
10h
51h
15:08
D8h
D8h
52h
23:16
00h
00h
53h
31:24
FFh
FFh
(2-2-2) Fast Read Number of Wait
states
(2-2-2) Fast Read Number of
Mode Bits
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8
Mode Bits:
000b: Not supported; 010b: 2 bits
(2-2-2) Fast Read Opcode
Unused
(4-4-4) Fast Read Number of Wait
states
(4-4-4) Fast Read Number of
Mode Bits
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8
Mode Bits:
000b: Not supported; 010b: 2 bits
(4-4-4) Fast Read Opcode
Sector Type 1 Size
Sector/block size = 2^N bytes (Note5)
0Ch: 4KB; 0Fh: 32KB; 10h: 64KB
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size = 2^N bytes
00h: N/A; 0Fh: 32KB; 10h: 64KB
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size = 2^N bytes
00h: N/A; 0Fh: 32KB; 10h: 64KB
Sector Type 3 erase Opcode
Sector Type 4 Size
00h: N/A, This sector type doesn't
exist
Sector Type 4 erase Opcode
P/N: PM2212
60
46h
4Ah
00h
00h
REV. 1.1, DEC. 19, 2014
MX25L6473F
Table 13. Parameter Table (1): Macronix Flash Parameter Tables
SFDP Table below is for MX25L6473FM2I-08G and MX25L6473FZNI-08G
Description
Vcc Supply Maximum Voltage
Vcc Supply Minimum Voltage
Comment
2000h=2.000V
2700h=2.700V
3600h=3.600V
1650h=1.650V, 1750h=1.750V
2250h=2.250V, 2300h=2.300V
2350h=2.350V, 2650h=2.650V
2700h=2.700V
Add (h) DW Add Data (h/b)
(Byte)
(Bit)
(Note1)
Data
(h)
61h:60h
07:00
15:08
00h
36h
00h
36h
63h:62h
23:16
31:24
50h
26h
50h
26h
H/W Reset# pin
0=not support 1=support
00
0b
H/W Hold# pin
0=not support 1=support
01
0b
Deep Power Down Mode
0=not support 1=support
02
1b
S/W Reset
0=not support 1=support
03
1b
S/W Reset Opcode
Reset Enable (66h) should be
issued before Reset Opcode
Program Suspend/Resume
0=not support 1=support
12
1b
Erase Suspend/Resume
0=not support 1=support
13
1b
14
1b
15
1b
66h
23:16
77h
77h
67h
31:24
64h
64h
65h:64h
Unused
Wrap-Around Read mode
0=not support 1=support
Wrap-Around Read mode Opcode
11:04
1001 1001b
F99Ch
(99h)
Wrap-Around Read data length
08h:support 8B wrap-around read
16h:8B&16B
32h:8B&16B&32B
64h:8B&16B&32B&64B
Individual block lock
0=not support 1=support
00
0b
Individual block lock bit
(Volatile/Nonvolatile)
0=Volatile 1=Nonvolatile
01
1b
09:02
1111 1111b
(FFh)
10
1b
11
1b
Individual block lock Opcode
Individual block lock Volatile
protect bit default protect status
0=protect 1=unprotect
Secured OTP
0=not support 1=support
Read Lock
0=not support 1=support
12
0b
Permanent Lock
0=not support 1=support
13
0b
Unused
15:14
11b
Unused
31:16
FFh
FFh
31:00
FFh
FFh
Unused
6Bh:68h
6Fh:6Ch
CFFEh
MX25L6473FM2I-08G-SFDP_2014-11-20,SF10
P/N: PM2212
61
REV. 1.1, DEC. 19, 2014
MX25L6473F
Note 1:h/b is hexadecimal or binary.
Note 2:(x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),
address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1),
(2-2-2), and (4-4-4)
Note 3:Wait States is required dummy clock cycles after the address bits or optional mode bits.
Note 4:Mode Bits is optional control bits that follow the address bits. These bits are driven by the system
controller if they are specified. (eg,read performance enhance toggling bits)
Note 5:4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 6:All unused and undefined area data is blank FFh for SFDP Tables that are defined in Parameter
Identification Header. All other areas beyond defined SFDP Table are reserved by Macronix.
P/N: PM2212
62
REV. 1.1, DEC. 19, 2014
MX25L6473F
10. POWER-ON STATE
The device is at the following states after power-up:
- Standby mode
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage until the VCC reaches the following
levels:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal Power-on Reset (POR) circuit may protect the device from data corruption and inadvertent data
change during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is
not guaranteed. The read, write, erase, and program command should be sent after the time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is
recommended. (generally around 0.1uF)
P/N: PM2212
63
REV. 1.1, DEC. 19, 2014
MX25L6473F
11. Electrical Specifications
11-1.
Absolute Maximum Ratings
RATING
VALUE
Ambient Operating Temperature
Industrial grade
-40°C to 85°C
Storage Temperature
-65°C to 150°C
Applied Input Voltage
-0.5V to 4.6V
Applied Output Voltage
-0.5V to 4.6V
VCC to Ground Potential
-0.5V to 4.6V
NOTICE:
1.Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is stress rating only and functional operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2.Specifications contained within the following tables are subject to change.
3.During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see
the figures below.
Figure 37. Maximum Negative Overshoot Waveform
20ns
Figure 38. Maximum Positive Overshoot Waveform
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
11-2.
Capacitance TA = 25°C, f = 1.0 MHz
Symbol Parameter
CIN
COUT
P/N: PM2212
20ns
Min.
Typ.
Max.
Unit
Input Capacitance
6
pF
VIN = 0V
Output Capacitance
8
pF
VOUT = 0V
64
Conditions
REV. 1.1, DEC. 19, 2014
MX25L6473F
Figure 39. Input Test Waveforms and Measurement Level
Input timing reference level
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Output timing reference level
AC
Measurement
Level
0.5VCC
Note: Input pulse rise and fall time are <2.4ns
Figure 40. Output Loading
DEVICE UNDER
TEST
2.7K ohm
CL
6.2K ohm
+3.3V
DIODES=IN3064
OR EQUIVALENT
CL=30/15pF Including jig capacitance
P/N: PM2212
65
REV. 1.1, DEC. 19, 2014
MX25L6473F
Table 14. DC Characteristics
Temperature = -40°C to 85°C for Industrial grade
Symbol Parameter
Notes
Min.
Typ.
Max.
ILI
Input Load Current
1
±2
ILO
Output Leakage Current
1
±2
ISB1
VCC Standby Current
1
ISB2
Deep Power-down
Current
ICC1
VCC Read
Units Test Conditions
VCC = VCC Max,
uA
VIN = VCC or GND
VCC = VCC Max,
uA
VOUT = VCC or GND
10
50
uA
VIN = VCC or GND, CS# = VCC
3
20
uA
VIN = VCC or GND, CS# = VCC
10
17
mA
fQ=133MHz (4 x I/O read)
SCLK=0.1VCC/0.9VCC,
SO=Open
2.5
5
mA
f=50MHz,
SCLK=0.1VCC/0.9VCC,
SO=Open
10
15
mA
Program in Progress, CS# =
VCC
10
15
mA
Program status register in
progress, CS#=VCC
1
ICC2
VCC Program Current
(PP)
ICC3
VCC Write Status
Register (WRSR) Current
ICC4
VCC Sector Erase
Current (SE)
1
10
15
mA
Erase in Progress, CS#=VCC
ICC5
VCC Chip Erase Current
(CE)
1
10
15
mA
Erase in Progress, CS#=VCC
1
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
0.7VCC
VCC+0.4
V
VOL
Output Low Voltage
0.4
V
IOL = 1.6mA
VOH
Output High Voltage
V
IOH = -100uA
VCC-0.2
Notes :
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and
speeds).
2.Typical value is calculated by simulation.
3.The value guaranteed by characterization, not 100% tested in production.
P/N: PM2212
66
REV. 1.1, DEC. 19, 2014
MX25L6473F
Table 15. AC Characteristics
Temperature = -40°C to 85°C for Industrial grade
Symbol
Alt. Parameter
fSCLK
fC
fRSCLK
fR
fT
fQ
fTSCLK
f4PP
tCH(1)
tCLH
tCL(1)
tCLL
tCLCH (2)
tCHCL(2)
tSLCH tCSS
tCHSL
tDVCH tDSU
tCHDX
tDH
tCHSH
tSHCH
tSHSL
tCSH
tSHQZ (2)
tDIS
tCLQV
tV
tCLQX
tESL (3)
tPSL (3)
tPRS (4)
tERS (5)
tRCR
tRCP
tRCE
tHO
P/N: PM2212
Clock Frequency for the following instructions:
FAST_READ, PP, SE, BE, CE, RES, WREN, WRDI,
RDID, RDSR, WRSR
Clock Frequency for READ instructions
Clock Frequency for 2READ/DREAD instructions
Clock Frequency for 4READ/QREAD instructions
Clock Frequency for 4PP (Quad page program)
Normal Read
(fRSCLK)
Clock High Time
Others (fSCLK)
Normal Read
(fRSCLK)
Clock Low Time
Others (fSCLK)
Clock Rise Time (peak to peak)
Clock Fall Time (peak to peak)
CS# Active Setup Time (relative to SCLK)
CS# Not Active Hold Time (relative to SCLK)
Data In Setup Time
Data In Hold Time
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
Read
CS# Deselect Time
Write/Erase/
Program
2.65V-3.6V
Output Disable Time
3.0V-3.6V
Loading: 15pF
Clock Low to Output Valid
VCC=2.65V~3.6V
Loading: 30pF
Output Hold Time
Erase Suspend Latency
Program Suspend Latency
Latency between Program Resume and next Suspend
Latency between Erase Resume and next Suspend
Recovery Time from Read
Recovery Time from Program
Recovery Time from Erase
67
Min.
Typ. Max. Unit
D.C.
133
MHz
50
133
133
133
MHz
MHz
MHz
MHz
9
ns
45% x (1/fSCLK)
ns
9
ns
45% x (1/fSCLK)
0.1
0.1
4
4
2
3
4
4
15
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
50
ns
10
8
6
8
1
0.3
0.3
20
20
12
100
200
20
20
ns
ns
ns
ns
ns
us
us
us
us
us
us
ms
REV. 1.1, DEC. 19, 2014
MX25L6473F
Symbol
tDP
tRES1
tRES2
tW
tBP
tPP
tSE
tBE32K
tBE
tCE
tWSR
Alt. Parameter
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic Signature
Read
CS# High to Standby Mode with Electronic Signature Read
Write Status Register Cycle Time
Byte-Program
Page Program Cycle Time
Sector Erase Cycle Time (4KB)
Block Erase Cycle Time (32KB)
Block Erase Cycle Time (64KB)
Chip Erase Cycle Time
Write Security Register Time
Min.
Typ.
10
0.33
25
0.14
0.25
20
Max.
10
Unit
us
100
us
100
40
50
1.2
200
0.6
1
60
1
us
ms
us
ms
ms
s
s
s
ms
Notes:
1. tCH + tCL must be greater than or equal to 1/ fC.
2. The value guaranteed by characterization, not 100% tested in production.
3. Latency time is required to complete Erase/Program Suspend operation until WIP bit is "0".
4. For tPRS, minimum timing must be observed before issuing the next program suspend command. However,
a period equal to or longer than the typical timing is required in order for the program operation to make
progress.
5. For tERS, minimum timing must be observed before issuing the next erase suspend command. However, a
period equal to or longer than the typical timing is required in order for the erase operation to make progress.
P/N: PM2212
68
REV. 1.1, DEC. 19, 2014
MX25L6473F
12. TIMING ANALYSIS
Figure 41. Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
LSB
MSB
SI
High-Z
SO
Figure 42. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQX
tCL
tCLQV
tCLQX
LSB
SO
SI
P/N: PM2212
tSHQZ
ADDR.LSB IN
69
REV. 1.1, DEC. 19, 2014
MX25L6473F
13. OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in "Figure 43. AC Timing at Device Power-Up" and "Figure 44. Power-Down Sequence"
are for the supply voltages and the control signals at device power-up and power-down. If the timing in the
figures is ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 43. AC Timing at Device Power-Up
VCC
VCC(min)
GND
tVR
tSHSL
CS#
tSLCH
tCHSL
tSHCH
tCHSH
SCLK
tDVCH
tCHCL
tCHDX
LSB IN
MSB IN
SI
High Impedance
SO
Symbol
tVR
tCLCH
Parameter
VCC Rise Time
Notes
1
Min.
20
Max.
500000
Unit
us/V
Notes :
1.Sampled, not 100% tested.
2.For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer
to "Table 15. AC Characteristics".
P/N: PM2212
70
REV. 1.1, DEC. 19, 2014
MX25L6473F
Figure 44. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
VCC
CS#
SCLK
Figure 45. Power-up Timing
VCC
VCC(max)
Chip Selection is Not Allowed
VCC(min)
tVSL
Device is fully accessible
VWI
time
P/N: PM2212
71
REV. 1.1, DEC. 19, 2014
MX25L6473F
Figure 46. Power Up/Down and Voltage Drop
For Power-down to Power-up operation, the VCC of flash device must below VPWD for at least tPWD timing.
Please check the table below for more detail.
VCC
VCC (max.)
Chip Select is not allowed
VCC (min.)
tVSL
Full Device
Access
Allowed
VPWD (max.)
tPWD
Time
Table 16. Power-Up/Down Voltage and Timing
Symbol
tVSL
VWI
VPWD
tPWD
tVR
VCC
Parameter
VCC(min.) to device operation
Write Inhibit Voltage
VCC voltage needed to below VPWD for ensuring initialization will occur
The minimum duration for ensuring initialization will occur
VCC Rise Time
VCC Power Supply
Min.
800
1.5
300
20
2.65
Max.
2.5
0.9
500000
3.6
Unit
us
V
V
us
us/V
V
Note: These parameters are characterized only.
13-1.
Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 40h (all Status Register bits are 0 except QE bit: QE=1).
P/N: PM2212
72
REV. 1.1, DEC. 19, 2014
MX25L6473F
14. ERASE AND PROGRAMMING PERFORMANCE
Parameter
Write Status Register Cycle Time
Sector Erase Time (4KB)
Block Erase Time (64KB)
Block Erase Time (32KB)
Typ. (1)
25
0.25
0.14
20
10
0.33
100,000
Chip Erase Time
Byte Program Time (via page program command)
Page Program Time
Erase/Program Cycle
Max. (2)
40
200
1
0.6
60
50
1.2
Unit
ms
ms
s
s
s
us
ms
cycles
Notes:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checkerboard pattern.
2. Under worst conditions of 85°C and 2.65V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming
command.
15. DATA RETENTION
Parameter
Condition
Min.
Data retention
55˚C
20
Max.
Unit
years
16. LATCH-UP CHARACTERISTICS
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
Current
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
P/N: PM2212
73
Min.
-1.0V
-1.0V
-100mA
Max.
2 VCCmax
VCC + 1.0V
+100mA
REV. 1.1, DEC. 19, 2014
MX25L6473F
17. ORDERING INFORMATION
PART NO.
CLOCK (MHz)
TEMPERATURE
MX25L6473FM2I-08G
133
-40°C~85°C
MX25L6473FZNI-08G
133
-40°C~85°C
P/N: PM2212
74
PACKAGE
Remark
8-SOP
(200mil)
8-WOSN
(6x5mm)
REV. 1.1, DEC. 19, 2014
MX25L6473F
18. PART NAME DESCRIPTION
MX 25
L
6473F
M2
I
08 G
OPTION:
G: RoHS Compliant & Halogen-free
SPEED:
08: 133MHz
TEMPERATURE RANGE:
I: Industrial (-40° C to 85° C)
PACKAGE:
M2: 200mil 8-SOP
ZN: 6x5mm 8-WOSN
DENSITY & MODE:
6473F: 64Mb standard type
TYPE:
L: 3V
DEVICE:
25: Serial Flash
P/N: PM2212
75
REV. 1.1, DEC. 19, 2014
MX25L6473F
19. PACKAGE INFORMATION
P/N: PM2212
76
REV. 1.1, DEC. 19, 2014
MX25L6473F
P/N: PM2212
77
REV. 1.1, DEC. 19, 2014
MX25L6473F
20. REVISION HISTORY
Revision No.Description
Page
Date
0.01
1. Revised pin configuration.
P7
NOV/12/2014
2. Updated suspend/resume descriptions.
P50-51,64
3. Modified tCH/tCL formula.
P64
4. Modified status register QE bit as OTP and Initial Delivery StateP21, 69
0.02
1. Revised the document version number.
All
NOV/19/2014
1.0
1. Removed document status "ADVANCED INFORMATION"
All
NOV/24/2014
2. Added command ENSO, EXSO, and WRSCUR.
P13,15,18,
49,51-53
3. Added content of Additional 8K-bit bit security OTP.
P4,11,51,
58-61
4. Removed SRWD.
P22,24-26
1.11. Revised the document P/N.
All
DEC/19/2014
2. Modified "Table 9. Acceptable Commands During Program/Erase Suspend after tPSL/tESL".P53
P/N: PM2212
78
REV. 1.1, DEC. 19, 2014
MX25L6473F
Except for customized products which has been expressly identified in the applicable agreement, Macronix's
products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or
household applications only, and not for use in any applications which may, directly or indirectly, cause death,
personal injury, or severe property damages. In the event Macronix products are used in contradicted to their
target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its
actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or
distributors shall be released from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2014. All rights reserved, including the trademarks and tradename
thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit,
Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC,
Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Au­dio, Rich Book, Rich TV, and FitCAM. The names
and brands of third party referred thereto (if any) are for identification purposes only.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
79