MX25L1636D DATASHEET

MX25L1636D
MX25L1636D
DATASHEET
P/N: PM1372
1
REV. 1.2, JUL. 06, 2009
MX25L1636D
Contents
FEATURES................................................................................................................................................................... 5
GENERAL.................................................................................................................................................................. 5
PERFORMANCE....................................................................................................................................................... 5
SOFTWARE FEATURES........................................................................................................................................... 5
HARDWARE FEATURES.......................................................................................................................................... 6
GENERAL DESCRIPTION.......................................................................................................................................... 7
Table 1. Additional Feature Comparison.................................................................................................................... 7
PIN CONFIGURATIONS .............................................................................................................................................. 8
PIN DESCRIPTION....................................................................................................................................................... 8
BLOCK DIAGRAM........................................................................................................................................................ 9
DATA PROTECTION................................................................................................................................................... 10
Table 2. Protected Area Sizes.................................................................................................................................. 11
Table 3. 512-bit Secured OTP Definition................................................................................................................. 11
Memory Organization................................................................................................................................................ 12
Table 4. Memory Organization (16Mb)................................................................................................................... 12
DEVICE OPERATION................................................................................................................................................. 13
Figure 1. Serial Modes Supported........................................................................................................................... 13
COMMAND DESCRIPTION........................................................................................................................................ 14
Table 5. Command Set............................................................................................................................................ 14
(1) Write Enable (WREN)........................................................................................................................................ 16
(2) Write Disable (WRDI)......................................................................................................................................... 16
(3) Read Identification (RDID)................................................................................................................................. 16
(4) Read Status Register (RDSR)............................................................................................................................ 17
(5) Write Status Register (WRSR)........................................................................................................................... 18
Table 6. Protection Modes....................................................................................................................................... 18
(6) Read Data Bytes (READ)................................................................................................................................... 19
(7) Read Data Bytes at Higher Speed (FAST_READ)............................................................................................. 19
(8) Dual Read Mode (DREAD)................................................................................................................................ 19
(9) Quad Read Mode (QREAD)............................................................................................................................... 20
(10) Sector Erase (SE)............................................................................................................................................ 20
(11) Block Erase (BE).............................................................................................................................................. 20
(12) Chip Erase (CE)............................................................................................................................................... 21
(13) Page Program (PP).......................................................................................................................................... 21
(14) 4 x I/O Page Program (4PP)............................................................................................................................ 21
(15) Continuously program mode (CP mode).......................................................................................................... 22
(16) Deep Power-down (DP)................................................................................................................................... 22
(17) Release from Deep Power-down (RDP), Read Electronic Signature (RES).................................................... 23
(18) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4).................................................. 23
Table 7. ID Definitions . ........................................................................................................................................... 24
(21) Enter Secured OTP (ENSO)............................................................................................................................ 24
P/N: PM1372
2
REV. 1.2, JUL. 06, 2009
MX25L1636D
(22) Exit Secured OTP (EXSO)............................................................................................................................... 24
(23) Read Security Register (RDSCUR).................................................................................................................. 24
Table 8. Security Register Definition........................................................................................................................ 25
(24) Write Security Register (WRSCUR)................................................................................................................. 25
POWER-ON STATE.................................................................................................................................................... 26
ELECTRICAL SPECIFICATIONS............................................................................................................................... 27
ABSOLUTE MAXIMUM RATINGS.......................................................................................................................... 27
Figure 2. Maximum Negative Overshoot Waveform................................................................................................ 27
CAPACITANCE TA = 25°C, f = 1.0 MHz.................................................................................................................. 27
Figure 3. Maximum Positive Overshoot Waveform.................................................................................................. 27
Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL................................................................... 28
Figure 5. OUTPUT LOADING................................................................................................................................. 28
Table 9. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) ........ 29
Table 10. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) . .... 30
Timing Analysis......................................................................................................................................................... 31
Figure 6. Serial Input Timing.................................................................................................................................... 31
Figure 7. Output Timing........................................................................................................................................... 31
Figure 8. WP# Setup Timing and Hold Timing during WRSR when SRWD=1........................................................ 32
Figure 9. Write Enable (WREN) Sequence (Command 06).................................................................................... 32
Figure 10. Write Disable (WRDI) Sequence (Command 04)................................................................................... 32
Figure 11. Read Identification (RDID) Sequence (Command 9F)........................................................................... 33
Figure 12. Read Status Register (RDSR) Sequence (Command 05)...................................................................... 33
Figure 13. Write Status Register (WRSR) Sequence (Command 01).................................................................... 33
Figure 14. Read Data Bytes (READ) Sequence (Command 03)............................................................................ 34
Figure 15. Read at Higher Speed (FAST_READ) Sequence (Command 0B)........................................................ 34
Figure 16. Dual Read Mode Sequence (Command 3B).......................................................................................... 35
Figure 17. Quad Read Mode Sequence (Command 6B)......................................................................................... 35
Figure 18. Page Program (PP) Sequence (Command 02)..................................................................................... 36
Figure 19. 4 x I/O Page Program (4PP) Sequence (Command 38)....................................................................... 36
Figure 20. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)........................ 37
Figure 21. Sector Erase (SE) Sequence (Command 20)....................................................................................... 37
Figure 22. Block Erase (BE) Sequence (Command D8)........................................................................................ 37
Figure 23. Chip Erase (CE) Sequence (Command 60 or C7)................................................................................ 38
Figure 24. Deep Power-down (DP) Sequence (Command B9).............................................................................. 38
Figure 25. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)... 38
Figure 26. Release from Deep Power-down (RDP) Sequence (Command AB)..................................................... 39
Figure 27. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)............... 39
Figure 28. Power-up Timing..................................................................................................................................... 40
Table 11. Power-Up Timing . ................................................................................................................................... 40
INITIAL DELIVERY STATE...................................................................................................................................... 40
RECOMMENDED OPERATING CONDITIONS.......................................................................................................... 41
ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 42
Data Retention......................................................................................................................................................... 42
P/N: PM1372
3
REV. 1.2, JUL. 06, 2009
MX25L1636D
LATCH-UP CHARACTERISTICS............................................................................................................................... 42
ORDERING INFORMATION....................................................................................................................................... 43
PART NAME DESCRIPTION...................................................................................................................................... 44
PACKAGE INFORMATION......................................................................................................................................... 45
REVISION HISTORY ................................................................................................................................................. 47
P/N: PM1372
4
REV. 1.2, JUL. 06, 2009
MX25L1636D
16M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 16M:16,777,216 x 1 bit structure or 8,388,608 x 2 bits (two I/O read mode) structure or 4,194,304 x 4 bits (four I/O read mode) structure
• 512 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• 32 Equal Blocks with 64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast read
- 1 I/O: 86MHz with 8 dummy cycles
- 4 I/O: 75MHz with 6 dummy cycles
- 2 I/O: 75MHz with 4 dummy cycles
- Fast access time: 86MHz serial clock
- Serial clock of four I/O read mode : 75MHz, which is equivalent to 300MHz
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Byte program time: 9us (typical)
- Continuously program mode (automatically increase address under word program mode)
- Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 14s(typ.) /chip
• Low Power Consumption
- Low active read current: 25mA(max.) at 86MHz and 10mA(max.) at 33MHz
- Low active programming current: 20mA (max.)
- Low active erase current: 20mA (max.)
- Low standby current: 20uA (max.)
• Typical 100,000 erase/program cycles
• 20 years of data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions
- Additional 512-bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first)
• Status Register Feature
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
- Both REMS,REMS2 and REMS4 commands for 1-byte manufacturer ID and 1-byte device ID
P/N: PM1372
5
REV. 1.2, JUL. 06, 2009
MX25L1636D
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SO0
- Serial Data Input or Serial Data Multiple Output for 2 x I/O read mode and 4 x I/O read mode
• SO/SO1
- Serial Data Output or Serial Data Multiple Output for 2 x I/O read mode and 4 x I/O read mode
• WP#/SO2
- Hardware write protection or serial data Multiple Output for 4 x I/O read mode
• NC/SO3
- NC pin or serial data Multiple Output for 4 x I/O read mode
• PACKAGE
- 16-pin SOP (300mil)
- 8-pin SOP (200mil)
- All Pb-free devices are RoHS Compliant
P/N: PM1372
6
REV. 1.2, JUL. 06, 2009
MX25L1636D
GENERAL DESCRIPTION
The MX25L1636D are 16,777,216 bit serial Flash memory, which is configured as 2,097,152 x 8 internally. When it
is in two or four I/O read mode, the structure becomes 8,388,608 bits x 2 or 4,194,304 bits x 4. The MX25L1636D
feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus
signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device
is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SO0 pin and SO1 pin for data output. When it is in
four I/O read mode, the SI pin, SO pin, WP# pin and NC pin become SO0 pin, SO1 pin, SO2 pin and SO3 pin for
data output.
The MX25L1636D provides sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for Continuously program mode, and erase command is executes on sector (4K-byte),
or block (64K-byte), or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for
more details.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 20uA DC current.
The MX25L1636D utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
Table 1. Additional Feature Comparison
Additional
Features
Part
Name
MX25L1636D
P/N: PM1372
Protection and
Security
Flexible
Block
Protection
(BP0-BP3)
512-bit
secured
OTP
V
V
Read Performance
Identifier
2 I/O
4 I/O
RES
REMS
REMS2
REMS4
RDID
Read
Read
(command: (command: (command: (command: (command:
(75 MHz) (75 MHz)
AB hex)
90 hex)
EF hex)
DF hex)
9F hex)
V
V
24 (hex)
7
C2 24 (hex) C2 24 (hex) C2 24 (hex)
(if ADD=0) (if ADD=0) (if ADD=0)
C2 24 15
(hex)
REV. 1.2, JUL. 06, 2009
MX25L1636D
PIN CONFIGURATIONS
16-PIN SOP (300mil)
NC/SO3
VCC
NC
NC
NC
NC
CS#
SO/SO1
1
2
3
4
5
6
7
8
8-PIN SOP (200mil)
16
15
14
13
12
11
10
9
SCLK
SI/SO0
NC
NC
NC
NC
GND
WP#/SO2
CS#
SO/SO1
WP#/SO2
GND
1
2
3
4
8
7
6
5
VCC
NC/SO3
SCLK
SI/SO0
PIN DESCRIPTION
SYMBOL
CS#
SI/SO0
SO/SO1
SCLK
WP#/SO2
NC/SO3
VCC
GND
P/N: PM1372
DESCRIPTION
Chip Select
Serial Data Input (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O or 4xI/O
read mode)
Serial Data Output (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O or 4xI/O
read mode)
Clock Input
Write protection: connect to GND or
Serial Data Input & Output (for 4xI/O
read mode)
NC pin (Not connect) or Serial Data
Input & Output (for 4xI/O read mode)
+ 3.3V Power Supply
Ground
8
REV. 1.2, JUL. 06, 2009
MX25L1636D
BLOCK DIAGRAM
X-Decoder
Address
Generator
Memory Array
Page Buffer
SI/SO0
Data
Register
Y-Decoder
SRAM
Buffer
CS#
WP#/SO2
NC/SO3
SCLK
Mode
Logic
State
Machine
HV
Generator
Clock Generator
Output
Buffer
SO/SO1
P/N: PM1372
Sense
Amplifier
9
REV. 1.2, JUL. 06, 2009
MX25L1636D
DATA PROTECTION
The MX25L1636D is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transition. During power up the device automatically resets the
state machine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system
noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Continuously Program mode (CP) instruction completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES).
• Advanced Security Features: there are some protection and securuity features which protect content from inadvertent write and hostile access.
I. Block lock protection
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected
as read only. The proected area definition is shown as table of "Protected Area Sizes", the protected areas are
more flexible which may protect various area by setting value of BP0-BP3 bits.
Please refer to table of "protected area sizes".
- The Hardware Proteced Mode (HPM) use WP#/SO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit. If
the system goes into four I/O read mode, the feature of HPM
will be disabled.
P/N: PM1372
10
REV. 1.2, JUL. 06, 2009
MX25L1636D
Table 2. Protected Area Sizes
BP3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Status bit
BP2
BP1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
BP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Protect Level
16Mb
0 (none)
1 (1block, block 31th)
2 (2blocks, block 30th-31th)
3 (4blocks, block 28th-31th)
4 (8blocks, block 24th-31th)
5 (16blocks, block 16th-31th)
6 (32blocks, all)
7 (32blocks, all)
8 (32blocks, all)
9 (32blocks, all)
10 (16blocks, block 0th-15th)
11 (24blocks, block 0th-23th)
12 (28blocks, block 0th-27th)
13 (30blocks, block 0th-29th)
14 (31blocks, block 0th-30th)
15 (32blocks, all)
II. Additional 512-bit secured OTP for unique identifier: to provide 512-bit one-time program area for setting
device unique serial number - Which may be set by factory or system customer. Please refer to table 3. 512-bit
secured OTP definition.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 512-bit secured OTP by entering 512-bit secured OTP mode (with ENSO command), and going
through normal program procedure, and then exiting 512-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to table of "security register definition" for security
register bit definition and table of "512-bit secured OTP definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 512-bit secured OTP mode, array access is not allowed.
Table 3. 512-bit Secured OTP Definition
Address range
Size
Standard Factory Lock
xxxx00~xxxx0F
128-bit
ESN (electrical serial number)
xxxx10~xxxx3F
384-bit
N/A
P/N: PM1372
11
Customer Lock
Determined by customer
REV. 1.2, JUL. 06, 2009
MX25L1636D
Memory Organization
Table 4. Memory Organization (16Mb)
Block
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P/N: PM1372
Sector
511
:
496
495
:
480
479
:
464
463
:
448
447
:
432
431
:
416
415
:
400
399
:
384
383
:
368
367
:
352
351
:
336
335
:
320
319
:
304
303
:
288
287
:
272
271
:
256
Block
Address Range
1FF000h
1FFFFFh
:
:
1F0000h
1F0FFFh
1EF000h
1EFFFFh
:
:
1E0000h
1E0FFFh
1DF000h
1DFFFFh
:
:
1D0000h
1D0FFFh
1CF000h
1CFFFFh
:
:
1C0000h
1C0FFFh
1BF000h
1BFFFFh
:
:
1B0000h
1B0FFFh
1AF000h
1AFFFFh
:
:
1A0000h
1A0FFFh
19F000h
19FFFFh
:
:
190000h
190FFFh
18F000h
18FFFFh
:
:
180000h
180FFFh
17F000h
17FFFFh
:
:
170000h
170FFFh
16F000h
16FFFFh
:
:
160000h
160FFFh
15F000h
15FFFFh
:
:
150000h
150FFFh
14F000h
14FFFFh
:
:
140000h
140FFFh
13F000h
13FFFFh
:
:
130000h
130FFFh
12F000h
12FFFFh
:
:
120000h
120FFFh
11F000h
11FFFFh
:
:
110000h
110FFFh
10F000h
10FFFFh
:
:
100000h
100FFFh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
12
Sector
255
:
240
239
:
224
223
:
208
207
:
192
191
:
176
175
:
160
159
:
144
143
:
128
127
:
112
111
:
96
95
:
80
79
:
64
63
:
48
47
:
32
31
:
16
15
:
2
1
0
Address Range
0FF000h
0FFFFFh
:
:
0F0000h
0F0FFFh
0EF000h
0EFFFFh
:
:
0E0000h
0E0FFFh
0DF000h
0DFFFFh
:
:
0D0000h
0D0FFFh
0CF000h
0CFFFFh
:
:
0C0000h
0C0FFFh
0BF000h
0BFFFFh
:
:
0B0000h
0B0FFFh
0AF000h
0AFFFFh
:
:
0A0000h
0A0FFFh
09F000h
09FFFFh
:
:
090000h
090FFFh
08F000h
08FFFFh
:
:
080000h
080FFFh
07F000h
07FFFFh
:
:
070000h
070FFFh
06F000h
06FFFFh
:
:
060000h
060FFFh
05F000h
05FFFFh
:
:
050000h
050FFFh
04F000h
04FFFFh
:
:
040000h
040FFFh
03F000h
03FFFFh
:
:
030000h
030FFFh
02F000h
02FFFFh
:
:
020000h
020FFFh
01F000h
01FFFFh
:
:
010000h
010FFFh
00F000h
00FFFFh
:
:
002000h
002FFFh
001000h
001FFFh
000000h
000FFFh
REV. 1.2, JUL. 06, 2009
MX25L1636D
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown as Figure 2.
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, 4READ,RES, REMS,
REMS2 and REMS4 the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data
being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP,
4PP, CP, RDP, DP, ENSO, EXSO,and WRSCUR, the CS# must go high exactly at the byte boundary; otherwise,
the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported
CPOL
CPHA
shift in
(Serial mode 0)
0
0
SCLK
(Serial mode 3)
1
1
SCLK
SI
shift out
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
P/N: PM1372
13
REV. 1.2, JUL. 06, 2009
MX25L1636D
COMMAND DESCRIPTION
Table 5. Command Set
Command
(byte)
1st byte
WREN (write WRDI (write
enable)
disable)
06 (hex)
04 (hex)
RDID
(read
identification)
9F (hex)
RDSR
WRSR
FAST READ DREAD (1I
READ (read
(read status (write status
(fast read
2O read
data)
register)
register)
data)
command)
05 (hex)
2nd byte
01 (hex)
Values
3rd byte
4th byte
5th byte
Action
Command
(byte)
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
Command
(byte)
1st byte
2nd byte
3rd byte
4th byte
Action
P/N: PM1372
sets the
resets the
(WEL) write (WEL) write
enable latch enable latch
bit
bit
0B (hex)
3B (hex)
AD1
AD1
AD2
AD2
AD3
AD3
Dummy
Dummy
outputs
to read out to write new n bytes read n bytes read n bytes read
JEDEC
the values
values of out until CS# out until CS# out by Dual
ID: 1-byte of the status the status
goes high
goes high output until
Manufactregister
register
CS# goes
urer ID &
high
2-byte Device
ID
QREAD (1I
4O read
command)
QPP (1I4P
Page
Program)
4PP (quad
page
program)
6B (hex)
AD1
AD2
AD3
Dummy
n bytes read
out by Quad
output until
CS# goes
high
32 (hex)
AD1
AD2
AD3
38 (hex)
AD1
SE (sector
erase)
BE (block
erase)
CE (chip
erase)
PP (page
program)
20 (hex)
AD1
AD2
AD3
D8 (hex)
AD1
AD2
AD3
60 or C7 (hex)
02 (hex)
AD1
AD2
AD3
to erase the
selected
block
to erase
whole chip
to program
the selected
page
Single
quad input to erase the
Address
to program
selected
and Quad the selected
sector
Data input
page
to program
the selected
page
RDP
(Release
RES (read
from deep electronic ID)
power down)
B9 (hex)
AB (hex)
AB (hex)
x
x
x
enters deep release from
to read
power down deep power out 1-byte
mode
down mode Device ID
DP (Deep
power down)
03 (hex)
AD1
(A23-A16)
AD2
(A15-A8)
AD3
(A7-A0)
REMS (read
electronic
manufacturer
& device ID)
90 (hex)
x
x
ADD (Note 2)
output the
Manufacturer
ID & Device
ID
14
CP
(continuously
program
mode)
AD (hex)
AD1
AD2
AD3
continously
program
whole
chip, the
address is
automatically
increase
REMS2 (read REMS4 (read ENSO (enter
EXSO (exit
ID for 2x I/O ID for 4x I/O
secured
secured OTP)
mode)
mode)
OTP)
EF (hex)
DF (hex)
B1 (hex)
C1 (hex)
x
x
x
x
ADD (Note 2) ADD (Note 2)
output the
output the
to enter
to exit the
Manufacturer Manufacturer the 512-bit
512-bit
ID & Device ID & Device secured OTP secured OTP
ID
ID
mode
mode
REV. 1.2, JUL. 06, 2009
MX25L1636D
Command
(byte)
1st byte
2nd byte
3rd byte
4th byte
Action
ESRY
DSRY
RDSCUR
WRSCUR
(enable SO (disable SO
(read security (write security
to output RY/ to output RY/
register)
register)
BY#)
BY#)
2B (hex)
2F (hex)
70 (hex)
80 (hex)
to read value
to set the
to enable SO to disable SO
of security lock-down bit to output RY/ to output RY/
register
as "1" (once BY# during
BY# during
lock-down,
CP mode
CP mode
cannot be
update)
Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SI/SO1 which is different from
1 x I/O condition.
Note 2: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.
Note 3: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode.
P/N: PM1372
15
REV. 1.2, JUL. 06, 2009
MX25L1636D
(1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP,
CP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the
WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high. (see
Figure 9)
(2) Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low-> sending WRDI instruction code→CS# goes high. (see
Figure 10)
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Quad Page Program (4PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
- Continuously program mode (CP) instruction completion
(3) Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC
Manufacturer ID is C2(hex), the memory type ID is 24(hex) as the first-byte device ID, and the individual device ID
of second-byte ID are listed as table of "ID Definitions". (see table 7 in page 23)
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out
on SO→ to end RDID operation can use CS# to high at any time during data out. (see Figure 11.)
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
P/N: PM1372
16
REV. 1.2, JUL. 06, 2009
MX25L1636D
(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register
data out on SO (see Figure 12)
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored and
not affect value of WEL bit if it is applied to a protected memory area.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected
area(as defined in table 1) of the device to against the program/erase instruction without hardware protection mode
being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector
Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed).
QE bit. The Quad Enable (QE) bit, non-volatile bit, performs Quad when it is reset to "0" (factory default) to enable
WP# or is set to "1" to enable Quad SO2 and SO3.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#/SO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets
to 1 and WP#/SO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR)
instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are
read only.
Status Register
bit7
SRWD (status
register write
protect)
bit6
QE
(Quad
Enable)
1=Quad
1=status
Enable
register write
0=not Quad
disable
Enable
Non-volatile Non-volatile
bit
bit
bit5
BP3
(level of
protected
block)
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
(note 1)
(note 1)
(note 1)
(note 1)
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
bit1
bit0
WEL
WIP
(write enable
(write in
latch)
progress bit)
1=write
1=write
enable
operation
0=not write 0=not in write
enable
operation
volatile bit
volatile bit
Note 1: see the table 2 "Protected Area Size" in page 11.
P/N: PM1372
17
REV. 1.2, JUL. 06, 2009
MX25L1636D
(5) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in table 1). The WRSR also can set or reset the Quad enable (QE) bit and set or
reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SO2) pin signal, but
has no effect on bit1(WEL) and bit0 (WIP) of the statur register. The WRSR instruction cannot be executed once the
Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→ CS# goes high. (see Figure 13)
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
Table 6. Protection Modes
Mode
Status register condition
WP# and SRWD bit status
Memory
Software protection
mode (SPM)
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
bits can be changed
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
Hardware protection
mode (HPM)
The SRWD, BP0-BP3 of
status register bits cannot be
changed
WP#=0, SRWD bit=1
The protected area
cannot
be program or erase.
Note:
1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.
As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP#/SO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,
BP0, is at software protected mode (SPM).
- When SRWD bit=1 and WP#/SO2 is high, the WREN instruction may set the WEL bit can change the values of
SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM)
Note:
If SRWD bit=1 but WP#/SO2 is low, it is impossible to write the Status Register even if the WEL bit has previously
been set. It is rejected to write the Status Register and not be executed.
P/N: PM1372
18
REV. 1.2, JUL. 06, 2009
MX25L1636D
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP#/SO2 is low (or WP#/SO2 is low before SRWD bit=1), it enters the hardware
protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,
BP1, BP0 and hardware protected mode by the WP#/SO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SO2 driving high once the hardware protected mode is entered.
If the WP#/SO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can
use software protected mode via BP3, BP2, BP1, BP0.
If the system goes into four I/O read mode, the feature of HPM will be disabled.
(6) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-byte address on
SI→ data out on SO→ to end READ operation can use CS# to high at any time during data out. (see Figure 14)
(7) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→3byte address on SI→ 1-dummy byte (default) address on SI→data out on SO→ to end FAST_READ operation can
use CS# to high at any time during data out. (see Figure 15)
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
(8) Dual Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits(interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing DREAD instruction is: CS# goes low→ sending DREAD instruction→3-byte address on
SO0→ 8-bit dummy cycle on SO0→ data out interleave on SO1 & SO0→ to end 2READ operation can use CS#
to high at any time during data out (see Figure 16 for Dual Read Mode Timing Waveform).
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
P/N: PM1372
19
REV. 1.2, JUL. 06, 2009
MX25L1636D
(9) Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status
Register must be set to "1" before seding the QREAD instruction.The address is latched on rising edge of SCLK,
and data of every four bits(interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency
fQ. The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction→ 24-bit address on
SO0→ 8 dummy cycles → data out interleave on SO3, SO2, SO1 & SO0→ to end QREAD operation can use
CS# to high at any time during data out (see Figure 17 for Quad Read Mode Timing Waveform).
While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(10) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see table 3) is a valid address for Sector Erase (SE)
instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in);
otherwise, the instruction will be rejected and not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low→sending SE instruction code→ 3-byte address on SI
→CS# goes high. (see Figure 21)
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.
(11) Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE)
instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in);
otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low→sending BE instruction code→ 3-byte address on SI
→CS# goes high. (see Figure 22)
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.
P/N: PM1372
20
REV. 1.2, JUL. 06, 2009
MX25L1636D
(12) Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go
high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will
be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low→ sending CE instruction code→CS# goes high. (see Figure 23)
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE
timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is
protected by BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed
when BP3, BP2, BP1, BP0 all set to "0".
(13) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs
only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-A0
(The eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are not
all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the
same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the last
256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent
to the device, the data is programmed at the requested address of the page without effect on other address of the
same page.
The sequence of issuing PP instruction is: CS# goes low→sending PP instruction code→ 3-byte address on SI→ at
least 1-byte on data on SI→ CS# goes high. (see Figure 18)
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the
tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.
(14) 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before
sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SO0, SO1, SO2, and SO3,
which can raise programer performance and and the effectiveness of application of lower clock less than 20MHz.
For system with faster clock, the Quad page program cannot provide more actual favors, because the required internal page program time is far more than the time data flows in. Therefore, we suggest that while executing this
command (especially during sending data), user can slow the clock speed down to 20MHz below. The other func-
P/N: PM1372
21
REV. 1.2, JUL. 06, 2009
MX25L1636D
tion descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SO[3:0]→at least 1-byte on data on SO[3:0]→CS# goes high. (see Figure 19)
(15) Continuously program mode (CP mode)
The CP mode may enhance program performance by automatically increasing address to the next higher address
after each byte data has been programmed.
The Continuously program (CP) instruction is for multiple byte program to Flash. A write Enable (WREN) instruction
must execute to set the Write Enable Latch(WEL) bit before sending the Continuously program (CP) instruction.
CS# requires to go high before CP instruction is executing. After CP instruction and address input, two bytes of
data is input sequentially from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the initial address
range with A0=0 and second byte data with A0=1. If only one byte data is input, the CP mode will not process. If
more than two bytes data are input, the additional data will be ignored and only two byte data are valid. The CP
program instruction will be ignored and not affect the WEL bit if it is applied to a protected memory area. Any byte to
be programmed should be in the erase state (FF) first. It will not roll over during the CP mode, once the last unprotected address has been reached, the chip will exit CP mode and reset write Enable Latch bit (WEL) as "0" and CP
mode bit as "0". Please check the WIP bit status if it is not in write progress before entering next valid instruction.
During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05
hex), and RDSCUR command (2B hex). And the WRDI command is valid after completion of a CP programming
cycle, which means the WIP bit=0.
The sequence of issuing CP instruction is : CS# high to low→ sending CP instruction code→ 3-byte address on
SI→ Data Byte on SI→CS# goes high to low→ sending CP instruction......→ last desired byte programmed or sending Write Disable (WRDI) instruction to end CP mode-> sending RDSR instruction to verify if CP mode is ended. (see
Figure 20 of CP mode timing waveform)
Three methods to detect the completion of a program cycle during CP mode:
1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode.
2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not.
3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a
program cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once it is
enable in CP mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage, "1" indicates ready stage, SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#) instruction to
disable the SO to output RY/BY# and return to status register data output during CP mode. Please note that the
ESRY/DSRY command are not accepted unless the completion of CP mode.
(16) Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode
requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep
power-down mode. It's different from Standby mode.
The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high. (see
Figure 24)
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
P/N: PM1372
22
REV. 1.2, JUL. 06, 2009
MX25L1636D
and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Powerdown, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby
mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction
code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay
of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.
(17) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip
Select (CS#) must remain High for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode,
the device waits to be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of
ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new
design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be
executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress.
The sequence is shown as Figure 25, 26.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at
least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and
execute instruction.
The RDP instruction is for releasing from Deep Power Down Mode.
(18) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)
The REMS, REMS2 & REMS4 instruction is an alternative to the Release from Power-down/Device ID instruction
that provides both the JEDEC assigned manufacturer ID and the specific device ID.
The REMS, REMS2 & REMS4 instruction is very similar to the Release from Power-down/Device ID instruction.
The instruction is initiated by driving the CS# pin low and shift the instruction code "90h" or "EFh" or "DFh"followed
by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in figure 27. The
Device ID values are listed in Table of ID Definitions. If the one-byte address is initially set to 01h, then the device
ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high.
P/N: PM1372
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REV. 1.2, JUL. 06, 2009
MX25L1636D
Table 7. ID Definitions
RDID Command
manufacturer ID
C2
memory type
24
electronic ID
24
device ID
24
RES Command
REMS/REMS2/REMS4/
Command
manufacturer ID
C2
memory density
15
(21) Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 512-bit secured OTP mode. The additional 512-bit secured OTP
is independent from main array, which may use to store unique serial number for system identifier. After entering the
Secured OTP mode, and then follow standard read or program, procedure to read out the data or update data. The
Secured OTP data cannot be updated again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→sending ENSO instruction to enter Secured OTP
mode→CS# goes high.
Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once security OTP is lock down, only read related commands are valid.
(22) Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 512-bit secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
(23) Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→ send ing RDSCUR instruction→Security Register
data out on SO→ CS# goes high.
The definition of the Security Register bits is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or
not. When it is "0", it indicates non- factory lock; "1" indicates factory- lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 512-bit Secured OTP
area cannot be update any more. While it is in 512-bit secured OTP mode, array access is not allowed.
Continuously Program Mode( CP mode) bit. The Continuously Program Mode bit indicates the status of CP
mode, "0" indicates not in CP mode; "1" indicates in CP mode.
P/N: PM1372
24
REV. 1.2, JUL. 06, 2009
MX25L1636D
Table 8. Security Register Definition
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
x
x
x
Continuously
Program mode
(CP mode)
x
x
LDSO
(indicate if
lock-down
Secrured OTP
indicator bit
reserved
reserved
0 = not lockdown
0 = non-factory
1 = lock-down
lock
(cannot
1 = factory
program/erase
lock
OTP)
volatile bit
volatile bit
non-volatile bit non-volatile bit
reserved
reserved
reserved
0=normal
Program mode
1=CP mode
(default=0)
volatile bit
volatile bit
volatile bit
volatile bit
(24) Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN
instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values
of bit1 (LDSO bit) for customer to lock-down the 512-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction→CS# goes high.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
P/N: PM1372
25
REV. 1.2, JUL. 06, 2009
MX25L1636D
POWER-ON STATE
The device is at below states when power-up:
- Standby mode ( please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the figure of "power-up timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.(generally around 0.1uF)
P/N: PM1372
26
REV. 1.2, JUL. 06, 2009
MX25L1636D
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Industrial grade
Ambient Operating Temperature
Storage Temperature
-40°C to 85°C
-55°C to 125°C
Applied Input Voltage
-0.5V to 4.6V
Applied Output Voltage
-0.5V to 4.6V
VCC to Ground Potential
-0.5V to 4.6V
NOTICE:
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is stress rating only and functional operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2.Specifications contained within the following tables are subject to change.
3.During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, please
refer to Figure 2 and 3.
Figure 3. Maximum Positive Overshoot Waveform
Figure 2. Maximum Negative Overshoot Waveform
20ns
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
20ns
CAPACITANCE TA = 25°C, f = 1.0 MHz
SYMBOL PARAMETER
CIN
COUT
P/N: PM1372
MIN.
TYP
MAX.
UNIT
Input Capacitance
6
pF
VIN = 0V
Output Capacitance
8
pF
VOUT = 0V
27
CONDITIONS
REV. 1.2, JUL. 06, 2009
MX25L1636D
Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing referance level
0.8VCC
0.7VCC
0.3VCC
0.2VCC
Output timing referance level
AC
Measurement
Level
0.5VCC
Note: Input pulse rise and fall time are <5ns
Figure 5. OUTPUT LOADING
DEVICE UNDER
TEST
2.7K ohm
CL
6.2K ohm
+3.3V
DIODES=IN3064
OR EQUIVALENT
CL=30pF Including jig capacitance
P/N: PM1372
28
REV. 1.2, JUL. 06, 2009
MX25L1636D
Table 9. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V)
SYMBOL PARAMETER
NOTES
MIN.
TYP.
MAX.
UNITS TEST CONDITIONS
ILI
Input Load Current
1
±2
uA
VCC = VCC Max,
VIN = VCC or GND
ILO
Output Leakage Current
1
±2
uA
VCC = VCC Max,
VIN = VCC or GND
ISB1
VCC Standby Current
1
20
uA
VIN = VCC or GND,
CS# = VCC
ISB2
Deep Power-down
Current
20
uA
VIN = VCC or GND,
CS# = VCC
ICC1
VCC Read
VIL
VCC Program Current
(PP)
VCC Write Status
Register (WRSR) Current
VCC Sector Erase
Current (SE)
VCC Chip Erase Current
(CE)
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
ICC2
ICC3
ICC4
ICC5
f=86MHz,
fQ=75MHz (4 x I/O read)
SCLK=0.1VCC/0.9VCC,
SO=Open
fT=75MHz (2 x I/O read)
SCLK=0.1VCC/0.9VCC,
SO=Open
25
mA
20
mA
10
mA
20
mA
20
mA
1
20
mA
1
20
mA
-0.5
0.3VCC
V
0.7VCC
VCC+0.4
V
0.4
V
IOL = 1.6mA
V
IOH = -100uA
1
1
VCC-0.2
f=33MHz,
SCLK=0.1VCC/0.9VCC,
SO=Open
Program in Progress,
CS# = VCC
Program status register in
progress, CS#=VCC
Erase in Progress,
CS#=VCC
Erase in Progress,
CS#=VCC
Notes :
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
P/N: PM1372
29
REV. 1.2, JUL. 06, 2009
MX25L1636D
Table 10. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V)
Symbol
Alt. Parameter
fSCLK
fC
fRSCLK
fR
fT
fQ
fTSCLK
tCH(1)
tCLH
tCL(1)
tCLL
tCLCH(2)
tCHCL(2)
tSLCH tCSS
tCHSL
tDVCH tDSU
tCHDX
tDH
tCHSH
tSHCH
tSHSL(3) tCSH
tSHQZ(2) tDIS
tCLQV
tV
tCLQX
tWHSL
tSHWL
tDP(2)
tHO
tRES1(2)
tRES2(2)
tC
tBP
tPP
tSE
tBE
tCE
Min.
Clock Frequency for the following instructions:
FAST_READ, PP, SE, BE, CE, DP, RES,RDP
WREN, WRDI, RDID, RDSR, WRSR
Clock Frequency for READ instructions
Clock Frequency for DREAD instructions
Clock Frequency for QREAD instructions
fC=86MHz
Clock High Time
fR=33MHz
fC=86MHz
Clock Low Time
fR=33MHz
Clock Rise Time (3) (peak to peak)
Clock Fall Time (3) (peak to peak)
CS# Active Setup Time (relative to SCLK)
CS# Not Active Hold Time (relative to SCLK)
Data In Setup Time
Data In Hold Time
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
Read
CS# Deselect Time
Write/Erase/Program
2.7V-3.6V
Output Disable Time
3.0V-3.6V
2.7V-3.6V
Clock Low to Output Valid
Loading: 30pF/15pF
3.0V-3.6V
Output Hold Time
Write Protect Setup Time
Write Protect Hold Time
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic
Signature Read
CS# High to Standby Mode with Electronic Signature
Read
Chip Unlock Cycle Time
Byte-Program
Page Program Cycle Time
Sector Erase Cycle Time
Block Erase Cycle Time
Chip Erase Cycle Time
Typ.
Max.
Unit
D.C.
86
MHz
D.C.
66
MHz
33
75
75
MHz
MHz
MHz
ns
5.5
13
5.5
13
0.1
0.1
5
5
2
5
5
5
15
50
ns
10
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
8.8
us
8.8
us
100
300
5
300
2
30
ms
us
ms
ms
s
s
10
8
10/8
8/6
0
20
100
40
9
1.4
60
0.7
14
Notes:
1. tCH + tCL must be greater than or equal to 1/ f (fC or fR)
2. Value guaranteed by characterization, not 100% tested in production.
3. tSHSL=15ns from read instruction, tSHSL=50ns from Write/Erase/Program instruction.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. Test condition is shown as Figure 4, 5.
P/N: PM1372
30
REV. 1.2, JUL. 06, 2009
MX25L1636D
Timing Analysis
Figure 6. Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
LSB
MSB
SI
High-Z
SO
Figure 7. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQX
tCL
tCLQV
tSHQZ
tCLQX
LSB
SO
tQLQH
tQHQL
SI
P/N: PM1372
ADDR.LSB IN
31
REV. 1.2, JUL. 06, 2009
MX25L1636D
Figure 8. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
WP#
tSHWL
tWHSL
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
01
SI
High-Z
SO
Figure 9. Write Enable (WREN) Sequence (Command 06)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
06
High-Z
SO
Figure 10. Write Disable (WRDI) Sequence (Command 04)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
SO
P/N: PM1372
04
High-Z
32
REV. 1.2, JUL. 06, 2009
MX25L1636D
Figure 11. Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
Command
SI
9F
Manufacturer Identification
High-Z
SO
7
6
5
3
2
1
Device Identification
0 15 14 13
MSB
3
2
1
0
MSB
Figure 12. Read Status Register (RDSR) Sequence (Command 05)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
05
SI
Status Register Out
High-Z
SO
7
6
5
4
3
2
Status Register Out
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 13. Write Status Register (WRSR) Sequence (Command 01)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
SI
SO
P/N: PM1372
Status
Register In
01
7
6
5
4
3
2
1
0
MSB
High-Z
33
REV. 1.2, JUL. 06, 2009
MX25L1636D
Figure 14. Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
command
24-Bit Address
23 22 21
03
SI
3
2
1
0
MSB
Data Out 1
High-Z
SO
7
6
5
4
3
Data Out 2
2
1
0
7
MSB
Figure 15. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
0B
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Configurable
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
3
2
1
0
7
MSB
MSB
P/N: PM1372
4
34
6
5
4
3
2
1
0
7
MSB
REV. 1.2, JUL. 06, 2009
MX25L1636D
Figure 16. Dual Read Mode Sequence (Command 3B)
CS#
0
1
2
3
4
5
6
7
8
9 10 11
39 40 41 42 43
30 31 32
SCLK
8 Bit Instruction
SO/SO1
address
bit23, bit22, bit21...bit0
3B(hex)
SI/SO0
8 dummy
cycle
24 BIT Address
dummy
High Impedance
Data Output
data
bit6, bit4, bit2...bit0, bit6, bit4....
data
bit7, bit5, bit3...bit1, bit7, bit5....
Figure 17. Quad Read Mode Sequence (Command 6B)
CS#
0
1
2
3
4
5
6
7
8
9
30 31 32 33
38 39 40 41 42 43
SCLK
8 Bit Instruction
SI/SO0
SO/SO1
WP#/SO2
NC/SO3
P/N: PM1372
6B(hex)
24 Bit Address
address
bit23, bit22..bit0
8 dummy
cycle
dummy
Data Output
data
bit4, bit0, bit4....
High Impedance
data
bit5 bit1, bit5....
High Impedance
data
bit6 bit2, bit6....
High Impedance
data
bit7 bit3, bit7....
35
REV. 1.2, JUL. 06, 2009
MX25L1636D
Figure 18. Page Program (PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
1
0
7
6
5
3
2
1
0
2079
2
2078
3
2077
23 22 21
02
SI
Data Byte 1
2076
24-Bit Address
2075
Command
4
1
0
MSB
MSB
2074
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2073
2072
CS#
SCLK
Data Byte 2
7
SI
6
5
4
3
2
Data Byte 3
0
1
7
MSB
6
5
4
3
2
Data Byte 256
1
7
0
MSB
6
5
4
3
2
MSB
Figure 19. 4 x I/O Page Program (4PP) Sequence (Command 38)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21
SCLK
Command
20 16 12 8
4
0
4
0
4
0
4
0
4
0
SO/SO1
21 17 13 9
5
1
5
1
5
1
5
1
5
1
WP#/SO2
22 18 14 10
6
2
6
2
6
2
6
2
6
2
NC/SO3
23 19 15 11
7
3
7
3
7
3
7
3
7
3
SI/SO0
P/N: PM1372
Data Data Data Data
Byte 1 Byte 2 Byte 3 Byte 4
6 Address cycle
38
36
REV. 1.2, JUL. 06, 2009
MX25L1636D
Figure 20. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)
CS#
0 1
6 7 8 9
30 31 31 32
0 1
47 48
6 7 8
20 21 22 23 24
0
7
0
7 8
SCLK
Command
SI
S0
AD (hex)
Valid
Command (1)
data in
Byte 0, Byte1
24-bit address
high impedance
data in
Byte n-1, Byte n
04 (hex)
05 (hex)
status (2)
Note: (1) During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05 hex), and RDSCUR command (2B hex).
(2) Once an internal programming operation begins, CS# goes low will drive the status on the SO pin and
CS# goes high will return the SO pin to tri-state.
(3) To end the CP mode, either reaching the highest unprotected address or sending Write Disable (WRDI)
command (04 hex) may achieve it and then it is recommended to send RDSR command (05 hex) to verify if
CP mode is ended
Figure 21. Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
24 Bit Address
Command
SI
7
20
6
2
1
0
MSB
Note: SE command is 20(hex).
Figure 22. Block Erase (BE) Sequence (Command D8)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24 Bit Address
23 22
D8
2
1
0
MSB
Note: BE command is D8(hex).
P/N: PM1372
37
REV. 1.2, JUL. 06, 2009
MX25L1636D
Figure 23. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
60 or C7
Note: CE command is 60(hex) or C7(hex).
Figure 24. Deep Power-down (DP) Sequence (Command B9)
CS#
0
1
2
3
4
5
6
tDP
7
SCLK
Command
B9
SI
Deep Power-down Mode
Stand-by Mode
Figure 25. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
SI
AB
tRES2
3 Dummy Bytes
23 22 21
3
2
1
0
MSB
SO
Electronic Signature Out
High-Z
7
6
5
4
3
2
1
0
MSB
Deep Power-down Mode
P/N: PM1372
38
Stand-by Mode
REV. 1.2, JUL. 06, 2009
MX25L1636D
Figure 26. Release from Deep Power-down (RDP) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
tRES1
7
SCLK
Command
SI
AB
High-Z
SO
Stand-by Mode
Deep Power-down Mode
Figure 27. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)
CS#
0
1
2
3
4
5
6
7
8
9 10
SCLK
Command
SI
2 Dummy Bytes
15 14 13
90
3
2
1
0
High-Z
SO
CS#
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
ADD (1)
SI
7
6
5
4
3
2
1
0
Manufacturer ID
SO
X
7
6
5
4
3
2
1
Device ID
0
7
6
5
4
3
2
MSB
MSB
1
0
7
MSB
Notes:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first
(2) Instruction is either 90(hex) or EF(hex) or DF(hex).
P/N: PM1372
39
REV. 1.2, JUL. 06, 2009
MX25L1636D
Figure 28. Power-up Timing
VCC
VCC(max)
Chip Selection is Not Allowed
VCC(min)
tVSL
Device is fully
accessible
time
Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V.
Table 11. Power-Up Timing
Symbol
tVSL(1)
Parameter
VCC(min) to CS# low
Min.
200
Max.
Unit
us
Note: 1. The parameter is characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
P/N: PM1372
40
REV. 1.2, JUL. 06, 2009
MX25L1636D
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
VCC
VCC(min)
GND
tSHSL
tVR
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
LSB IN
MSB IN
SI
High Impedance
SO
Figure A. AC Timing at Device Power-Up
Symbol
tVR
Parameter
VCC Rise Time
Notes
1
Min.
20
Max.
500000
Unit
us/V
Notes :
1.Sampled, not 100% tested.
2.For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
"AC CHARACTERISTICS" table.
P/N: PM1372
41
REV. 1.2, JUL. 06, 2009
MX25L1636D
ERASE AND PROGRAMMING PERFORMANCE
PARAMETER
Min.
TYP. (1)
Max. (2)
UNIT
Write Status Register Cycle Time
40
100
ms
Sector Erase Cycle Time
60
300
ms
Block Erase Cycle Time
0.7
2
s
Chip Erase Cycle Time
14
30
s
Byte Program Time (via page program command)
9
300
us
1.4
5
ms
Page Program Cycle Time
Erase/Program Cycle
100,000
cycles
Note:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern.
2. Under worst conditions of 85°C and 2.7V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command.
4. The maximum chip programming time is evaluated under the worst conditions of 0C, VCC=3.0V, and 100K cycle
with 90% confidence level.
Data Retention
PARAMETER
Condition
Min.
Data retention
55˚C
20
Max.
UNIT
years
LATCH-UP CHARACTERISTICS
MIN.
MAX.
Input Voltage with respect to GND on all power pins, SI, CS#
-1.0V
2 VCCmax
Input Voltage with respect to GND on SO
-1.0V
VCC + 1.0V
-100mA
+100mA
Current
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
P/N: PM1372
42
REV. 1.2, JUL. 06, 2009
MX25L1636D
ORDERING INFORMATION
MX25L1636DMI-12G
86
OPERATING
CURRENT
MAX. (mA)
25
MX25L1636DM2I-12G
86
25
PART NO.
P/N: PM1372
CLOCK
(MHz)
STANDBY
CURRENT
MAX. (uA)
20
20
43
TEMPERATURE
PACKAGE
Remark
-40°C~85°C
16-SOP
8-SOP
(200mil)
Pb-free
-40°C~85°C
Pb-free
REV. 1.2, JUL. 06, 2009
MX25L1636D
PART NAME DESCRIPTION
MX 25
L 1636D
M
I
12 G
OPTION:
G: Pb-free
SPEED:
12: 86MHz
TEMPERATURE RANGE:
I: Industrial (-40C to 85C)
PACKAGE:
M: 300mil 16-SOP
M2: 200mil 8-SOP
DENSITY & MODE:
1636D: 16Mb standard type
TYPE:
L: 3V
DEVICE:
25: Serial Flash
P/N: PM1372
44
REV. 1.2, JUL. 06, 2009
MX25L1636D
PACKAGE INFORMATION
P/N: PM1372
45
REV. 1.2, JUL. 06, 2009
MX25L1636D
P/N: PM1372
46
REV. 1.2, JUL. 06, 2009
MX25L1636D
REVISION HISTORY
Revision No. Description
Page
Date
1.0
1. Revised sector erase time spec from 90ms(typ.) to 60ms(typ.)
P5,44
OCT/14/2008
2. Revised sector erase time spec from 120ms(max.) to 300ms(max.) P30
3. Revised block erase time spec from 1s(typ.) to 0.7s(typ.)
P30
4. Removed "Preliminary"
P5
5. Removed 8-WSON & 8-SOP(150mil) package option
P6,8,45,46
6. Rewrite 4xI/O Read performance enhance mode process flow P19,20
description
7. Added "Release Read Enhance mode" in command table
P14
1.1
1. Removed "Low Vcc write inhibit is from 1.5V to 2.5V."
P1,10,26,40 FEB/23/2009
2. Revised Maximum Negative and Positive overshoot waveform
P27
3. Revised the NOTICE of absolute maximum ratings
P27
1.2
1. Revised 1406-8SOP (mil) package information
P46
JUL/03/2009
2. Removed loading condition
P5,28,30
3. Revised data retention as 20 years and added the condition
P5,42
4. Removed 20mA low active current (VCC Read) condition
P5,29
5. Revised pin symbol: SIO into SO
P6-10,15,
17-22,35,36
6. Revised data input as data multiple
P6
7. Revised wording: 2READ into DREAD, 4READ into QREAD
P14,20,21,22
and removed 2READ/4READ command
23,30,35,36
8. Added the fC/fR condition of tCH/tCL
P30
9. Removed Release Read Enhanced command
P14
10. Added MXSMIO trademark
P5,48
P/N: PM1372
47
REV. 1.2, JUL. 06, 2009
MX25L1636D
Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which
the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft
and military application. Macronix and its suppliers will not be liable to you and/or any third party for any claims,
injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications.
Copyright Macronix International Co., Ltd. 2008~2009. All Rights Reserved. Macronix, MXIC, MXIC Logo, MX
and MXSMIO Logo, are trademarks or registered trademarks of Macronix International Co., Ltd.. The names
and brands of other companies are for identification purposes only and may be claimed as the property of the
respective companies.
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