MX30LFxG28AB

MX30LF2G28AB
MX30LF4G28AB
3V, 2G/4G-bit NAND Flash Memory
MX30LFxG28AB
P/N: PM2029
REV. 1.2, JAN. 09, 2015
1
MX30LF2G28AB
MX30LF4G28AB
Contents
1.FEATURES........................................................................................................................................6
2. GENERAL DESCRIPTIONS..............................................................................................................7
Figure 1. Logic Diagram.......................................................................................................................... 7
2-1. ORDERING INFORMATION....................................................................................................8
3. PIN CONFIGURATIONS..................................................................................................................10
3-1. PIN DESCRIPTIONS..............................................................................................................12
4. BLOCK DIAGRAM...........................................................................................................................14
5. SCHEMATIC CELL LAYOUT AND ADDRESS ASSIGNMENT.......................................................15
Table 1-1. Address Allocation................................................................................................................ 15
6. DEVICE OPERATIONS....................................................................................................................16
6-1. Address Input/Command Input/Data Input.........................................................................16
Figure 2. AC Waveforms for Command / Address / Data Latch Timing................................................ 16
Figure 3. AC Waveforms for Address Input Cycle................................................................................. 16
Figure 4. AC Waveforms for Command Input Cycle............................................................................. 17
Figure 5. AC Waveforms for Data Input Cycle...................................................................................... 17
6-2. Page Read.............................................................................................................................18
Figure 6. AC Waveforms for Read Cycle.............................................................................................. 18
Figure 7. AC Waveforms for Read Operation (Intercepted by CE#)..................................................... 19
Figure 8. AC Waveforms for Read Operation (with CE# Don't Care).................................................... 20
Figure 9-1. AC Waveforms for Sequential Data Out Cycle (After Read)............................................... 20
Figure 9-2. AC Waveforms for Sequential Data Out Cycle (After Read) - EDO Mode.......................... 21
Figure 10. AC Waveforms for Random Data Output............................................................................. 22
6-3. Cache Read Sequential........................................................................................................23
Figure 11-1. AC Waveforms for Cache Read Sequential...................................................................... 24
6-4. Cache Read Random............................................................................................................25
Figure 11-2. AC Waveforms for Cache Read Random......................................................................... 26
6-5. Page Program.......................................................................................................................27
Figure 12. AC Waveforms for Program Operation after Command 80H............................................... 27
Figure 13. AC Waveforms for Random Data In (For Page Program).................................................... 28
Figure 14. AC Waveforms for Program Operation with CE# Don't Care............................................... 29
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MX30LF2G28AB
MX30LF4G28AB
6-6. Cache Program.....................................................................................................................30
Figure 15-1. AC Waveforms for Cache Program ................................................................................. 31
Figure 15-2. AC Waveforms for Sequence of Cache Program ............................................................ 32
6-7. Block Erase...........................................................................................................................33
Figure 16. AC Waveforms for Erase Operation..................................................................................... 33
6-8. ID Read..................................................................................................................................34
Table 2. ID Codes Read Out by ID Read Command 90H..................................................................... 34
Table 3. The Definition of Byte2~Byte4 of ID Table............................................................................... 35
Figure 17-1. AC Waveforms for ID Read Operation.............................................................................. 36
Figure 17-2. AC Waveforms for ID Read (ONFI Identifier) Operation................................................... 36
6-9. Status Read...........................................................................................................................37
Table 4. Status Output........................................................................................................................... 37
Figure 18. Bit Assignment (HEX Data).................................................................................................. 38
Figure 19. AC Waveforms for Status Read Operation.......................................................................... 38
6-10. Status Enhance Read...........................................................................................................39
Figure 20. AC Waveforms for Status Enhance Operation..................................................................... 39
6-11.Reset......................................................................................................................................40
Figure 21. AC waveforms for Reset Operation..................................................................................... 40
6-12. Parameter Page Read (ONFI)...............................................................................................41
Figure 22. AC waveforms for Parameter Page Read (ONFI) Operation .............................................. 41
Figure 23. AC Waveforms for Parameter Page Read (ONFI) Random Operation (For 05h-E0h)........ 42
Table 5. Parameter Page (ONFI).......................................................................................................... 43
6-13. Unique ID Read (ONFI).........................................................................................................45
Figure 24. AC waveforms for Unique ID Read Operation..................................................................... 46
Figure 25. AC waveforms for Unique ID Read Operation (For 05h-E0h).............................................. 47
6-14. Feature Set Operation (ONFI)..............................................................................................48
Table 6-1. Definition of Feature Address............................................................................................... 48
Table 6-2. Sub-Feature Parameter Table of Feature Address - 90h (Array Operation Mode)............... 48
6-14-1. Set Feature (ONFI).................................................................................................................. 49
Figure 26. AC Waveforms for Set Feature (ONFI) Operation .............................................................. 49
6-14-2. Get Feature (ONFI).................................................................................................................. 50
Figure 27. AC Waveforms for Get Feature (ONFI) Operation............................................................... 50
6-14-3. Secure OTP (One-Time-Programmable) Feature................................................................. 51
Figure 28. AC Waveforms for OTP Data Read..................................................................................... 51
Figure 29. AC Waveforms for OTP Data Read with Random Data Output........................................... 52
Figure 30. AC Waveforms for OTP Data Program................................................................................ 53
Figure 31. AC Waveforms for OTP Data Program with Random Data Input......................................... 54
Figure 32. AC Waveforms for OTP Protection Operation ..................................................................... 55
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MX30LF2G28AB
MX30LF4G28AB
6-15. Two-Plane Operations..........................................................................................................56
6-16. Two-plane Program (ONFI) and Two-plane Cache Program (ONFI).................................56
Figure 33-1. AC Waveforms for Two-plane Program (ONFI)................................................................ 57
Figure 33-2. AC Waveforms for Page Program Random Data Two-plane (ONFI)................................ 58
Figure 34. AC Waveforms for Two-plane Cache Program (ONFI)........................................................ 59
6-17. Two-plane Block Erase (ONFI).............................................................................................60
Figure 35. AC Waveforms for Two-plane Erase (ONFI)........................................................................ 60
7.PARAMETERS.................................................................................................................................61
7-1. ABSOLUTE MAXIMUM RATINGS........................................................................................61
Table 7. Operating Range..................................................................................................................... 62
Table 8. DC Characteristics................................................................................................................... 62
Table 9. Capacitance............................................................................................................................. 63
Table 10. AC Testing Conditions........................................................................................................... 63
Table 11. Program and Erase Characteristics....................................................................................... 63
Table 12. AC Characteristics................................................................................................................. 64
8. OPERATION MODES: LOGIC AND COMMAND TABLES.............................................................65
Table 13. Logic Table............................................................................................................................ 65
Table 14-1. HEX Command Table......................................................................................................... 66
Table 14-2. Two-plane Command Set................................................................................................... 66
8-1. R/B#: Termination for The Ready/Busy# Pin (R/B#).........................................................67
Figure 36. R/B# Pin Timing Information................................................................................................ 68
8-2. Power On/Off Sequence.......................................................................................................69
Figure 37. Power On/Off Sequence ..................................................................................................... 69
8-2-1. WP# Signal .............................................................................................................................. 70
Figure 38-1. Enable Programming of WP# Signal................................................................................ 70
Figure 38-2. Disable Programming of WP# Signal................................................................................... 70
Figure 38-3. Enable Erasing of WP# Signal.......................................................................................... 70
Figure 38-4. Disable Erasing of WP# Signal......................................................................................... 70
9. SOFTWARE ALGORITHM...............................................................................................................71
9-1. Invalid Blocks (Bad Blocks) ................................................................................................71
Figure 39. Bad Blocks........................................................................................................................... 71
Table 15. Valid Blocks........................................................................................................................... 71
9-2. Bad Block Test Flow.............................................................................................................72
Figure 40. Bad Block Test Flow............................................................................................................. 72
9-3. Failure Phenomena for Read/Program/Erase Operations................................................72
Table 16. Failure Modes........................................................................................................................ 72
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MX30LF2G28AB
MX30LF4G28AB
9-4.Program.................................................................................................................................73
Figure 41. Failure Modes...................................................................................................................... 73
Figure 42. Program Flow Chart............................................................................................................. 73
9-5.Erase......................................................................................................................................73
Figure 43. Erase Flow Chart................................................................................................................. 74
Figure 44. Read Flow Chart.................................................................................................................. 74
10.PACKAGE INFORMATION..............................................................................................................75
11.REVISION HISTORY .......................................................................................................................77
P/N: PM2029
REV. 1.2, JAN. 09, 2015
5
MX30LF2G28AB
MX30LF4G28AB
3V 2Gb/4Gb NAND Flash Memory
1. FEATURES
• 2G-bit/4G-bit
• Hardware Data Protection: WP# pin
SLC NAND Flash
- Bus: x8
• Device Status Indicators
- Page size: (2048+112) byte,
- Block size: (128K+7K) byte, - Plane size:
1024-block/plane x 2 for 2Gb
- Ready/Busy (R/B#) pin
- Status Register
• Chip Enable Don't Care
- Simplify System Interface
2048-block/plane x 2 for 4Gb
• Unique ID Read support (ONFI)
• ONFI 1.0 compliant
• Secure OTP support
• Multiplexed Command/Address/Data
• Electronic Signature
• User Redundancy
• High Reliability
- 112-byte attached to each page
- Endurance: typical 100K cycles (with 8-bit ECC
per (512+28) Byte)
• Fast Read Access
- Latency of array to register: 25us
- Data Retention: 10 years
- Sequential read: 20ns
• Wide Temperature Operating Range
• Cache Read Support
-40°C to +85°C
• Page Program Operation
• Package:
- Page program time: 300us( typ.)
1) 48-TSOP(I) (12mm x 20mm)
• Cache Program Support
2) 63-ball 9mmx11mm VFBGA
• Block Erase Operation
All packaged devices are RoHS Compliant and
Halogen-free.
- Block erase time: 1ms (typ.)
• Single Voltage Operation:
- VCC: 2.7 ~ 3.6V
• Low Power Dissipation
- Max. 30mA
Active current (Read/Program/Erase)
• Sleep Mode
- 50uA (Max) standby current
P/N: PM2029
REV. 1.2, JAN. 09, 2015
6
MX30LF2G28AB
MX30LF4G28AB
2. GENERAL DESCRIPTIONS
The MX30LFxG28AB is a 2Gb to 4Gb SLC NAND Flash memory device. Its standard NAND Flash features
and reliable quality of typical P/E cycles 100K (with ECC), which makes it most suitable for embedded
system code and data storage.
The product family requires 8-bit ECC per (512+28)B.
The MX30LFxG28AB is typically accessed in pages of 2,160 bytes for read and program operations.
The MX30LFxG28AB array is organized as thousands of blocks, which is composed by 64 pages of (2,048+112)
byte in two NAND strings structure with 32 serial connected cells in each string. Each page has an additional
112 bytes for ECC and other purposes. The device has an on-chip buffer of 2160 bytes for data load and
access.
The Cache Read Operation of the MX30LFxG28AB enables first-byte read-access latency of 25us and sequential read of 20ns and the latency time of next sequential page will be shorten from tR to tRCBSY.
The MX30LFxG28AB power consumption is 30mA during all modes of operations (Read/Program/Erase),
and 50uA in standby mode.
Figure 1. Logic Diagram
IO7 - IO0
ALE
CLE
CE#
RE#
2Gb
4Gb
WE#
R/B#
WP#
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MX30LF2G28AB
MX30LF4G28AB
2-1. ORDERING INFORMATION
Part Name Description
MX 30 L F 2G 28A B - T
I
xx
RESERVE
OPERATING TEMPERATURE:
I: Industrial (-40°C to 85°C)
PACKAGE TYPE:
T: 48TSOP
XK: 0.8mm Ball Pitch, 0.45mm Ball Size and 1.0mm height of VFBGA
Package: RoHS Compliant & Halogen-free
GENERATION (Tech. Code): B
OPTION CODE:
28A= 8-bit ECC with standard feature, x8, mode A
(Mode A: number of die=1,
number of CE#=1,
number of R/B#=1)
DENSITY:
2G= 2G-bit
4G= 4G-bit
CLASSIFICATION:
F = SLC + Large Block
VOLTAGE:
L = 2.7V to 3.6V
TYPE:
30 = NAND Flash
BRAND:
MX
P/N: PM2029
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MX30LF2G28AB
MX30LF4G28AB
Part Number
Density
Organization
VCC Range
Package
Temperature Grade
MX30LF2G28AB-TI
2Gb
x8
3V
48-TSOP
Industrial
MX30LF2G28AB-XKI
2Gb
x8
3V
63-VFBGA
Industrial
MX30LF4G28AB-TI
4Gb
x8
3V
48-TSOP
Industrial
MX30LF4G28AB-XKI
4Gb
x8
3V
63-VFBGA
Industrial
P/N: PM2029
REV. 1.2, JAN. 09, 2015
9
MX30LF2G28AB
MX30LF4G28AB
3. PIN CONFIGURATIONS
48-TSOP
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VSS1
NC
NC
NC
IO7
IO6
IO5
IO4
NC
VCC1
DNU
VCC
VSS
NC
VCC1
NC
IO3
IO2
IO1
IO0
NC
NC
NC
VSS1
Note 1. These pins might not be connected internally. However, it is recommended to connect these pins to power(or ground) as designated for ONFI compatibility.
P/N: PM2029
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MX30LF2G28AB
MX30LF4G28AB
63-ball 9mmx11mm VFBGA
1
2
A
NC
NC
B
NC
3
4
5
6
8
7
C
WP#
ALE
Vss
CE#
WE#
R/B#
D
Vcc
1
RE#
CLE
NC
NC
NC
E
NC
NC
NC
NC
NC
NC
F
NC
NC
NC
NC
Vss
1
NC
G
NC
Vcc
DNU
NC
NC
NC
H
NC
I/O0
NC
NC
NC
Vcc
J
NC
IO1
NC
Vcc
IO5
IO7
K
Vss
IO2
IO3
IO4
I/O6
Vss
1
9
10
NC
NC
NC
NC
L
NC
NC
NC
NC
M
NC
NC
NC
NC
Note 1. These pins might not be connected internally; however, it is recommended to connect these pins to power (or ground) as designated for ONFI compatibility.
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MX30LF2G28AB
MX30LF4G28AB
3-1. PIN DESCRIPTIONS
SYMBOL
IO7 - IO0
PIN NAME
Data I/O port
CE#
Chip Enable (Active Low)
RE#
Read Enable (Active Low)
WE#
Write Enable (Active Low)
CLE
Command Latch Enable
ALE
Address Latch Enable
WP#
Write Protect (Active Low)
R/B#
Ready/Busy (Open Drain)
VSS
Ground
VCC
Power Supply for Device Operation
NC
DNU
Not Connected Internally
Do Not Use (Do Not Connect)
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MX30LF2G28AB
MX30LF4G28AB
PIN FUNCTIONS
COMMAND LATCH ENABLE: CLE
The MX30LFxG28AB is a sequential access
memory that utilizes multiplexing input of
Command/Address/Data.
The CLE controls the command input. When the
CLE goes high, the command data is latched at the
rising edge of the WE#.
I/O PORT: IO7 - IO0
ADDRESS LATCH ENABLE: ALE
The IO7 to IO0 pins are for address/command
input and data output to/from the device.
The ALE controls the address input. When the ALE
goes high, the address is latched at the rising edge
of WE#.
CHIP ENABLE: CE#
The device goes into low-power Standby Mode
when CE# goes high during a read operation and
not at busy stage.
WRITE PROTECT: WP#
The WP# signal keeps low and then the memory will
not accept the program/erase operation. It is recommended to keep WP# pin low during power on/off
sequence. Please refer to the waveform of "Power
On/Off Sequence".
The CE# goes low to enable the device to be
ready for standard operation. When the CE# goes
high, the device is deselected. However, when the
device is at busy stage, the device will not go to
standby mode when CE# pin goes high.
READY/Busy: R/B#
READ ENABLE: RE#
The R/B# is an open-drain output pin. The R/B#
outputs the ready/busy status of read/program/
erase operation of the device. When the R/B# is at
low, the device is busy for read or program or erase
operation. When the R/B# is at high, the read/
program/erase operation is finished.
The RE# (Read Enable) allows the data to be
output by a tREA time after the falling edge of
RE#. The internal address counter is automatically
increased by one at the falling edge of RE#.
Please refer to Section 9-1 for details.
WRITE ENABLE: WE#
When the WE# goes low, the address/data/
command are latched at the rising edge of WE#.
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MX30LF2G28AB
MX30LF4G28AB
CE#
High Voltage
Circuit
WE#
WP#
RE#
IO Port
CLE
ALE
Control
Logic
X-DEC
4. BLOCK DIAGRAM
Memory Array
(Two planes)
Page Buffer
ADDRESS
COUNTER
Y-DEC
R/B#
IO[7:0]
Data
Buffer
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MX30LF2G28AB
MX30LF4G28AB
5. SCHEMATIC CELL LAYOUT AND ADDRESS ASSIGNMENT
MX30LFxG28AB NAND device is divided into two planes, which is composed by 64 pages of (2,048+112)-byte
in two NAND strings structure with 32 serial connected cells in each string. Each page has an additional 112
bytes for ECC and other purposes. The device has an on-chip buffer of 2160 bytes for data load and access.
Each 2K-Byte page has the two area, one is the main area which is 2048-bytes and the other is spare area
which is 112-byte.
There are five address cycles for the address allocation, please refer to the table below.
Table 1-1. Address Allocation
Addresses
Column address - 1st cycle
Column address - 2nd cycle
Row address - 3rd cycle
Row address - 4th cycle
Row address - 5th cycle
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
A7
L
A19
A27
L
A6
L
A181
A26
L
A5
L
A17
A25
L
A4
L
A16
A24
L
A3
A11
A15
A23
L
A2
A10
A14
A22
L
A1
A9
A13
A21
A292
A0
A8
A12
A20
A28
Notes:
1. A18 is the plane selection.
2. A29 is for 4Gb, "L" (Low) is for 2Gb.
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MX30LF2G28AB
MX30LF4G28AB
6. DEVICE OPERATIONS
6-1. Address Input/Command Input/Data Input
Address input bus operation is for address input to select the memory address. The command input bus
operation is for giving command to the memory. The data input bus is for data input to the memory device.
Figure 2. AC Waveforms for Command / Address / Data Latch Timing
CLE
ALE
CE#
tCS
/
/ tCLS / tALS
tCH tCLH
tWP
WE#
tDS
tDH
IO[7:0]
Figure 3. AC Waveforms for Address Input Cycle
tCLS
CLE
tWC
tWC
tWC
tWC
CE#
tWP
tWH
tWP
tWH
tWP
tWH
tWP
tWH
tWP
WE#
tALS
tALH
ALE
tDS
IO[7:0]
tDH
1st Address
Cycle
tDS
tDH
2nd Address
Cycle
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tDS
tDH
3rd Address
Cycle
tDS
tDH
4th Address
Cycle
tDS
tDH
5th Address
Cycle
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MX30LF4G28AB
Figure 4. AC Waveforms for Command Input Cycle
CLE
tCLS
tCLH
tCS
tCH
CE#
tWP
WE#
tALS
tALH
ALE
tDS
tDH
IO[7:0]
Figure 5. AC Waveforms for Data Input Cycle
tCLH
CLE
tCH
CE#
tWC
tWP
tWH
tWP
tWH
tWP
tWP
WE#
ALE
tALS
tDS
IO[7:0]
tDH
Din0
tDS
tDH
Din1
P/N: PM2029
tDS
tDH
Din2
tDS
tDH
DinN
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6-2. Page Read
The MX30LFxG28AB array is accessed in Page of 2160 bytes. External reads begins after the R/B# pin goes
to READY.
The Read operation may also be initiated by writing the 00h command and giving the address (column and
row address) and being confirmed by the 30h command, the MX30LFxG28AB begins the internal read
operation and the chip enters busy state. The data can be read out in sequence after the chip is ready. Refer
to the waveform for Read Operation as below.
If the host side uses a sequential access time (tRC) of less than 30ns, the data can be latched on the next
falling edge of RE# as the waveform of EDO mode (Figure 9-2).
To access the data in the same page randomly, a command of 05h may be written and only column address
following and then confirmed by E0h command.
Figure 6. AC Waveforms for Read Cycle
CLE
tCLS
tCLS
tCLH
tCLH
tCS
CE#
tWC
WE#
tALS
tAR
tALH
tALH
ALE
tRR
tR
tRC
tOH
RE#
tWB
tDS
IO[7:0]
00h
tDH
tDS tDH
1st Address
Cycle
tDS tDH
2nd Address
Cycle
tDS tDH
3rd Address
Cycle
tDS tDH
4th Address
Cycle
tDS tDH
5th Address
Cycle
tREA
tDS tDH
Dout
30h
Dout
R/B#
Busy
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Figure 7. AC Waveforms for Read Operation (Intercepted by CE#)
CLE
tCHZ
CE#
WE#
tAR
ALE
tOH
tRC
RE#
tRR
tR
tWB
IO[7:0]
00h
1st Address
Cycle
2nd Address
Cycle
3rd Address
Cycle
4th Address
Cycle
5th Address
Cycle
30h
Dout 0
Dout 1
Dout 2
Dout 3
R/B#
Busy
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Figure 8. AC Waveforms for Read Operation (with CE# Don't Care)
CLE
CE# Don’t Care
CE#
WE#
ALE
RE#
IO[7:0]
Start Addr (5 Cycles)
00h
Data Output (Sequential)
30h
R/B#
Busy
Note: The CE# "Don't Care" feature may simplify the system interface, which allows controller to directly
download the code from flash device, and the CE# transitions will not stop the read operation
during the latency time.
Figure 9-1. AC Waveforms for Sequential Data Out Cycle (After Read)
t CEA
CE#
tRC
tRP
RE#
t REH
t RP
t RHZ
tREA
IO[7:0]
tOH
Dout0
t REH
t RP
tRHZ
t REA
tOH
Dout1
t REA
t RP
tCOH
t CHZ
t RHZ
tRHZ
t OH
tOH
Dout2
DoutN
tRR
R/B#
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MX30LF4G28AB
Figure 9-2. AC Waveforms for Sequential Data Out Cycle (After Read) - EDO Mode
t CEA
CE#
tRC
tRP
RE#
t REH
tRHZ
t REA
IO[7:0]
t RP
tRLOH t
Dout0
t REH
tRHZ
REA
t RP
tRLOH t
Dout1
t RP
t REH
t CHZ
t COH
tRHZ
REA
t RLOH
Dout2
tOH
DoutN
tRR
R/B#
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Figure 10. AC Waveforms for Random Data Output
A
tCLR
CLE
CE#
WE#
tAR
ALE
tRC
RE#
tRHW
tRR
tR
tWB
IO[7:0]
00h
1st Address
Cycle
2nd Address
Cycle
3rd Address
Cycle
4th Address
Cycle
5th Address
Cycle
Dout M
30h
Dout M+1
05h
R/B#
CLE
Busy
A
CE#
WE#
tWHR
ALE
RE#
tREA
IO[7:0]
05h
1st Address
Cycle
2nd Address
Cycle
E0h
Dout N
Dout N+1
R/B#
Repeat if needed
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MX30LF4G28AB
6-3. Cache Read Sequential
The cache read sequential operation is for throughput enhancement by using the internal cache buffer. It
allows the consecutive pages to be read-out without giving next page address, which reduces the latency
time from tR to tRCBSY between pages or blocks. While the data is read out on one page, the data of next
page can be read into the cache buffer.
After writing the 00h command, the column and row address should be given for the start page selection,
and followed by the 30h command for address confirmation. After that, the CACHE READ operation starts
after a latency time tR and following a 31h command with the latency time of tRCBSY, the data can be readout sequentially from 1st column address (A[11:0]=00h) without giving next page address input. The 31h
command is necessary to confirm the next cache read sequential operation and followed by a tRCBSY
latency time before next page data is necessary. The CACHE READ SEQUENTIAL command is also valid
for the consecutive page cross block.
The random data out (05h-E0h) command set is available to change the column address of the current page
data in the cache register.
The user can check the chip status by the following method:
- R/B# pin ("0" means the data is not ready, "1" means the user can read the data)
- Status Register (SR[6] functions the same as R/B# pin, SR[5] indicates the internal chip operation, "0"
means the chip is in internal operation and "1" means the chip is idle.) Status Register can be checked
after the Read Status command (70h) is issued. Command 00h should be given to return to the cache read
sequential operation.
To confirm the last page to be read-out during the cache read sequential operation, a 3Fh command is
needed to replace the 31h command prior to the last data-out.
P/N: PM2029
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MX30LF2G28AB
MX30LF4G28AB
Figure 11-1. AC Waveforms for Cache Read Sequential
A
tCLR
CLE
CE#
WE#
tAR
ALE
tRC
RE#
tRR
tRCBSY
tR
tWB
IO[7:0]
00h
1st Address
Cycle
3rd Address
Cycle
2nd Address
Cycle
4th Address
Cycle
5th Address
Cycle
tWB
Page 1
Dout 0
31h
30h
Page 1
Dout 1
Page 1
Dout 2159
R/B#
Busy
Busy
CLE
A
tCLR
tCLR
tAR
tAR
CE#
WE#
ALE
tRC
tRC
RE#
tRR
tRR
tRCBSY
tRCBSY
tWB
tWB
IO[7:0]
Page 1
Dout 2159
Page 2
Dout 0
31h
Page 2
Page 2
Dout 1
Dout 2159
Page 3
Dout 0
3Fh
Page 3
Dout 1
Page 3
Dout 2159
R/B#
Busy
Busy
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6-4. Cache Read Random
The main difference from the Cache Read Sequential operation is the Cache Read Random operation may
allow the random page to be read-out with cache operation not just for the consecutive page only.
After writing the 00h command, the column and row address should be given for the start page selection,
and followed by the 30h command for address confirmation. The column address is ignored in the cache
read random operation. And then, the CACHE READ RANDOM operation starts after a latency time tR and
following a 00h command with the selected page address and following a 31h command, the data can be
read-out after the latency time of tRCBSY. After the previous selected page data out, a new selected page
address can be given by writing the 00h-31h command set again. The CACHE READ RANDOM command is
also valid for the consecutive page cross block.
The random data out (05h-E0h) command set is available to change the column address of the current page
data in the cache register.
The user can check the chip status by the following method:
- R/B# pin ("0" means the data is not ready, "1" means the user can read the data)
- Status Register can be checked after the Read Status command (70h) is issued. (SR[6] behaves the same
as R/B# pin, SR[5] indicates the internal chip operation, "0" means the chip is in internal operation and "1"
means the chip is idle.) Command 00h should be given to return to the cache read operation.
To confirm the last page to be read-out during the cache read operation, a 3Fh command is needed to replace
the 31h command prior to the last data-out.
P/N: PM2029
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MX30LF2G28AB
MX30LF4G28AB
Figure 11-2. AC Waveforms for Cache Read Random
A
tCLR
CLE
CE#
WE#
tAR
ALE
tRC
RE#
tRR
tR
tWB
tWB
IO[7:0]
00h
1st Address
Cycle
2nd Address 3rd Address
Cycle
Cycle
4th Address
Cycle
5th Address
Cycle
1st Address
Cycle
00h
30h
2nd Address 3rd Address
Cycle
Cycle
4th Address
Cycle
5th Address
Cycle
tRCBSY
Page n
Dout 0
31h
Page n
Dout 1
Page n
Dout 2159
Page m address
Page n address
R/B#
Busy
Busy
A
CLE
tCLR
CE#
WE#
tAR
ALE
tRC
RE#
tRR
tWB
IO[7:0]
Page n
Dout 0
Page n
Dout 1
Page n
Dout 2159
00h
1st Address
Cycle
2nd Address 3rd Address
Cycle
Cycle
4th Address
Cycle
5th Address
Cycle
tRCBSY
Page m
Dout 0
31h
Page m
Dout 1
Page m
Dout 2159
Page x address
R/B#
Busy
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6-5. Page Program
The memory is programmed by page, which is 2,160 bytes. After Program load command (80h) is issued
and the row and column address is given, the data will be loaded into the chip sequentially. Random Data
Input command (85h) allows multi-data load in non-sequential address. After data load is complete, program
confirm command (10h) is issued to start the page program operation. The page program operation in a block
should start from the low address to high address (A[17:12]). Partial program in a page is allowed up to 4
times. However, the random data input mode for programming a page is allowed and number of times is not
limited.
The status of the program completion can be detected by R/B# pin or Status register bit SR[6].
The program result is shown in the chip status bit (SR[0]). SR[0] = 1 indicates the Page Program is not
successful and SR[0] = 0 means the program operation is successful.
During the Page Program progressing, only the read status register command and reset command are
accepted, others are ignored.
Figure 12. AC Waveforms for Program Operation after Command 80H
CLE
tCLS
tCLH
CE#
tCS
tWC
WE#
tALS
tWB
tALH
tALH
ALE
RE#
tDS tDH
IO[7:0]
80h
tDS/tDH
Din
0
-
1st Address
Cycle
2nd Address 3rd Address 4th Address 5th Address
Cycle
Cycle
Cycle
Cycle
Din
n
10h
70h
Status
Output
tPROG
R/B#
P/N: PM2029
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Figure 13. AC Waveforms for Random Data In (For Page Program)
A
CLE
CE#
tWC
tADL
WE#
ALE
RE#
IO[7:0]
80h
1st Address 2nd Address 3rd Address 4th Address 5th Address
Cycle
Cycle
Cycle
Cycle
Cycle
Din A
Din A+N
R/B#
A
CLE
CE#
tWC
tADL
WE#
tWB
ALE
RE#
IO[7:0]
85h
1st Address 2nd Address
Cycle
Cycle
Din B+M
Din B
70h
10h
Status
tPROG
R/B#
Repeat if needed
IO0 = 0; Pass
IO0 = 1; Fail
Note: Random Data In is also supported in cache program.
P/N: PM2029
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Figure 14. AC Waveforms for Program Operation with CE# Don't Care
A
CLE
CE#
WE#
ALE
IO[7:0]
Start Add. (5 Cycles)
80h
Data Input
A
CLE
CE#
WE#
ALE
IO[7:0]
Data Input
Data Input
10h
Note: The CE# "Don't Care" feature may simplify the system interface, which allows the controller to
directly write data into flash device, and the CE# transitions will not stop the program operation
during the latency time.
P/N: PM2029
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6-6. Cache Program
The cache program feature enhances the program performance by using the cache buffer of 2,160-byte.
The serial data can be input to the cache buffer while the previous data stored in the buffer are programming
into the memory cell. Cache Program command sequence is almost the same as page program command
sequence. Only the Program Confirm command (10h) is replaced by cache Program command (15h).
After the Cache Program command (15h) is issued. The user can check the status by the following methods.
- R/B# pin
- Cache Status Bit (SR[6] = 0 indicates the cache is busy; SR[6] = 1 means the cache is ready).
The user can issue another Cache Program Command Sequence after the Cache is ready. The user can
always monitor the chip state by Ready/Busy Status Bit (SR[5]). The user can issues either program confirm
command (10h) or cache program command (15h) for the last page if the user monitor the chip status by
issuing Read Status Command (70h).
However, if the user only monitors the R/B# pin, the user needs to issue the program confirm command (10h)
for the last page.
The user can check the Pass/Fail Status through P/F Status Bit (SR[0]) and Cache P/F Status Bit (SR[1]).
SR[1] represents Pass/Fail Status of the previous page. SR[1] is updated when SR[6] change from 0 to 1 or
Chip is ready. SR[0] shows the Pass/Fail status of the current page. It is updated when SR[5] change from "0"
to "1" or the end of the internal programming. For more details, please refer to the related waveforms.
P/N: PM2029
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MX30LF2G28AB
MX30LF4G28AB
Figure 15-1. AC Waveforms for Cache Program
A
CLE
CE#
tADL
tWC
WE#
tWB
ALE
RE#
IO[7:0]
80h
1st Address
Cycle
2nd Address
Cycle
3rd Address
Cycle
4th Address
Cycle
5th Address
Cycle
Din
Din
15h
tCBSY
R/B#
Busy
A
CLE
CE#
tADL
WE#
tWB
ALE
RE#
IO[7:0]
80h
1st Address
Cycle
2nd Address
Cycle
3rd Address
Cycle
4th Address
Cycle
5th Address
Cycle
Din
Din
70h
10h
Status
Output
tPROG
R/B#
Note
Busy
Note: It indicates the last page Input & Program.
P/N: PM2029
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Figure 15-2. AC Waveforms for Sequence of Cache Program
A
IO[7:0]
1st Address 2nd Address 3rd Address 4th Address 5th Address
Cycle
Cycle
Cycle
Cycle
Cycle
80h
Din
Din
15h
80h
1st Address 2nd Address 3rd Address 4th Address 5th Address
Cycle
Cycle
Cycle
Cycle
Cycle
Din
Din
15h
80h
R/B#
Busy - tCBSY
Busy - tCBSY
A
IO[7:0]
80h
1st Address 2nd Address 3rd Address 4th Address 5th Address
Cycle
Cycle
Cycle
Cycle
Cycle
Din
Din
15h
80h
1st Address 2nd Address 3rd Address 4th Address 5th Address
Cycle
Cycle
Cycle
Cycle
Cycle
Din
Din
10h
70h
R/B#
Busy - tCBSY
Busy - tPROG
Note: tPROG = Page(Last) programming time + Page (Last-1) programming time - Input cycle time of
command & address - Data loading time of page (Last).
Note 2
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6-7. Block Erase
The MX30LFxG28AB supports a block erase command. This command will erase a block of 64 pages associated with the most significant address bits.
The completion of the erase operation can be detected by R/B# pin or Status register bit (IO6). Recommend
to check the status register bit IO0 after the erase operation completes.
During the erasing process, only the read status register command and reset command can be accepted,
others are ignored.
Figure 16. AC Waveforms for Erase Operation
CLE
tCLS
tCLH
CE#
tCS
tWC
WE#
tALH
tALS
ALE
tWB
RE#
tDS
IO[7:0]
tDH
tDS
tDH
tDS
tDH
60h
tDS
tDH
70h
D0h
3rd Address Cycle
4th Address Cycle 5th Address Cycle
Stauts
Output
tERASE
R/B#
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MX30LF4G28AB
6-8. ID Read
The device contains ID codes that identify the device type and the manufacturer. The ID READ command
sequence includes one command Byte (90h), one address byte (00h). The Read ID command 90h may
provide the manufacturer ID (C2h) of one-byte and device ID (DAh for 2Gb and DCh for 4Gb) of one-byte,
also Byte2, Byte3, and Byte4 ID code are followed.
The device support ONFI Parameter Page Read, by sending the ID Read (90h) command and following one
byte address (20h), the four-byte data returns the value of 4Fh-4Eh-46h-49h for the ASCII code of "O"-"N""F"-"I" to identify the ONFI parameter page.
Table 2. ID Codes Read Out by ID Read Command 90H
2Gb
Byte0-Manufacturer
Byte1: Device ID
Byte2
2Gb, x8, 3V
C2h
DAh
90h
Byte3
Byte4
4Gb
Byte0-Manufacturer
Byte1: Device ID
Byte2
Byte3
Byte4
95h
07h
4Gb, x8, 3V
C2h
DCh
90h
95h
57h
P/N: PM2029
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Table 3. The Definition of Byte2~Byte4 of ID Table
Terms
Description
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
0
0
0
1
0
1
1
1
Byte 2
Die Number
1
2
Cell Structure
SLC
# of Concurrently
Programmed page
Interleaved operations
between Multiple die
Cache Program
Byte 3
Page size (Exclude spare)
Spare area size (Per 512B)
Block size (Exclude spare)
Organization
1
2
0
0
0
Not supported
Supported
2KB
28B
128KB
x8
25ns
Sequential Read Cycle Time
20ns
Byte 4
ECC level requirement
8-bit ECC/540B
1
#Plane per CE
2
4
1Gb
Plane size
2Gb
Reserved
0
0
1
0
1
1
0
1
0
0
1
0
0
0
0
1
0
1
0
0
0
1
0
0
1
0
P/N: PM2029
REV. 1.2, JAN. 09, 2015
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MX30LF2G28AB
MX30LF4G28AB
Figure 17-1. AC Waveforms for ID Read Operation
CLE
tCLS
tCS
CE#
tCHZ
WE#
tALH
tALS
tAR
ALE
tOH
RE#
tWHR
tDS
IO[7:0]
90h
tREA
tDH
00h
C2h
(note)
(note)
(note)
(note)
Note: See also Table 2. ID Codes Read Out by ID Read Command 90H.
Figure 17-2. AC Waveforms for ID Read (ONFI Identifier) Operation
CLE
tCLS
tCS
CE#
tCHZ
WE#
tALH
tALS
tAR
ALE
tOH
RE#
tWHR
tDS
IO[7:0]
90h
tDH
20h
tREA
4Fh
P/N: PM2029
4Eh
46h
49h
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6-9. Status Read
The MX30LFxG28AB provides a status register that outputs the device status by writing a command code
70h, and then the IO pins output the status at the falling edge of CE# or RE# which occurs last. Even though
when multiple flash devices are connecting in system and the R/B#pins are common-wired, the two lines of
CE# and RE# may be checked for individual devices status separately.
The status read command 70h will keep the device at the status read mode unless next valid command is
issued. The resulting information is outlined in Table 4 as below.
Table 4. Status Output
Pin
SR[0]
SR[1]
SR[2-4]
SR[5]
SR[6]
SR[7]
Status
Chip Status
Cache Program
Result
Not Used
Related Mode
Page Read, Cache Read,
Page Program, Cache
Program (Page N),
Block Erase
Cache Program
(Page N-1)
Cache Program/Cache
Ready / Busy
Read operation, other Page
(For P/E/R Controller) Program/Block Erase/Read
are same as IO6 (Note 1)
Page Program, Block Erase,
Ready / Busy
Cache Program, Read,
Cache Read (Note 2)
Page Program, Block Erase,
Write Protect
Cache Program, Read
Value
0: Passed
1: Failed 0: Passed
1: Failed
0: Busy
1: Ready
0: Busy
1: Ready
0: Protected
1: Unprotected
Notes:
1. During the actual programming operation, the SR[5] is "0" value; however, when the internal operation is completed during the cache mode, the SR[5] returns to "1".
2. The SR[6] returns to "1" when the internal cache is available to receive new data. The SR[6] value is
consistent with the R/B#.
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The following is an example of a HEX data bit assignment:
Figure 18. Bit Assignment (HEX Data)
Status Read: 70h
0
1
1
1
0
0
0
0
SR7
6
5
4
3
2
1 SR0
Figure 19. AC Waveforms for Status Read Operation
tCLR
CLE
tCLS
tCLH
CE#
tCS
tWP
WE#
tCHZ
tWHR
RE#
tOH
tIR
tDS tDH
IO[7:0]
tREA
Status
Output
70h
P/N: PM2029
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MX30LF4G28AB
6-10. Status Enhance Read
The 2Gb and 4Gb support the two-plane operation, the Status Enhanced Read command (78h) offers the
alternative method besides the Status Read command to get the status of specific plane in the same NAND
Flash device. The result information is outlined in Table 4.
The [SR]6 and SR[5] bits are shared with all planes. However, the SR[0], SR[1], SR[3], SR[4] are for the
status of specific plane in the row address. The Status Enhanced Read command is not allowed at power-on
Reset (FFh) command, OTP enabled operation.
Figure 20. AC Waveforms for Status Enhance Operation
CLE
tCLS
tCS
CE#
tCHZ
WE#
tALH
tALS
tAR
ALE
tOH
RE#
tWHR
tDS
IO[7:0]
78h
tREA
tDH
3rd Address
Cycle
4th Address
Cycle
P/N: PM2029
5th Address
Cycle
Status
Output
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6-11. Reset
The reset command FFh resets the read/program/erase operation and clear the status register to be E0h (when
WP# is high). The reset command during the program/erase operation will result in the content of the selected
locations(perform programming/erasing) might be partially programmed/erased.
If the Flash memory has already been set to reset stage with reset command, the additional new reset
command is invalid.
Figure 21. AC waveforms for Reset Operation
CLE
CE#
WE#
ALE
RE#
tWB
IO[7:0]
FFh
tRST
R/B#
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6-12. Parameter Page Read (ONFI)
The NAND Flash device support ONFI Parameter Page Read and the parameter can be read out by sending
the command of ECh and giving the address 00h. The NAND device information may refer to the table of
parameter page(ONFI), there are three copies of 256-byte data and additional redundant parameter pages.
Once sending the ECh command, the NAND device will remain in the Parameter Page Read mode until next
valid command is sent.
The Random Data Out command set (05h-E0h) can be used to change the parameter location for the specific
parameter data random read out.
The Status Read command (70h) can be used to check the completion with a following read command (00h)
to enable the data out.
Figure 22. AC waveforms for Parameter Page Read (ONFI) Operation
tCLR
CLE
CE#
WE#
tAR
ALE
tRC
RE#
tRR
tWB
tR
IO[7:0]
ECh
Parameter 0
Dout 0
00h
Parameter 0
Dout 1
Parameter 0
Dout 255
Parameter 1
Dout 0
R/B#
Busy
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Figure 23. AC Waveforms for Parameter Page Read (ONFI) Random Operation (For 05h-E0h)
tCLR
CLE
CE#
WE#
tWHR
tAR
ALE
tRC
RE#
tRR
tWB
tR
IO[7:0]
ECh
tREA
Parameter 0
Dout 0
00h
Parameter 0
Dout 1
05h
R/B#
1st Address
Cycle
2nd Address
Cycle
E0h
Parameter m
Dout n
Parameter m
Dout n+1
Repeat if needed
Busy
P/N: PM2029
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Table 5. Parameter Page (ONFI)
Byte#
0-3
4-5
6-7
8-9
10-31
Revision Information and Features Block
Description
Data
Parameter Page Signature
Revision Number
Features Supported
Optional Commands
Supported
Reserved
Manufacturer Information Block
Description
Data
Byte#
32-43
2Gb, x8
4Gb, x8
2Gb
4Gb
Device Manufacturer (12 ASCII characters)
MX30LF2G28AB
44-63
64
65-66
67-79
4Fh, 4Eh, 46h, 49h
02h, 00h
18h, 00h
18h, 00h
3Fh, 00h
3Fh, 00h
00h
Device Model
(20 ASCII Characters)
MX30LF4G28AB
JEDEC Manufacturer ID
Date Code
Reserved
P/N: PM2029
4Dh,41h,43h,52h,4Fh,4Eh,49h,58h,
20h,20h,20h,20h
4Dh,58h,33h,30h,4Ch,46h,32h,47h,
32h,38h,41h,42h,20h,20h,20h,20h,2
0h,20h,20h,20h,
4Dh,58h,33h,30h,4Ch,46h,34h,47h,
32h,38h,41h,42h,20h,20h,20h,20h,2
0h,20h,20h,20h,
C2h
00h, 00h
00h
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Byte#
Memory Organization Block
Description
80-83
84-85
86-89
90-91
92-95
Number of Data Bytes per Page
Number of Spare Bytes per Page
Number of Data Bytes per Partial Page
Number of Spare Bytes per Partial Page
Number of Pages per Block
96-99
Number of Blocks per Logical Unit
100
Number of Logical Units (LUNs)
101
Number of Address Cycles
102
Number of Bits per Cell
2048-byte
112-byte
512-byte
28-byte
2Gb
4Gb
2Gb
4Gb
2Gb
4Gb
103-104 Bad Blocks Maximum per LUN
105-106
107
108-109
110
111
112
Block endurance
Guarantee Valid Blocks at Beginning of Target
Block endurance for guaranteed valid blocks
Number of Programs per Page
Partial Programming Attributes
Number of Bits ECC Correctability
113
Number of Interleaved Address Bits
114
Interleaved Operation Attributes
115-127 Reserved
Byte#
128
2Gb
4Gb
2Gb
4Gb
Electrical Parameters Block
Description
Data
00h,08h,00h,00h
70h,00h
00h,02h,00h,00h
1Ch,00h
40h,00h,00h,00h
00h,08h,00h,00h
00h,10h,00h,00h
01h
23h
23h
01h
28h,00h
50h,00h
01h, 05h
01h
01h, 03h
04h
00h
08h
01h
01h
0Eh
0Eh
00h
Data
I/O Pin Capacitance
0Ah
129-130 Timing Mode Support
3Fh,00h
131-132 Program Cache Timing Mode Support
3Fh,00h
133-134 tPROG Maximum Page Program Time (uS)
600us
58h,02h
135-136 tBERS(tERASE) Maximum Block Erase Time (uS)
3,500us
ACh,0Dh
137-138 tR Maximum Page Read Time (uS)
25us
19h,00h
139-140 tCCS Minimum Change Column Setup Time (ns)
60ns
3Ch,00h
141-163 Reserved
00h
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Vendor Blocks
Description
Byte#
164-165 Vendor Specific Revision Number
166-253 Vendor Specific
254-255 Integrity CRC
Redundant Parameter Pages
Description
Byte#
256-511 Value of Bytes 0-255
512-767 Value of Bytes 0-255
768+
Additional Redundant Parameter Pages
Data
00h
00h
Set at Test (Note)
Data
Note:
The Integrity CRC (Cycling Redundancy Check) field is used to verify that the contents of the
parameters page were transferred correctly to the host. Please refer to ONFI 1.0 specifications for
details.
The CRC shall be calculated using the following 16-bit generator polynomial:
G(X) = X16 + X15 +X2 + 1
6-13. Unique ID Read (ONFI)
The unique ID is 32-byte and with 16 copies for back-up purpose. After writing the Unique ID read command
(EDh) and following the one address byte (00h), the host may read out the unique ID data. The host need to
XOR the 1st 16-byte unique data and the 2nd 16-byte complement data to get the result, if the result is FFh,
the unique ID data is correct; otherwise, host need to repeat the XOR with the next copy of Unique ID data.
Once sending the EDh command, the NAND device will remain in the Unique ID read mode until next valid
command is sent.
To change the data output location, it is recommended to use the Random Data Out command set (05h-E0h).
The Status Read command (70h) can be used to check the completion. To continue the read operation, a
following read command (00h) to re-enable the data out is necessary.
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Figure 24. AC waveforms for Unique ID Read Operation
tCLR
CLE
CE#
WE#
tAR
ALE
tRC
RE#
tRR
tWB
tR
IO[7:0]
EDh
Unique ID 0
Dout 0
00h
Unique ID 0
Dout 1
Unique ID 0
Dout 31
Unique ID 1
Dout 0
R/B#
Busy
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Figure 25. AC waveforms for Unique ID Read Operation (For 05h-E0h)
tCLR
CLE
CE#
WE#
tWHR
tAR
ALE
tRC
RE#
tRR
tWB
tR
IO[7:0]
EDh
tREA
Unique ID 0
Dout 0
00h
Unique ID 0
Dout 1
05h
R/B#
1st Address
Cycle
2nd Address
Cycle
E0h
Unique ID m
Dout n
Unique ID m
Dout n+1
Repeat if needed
Busy
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6-14. Feature Set Operation (ONFI)
The Feature Set operation is to change the default power-on feature sets by using the Set Feature and Get
Feature command and writing the specific parameter data (P1-P4) on the specific feature addresses. The
NAND device may remain the current feature set until next power cycle since the feature set data is volatile.
However, the reset command (FFh) can not reset the current feature set.
Table 6-1. Definition of Feature Address
Feature Address
00h-8Fh, 91h-FFh,
90h
Description
Reserved
Array Operation Mode
Table 6-2. Sub-Feature Parameter Table of Feature Address - 90h (Array Operation Mode)
Sub Feature
Parameter
Definition
P1
Normal
Array
Operation OTP Operation
Mode
OTP Protection
P2
P3
P4
IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
Reserved (0)
Reserved (0)
x
0
Reserved (0)
x
0
Reserved (0)
Reserved (0)
Reserved (0)
0
0
1
Values
0 0000 0000b
1 0000 x001b
1 0000 x011b
0000 0000b
0000 0000b
0000 0000b
Notes
1
Note 1. The value is clear to 00h at power cycle.
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6-14-1.Set Feature (ONFI)
The Set Feature command is to change the power-on default feature set. After sending the Set Feature
command (EFh) and following specific feature and then input the P1-P4 parameter data to change the default
power-on feature set. Once sending the EFh command, the NAND device will remain in the Set Feature
mode until next valid command is sent.
The Status Read command (70h) may check the completion of the Set Feature.
Figure 26. AC Waveforms for Set Feature (ONFI) Operation
CLE
CE#
tADL
tWC
WE#
tWB
ALE
RE#
IO[7:0]
EFh
Feature
Address
Din
Din
Din
Din
tFEAT
R/B#
Busy
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6-14-2.Get Feature (ONFI)
The Get Feature command is to read sub-feature parameter. After sending the Get Feature command (EEh)
and following specific feature, the host may read out the P1-P4 sub- feature parameter data. Once sending
the EEh command, the NAND device will remain in the Get Feature mode until next valid command is sent.
The Status Read command (70h) can be used to check the completion. To continue the read operation, a
following read command (00h) to re-enable the data out is necessary.
Please refer to the following waveform of Get Feature Operation for details.
Figure 27. AC Waveforms for Get Feature (ONFI) Operation
tCLR
CLE
CE#
WE#
tAR
ALE
tRC
RE#
tRR
tWB
tFEAT
IO[7:0]
EEh
Feature
Address
Feature
Dout 0
Feature
Dout 1
Feature
Dout 2
Feature
Dout 3
R/B#
Busy
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6-14-3.Secure OTP (One-Time-Programmable) Feature
There is an OTP area which has thirty full pages (30 x 2160-byte) guarantee to be good for system
device serial number storage or other fixed code storage. The OTP area is a non-erasable and one-timeprogrammable area, which is default to “1” and allows whole page or partial page program to be “0”, once the
OTP protection mode is set, the OTP area becomes read-only and cannot be programmed again.
The OTP operation is operated by the Set Feature/ Get Feature operation to access the OTP operation mode
and OTP protection mode.
To check the NAND device is ready or busy in the OTP operation mode, either checking the R/B# or writing
the Status Read command (70h) may collect the status.
To exit the OTP operation or protect mode, it can be done by writing 00h to P1 at feature address 90h.
OTP Read/Program Operation
To enter the OTP operation mode, it is by using the Set Feature command (EFh) and followed by the feature
address (90h) and then input the 01h to P1 and 00h to P2-P4 of sub-Feature Parameter data( please refer to
the sub-Feature Parameter table). After enter the OTP operation mode, the normal Read command (00h-30h)
or Page program( 80h-10h) command can be used to read the OTP area or program it. The address of OTP
is located on the 02h-1Fh of page address.
Besides the normal Read command, the Random Data Output command (05h-E0h) can be used for read
OTP data. However, the Cache Read command is not supported in the OTP area.
Besides the normal page program command, the Random Data Input command (85h) allows multi-data load
in non-sequential address. After data load is completed, a program confirm command (10h) is issued to start
the page program operation. The number of partial-page OTP program is 8 per each OTP page.
Figure 28. AC Waveforms for OTP Data Read
tCLR
CLE
CE#
WE#
tAR
ALE
tRC
RE#
tRR
tR
tWB
IO[7:0]
00h
1st Address 2nd Address
Cycle
Cycle
OTP
Page
00h
00h
Dout 0
30h
Dout 1
Dout n
R/B#
Busy
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Figure 29. AC Waveforms for OTP Data Read with Random Data Output
A
tCLR
CLE
CE#
WE#
tAR
ALE
tRC
RE#
tRHW
tRR
tWB
IO[7:0]
00h
1st Address
Cycle
2nd Address
Cycle
OTP
Page
00h
00h
tR
Dout M
30h
Dout M+1
05h
R/B#
Busy
CLE
A
CE#
WE#
tWHR
ALE
RE#
tREA
IO[7:0]
05h
1st Address
Cycle
2nd Address
Cycle
E0h
Dout N
Dout N+1
R/B#
Repeat if needed
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Figure 30. AC Waveforms for OTP Data Program
CLE
CE#
tADL
WE#
tWB
ALE
RE#
IO[7:0]
80h
1st Address 2nd Address 3rd Address 4th Address
Cycle
Cycle
Cycle
Cycle
5th Address
Cycle
Din
Din
70h
10h
Status
Output
tPROG
R/B#
Busy
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Figure 31. AC Waveforms for OTP Data Program with Random Data Input
A
CLE
CE#
tADL
tWC
WE#
ALE
RE#
IO[7:0]
80h
1st Address 2nd Address
Cycle
Cycle
OTP
Page
00h
00h
Din
Din
R/B#
A
CLE
CE#
tADL
WE#
tWB
ALE
RE#
IO[7:0]
85h
1st Address 2nd Address
Cycle
Cycle
Din
Din
70h
10h
Status
Output
tPROG
R/B#
Busy
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OTP Protection Operation
To prevent the further OTP data to be changed, the OTP protection mode operation is necessary. To enter the
OTP protection mode, it can be done by using the Set Feature command (EFh) and followed by the feature
address (90h) and then input the 03h to P1 and 00h to P2-P4 of sub-Feature Parameter data (please refer to
the sub-Feature Parameter table). And then the normal page program command (80h-10h) with the address
00h before the 10h command is required.
The OTP Protection mode is operated by the whole OTP area instead of individual OTP page. Once the OTP
protection mode is set, the OTP area cannot be programmed or unprotected again.
Figure 32. AC Waveforms for OTP Protection Operation
CLE
tCLS
tCLH
CE#
tCS
tWC
WE#
tALS
tALH
tWB
tALH
ALE
RE#
tDS
IO[7:0]
tDH
-
80h
1st Address
Cycle
Note
-
00h
00h
00h
10h
70h
Status
Output
Dummy data
input
2nd Address
Cycle
tPROG
R/B#
Note: This address cycle can be any value since the OTP protection protects the entire OTP area
instead of individual OTP page.
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6-15. Two-Plane Operations
The 2Gb/4Gb NAND device is divided into two planes for performance improvement. In the two-plane
operation, the NAND device may proceed the same type operation (for example: Program or Erase) on the
two planes concurrent or overlapped by the two-plane command sets. The different type operations cannot
be done in the two-plane operations; for example, it cannot be done to erase one plane and program the
other plane concurrently.
The plane address A18 must be different from each selected plane address. The page address A12-A17 of
individual plane must be the same for two-plane operation.
The Status Read command( 70h) may check the device status in the two-plane operation, if the result is
failed and then the Status Enhanced Read (78h) may check which plane is failed.
6-16. Two-plane Program (ONFI) and Two-plane Cache Program (ONFI)
The two-plane program command (80h-11h) may input data to cache buffer and wait for the final plane data
input with command (80h-10h) and then transfer all data to NAND array. As for the two-plane cache program
operation, it can be achieved by a two-plane program command (80h-11h) with a cache program command
(80h-15h), and the final address input with the confirm command (80h-10h). Please refer to the waveforms of
two-plane program and two-plane cache program for details. The random data input command (85h) can be
also used in the two-plane program operation for changing the column address, please refer to the waveform
of two-plane program with random data input.
Notes:
1. Page number should be the same for both planes.
2. Block address [29:18] can be different.
For examples:
If the user issues 80h-(block address 5h, page address 5h) -11h - 80h (block address - 18h, page address 5h) - 10h,
the programmed page is
- Plane 0: block address 18h, page address 5h
- Plane 1: block address 5h, page address 5h
(Note: Block address = A [29:18], page address = A [17:12])
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Figure 33-1. AC Waveforms for Two-plane Program (ONFI)
A
CLE
CE#
tADL
tWC
WE#
tWB
ALE
RE#
IO[7:0]
80h
1st Address 2nd Address 3rd Address
Cycle
Cycle
Cycle
4th Address
Cycle
5th Address
Cycle
Din
Din
11h
tDBSY
R/B#
Busy
A
CLE
CE#
tADL
WE#
tWB
ALE
RE#
IO[7:0]
80h
1st Address 2nd Address 3rd Address 4th Address
Cycle
Cycle
Cycle
Cycle
5th Address
Cycle
Din
Din
70h
10h
Status
Output
tPROG
R/B#
Busy
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Figure 33-2. AC Waveforms for Page Program Random Data Two-plane (ONFI)
A
CLE
CE#
tADL
tWC
tADL
tWC
WE#
tWB
ALE
RE#
IO[7:0]
80h
1st Address 2nd Address 3rd Address 4th Address 5th Address
Cycle
Cycle
Cycle
Cycle
Cycle
Din
Din
85h
1st Address 2nd Address
Cycle
Cycle
Din
Din
11h
tDBSY
R/B#
Reapeat if needed
Busy
A
CLE
CE#
tADL
tADL
tWC
WE#
tWB
ALE
RE#
IO[7:0]
80h
1st Address 2nd Address 3rd Address 4th Address
Cycle
Cycle
Cycle
Cycle
5th Address
Cycle
Din
85h
Din
1st Address 2nd Address
Cycle
Cycle
Din
Din
70h
10h
Status
Output
tPROG
R/B#
Reapeat if needed
P/N: PM2029
Busy
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Figure 34. AC Waveforms for Two-plane Cache Program (ONFI)
A
CLE
CE#
tADL
tWC
tADL
tWC
WE#
tWB
tWB
ALE
RE#
IO[7:0]
80h
1st Address
Cycle
2nd Address
Cycle
3rd Address
Cycle
4th Address
Cycle
5th Address
Cycle
Din
Din
80h
11h
1st Address
Cycle
2nd Address
Cycle
3rd Address
Cycle
4th Address
Cycle
5th Address
Cycle
tDBSY
Plane 1
Din
Din
15h
tCBSY
Plane 2
R/B#
Busy
Busy
Repeat if needed
A
CLE
CE#
tADL
tADL
tWC
WE#
tWB
tWB
ALE
RE#
IO[7:0]
80h
1st Address
Cycle
2nd Address
Cycle
3rd Address
Cycle
4th Address
Cycle
5th Address
Cycle
Plane 1
Din
Din
11h
80h
tDBSY
1st Address
Cycle
2nd Address
Cycle
3rd Address
Cycle
4th Address
Cycle
5th Address
Cycle
Plane 2
Din
Din
10h
70h
Status
Output
tPROG
R/B#
Busy
Busy
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6-17. Two-plane Block Erase (ONFI)
The two-plane erase command (60h-D1h) may erase the selected blocks in parallel from each plane, with
setting the 1st and 2nd block address by (60h-D1h) & (60h-D0h) command and then erase two selected
blocks from NAND array. Please refer to the waveforms of two-plane erase for details.
Figure 35. AC Waveforms for Two-plane Erase (ONFI)
CLE
tCLS
tCLS
tCLH
CE#
tCLH
tCS
tWC
WE#
tALH
tWC
tALS
tALH
tALS
ALE
tWB
RE#
tDS
IO[7:0]
R/B#
tDH
tDS
tDH
tDS
tDH
tDS
tWB
tDH
60h
tDS
D1h
3rd Address
Cycle
4th Address
Cycle
5th Address
Cycle
tDH
tDS
tDH
tDS
tDH
tDS
tDH
60h
3rd Address
Cycle
tDBSY
P/N: PM2029
70h
D0h
4th Address
Cycle
5th Address
Cycle
Stauts
Output
tERASE
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7. PARAMETERS
7-1. ABSOLUTE MAXIMUM RATINGS
Temperature under Bias
-50°C to +125°C
Storage temperature
-65°C to +150°C
All input voltages with respect to ground (Note 2)
-0.6V to 4.6V
VCC supply voltage with respect to ground (Note 2)
-0.6V to 4.6V
ESD protection
>2000V
Notes:
1. Minimum voltage may undershoot to -2V for the period of time less than 20ns.
2. The reliability of device may be impaired by exposing to extreme maximum rating conditions for long range of time.
3. Permanent damage may be caused by the stresses higher than the "Absolute Maximum Ratings" listed.
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Table 7. Operating Range
VCC
Tolerance
+3.3V
2.7 ~ 3.6V
Temperature
-40°C to +85°C
Table 8. DC Characteristics
Symbol
Parameter
Test Conditions
Min.
Typical
Max.
Unit Notes
VIL
Input low level
-0.3
0.2VCC
V
VIH
Input high level
0.8VCC
VCC + 0.3
V
0.2
V
VOL
VOH
ISB1
ISB2
ICC0
ICC1
IOL= 2.1mA, VCC=
VCC Min.
IOH= -400uA, VCC=
Output high voltage
VCC-0.2V
VCC Min.
CE# = VCC -0.2V,
VCC standby current (CMOS)
WP# = 0/VCC
CE# = VIH Min.,
VCC standby current (TTL)
WP# = 0/VCC
Power on current (Including
POR current)
VCC active current
tRC Min., CE# = VIL,
(Sequential Read)
IOUT= 0mA
Output low voltage
V
10
50
uA
1
mA
30
mA
20
30
mA
ICC2
VCC active current (Program)
20(Note)
30
mA
ICC3
VCC active current (Erase)
15
30
mA
ILI
Input leakage current
VIN= 0 to VCC Max.
+/- 10
uA
ILO
Output leakage current
VOUT= 0 to VCC
Max.
+/- 10
uA
ILO
Output current of R/B# pin
(R/B#)
VOL=0.4V
8
10
mA
Note: The typical program current (ICC2) for two-plane program operation is 25mA.
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Table 9. Capacitance
TA = +25°C, F = 1 MHz
Symbol
Parameter
CIN
COUT
Typ.
Max.
Units
Conditions
Input capacitance
10
pF
VIN = 0 V
Output capacitance
10
pF
VOUT = 0 V
Table 10. AC Testing Conditions
Testing Conditions
Value
Unit
0 to VCC
V
1TTL+CL(50)
pF
5
VCC/2
VCC/2
ns
V
V
Input pulse level
Output load capacitance
Input rise and fall time
Input timing measurement reference levels
Output timing measurement reference levels
Table 11. Program and Erase Characteristics
Symbol
tPROG
tCBSY (Program)
tRCBSY (Read)
tDBSY
tFEAT
tOBSY
tPBSY
NOP
tERASE (Block)
Parameter
Page programming time
Dummy busy time for cache program
Dummy busy time for cache read
The busy time for two-plane program/erase operation
The busy time for Set Feature/ Get Feature
The busy time for OTP program at OTP protection mode
The busy time for program/erase at protected blocks
Number of partial program cycles in same page
Block erase time
P/N: PM2029
Min. Typ. Max. Unit Note
300
3
2
0.5
1
600
us
600
us
25
us
1
us
1
us
30
us
3
us
4 cycles
3.5
ms
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Table 12. AC Characteristics
Symbol
Parameter
Min. Typical
Max.
Unit
Note
tCLS
tCLH
tCS
tCH
tWP
tALS
CLE setup time
CLE hold time
CE# setup time
CE# hold time
Write pulse width
ALE setup time
10
5
15
5
10
10
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
tALH
ALE hold time
5
ns
1
tDS
Data setup time
7
ns
1
tDH
Data hold time
5
ns
1
tWC
Write cycle time
20
ns
1
tWH
WE# high hold time
7
ns
1
tADL
70
ns
1
tWW
tRR
Last address latched to data loading time during
program operations
WP# transition to WE# high
Ready to RE# falling edge
100
20
ns
ns
1
1
tRP
Read pulse width
10
ns
1
tRC
Read cycle time
20
ns
1
tREA
RE# access time (serial data access)
16
ns
1
tCEA
CE# access time
25
ns
1
tRLOH
RE#-low to data hold time (EDO)
5
ns
tOH
Data output hold time
15
ns
1
tRHZ
RE#-high to output-high impedance
60
ns
1
tCHZ
CE#-high to output-high impedance
50
ns
1
tCOH
CE# high to output hold time
15
ns
tREH
RE# high hold time
7
ns
1
tIR
Output high impedance to RE# falling edge
0
ns
1
tRHW
RE# high to WE# low
60
ns
1
tWHR
WE# high to RE# low
60
ns
1
tR
The data transfering from array to buffer
25
us
1
tWB
WE# high to busy
100
ns
1
tCLR
CLE low to RE# low
10
ns
1
tAR
ALE low to RE# low
10
ns
1
tRST
Device reset time (Idle/ Read/ Program/ Erase)
us
1
5/10/500
Note 1. ONFI Mode 5 compliant
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8. OPERATION MODES: LOGIC AND COMMAND TABLES
Address input, command input and data input/output are managed by the CLE, ALE, CE#, WE#, RE# and
WP# signals, as shown in Table 13. Logic Table below.
Program, Erase, Read and Reset are four major operations modes controlled by command sets, please refer
to Table 14-1 and 14-2.
Table 13. Logic Table
Mode
CE#
RE#
Address Input (Read Mode)
L
Address Input (Write Mode)
WE#
CLE
ALE
WP#
H
L
H
X
L
H
L
H
H
Command Input (Read Mode)
L
H
H
L
X
Command Input (Write Mode)
L
H
H
L
H
Data Input
L
H
L
L
H
Data Output
L
H
L
L
X
During Read (Busy)
X
H
H
L
L
X
During Programming (Busy)
X
X
X
X
X
H
During Erasing (Busy)
X
X
X
X
X
H
Program/Erase Inhibit
X
X
X
X
X
L
Stand-by
H
X
X
X
X
0V/VCC
Notes:
1. H = VIH; L = VIL;
X = VIH or VIL
2. WP# should be biased to CMOS high or CMOS low for stand-by.
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Table 14-1. HEX Command Table
First Cycle
Second Cycle
00H
85H
05H
00H
31H
3FH
90H
ECH
EDH
EFH
EEH
FFH
80H
80H
60H
70H
78H
30H
E0H
31H
10H
15H
D0H
-
Read Mode
Random Data Input
Random Data Output
Cache Read Random
Cache Read Sequential
Cache Read End
ID Read
Parameter Page Read (ONFI)
Unique ID Read (ONFI)
Set Feature (ONFI)
Get Feature (ONFI)
Reset
Page Program
Cache Program
Block Erase
Status Read
Status Enhanced Read (ONFI)
Acceptable While Busy
V
V
V
Table 14-2. Two-plane Command Set
Two-plane Program (ONFI)
Two-plane Cache Program (ONFI)
Two-plane Block Erase (ONFI)
First Cycle
80H
80H
60H
Second Cycle
11H
11H
D1H
Third Cycle
80H
80H
60H
Fourth Cycle
10H
15H
D0H
Caution: None of the undefined command inputs can be accepted except for the command set in the above table.
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8-1. R/B#: Termination for The Ready/Busy# Pin (R/B#)
The R/B# is an open-drain output pin and a pull-up resistor is necessary to add on the R/B# pin. The R/B#
outputs the ready/busy status of read/program/ erase operation of the device. When the R/B# is at low, the
device is busy for read or program or erase operation. When the R/B# is at high, the read/program/erase
operation is finished.
Rp Value Guidence
The rise time of the R/B# signal depends on the combination of Rp and capacitive loading of the R/B# circuit.
It is approximately two times constants (Tc) between the 10% and 90% points on the R/B# waveform.
TC = R × C
Where R = Rp (Resistance of pull-up resistor), and C = CL (Total capacitive load)
The fall time of the R/B# signal majorly depends on the output impedance of the R/B# signal and the total
load capacitance.
Rp (Min.) =
Vcc (Max.) - VOL (Max.)
IOL+ΣIL
Notes:
1. Considering of the variation of device-by-device, the above data is for reference to decide the resistor value.
2. Rp maximum value depends on the maximum permissible limit of tr.
3. IL is the total sum of the input currents of all devices tied to the R/B pin.
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Figure 36. R/B# Pin Timing Information
@ Vcc = 3.3 V, Ta = 25°C, CL=100pF
Tc
800
800ns
600
400
400ns
200
2k
4k
6k
8k
Rp (ohm)
@ Vcc = 3.3 V, Ta = 25°C, CL=100pF
1.6
ibusy 1mA
0.83
0.4mA
0.55
0.41
2k
4k
6k
8k
Rp (ohm)
VCC
VCC
Device
Ready State
Rp
CL
R/B#
~90%
VCC
~90%
VOH
VOH
VOL
VOL
~10%
VSS
tf
P/N: PM2029
Busy State
~10%
tr
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8-2. Power On/Off Sequence
After the Chip reaches the power on level (Vth = Vcc min.), the internal power on reset sequence will be
triggered. During the internal power on reset period, no any external command is accepted. There are two
ways to identify the termination of the internal power on reset sequence. Please refer to Figure 48. Power
On/Off Sequence.
•
R/B# pin
•
Wait 1 ms
During the power on and power off sequence, it is recommended to keep the WP# = Low for internal data
protection.
Figure 37. Power On/Off Sequence
Vcc min.
Vcc
WP#
WE#
1 ms (Max.)
100 us
R/B#
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8-2-1. WP# Signal
WP# going Low can cause program and erase operations automatically reset.
The enabling & disabling of the both operations are as below:
Figure 38-1. Enable Programming of WP# Signal
WE#
IO[7:0]
WP#
Figure 38-2. Disable Programming of WP# Signal
80h
10h
tWW
WE#
IO[7:0]
80h
10h
tWW
WP#
Figure 38-3. Enable Erasing of WP# Signal
WE#
IO[7:0]
WP#
Figure 38-4. Disable Erasing of WP# Signal
60h
D0h
tWW
WE#
IO[7:0]
60h
D0h
tWW
WP#
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9. SOFTWARE ALGORITHM
9-1. Invalid Blocks (Bad Blocks)
The bad blocks are included in the device while it gets shipped. During the time of using the device, the
additional bad blocks might be increasing; therefore, it is recommended to check the bad block marks
and avoid using the bad blocks. Furthermore, please read out the bad block information before any erase
operation since it may be cleared by any erase operation.
Figure 39. Bad Blocks
Bad Block
Bad Block
While the device is shipped, the value of all data bytes of the good blocks are FFh. The 1st byte of the
1st and 2nd page in the spare area for bad block will be 00h. The erase operation at the bad blocks is not
recommended.
After the device is installed in the system, the bad block checking is recommended. The figure shows the brief
test flow by the system software managing the bad blocks while the bad blocks were found. When a block
gets damaged, it should not be used any more.
Due to the blocks are isolated from bit-line by the selected gate, the performance of good blocks will not be
impacted by bad ones.
Table 15. Valid Blocks
Valid (Good)
Block Number
Density
Min.
2Gb
4Gb
Typ.
Max.
Unit
2008
2048
Block
4016
4096
Block
P/N: PM2029
Remark
Block 0 is guaranteed to be good
(with ECC).
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9-2. Bad Block Test Flow
Although the initial bad blocks are marked by the flash vendor, they could be inadvertently erased and
destroyed by a user that does not pay attention to them. To prevent this from occurring, it is necessary to
always know where any bad blocks are located. Continually checking for bad block markers during normal
use would be very time consuming, so it is highly recommended to initially locate all bad blocks and build a
bad block table and reference it during normal NAND flash use. This will prevent having the initial bad block
markers erased by an unexpected program or erase operation. Failure to keep track of bad blocks can be
fatal for the application. For example, if boot code is programmed into a bad block, a boot up failure may
occur. The following section shows the recommended flow for creating a bad block table.
Figure 40. Bad Block Test Flow
Start
Block No. = 0
Yes
Read 00h
Check
Create (or Update)
Bad Block Table
(Note1)
No
Block No. = 4095
Block No. = Block No. + 1
(Note2)
No
Yes
End
Note 1. Read 00h check is at the 1st byte of 1st and 2nd pages of the block spare area
Note 2. The block No. = 2047 for 2Gb, 4095 for 4Gb
9-3. Failure Phenomena for Read/Program/Erase Operations
The device may fail during a Read, Program or Erase operation. The following possible failure modes should
be considered when implementing a highly reliable system:
Table 16. Failure Modes
Failure Mode
Detection and Countermeasure
Sequence
Erase Failure
Status Read after Erase
Block Replacement
Programming Failure
Status Read after Program
Block Replacement
Read Failure
Read Failure
P/N: PM2029
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9-4. Program
It is feasible to reprogram the data into another page (Page B) when an error occurred in Page A by loading
from an external buffer. Then create a bad block table or by using another appropriate scheme to prevent
further system accesses to Page A.
Figure 41. Failure Modes
Program error occurs in Page A
Buffer
Memory
Block
Another good block
Page B
Figure 42. Program Flow Chart
Start
Command 80h
Program
Command
Flow
Set Address
Write Data
Write 10h
Read Status Register
No
SR[6] = 1 ?
(or R/B# = 1 ?)
Yes
* Program Error
No
SR[0] = 0 ?
Yes
Program Completed
9-5. Erase
To prevent future accesses to this bad block, it is feasible to create a table within the system or by using
another appropriate scheme when an error occurs in an Erase operation.
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Figure 43. Erase Flow Chart
Start
Command 60h
Set Block Address
Command D0h
Read Status Register
No
SR[6] = 1 ?
(or R/B# = 1 ?)
Yes
No
SR[0] = 0 ?
* Erase Error
Yes
Erase Completed
*
The failed blocks will be identified and given errors
in status register bits for attempts on erasing them.
Figure 44. Read Flow Chart
Start
Command 00h
Set Address
Command 30h
Read Status Register
SR[6] = 1 ?
(or R/B# = 1 ?)
No
Yes
Read Data Out
ECC Generation
ECC handling
by the host controller
Verify ECC
No
Reclaim the Error
Yes
Page Read Completed
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10. PACKAGE INFORMATION
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Title: Package Outline for 63-VFBGA (9x11x1.0mm, Ball-pitch: 0.8mm, Ball-diameter: 0.45mm)
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11. REVISION HISTORY
Rev. No.
DescriptionsPageDate
0.01
Removed parameter feature address of 01h, 80h & 81h
P48
Revised the tCBSY/tRCBSY from 3us to 5usP63
NOV/08/2013
0.02
APR/02/2014
1. Changed title from "Advanced Information" to "Preliminary" P6
2. Supplement of the rule from low to high address for page program P27
3. Added notes of parameter page for the CRC formula.
P45
4. Adding more explanation on the two-plane operation.
P56
5. Supplement the recommendation for bad block management. P72
1.0
1. Removed "Preliminary" title
2. Specifications improvement for the folllowing parameters:
tPROG, tCBSY, tRCBSY, tERASE,
VOH, VOL, ICC0, ICC1, ICC2, ICC3, tRHW, tRHZ
1.1
1. Added a note for AC waveforms for Sequence of Cache Program P32
2. Added a note for AC waveform of OTP protection operation P55
3. Updating notes for the two-plane operation.
P56
1.2
1. Corrected tALS timing waveform as ALE high till WE# high
P27,55
2. Corrected waveform of OTP protection tWB timing
from WE# high to busy
P55
3. Revised R/B# timing of Power-on as 100us
P69
4. Revised the bad block mark from non-FFh to 00h,
also revised the page of bad block mark from 1st
or 2nd page to 1st and 2nd page
P71,72
P/N: PM2029
P6
MAY/22/2014
P6,7,44,62,63,64
JUN/23/2014
JAN/09/2015
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