MX25L512 DATASHEET

MX25L512
MX25L512
DATASHEET
The MX25L512 product family is not recommended for new designs. The MX25L512C
family is the recommended replacement. Please refer to MX25L512C datasheet for full
specifications and ordering information, or contact your local sales representative for
additional support.
P/N: PM1214
1
REV. 1.7, APR. 15, 2009
MX25L512
512K-BIT [x 1] CMOS SERIAL FLASH
The MX25L512 product family is not recommended for new designs. The MX25L512C
family is the recommended replacement. Please refer to MX25L512C datasheet for full
specifications and ordering information, or contact your local sales representative for
additional support.
FEATURES
GENERAL
• Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3
• 524,288 x 1 bit structure
• 16 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast access time: 85MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock (30pF + 1TTL Load)
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Fast erase time: 60ms(typ.) and 120ms(max.)/sector (4K-byte per sector) ; 1s(typ.) and 2s(max.)/chip(512Kb)
• Low Power Consumption
- Low active read current: 12mA(max.) at 85MHz, 8mA(max.) at 66MHz and 4mA(max.) at 33MHz
- Low active programming current: 15mA (max.)
- Low active erase current: 15mA (max.)
- Low standby current: 10uA (max.)
- Deep power-down mode 1uA (typical)
• Minimum 100,000 erase/program cycles
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Block Lock protection
- The BP0~BP1 status bit defines the size of the area to be software protected against Program and Erase instructions.
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
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REV. 1.7, APR. 15, 2009
MX25L512
• Status Register Feature
• Electronic Identification
- JEDEC 2-byte Device ID
- RES command, 1-byte Device ID
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI Input
- Serial Data Input
• SO Output
- Serial Data Output
• WP# pin
- Hardware write protection
• HOLD# pin
- pause the chip without diselecting the chip
• PACKAGE
- 8-pin SOP (150mil)
- 8-USON (2x3mm)
- All Pb-free devices are RoHS Compliant
GENERAL DESCRIPTION
MX25L512 is a CMOS 524,288 bit serial Flash memory, which is configured as 65,536 x 8 internally. MX25L512
features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus
signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the device is
enabled by CS# input.
MX25L512 provide sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and
erase command is executes on chip or sector (4K-bytes).
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 10uA DC current.
The MX25L512 utilize MXIC's proprietary memory cell, which reliably stores memory contents even after 100,000
program and erase cycles.
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PIN CONFIGURATIONS
PIN DESCRIPTION
8-PIN SOP (150mil)
SYMBOL
CS#
SI
SO
SCLK
HOLD#
CS#
SO
WP#
GND
1
2
3
4
8
7
6
5
VCC
HOLD#
SCLK
SI
WP#
VCC
GND
8-LAND USON (2x3mm)
CS#
SO
WP#
GND
P/N: PM1214
1
2
3
4
8
7
6
5
DESCRIPTION
Chip Select
Serial Data Input
Serial Data Output
Clock Input
Hold, to pause the device without
deselecting the device
Write Protection
+ 3.3V Power Supply
Ground
VCC
HOLD#
SCLK
SI
4
REV. 1.7, APR. 15, 2009
MX25L512
BLOCK DIAGRAM
X-Decoder
Address
Generator
Memory Array
Page Buffer
SI
Data
Register
Y-Decoder
SRAM
Buffer
CS#
Mode
Logic
Sense
Amplifier
State
Machine
Output
Buffer
HV
Generator
SO
SCLK
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Clock Generator
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REV. 1.7, APR. 15, 2009
MX25L512
DATA PROTECTION
MX25L512 is designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transition. During power up the device automatically resets the state machine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only
occurs after successful completion of specific command sequences. The device also incorporates several features
to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
• Software Protection Mode (SPM): by using BP0-BP1 bits to set the part of Flash protected from data change.
• Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP1 bits and SRWD bit from data
change.
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES).
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MX25L512
Table 1. Protected Area Sizes
BP1
0
0
1
1
Status bit
BP0
0
1
0
1
Protect level
512b
0 (none)
1 (All)
2 (All)
3 (All)
None
All
All
All
HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the
operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal
while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start
until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial
Clock being low), see Figure 1.
Figure 1. Hold Condition Operation
CS#
SCLK
HOLD#
Hold
Condition
(standard)
Hold
Condition
(non-standard)
The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care
during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of
the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low.
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MX25L512
Table 2. COMMAND DEFINITION
COMMAND WREN (write WRDI (write
RDID (read
(byte)
enable)
disable)
identification)
1st
2nd
3rd
4th
5th
Action
06 (hex)
04 (hex)
9F (hex)
sets the (WEL) resets the
write enable (WEL) write
latch bit
enable latch
bit
COMMAND SE(Sector
(byte)
Erase)
1st
20 (hex)
2nd
3rd
4th
5th
AD1
AD2
AD3
BE (2)
(Block
Erase)
52 or D8
(hex)
AD1
AD2
AD3
outputs
manufacturer
ID and 2-byte
device ID
CE (Chip
Erase)
60 or C7
(hex)
RDSR (read
WRSR
Fast Read
READ
status
(write status
(fast read
(read data)
register)
register)
data)
05 (hex)
01 (hex)
03 (hex)
0B (hex)
AD1
AD1
AD2
AD2
AD3
AD3
x
to read out to write new n bytes read
the status values to the out until CS#
register
status register goes high
RDP
REMS (Read
DP(Deep (Release RES (Read
PP(Page
Electronic
Power from Deep Electronic
Program)
Manufacturer
Down)
PowerID)
& Device ID)
down)
02 (hex)
AD1
AD2
AD3
B9 (hex)
AB (hex)
AB (hex)
90 (hex)
x
x
x
x
x
ADD(1)
Output the
manufacturer
ID and device
ID
Action
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.
(2) BE command may erase whole 512Kb chip.
(3) It is not recommended to adopt any other code which is not in the above command definition table.
P/N: PM1214
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REV. 1.7, APR. 15, 2009
MX25L512
Table 3. Memory Organization
Sector
15
:
3
2
1
0
Address Range
00F000h
00FFFFh
:
:
003000h
003FFFh
002000h
002FFFh
001000h
001FFFh
000000h
000FFFh
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK.
The difference of SPI mode 0 and mode 3 is shown as Figure 2.
5. For the following instructions: RDID, RDSR, READ, FAST_READ, RES and REMS the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the
following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP and DP the CS# must go high exactly at the
byte boundary; otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase.
Figure 2. SPI Modes Supported
CPOL
CPHA
shift in
(Serial mode 0)
0
0
SCLK
(Serial mode 3)
1
1
SCLK
SI
shift out
MSB
SO
MSB
Note:
CPOL indicates clock polarity of SPI master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which SPI mode is
supported.
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REV. 1.7, APR. 15, 2009
MX25L512
COMMAND DESCRIPTION
(1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE,
BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low-> sending WREN instruction code-> CS# goes high. (see
Figure 11)
(2) Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low-> sending WRDI instruction code-> CS# goes high. (see
Figure 12)
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
(3) Read Identification (RDID)
RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of
second-byte ID is as followings: 10(hex) for MX25L512.
The sequence of issuing RDID instruction is: CS# goes low→sending RDID instruction code→24-bits ID data out on
SO→to end RDID operation can use CS# to high at any time during data out. (see Figure. 13)
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
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REV. 1.7, APR. 15, 2009
MX25L512
(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→sending RDSR instruction code→Status Register
data out on SO (see Figure. 14)
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits, non-volatile bits, indicate the protected area(as defined in table
1) of the device to against the program/erase instruction without hardware protection mode being set. To write the
Block Protect (BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits
define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and
Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed)
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1
and WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is
no longer accepted for execution and the SRWD bit and Block Protect bits (BP1, BP0) are read only.
bit7
bit6
bit5
bit4
SRWD (status
register write
protect)
0
0
0
1=status
register write
disable
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
(note 1)
(note 1)
bit1
bit0
WEL
WIP
(write enable
(write in
latch)
progress bit)
1=write
1=write
enable
operation
0=not write 0=not in write
enable
operation
Note: 1. See the table "Protected Area Sizes".
2. The endurance cycles of protect bits are 100,000 cycles; however, the tW time out spec of protect bits is
relaxed as tW = N x 15ms (N is a multiple of 10,000 cycles, ex. N = 2 for 20,000 cycles) after 10,000 cycles
on those bits.
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(5) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP1, BP0) bits to define the protected area
of memory (as shown in table 1). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in
accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware
Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low-> sending WRSR instruction code-> Status Register
data on SI-> CS# goes high. (see Figure 15)
The WRSR instruction has no effect on b6, b5, b4, b1, b0 of the status register.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
Table 4. Protection Modes
Mode
Software protection
mode (SPM)
Hardware protection
mode (HPM)
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP1
bits can be changed
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
The SRWD, BP0-BP1 of
status register bits cannot be
changed
WP#=0, SRWD bit=1
The protected area
cannot
be program or erase.
Note:
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 1.
As the table above showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change
the values of SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected
mode (SPM).
- When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of
SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected mode (SPM)
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Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously
been set. It is rejected to write the Status Register and not be executed.
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected
mode (HPM). The data of the protected area is protected by software protected mode by BP1, BP0 and hardware protected mode by the WP# to against data modification.
Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered.
If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use
software protected mode via BP1, BP0.
(6) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-byte address on
SI→ data out on SO→ to end READ operation can use CS# to high at any time during data out. (see Figure. 16)
(7) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→
3-byte address on SI→ 1-dummy byte address on SI→data out on SO→ to end FAST_READ operation can use
CS# to high at any time during data out. (see Figure. 17)
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
(8) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address
of the sector (see table 3) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the
byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not
executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI →
CS# goes high. (see Figure 19)
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The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.
(9) Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address
of the block (see table 3) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the
byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not
executed.
The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code→ 3-byte address on SI →
CS# goes high. (see Figure 20)
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.
(10) Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the
sector (see table 3) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte
boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low→ sending CE instruction code→ CS# goes high. (see
Figure 20)
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE
timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip
is protected by BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when
BP1, BP0 all set to "0".
(11) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). If the eight least significant address bits (A7-A0) are not all 0, all transmitted data which goes beyond the end of the current page are
programmed from the start address if the same page (from the address whose 8 least significant address bits (A7A0) are all 0). The CS# must keep during the whole Page Program cycle. The CS# must go high exactly at the
byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not
executed. If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request
page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed
at the request address of the page without effect on other address of the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→
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at least 1-byte on data on SI→ CS# goes high. (see Figure 18)
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the
tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP1, BP0 bits, the Page Program (PP) instruction will not be executed.
(12) Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode
requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep
power-down mode. It's different from Standby mode.
The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high. (see Figure 22)
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out). When Powerdown, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby
mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction
code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay
of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.
(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip
Select (CS#) must remain High for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode,
the device waits to be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID
Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new deisng,
please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed,
only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/
write cycle in progress.
The sequence is shown as Figure 23,24.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute
instruction.
The RDP instruction is for releasing from Deep Power Down Mode.
P/N: PM1214
15
REV. 1.7, APR. 15, 2009
MX25L512
(14) Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the
JEDEC assigned manufacturer ID and the specific device ID.
The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes
address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and the Device ID are shifted out on the falling
edge of SCLK with most significant bit (MSB) first as shown in figure 25. The Device ID values are listed in Table of
ID Definitions on page 16. If the one-byte address is initially set to 01h, then the device ID will be read first and then
followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one
to the other. The instruction is completed by driving CS# high.
Table of ID Definitions:
RDID Command
manufacturer ID
C2
memory type
20
electronic ID
05
device ID
05
RES Command
REMS Command
P/N: PM1214
manufacturer ID
C2
16
memory density
10
REV. 1.7, APR. 15, 2009
MX25L512
POWER-ON STATE
The device is at below states when power-up:
- Standby mode ( please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the figure of "power-up timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.(generally around 0.1uF)
P/N: PM1214
17
REV. 1.7, APR. 15, 2009
MX25L512
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Ambient Operating Temperature
Industrial grade
-40°C to 85°C
Commercial grade
0°C to 70°C
Storage Temperature
-55°C to 125°C
Applied Input Voltage
-0.5V to 4.6V
Applied Output Voltage
-0.5V to 4.6V
VCC to Ground Potential
-0.5V to 4.6V
NOTICE:
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability.
2.Specifications contained within the following tables are subject to change.
3.During voltage transitions, all pins may overshoot to 4.6V or -0.5V for period up to 20ns.
4.All input and output pins may overshoot to VCC+0.5V while VCC+0.5V is smaller than or equal to 4.6V.
Figure 4. Maximum Positive Overshoot Waveform
Figure 3.Maximum Negative Overshoot Waveform
20ns
4.6V
0V
3.6V
-0.5V
20ns
CAPACITANCE TA = 25°C, f = 1.0 MHz
SYMBOL PARAMETER
CIN
COUT
P/N: PM1214
MIN.
TYP
MAX.
UNIT
Input Capacitance
6
pF
VIN = 0V
Output Capacitance
8
pF
VOUT = 0V
18
CONDITIONS
REV. 1.7, APR. 15, 2009
MX25L512
Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing referance level
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Output timing referance level
AC
Measurement
Level
0.5VCC
Note: Input pulse rise and fall time are <5ns
Figure 6. OUTPUT LOADING
DEVICE UNDER
TEST
2.7K ohm
CL
6.2K ohm
+3.3V
DIODES=IN3064
OR EQUIVALENT
CL=30pF Including jig capacitance
(CL=15pF Including jig capacitance for 70MHz)
P/N: PM1214
19
REV. 1.7, APR. 15, 2009
MX25L512
Table 5. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, Temperature = 0°C to
70°C for Commercial grade, VCC = 2.7V ~ 3.6V)
SYMBOL
PARAMETER
NOTES
ILI
Input Load Current
1
ILO
Output Leakage Current
1
ISB1
VCC Standby Current
1
ISB2
Deep Power-down
Current
ICC1
VCC Read
ICC2
ICC3
ICC4
ICC5
VIL
VIH
VOL
VOH
VCC Program Current
(PP)
VCC Write Status
Register (WRSR)
Current
VCC Sector Erase
Current (SE)
VCC Chip Erase
Current (CE)
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
MIN.
TYP.
1
1
1
1
1
-0.5
0.7VCC
VCC-0.2
MAX.
UNITS TEST CONDITIONS
VCC = VCC Max
±2
uA
VIN = VCC or GND
VCC = VCC Max
±2
uA
VIN = VCC or GND
VIN = VCC or GND
10
uA
CS#=VCC
VIN = VCC or GND
5
uA
CS#=VCC
f=85MHz
12
mA SCLK=0.1VCC/0.9VCC,
SO=Open
f=66MHz
8
mA SCLK=0.1VCC/0.9VCC,
SO=Open
f=33MHz
4
mA SCLK=0.1VCC/0.9VCC,
SO=Open
Program in Progress
15
mA
CS#=VCC
Program status register in
15
mA progress
CS#=VCC
Erase in Progress
15
mA
CS#=VCC
Erase in Progress
15
mA
CS#=VCC
0.3VCC
V
VCC+0.4
V
0.4
V
IOL = 1.6mA
V
IOH = -100uA
Notes :
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
P/N: PM1214
20
REV. 1.7, APR. 15, 2009
MX25L512
Table 6. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, Temperature = 0°C to
70°C for Commercial grade, VCC = 2.7V ~ 3.6V)
Symbol Alt.
fSCLK
fRSCLK
tCH(1)
tCL(1)
tCLCH(2)
tCHCL(2)
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
tSHQZ(2)
tCLQV
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
tHHQX(2)
tHLQZ(2)
tWHSL(4)
tSHWL(4)
tDP(2)
tRES1(2)
tRES2(2)
tW
tPP
tSE
tBE
tCE
fC
Parameter
Min. Typ.
Clock Frequency for the following instructions:
FAST_READ, PP, SE, BE, CE, DP, RES,RDP
WREN, WRDI, RDID, RDSR, WRSR
1KHz
fR Clock Frequency for READ instructions
tCLH Clock High Time
tCLL Clock Low Time
Clock Rise Time (3) (peak to peak)
Clock Fall Time (3) (peak to peak)
tCSS CS# Active Setup Time (relative to SCLK)
CS# Not Active Hold Time (relative to SCLK)
tDSU Data In Setup Time
tDH Data In Hold Time
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
tCSH CS# Deselect Time
tDIS Output Disable Time
@33MHz 30pF
tV Clock Low to Output Valid
@85MHz 15pF or
@66MHz 30pF
tHO Output Hold Time
HOLD# Setup Time (relative to SCLK)
HOLD# Hold Time (relative to SCLK)
HOLD Setup Time (relative to SCLK)
HOLD Hold Time (relative to SCLK)
tLZ HOLD to Output Low-Z
tHZ HOLD# to Output High-Z
Write Protect Setup Time
Write Protect Hold Time
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic Signature
Read
CS# High to Standby Mode with Electronic Signature Read
Write Status Register Cycle Time
Page Program Cycle Time
Sector Erase Cycle Time
Block Erase Cycle Time
Chip Erase Cycle Time
1KHz
5.5
5.5
0.1
0.1
5
5
2
5
5
5
100
0
5
5
5
5
Max.
85
(Condition:15pF)
66
(Condition:30pF)
33
5
1.4
60
1
1
MHz
MHz
6
8
MHz
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
ns
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
3
us
1.8
15
5
120
2
2
us
ms
ms
ms
s
s
6
6
20
100
Unit
Note:
1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. Test condition is shown as Figure 3.
P/N: PM1214
21
REV. 1.7, APR. 15, 2009
MX25L512
Table 7. Power-Up Timing
Symbol
tVSL(1)
Parameter
VCC(min) to CS# low
Min.
10
Max.
Unit
us
Note: 1. The parameter is characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
P/N: PM1214
22
REV. 1.7, APR. 15, 2009
MX25L512
Figure 7. Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
LSB
MSB
SI
High-Z
SO
Figure 8. Output Timing
CS#
tCH
SCLK
tCLQV
tCL
tCLQV
tSHQZ
tCLQX
LSB
SO
tQLQH
tQHQL
SI
P/N: PM1214
ADDR.LSB IN
23
REV. 1.7, APR. 15, 2009
MX25L512
Figure 9. Hold Timing
CS#
tHLCH
tCHHL
tHHCH
SCLK
tCHHH
tHLQZ
tHHQX
SO
HOLD#
* SI is "don't care" during HOLD operation.
Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1
WP#
tSHWL
tWHSL
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
01
SI
SO
P/N: PM1214
High-Z
24
REV. 1.7, APR. 15, 2009
MX25L512
Figure 11. Write Enable (WREN) Sequence (Command 06)
CS#
1
0
2
3
4
5
6
7
SCLK
Command
SI
06
High-Z
SO
Figure 12. Write Disable (WRDI) Sequence (Command 04)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
04
High-Z
SO
Figure 13. Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
Command
SI
9F
Manufacturer Identification
SO
High-Z
7
6
5
3
MSB
P/N: PM1214
2
1
Device Identification
0 15 14 13
3
2
1
0
MSB
25
REV. 1.7, APR. 15, 2009
MX25L512
Figure 14. Read Status Register (RDSR) Sequence (Command 05)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
05
SI
Status Register Out
High-Z
SO
7
6
5
4
3
2
1
Status Register Out
0
7
6
5
4
3
2
1
7
0
MSB
MSB
Figure 15. Write Status Register (WRSR) Sequence (Command 01)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
SI
Status
Register In
01
7
5
4
3
2
1
0
MSB
High-Z
SO
6
Figure 16. Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
command
SI
03
24-Bit Address
23 22 21
3
2
1
0
MSB
Data Out 1
High-Z
7
SO
6
5
4
3
2
Data Out 2
1
0
7
MSB
P/N: PM1214
26
REV. 1.7, APR. 15, 2009
MX25L512
Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
0B
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
3
2
1
0
7
MSB
MSB
P/N: PM1214
4
27
6
5
4
3
2
1
0
7
MSB
REV. 1.7, APR. 15, 2009
MX25L512
Figure 18. Page Program (PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
1
0
7
6
5
3
2
1
0
2079
2
2078
3
2077
23 22 21
02
SI
Data Byte 1
2076
24-Bit Address
2075
Command
4
1
0
MSB
MSB
2074
2073
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
CS#
SCLK
Data Byte 2
SI
7
6
MSB
P/N: PM1214
5
4
3
2
Data Byte 3
1
0
7
6
5
4
MSB
3
2
Data Byte 256
1
0
7
6
5
4
3
2
MSB
28
REV. 1.7, APR. 15, 2009
MX25L512
Figure 19. Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
24 Bit Address
Command
SI
7
20
6
2
1
0
9
29 30 31
MSB
Note: SE command is 20(hex).
Figure 20. Block Erase (BE) Sequence (Command 52 or D8)
CS#
0
1
2
3
4
5
6
7
8
SCLK
Command
SI
24 Bit Address
23 22
52 or D8
2
1
0
MSB
Note: BE command is 52 or D8(hex).
P/N: PM1214
29
REV. 1.7, APR. 15, 2009
MX25L512
Figure 21. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
60 or C7
Note: CE command is 60(hex) or C7(hex).
Figure 22. Deep Power-down (DP) Sequence (Command B9)
CS#
0
1
2
3
4
5
6
tDP
7
SCLK
Command
B9
SI
Stand-by Mode
Deep Power-down Mode
Figure 23. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
SI
AB
tRES2
3 Dummy Bytes
23 22 21
3
2
1
0
MSB
Electronic Signature Out
High-Z
7
SO
6
5
4
3
2
1
0
MSB
Deep Power-down Mode
P/N: PM1214
30
Stand-by Mode
REV. 1.7, APR. 15, 2009
MX25L512
Figure 24. Release from Deep Power-down (RDP) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
tRES1
7
SCLK
Command
SI
AB
High-Z
SO
Stand-by Mode
Deep Power-down Mode
Figure 25. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)
CS#
0
1
2
3
4
5
6
7
8
9 10
SCLK
Command
SI
2 Dummy Bytes
15 14 13
90
3
2
1
0
High-Z
SO
CS#
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
ADD (1)
SI
7
6
5
4
3
2
1
0
Manufacturer ID
SO
X
7
6
5
4
3
2
1
Device ID
0
7
6
5
4
3
2
MSB
MSB
1
0
7
MSB
Notes:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first
P/N: PM1214
31
REV. 1.7, APR. 15, 2009
MX25L512
Figure 26. Power-up Timing
VCC
VCC(max)
Chip Selection is Not Allowed
VCC(min)
tVSL
Device is fully
accessible
time
P/N: PM1214
32
REV. 1.7, APR. 15, 2009
MX25L512
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
VCC
VCC(min)
GND
tSHSL
tVR
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
LSB IN
MSB IN
SI
High Impedance
SO
Figure A. AC Timing at Device Power-Up
Symbol
tVR
Parameter
VCC Rise Time
Notes
1
Min.
0.5
Max.
500000
Unit
us/V
Notes :
1.Sampled, not 100% tested.
2.For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
"AC CHARACTERISTICS" table.
P/N: PM1214
33
REV. 1.7, APR. 15, 2009
MX25L512
ERASE AND PROGRAMMING PERFORMANCE
PARAMETER
Write Status Register Cycle Time
Sector erase Time
Block erase Time
Chip Erase Time
Page Program Time
Erase/Program Cycle
Min.
TYP. (1)
5
60
1
1
1.4
Max. (2)
15
120
2
2
5
100,000
UNIT
ms
ms
s
s
ms
cycles
Note:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern.
2. Under worst conditions of 85°C and 2.7V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command.
LATCH-UP CHARACTERISTICS
Input Voltage with respect to GND on ACC
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
Current
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
P/N: PM1214
34
MIN.
-1.0V
-1.0V
-1.0V
-100mA
MAX.
12.5V
2 VCCmax
VCC + 1.0V
+100mA
REV. 1.7, APR. 15, 2009
MX25L512
ORDERING INFORMATION
PART NO.
MX25L512MC-12G
MX25L512MI-12G
MX25L512ZUI-12G
P/N: PM1214
CLOCK
OPERATING
STANDBY CURRENT
Temperature PACKAGE
(MHz) CURRENT MAX. (mA)
MAX. (uA)
8-SOP
85
12
10
0~70°C
(150mil)
8-SOP
85
12
10
-40~85°C
(150mil)
8-USON
85
12
10
-40~85°C
(2x3mm)
35
Remark
Pb-free
Pb-free
Pb-free
REV. 1.7, APR. 15, 2009
MX25L512
PART NAME DESCRIPTION
MX 25
L
512
M
I
12 G
OPTION:
G: Pb-free
blank: normal
SPEED:
12: 85MHz
TEMPERATURE RANGE:
I: Industrial (-40 to 85)
C: Commercial (0 to 70)
PACKAGE:
M: 150mil 8-SOP
ZU: 2x3mm 8-USON
DENSITY & MODE:
512: 512Kb
TYPE:
L: 3V
DEVICE:
25: Serial Flash
P/N: PM1214
36
REV. 1.7, APR. 15, 2009
MX25L512
PACKAGE INFORMATION
P/N: PM1214
37
REV. 1.7, APR. 15, 2009
MX25L512
P/N: PM1214
38
REV. 1.7, APR. 15, 2009
MX25L512
REVISION HISTORY
Revision No.
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
P/N: PM1214
Description
Page
Date
1. Modified read current:6mA@85MHz/4mA@66MHz/2mA@33MHz P1,18,33
OCT/03/2005
→ 12mA@85MHz/8mA@66MHz/4mA@33MHz
2. Modified tSE:90ms(typ)/270ms(max)→60ms(typ)/120ms(max) ; P1,19,32
tBE:3s(max)→2s(max); tCE:3s(max)→2s(max)
3. Added description about Pb-free device is RoHS compliant
P1
4. Removed "Advanced Information" title
P1
5. Added C-grade part number
P33
1. Format change
All
JUN/08/2006
2. Supplemented the footnote for tW of protect/unprotect bits
P9
1. Added statement P38
NOV/06/2006
1. Defined min. clock frequency of fSCLK & fRSCLK as 1KHz
P20
NOV/30/2006
1. Removed 8-land SON package and order information
P2,3,34,35
MAR/24/2008
1. Removed wrong Block Protect bit: BP2
P5,11
AUG/12/2008
2. Removed non Pb-free EPN
P34,35
1. Modified Figure 13, 14, 16, 17, 23 (waveform)
P24,25,26,29 FEB/17/2009
2. Added 8-USON package
P3,34,37
3. Removed "Low Vcc write inhibit" function
P1,5,16,21,31
4. Changed tCH/tCL spec from 7/7(ns) to 5.5/5.5(ns)
P20
1. Announced "not recommended for new designs" wording
P1,2
APR/15/2009
39
REV. 1.7, APR. 15, 2009
MX25L512
Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which
the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft
and military application. Macronix and its suppliers will not be liable to you and/or any third party for any claims,
injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications.
Copyright© Macronix International Co. Ltd. 2005~2009. All Rights Reserved. Macronix, MXIC, MXIC Logo, MX
Logo, are trademarks or registered trademarks of Macronix International Co., Ltd.. The names and brands
of other companies are for identification purposes only and may be claimed as the property of the respective
companies.
MACRONIX INTERNATIONAL CO., LTD.
Macronix Offices : Japan
Macronix Asia Limited.
Macronix Offices : Taiwan
Headquarters, FAB2
Macronix, International Co., Ltd.
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Macronix Pte. Ltd.
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