MX25L2026C

MX25L2026C
2M-BIT [x 1] CMOS SERIAL FLASH
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 2,097,152 x 1 bit structure
• 64 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• 4 Equal Blocks with 64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast access time: 85MHz serial clock and 66MHz serial clock
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Fast erase time: 60ms(typ.)/sector (4K-byte per sector) ; 1s(typ.) and 2s(max.)/block (64K-byte per block)
• Low Power Consumption
- Low active read current: 12mA(max.) at 85MHz, 8mA(max.) at 66MHz and 4mA(max.) at 33MHz
- Low active programming current: 15mA (max.)
- Low active erase current: 15mA (max.)
- Low standby current: 10uA (max.) - Deep power-down mode 1uA (typical)
• Minimum 100,000 erase/program cycles
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Block Lock protection
- The BP0~BP4 status bits define the size of the area to be software protected against Program and Erase instructions
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first)
• Status Register Feature
• Electronic Identification
- JEDEC 2-byte Device ID
- RES command, 1-byte Device ID
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI Input
- Serial Data Input
• SO Output
- Serial Data Output
• WP# pin
- Hardware write protection
• HOLD# pin
- pause the chip without diselecting the chip
• PACKAGE
- 8-pin SOP (150mil)
- All Pb-free devices are RoHS Compliant
P/N: PM1476
1
REV. 1.1, JUL. 21, 2009
MX25L2026C
GENERAL DESCRIPTION
The MX25L2026C is a CMOS 2,097,152 bit serial Flash memory, which is configured as 262,144 x 8 internally. The
MX25L2026C feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus.
The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access
to the device is enabled by CS# input.
The MX25L2026C provide sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and
erase command is executes on chip or sector(4K-bytes) or block(64K-bytes).
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 10uA DC current.
The MX25L2026C utilize Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
PIN CONFIGURATIONS
PIN DESCRIPTION
SYMBOL
8-PIN SOP (150mil)
CS#
SO
WP#
GND
1
2
3
4
CS#
8
7
6
5
VCC
HOLD#
SCLK
SI
Serial Data Input
SO
Serial Data Output
SCLK
2
Chip Select
SI
Clock Input
VCC
Hold, to pause the device without
deselecting the device
+ 3.3V Power Supply
GND
Ground
WP#
Write Protection
HOLD#
P/N: PM1476
DESCRIPTION
REV. 1.1, JUL. 21, 2009
MX25L2026C
BLOCK DIAGRAM
X-Decoder
Address
Generator
Memory Array
Page Buffer
SI
Data
Register
Y-Decoder
SRAM
Buffer
CS#
Mode
Logic
State
Machine
WP#
SCLK
P/N: PM1476
Sense
Amplifier
Output
Buffer
HV
Generator
SO
Clock Generator
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REV. 1.1, JUL. 21, 2009
MX25L2026C
DATA PROTECTION
The MX25L2026C is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transition. During power up the device automatically resets the
state machine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system
noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
• Software Protection Mode (SPM): by using BP0-BP4 bits to set the part of Flash protected from data change.
• Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP4 bits and SRWD bit from data
change.
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES).
P/N: PM1476
4
REV. 1.1, JUL. 21, 2009
MX25L2026C
PROTECTED & UNPROTECTED
All of MX25L2026C protection bits, BP0~BP4, default is set to "1" (Protected) after Power-on and Erase/Program
process completion. MX25L2026C provides 2 kinds of unprotected methods, General Unprotection & Special
Unprotection. Table 1.
Name
BP0
BP1
BP2
BP3
BP4
Status
Register
bit 2
bit 3
bit 4
bit 5
bit 6
Address Range
03F000h
03E000h
03C000h
03A000h
000000h
Note: BP0~BP4 Default set to "1", Protected.
Size
03FFFFh
03EFFFh
03DFFFh
03BFFFh
039FFFh
4KB
4KB
8KB
8KB
232KB
Method
General Unprotection
Special Unprotection
General Unprotection
General Unprotection is required on the range from address 03A000h to address 03FFFFh area unprotection,
BP0~BP3.
Firstly, SRWD status bit needs to individual set to 0. Then, set the protected bit to 0, BP0 or BP1 or BP2 or BP3,
which range needs to be Programmed/Erased. Finally, do the Program/Erase process.
Please refer to Flowchart 1.
Special Unprotection
Special Unprotection is required on the range from address 000000h to address 039FFFh area unprotection, BP4.
Firstly, SRWD status bit needs to individual set to 0. Then, it needs to write 4-command KEY to uplock BP4,
command C3/A5/C3/A5 sequence. This KEY command cannot insert any other command in this 4-command KEY
period. After KEY command pressed, set the protected bit BP4=0. Finally, do the Program/Erase command.
Please refer to Flowchart 2.
P/N: PM1476
5
REV. 1.1, JUL. 21, 2009
MX25L2026C
HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the
operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal
while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start
until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial
Clock being low), see Figure 1.
Figure 1. Hold Condition Operation
CS#
SCLK
HOLD#
Hold
Condition
(standard)
Hold
Condition
(non-standard)
The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care
during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of
the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low.
P/N: PM1476
6
REV. 1.1, JUL. 21, 2009
MX25L2026C
Table 2. COMMAND DEFINITION COMMAND WREN (write WRDI (write
(byte)
Enable)
disable)
1st
2nd
3rd
4th
5th
Action
06 Hex
04 Hex
RDID (read
identification)
9F Hex
RDSR(read
WRSR
READ (read
status
(write status
data)
register)
register)
05 Hex
01 Hex
03 Hex
AD1
AD2
AD3
sets the
reset the
output the
to read out
(WEL) write (WEL) write manufacturer the status
enable latch enable latch ID and 2-byte register
bit
bit
device ID
COMMAND
(byte)
SE (Sector
Erase)
1st
2nd
3rd
4th
5th
Action
20 Hex
AD1
AD2
AD3
BE (Block
Erase)
CE (Chip
Erase)
PP (Page
Program)
52 or D8 Hex 60 or C7 Hex
AD1
AD2
AD3
REMS (Read
COMMAND Electronic
KEY1
(byte)
Manufacturer
& Device ID)
1st
90 Hex
C3 Hex
2nd
x
3rd
x
4th
ADD(1)
5th
Action
Output the
One of key
manufacturer command to
ID and device
set BP4
ID
02 Hex
AD1
AD2
AD3
to write new n bytes read
values to
out until CS#
the status
goes high
register
DP(Deep
Power
Down)
B9 Hex
RDP
(Release
from Deep
Powerdown)
AB Hex
Fast Read
(fast read
data)
0B Hex
AD1
AD2
AD3
x
RES (Read
Electronic
ID)
AB Hex
x
x
x
KEY2
A5 Hex
One of key
command to
set BP4
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.
(2) It is not recommended to adopt any other code which is not in the above command definition table.
P/N: PM1476
7
REV. 1.1, JUL. 21, 2009
MX25L2026C
Table 3. Memory Organization
"Block (64KB)"
"Total Sector"
"Sector (4KB)"
1
1
Address Range
Protect Status Bit
Start
End
63
03F000h
03FFFFh
BP0
62
03E000h
03EFFFh
BP1
61
03D000h
03DFFFh
60
03C000h
03CFFFh
59
03B000h
03BFFFh
58
03A000h
03AFFFh
10
48~57
030000h
039FFFh
2
16
32~47
020000h
02FFFFh
1
16
16~31
010000h
01FFFFh
0
16
0~15
000000h
00FFFFh
3
2
2
P/N: PM1476
8
BP2
BP3
BP4
REV. 1.1, JUL. 21, 2009
MX25L2026C
Flowchart 1-- General Unprotection
START
WREN Command
06h
WRSR Command
01h + Data
Set SRWD = 0
Write Register
Enable
WREN Command
06h
Yes
WRSR Command
01h + Data
Set BP0 or BP1 or
BP2 or BP3 = 0
Area Unprotected
WREN Command
06h
Program/Erase
Command
After Program/Erase Process
Completed, All of Protection
Bits (BP0~BP4) to be set to 1.
(Protected)
Command
Completed
Next Write
Command
No
END
P/N: PM1476
9
REV. 1.1, JUL. 21, 2009
MX25L2026C
Flowchart 2-- Special Unprotection
START
WREN Command
06h
WRSR Command
01h + Data
Set SRWD = 0
Write Status Register Enable
Key 1 Command
C3h
Key 2 Command
A5h
Key 1 Command
C3h
Yes
This sequential Command
(4 Commands)
cannot insert any other
Process or Command.
Key 2 Command
A5h
WREN Command
06h
WRSR Command
01h + Data
Set bit 6 (BP4) = 0
For Area Unprotected
or
Set bit[2:6] (BP0~BP4) = 0
For Unprotected Full Chip
WREN Command
06h
Program/Erase
Command
After Program/Erase Process
Completed, All of Protection
Bits (BP0~BP4) to be set to 1.
(Protected)
Command
Completed
Next Write
Command
No
END
P/N: PM1476
10
REV. 1.1, JUL. 21, 2009
MX25L2026C
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown as Figure 2.
5. For the following instructions: RDID, RDSR, READ, FAST_READ, RES and REMS the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the
following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP and DP the CS# must go high exactly at the
byte boundary; otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase.
Figure 2. Serial Modes Supported
CPOL
CPHA
shift in
(Serial mode 0) 0
0
SCLK
(Serial mode 3) 1
1
SCLK
SI
shift out
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
P/N: PM1476
11
REV. 1.1, JUL. 21, 2009
MX25L2026C
COMMAND DESCRIPTION
(1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE,
BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low-> sending WREN instruction code-> CS# goes high. (see
Figure 11)
(2) Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low-> sending WRDI instruction code-> CS# goes high. (see
Figure 12)
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
(3) Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC
Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID
of second-byte ID is as followings: 12(hex) for MX25L2026C.
The sequence of issuing RDID instruction is: CS# goes low-> sending RDID instruction code -> 24-bits ID data out
on SO -> to end RDID operation can use CS# to high at any time during data out. (see Figure. 13)
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
P/N: PM1476
12
REV. 1.1, JUL. 21, 2009
MX25L2026C
(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low-> sending RDSR instruction code-> Status Register
data out on SO (see Figure. 14)
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction.
BP0~BP4 bits. The Block Protect (BP0~BP4) bits, volatile bits, indicate the protected area(as defined in table 1) of
the device to against the program/erase instruction without hardware protection mode being set. To write the Block
Protect (BP0~BP4) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define
the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip
Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed)
SRWD bit. The Status Register Write Disable (SRWD) bit, volatile bit, is operated together with Write Protection (WP#)
pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin
signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP0~BP4) are read only.
bit 7
SRWD Status
Register Write Protect
bit 6
BP4
Protected
Area
bit 5
bit 4
bit 3
bit 2
BP3
BP2
BP1
BP0
1= status
register write
disable (note 2)
(note 1)
(note 1)
(note 1)
(note 1)
(note 1)
bit 1
bit 0
WEL (write WIP (write in
enable latch) progress bit)
1=write
1=write
enable operation
0=not write 0=not in write enable
operation
Note: 1. See the table "Protected Area Sizes". The (BP0~BP4) default values are "1" (protected).
2. The SRWD default value is "1".
P/N: PM1476
13
REV. 1.1, JUL. 21, 2009
MX25L2026C
(5) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP0~BP4) bits to define the protected area
of memory (as shown in table 1). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in
accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware
Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low-> sending WRSR instruction code-> Status Register
data on SI-> CS# goes high. (see Figure 15)
The WRSR instruction has no effect on b1, b0 of the status register.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
Table 4. Protection Modes
WP#
Signal
SRWD
bit
KEY
Mode
1
0
0
Software Protect
1
0
1
1
1
X
0
0
X
0
1
X
Write Protection of
Status Register
Memory Content
Protected Area
Unprotected Area
Protect against page
program, chip erase
and sector/erase block
NA
Status Register are
Protect against page Ready to accept Page
Writable (except BP4)
program, chip erase program, chip erase
All Status Register are
and sector/erase block and sector/erase block
Software Protect
Writable
Only Status Register Protect against page
Software Protect
SRWD is writable
program, chip erase
NA
other register can’t and sector/erase block
Hardware Protect
Status Register are
not Writable
Note:
1. It is defined by the values in the Protect Status bits (BP0~BP4) of the Status Register, as shown in Table 1.
As the table above, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM):
Software Protected Mode (SPM) (when WP# = high):
- When SRWD bit=0, and WP# is high, the WREN instruction may set the WEL bit and can change the values of
SRWD or BP0~BP4=0. The protected area, which is defined by BP0~BP4, is at Software Protected Mode (SPM).
- When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit, which can change the values
of SRWD. After setting SRWD bit=0, BP0~BP4 can be changed to 0.
- Please refer to Flowchart 1 and 2 for the process flow of changing BP0~BP4 as 0.
- KEY is a 4 command flow. In this flow period, any other process can not be accessed, otherwise KEY will not be
set to 1. KEY is a special protection for BP4 area.
Hardware Protected Mode (HPM) (when WP# = low):
- HPM protect the Status Register from being changed. If WP# = low, the Status Register can't be changed.
- Exit the HPM just by changing WP# to high.
P/N: PM1476
14
REV. 1.1, JUL. 21, 2009
MX25L2026C
(6) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low-> sending READ instruction code-> 3-byte address on
SI-> data out on SO-> to end READ operation can use CS# to high at any time during data out. (see Figure. 16)
(7) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be
at any location. The address is automatically increased to the next higher address after each byte data is shifted
out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0
when the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low-> sending FAST_READ instruction code->
3-byte address on SI-> 1-dummy byte address on SI->data out on SO-> to end FAST_READ operation can use
CS# to high at any time during data out. (see Figure. 17)
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
(8) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address
of the sector (see table 3) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the
byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not
executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low -> sending SE instruction code-> 3-byte address on SI ->
CS# goes high. (see Figure 19)
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP0~BP4 bits, the Sector Erase (SE) instruction will not be executed on the page.
If the proccess range covers or crosses address 000000h to address 039FFFh area, please use special unprotection method to unprotect the protected bits BP0~BP4. See the Flowchart 2.
P/N: PM1476
15
REV. 1.1, JUL. 21, 2009
MX25L2026C
(9) Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address
of the block (see table 3) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the
byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not
executed.
The sequence of issuing BE instruction is: CS# goes low -> sending BE instruction code-> 3-byte address on SI ->
CS# goes high. (see Figure 20)
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP0~BP4 bits, the Block Erase (BE) instruction will not be executed on the page.
If the proccess range covers or crosses address 000000h to address 039FFFh area, please use special unprotection method to unprotect the protected bits BP0~BP4. See the Flowchart 2.
(10) Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the
sector (see table 3) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte
boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low-> sending CE instruction code-> CS# goes high. (see Figure 20)
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE
timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip
is protected by BP0~BP4 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when
BP0~BP4 all set to "0".
Please use special unprotection method to set BP0~BP4 to 0, see the Flow chart 2.
(11) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). If the eight least significant address bits (A7-A0) are not all 0, all transmitted data which goes beyond the end of the current page are
programmed from the start address if the same page (from the address whose 8 least significant address bits (A7A0) are all 0). The CS# must keep during the whole Page Program cycle. The CS# must go high exactly at the
byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not
executed. If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request
page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed
at the request address of the page without effect on other address of the same page.
The sequence of issuing PP instruction is: CS# goes low-> sending PP instruction code-> 3-byte address on SI-> at
P/N: PM1476
16
REV. 1.1, JUL. 21, 2009
MX25L2026C
least 1-byte on data on SI-> CS# goes high. (see Figure 18)
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the
tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP1, BP0 bits, the Page Program (PP) instruction will not be executed.
If the proccess range covers or crosses address 000000h to address 039FFFh area, please use special unprotection method to unprotect the protected bits BP0~BP4. See the Flowchart 2.
(12) Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode
requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep
power-down mode. It's different from Standby mode.
The sequence of issuing DP instruction is: CS# goes low-> sending DP instruction code-> CS# goes high. (see Figure 22)
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out). When Powerdown, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby
mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction
code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay
of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.
(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip
Select (CS#) must remain High for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode,
the device waits to be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID
Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new deisng,
please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed,
only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/
write cycle in progress.
The sequence is shown as Figure 23,24.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute
instruction.
P/N: PM1476
17
REV. 1.1, JUL. 21, 2009
MX25L2026C
The RDP instruction is for releasing from Deep Power Down Mode.
(14) Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the
JEDEC assigned manufacturer ID and the specific device ID.
The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes
address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and the Device ID are shifted out on the falling
edge of SCLK with most significant bit (MSB) first as shown in figure 25. The Device ID values are listed in Table of
ID Definitions on page 16. If the one-byte address is initially set to 01h, then the device ID will be read first and then
followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one
to the other. The instruction is completed by driving CS# high.
Table of ID Definitions:
RDID Command
manufacturer ID
C2
memory type
20
electronic ID
03
device ID
03
RES Command
REMS Command
P/N: PM1476
manufacturer ID
C2
18
memory density
12
REV. 1.1, JUL. 21, 2009
MX25L2026C
POWER-ON STATE
The device is at below states when power-up:
- Standby mode ( please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the figure of "power-up timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.(generally around 0.1uF)
P/N: PM1476
19
REV. 1.1, JUL. 21, 2009
MX25L2026C
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Industrial grade
Ambient Operating Temperature
Storage Temperature
-40°C to 85°C
-55°C to 125°C
Applied Input Voltage
-0.5V to 4.6V
Applied Output Voltage
-0.5V to 4.6V
VCC to Ground Potential
-0.5V to 4.6V
NOTICE:
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is stress rating only and functional operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended period may affect reliability.
2.Specifications contained within the following tables are subject to change.
3.During voltage transitions, all pins may overshoot to 4.6V or -0.5V for period up to 20ns.
4.All input and output pins may overshoot to VCC+0.5V while VCC+0.5V is smaller than or equal to 4.6V.
Figure 4. Maximum Positive Overshoot Waveform
Figure 3.Maximum Negative Overshoot Waveform
20ns
4.6V
0V
3.6V
-0.5V
20ns
CAPACITANCE TA = 25°C, f = 1.0 MHz
SYMBOL PARAMETER
CIN
COUT
P/N: PM1476
MIN.
TYP
MAX.
UNIT
Input Capacitance
6
pF
VIN = 0V
Output Capacitance
8
pF
VOUT = 0V
20
CONDITIONS
REV. 1.1, JUL. 21, 2009
MX25L2026C
Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing referance level
0.8VCC
0.7VCC
0.2VCC
0.3VCC
Output timing referance level
AC
Measurement
Level
0.5VCC
Note: Input pulse rise and fall time are <5ns
Figure 6. OUTPUT LOADING
DEVICE UNDER
TEST
2.7K ohm
CL
6.2K ohm
+3.3V
DIODES=IN3064
OR EQUIVALENT
CL=30pF Including jig capacitance
(CL=15pF Including jig capacitance for 70MHz & 85MHz)
P/N: PM1476
21
REV. 1.1, JUL. 21, 2009
MX25L2026C
Table 5. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~
3.6V)
SYMBOL PARAMETER
NOTES
MIN.
TYP.
MAX.
UNITS TEST CONDITIONS
ILI
Input Load Current
1
±2
uA
ILO
Output Leakage Current
1
±2
uA
ISB1
VCC Standby Current
1
10
uA
ISB2
Deep Power-down
Current
10
uA
12
mA
f=85MHz & 70MHz, SCLK=0.1VCC/0.9VCC,
SO=Open
8
mA
f=66MHz,
SCLK=0.1VCC/0.9VCC,
SO=Open
4
mA
f=33MHz,
SCLK=0.1VCC/0.9VCC,
SO=Open
15
mA
15
mA
1
15
mA
1
15
mA
-0.5
0.3VCC
V
0.7VCC
VCC+0.4
V
0.4
V
IOL = 1.6mA
V
IOH = -100uA
ICC1
VCC Read
VIL
VCC Program Current
(PP)
VCC Write Status
Register (WRSR) Current
VCC Sector Erase Current (SE)
VCC Chip Erase Current
(CE)
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
VWI
Low VCC Write Inhibit
Voltage
ICC2
ICC3
ICC4
ICC5
1
1
VCC-0.2
3
2.1
2.3
2.5
VCC = VCC Max,
VIN = VCC or GND
VCC = VCC Max,
VIN = VCC or GND
VIN = VCC or GND,
CS# = VCC
VIN = VCC or GND,
CS# = VCC
Program in Progress,
CS# = VCC
Program status register in
progress, CS#=VCC
Erase in Progress,
CS#=VCC
Erase in Progress,
CS#=VCC
V
Notes :
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
3. Not 100% tested.
P/N: PM1476
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REV. 1.1, JUL. 21, 2009
MX25L2026C
Table 6. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V)
Symbol
Alt.
fSCLK
fC
fRSCLK
fR
tCH(1)
tCLH
tCL(1)
tCLL
tCLCH(2)
tCHCL(2)
tSLCH
tCSS
tCHSL
tDVCH tDSU
tCHDX
tDH
tCHSH
tSHCH
tSHSL
tCSH
tSHQZ(2) tDIS
tCLQV
tV
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
tHHQX(2)
tHLQZ(2)
tWHSL(4)
tSHWL(4)
tDP(2)
tHO
tRES1(2)
tRES2(2)
tW
tPP
tSE
tBE
tCE
tLZ
tHZ
Parameter
Clock Frequency for the following instructions:
FAST_READ, PP, SE, BE, CE, DP, RES,RDP,
WREN, WRDI, RDID, RDSR, WRSR
Clock Frequency for READ instructions
@33MHz Clock High Time
@85MHz
@33MHz Clock Low Time
@85MHz
Clock Rise Time (3) (peak to peak)
Clock Fall Time (3) (peak to peak)
CS# Active Setup Time (relative to SCLK)
CS# Not Active Hold Time (relative to SCLK)
Data In Setup Time
Data In Hold Time
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
CS# Deselect Time
Output Disable Time
30pF
Clock Low to Output Valid 15pF
Output Hold Time
HOLD# Setup Time (relative to SCLK)
HOLD# Hold Time (relative to SCLK)
HOLD Setup Time (relative to SCLK)
HOLD Hold Time (relative to SCLK)
HOLD to Output Low-Z
HOLD# to Output High-Z
Write Protect Setup Time
Write Protect Hold Time
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic
Signature Read
CS# High to Standby Mode with Electronic
Signature Read
Write Status Register Cycle Time Page Program Cycle Time
Sector Erase Cycle Time
Block Erase Cycle Time
Chip Erase Cycle Time
Min.
Typ.
Max.
Unit
D.C.
85
MHz
D.C.
15
5.5
15
5.5
0.1
0.1
5
5
2
5
5
5
100
33
3
MHz
ns
ns
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
3
us
1.8
us
15
5
ms
ms
ms
s
s
6
8
6
0
5
5
5
5
6
6
20
100
5
1.4
60
1
1.8
2
3.8
Note:
1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. Test condition is shown as Figure 3.
P/N: PM1476
23
REV. 1.1, JUL. 21, 2009
MX25L2026C
Table 7. Power-Up Timing
Symbol
Parameter
tVSL(1)
VCC(min) to CS# low
Min.
10
Max.
Unit
us
Note: 1. The parameter is characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
P/N: PM1476
24
REV. 1.1, JUL. 21, 2009
MX25L2026C
Figure 7. Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
LSB
MSB
SI
High-Z
SO
Figure 8. Output Timing
CS#
tCH
SCLK
tCLQV
tCL
tCLQV
tSHQZ
tCLQX
LSB
SO
tQLQH
tQHQL
SI
P/N: PM1476
ADDR.LSB IN
25
REV. 1.1, JUL. 21, 2009
MX25L2026C
Figure 9. Hold Timing
CS#
tHLCH
tCHHL
tHHCH
SCLK
tCHHH
tHLQZ
tHHQX
SO
HOLD#
* SI is "don't care" during HOLD operation.
Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1
WP#
tSHWL
tWHSL
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
01
SI
SO
P/N: PM1476
High-Z
26
REV. 1.1, JUL. 21, 2009
MX25L2026C
Figure 11. Write Enable (WREN) Sequence (Command 06)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
06
High-Z
SO
Figure 12. Write Disable (WRDI) Sequence (Command 04)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
04
High-Z
SO
Figure 13. Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
Command
SI
9F
Manufacturer Identification
SO
High-Z
7
6
5
3
MSB
P/N: PM1476
2
1
Device Identification
0 15 14 13
3
2
1
0
MSB
27
REV. 1.1, JUL. 21, 2009
MX25L2026C
Figure 14. Read Status Register (RDSR) Sequence (Command 05)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
05
SI
Status Register Out
High-Z
SO
7
6
5
4
3
2
Status Register Out
1
0
7
6
5
4
3
2
1
7
0
MSB
MSB
Figure 15. Write Status Register (WRSR) Sequence (Command 01)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
SI
Status
Register In
01
7
5
4
3
2
1
0
MSB
High-Z
SO
6
Figure 16. Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
command
SI
03
24-Bit Address
23 22 21
3
2
1
0
MSB
Data Out 1
High-Z
7
SO
6
5
4
3
2
Data Out 2
1
0
7
MSB
P/N: PM1476
28
REV. 1.1, JUL. 21, 2009
MX25L2026C
Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
0B
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
P/N: PM1476
4
3
2
1
0
7
MSB
MSB
29
6
5
4
3
2
1
0
7
MSB
REV. 1.1, JUL. 21, 2009
MX25L2026C
Figure 18. Page Program (PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
24-Bit Address
23 22 21
02
SI
3
2
Data Byte 1
1
0
7
6
5
4
3
2
0
1
MSB
MSB
2078
2079
2077
2076
2075
2074
2073
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
CS#
1
0
SCLK
Data Byte 2
SI
7
6
MSB
P/N: PM1476
5
4
3
2
Data Byte 3
1
0
7
6
5
4
MSB
3
2
Data Byte 256
1
0
7
6
5
4
3
2
MSB
30
REV. 1.1, JUL. 21, 2009
MX25L2026C
Figure 19. Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
24 Bit Address
Command
SI
7
20
6
2
1
0
MSB
Note: SE command is 20(hex).
Figure 20. Block Erase (BE) Sequence (Command 52 or D8)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24 Bit Address
23 22
52 or D8
2
1
0
MSB
Note: BE command is 52 or D8(hex).
P/N: PM1476
31
REV. 1.1, JUL. 21, 2009
MX25L2026C
Figure 21. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
60 or C7
Note: CE command is 60(hex) or C7(hex).
Figure 22. Deep Power-down (DP) Sequence (Command B9)
CS#
0
1
2
3
4
5
6
tDP
7
SCLK
Command
B9
SI
Deep Power-down Mode
Stand-by Mode
Figure 23. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
SI
AB
tRES2
3 Dummy Bytes
23 22 21
3
2
1
0
MSB
Electronic Signature Out
High-Z
7
SO
6
5
4
3
2
1
0
MSB
Deep Power-down Mode
P/N: PM1476
32
Stand-by Mode
REV. 1.1, JUL. 21, 2009
MX25L2026C
Figure 24. Release from Deep Power-down (RDP) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
tRES1
7
SCLK
Command
SI
AB
High-Z
SO
Deep Power-down Mode
Stand-by Mode
Figure 25. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)
CS#
0
1
2
3
4
5
6
7
8
9 10
SCLK
Command
SI
2 Dummy Bytes
15 14 13
90
3
2
1
0
High-Z
SO
CS#
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
ADD (1)
SI
7
6
5
4
3
2
1
0
Manufacturer ID
SO
X
7
6
5
4
3
2
1
Device ID
0
7
6
5
4
3
2
1
MSB
MSB
0
7
MSB
Notes:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first
P/N: PM1476
33
REV. 1.1, JUL. 21, 2009
MX25L2026C
Figure 26. Power-up Timing
VCC
VCC(max)
Chip Selection is Not Allowed
VCC(min)
tVSL
Device is fully
accessible
time
P/N: PM1476
34
REV. 1.1, JUL. 21, 2009
MX25L2026C
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
VCC(min)
VCC
GND
tSHSL
tVR
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
LSB IN
MSB IN
SI
High Impedance
SO
Figure A. AC Timing at Device Power-Up
Symbol Parameter
tVR
VCC Rise Time
Notes
Min.
Max.
Unit
1
0.5
500000
us/V
Notes :
1.Sampled, not 100% tested.
2.For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
"AC CHARACTERISTICS" table.
P/N: PM1476
35
REV. 1.1, JUL. 21, 2009
MX25L2026C
ERASE AND PROGRAMMING PERFORMANCE
PARAMETER
Write Status Register Cycle Time
Sector erase Time
Block erase Time
Chip Erase Time
Page Program Time
Erase/Program Cycle
Min.
TYP. (1)
5
60
1
1.8
1.4
Max. (2)
15
2
3.8
5
100,000
UNIT
ms
ms
s
s
ms
cycles
Note:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern.
2. Under worst conditions of 85°C and 2.7V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command.
LATCH-UP CHARACTERISTICS
Input Voltage with respect to GND on ACC
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
Current
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
P/N: PM1476
36
MIN.
-1.0V
-1.0V
-1.0V
-100mA
MAX.
12.5V
2 VCCmax
VCC + 1.0V
+100mA
REV. 1.1, JUL. 21, 2009
MX25L2026C
ORDERING INFORMATION
PART NO.
MX25L2026CMI-12G
P/N: PM1476
CLOCK
(MHz)
Operating
Current Max.
(mA)
Standby
Current Max.
(uA)
Temperature
PACKAGE
Remark
85
12
10
-40~85°C
8-SOP (150mil)
Pb-free
37
REV. 1.1, JUL. 21, 2009
MX25L2026C
PART NAME DESCRIPTION
MX 25
L 2026C
M
I
12 G
OPTION:
G: Pb-free
SPEED:
12: 85MHz
TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)
PACKAGE:
M: 150mil 8-SOP
DENSITY & MODE:
2026C: 2Mb
TYPE:
L: 3V
DEVICE:
25: Serial Flash
P/N: PM1476
38
REV. 1.1, JUL. 21, 2009
MX25L2026C
PACKAGE INFORMATION
P/N: PM1476
39
REV. 1.1, JUL. 21, 2009
MX25L2026C
REVISION HISTORY
Revision No.
1.0
1.1
P/N: PM1476
Description
1. Removed "Preliminary" title
2. Added "Low Vcc write inhibit" voltage (VWI) parameter
1. Removed the loading description of fSCLK
2. Removed Sector Erase maximum timing
40
Page
P1
P22
P23
P1,23,36
Date
MAY/14/2009
JUL/21/2009
REV. 1.1, JUL. 21, 2009
MX25L2026C
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