M52347SP/FP Sync Signal Processor REJ03F0190-0200 Rev.2.00 Sep 14, 2006 Description The M52347 automatically selects three types of synchronous signals containing separate sync (positive and negative polarities of 0.5 to 2.5 VP-P), composite sync (positive and negative polarities of 0.5 to 2.5 VP-P) and sync-on-video (sync negative polarity), and performs waveform shaping. The IC is optimum to synchronous signal processing for multi-scan type display monitor. Features • • • • • Low power consumption with supply voltage of 5 V Capable of obtaining output information on whether to input synchronous signal, and on polarity Output of clamp pulse Equipped with V TIME GATE SW that enables selecting whether or not VD portion pulse is output from pin 14/15. Equipped with CLAMP SW that enables switching the clamp pulse output position. Application Display monitor Recommended Operating Condition Supply voltage range: VCC = 4.5 to 5.5 V Rated supply voltage: VCC = 5 V Block Diagram CLAMP TIMING V.POL. H.POL. CLAMP+ OUT VCC HD− OUT HD+ OUT VD+ OUT V S/S OUT V S/S IN 20 19 18 17 16 15 14 13 12 11 EDGE SW CLAMP GEN V.TIME GATE V.SYNC SEP LOGIC LOGIC SYNC SEP 1 2 3 H.STATE V.STATE CLAMP SW Rev.2.00 Sep 14, 2006 page 1 of 16 4 5 GREEN IN GND H SHAPE H DET 6 7 COMP/H COMP/H IN DET V SHAPE 8 V IN V DET 9 10 V DET V TIME GATE SW M52347SP/FP Pin Arrangement M52347SP/FP H.STATE 1 20 CLAMP TIMING V.STATE 2 19 V.POL. CLAMP SW 3 18 H.POL. GREEN IN 4 17 CLAMP+ OUT GND 5 16 VCC COMP/H IN 6 15 COMP/H DET 7 14 HD− OUT HD+ OUT V IN 8 13 VD+ OUT V DET 9 12 V S/S OUT V TIME GATE SW 10 11 V S/S IN (Top view) Outline: PRDP0020BA-A (20P4B) [SP] PRSP0020DA-A (20P2N-A) [FP] Rev.2.00 Sep 14, 2006 page 2 of 16 M52347SP/FP Absolute Maximum Ratings (Ta = 25°C, unless otherwise noted) Item Symbol Supply voltage VCC Power dissipation Electrostatic discharge Pd Surge Operating temperature Storage temperature Topr Tstg Ratings 6.0 Unit V 1237.6 (SP), 827.8 (FP) ±200 mW V −20 to +85 −40 to +150 °C °C Electrical Characteristics (Ta = 25°C, VCC = 12 V, unless otherwise noted) Item Circuit current Pin 1 output Hi level Pin 1 output Low level TP In Limits Relay Condition Condition put 10 Pin Symbol Min. Typ. Max. Unit 4 6 8 16 3 ICC 40 53 66 mA 2 2 2 2 5 V 5 V 16 1 OH 1 OL Pin 2 output Hi level 2 OH Pin 2 output Low level 2 OL Pin 18 output Hi level 18 OH Pin 18 output Low level 18 OL Pin 19 output Hi level 19 OH Pin 19 output Low level 19 OL Pin 14 output Hi level 14 OH Pin 14 output Low level 14 OL 4.0 0 4.0 0 4.0 0 4.0 0 4.0 0 5.0 5.0 0.04 0.5 5.0 5.0 0.04 0.5 5.0 5.0 0.04 0.5 5.0 5.0 0.04 0.5 5.0 5.0 0.25 0.5 V V V V V V V V V V 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 0V 5V 2.5 V 5V 8 0V 5V 2.5 V 5V 6 0V 5V 2.5 V 5V 6 0V 5V 2.5 V 5V 6 0V 5V 2.5 V 5V 6 0V 5V 2.5 V 5V 6 0V 5V 2.5 V 5V 6 0V 5V 2.5 V 5V 6 0V 5V 2.5 V 5V 4 0V 5V 2.5 V 5V 4 Notes: 1. The true value table depends on Table 1 2. 0.2 VP-P of input signal is equivalent to NON SYNC. Rev.2.00 Sep 14, 2006 page 3 of 16 6 8 8 8 8 8 8 8 6 6 Input Condition 50 kHz 1 µs 1 V P-P 50 kHz 1 µs 1 V P-P 50 kHz 1 µs 0.2 V P-P 50 kHz 1 µs 1.0 V P-P 50 kHz 1 µs 1 V P-P 50 kHz 1 µs 1 V P-P 50 kHz 1 µs 1.0 V P-P 50 kHz 1 µs 0.2 V P-P 50 kHz 1 µs 1 V P-P 50 kHz 1 µs 1 V P-P 50 kHz 1 µs 1 V P-P 50 kHz 1 µs 1 V P-P 50 kHz 1 µs 1 V P-P 50 kHz 1 µs 1 V P-P 50 kHz 1 µs 1 V P-P 50 kHz 1 µs 1 V P-P 50 kHz 1 µs 0.6 V P-P 50 kHz 1 µs 2 V P-P 50 kHz 1 µs 0.6 V P-P 50 kHz 1 µs 2 V P-P Output pin A Output waveform 1 DC *1 1 DC *1, *2 2 DC *1 2 DC *1, *2 18 DC *1 18 DC *1 19 DC *1 19 DC *1 14 V Meas 14 V Meas Note M52347SP/FP Electrical Characteristics (cont.) Item Pin 15 output Hi level Pin 15 output Low level Pin 17 output Hi level Pin 17 output Low level TP In Limits Relay Condition Condition put Symbol Min. Typ. Max. Unit 4 6 8 16 3 10 Pin 15 OH 15 OL 17 OH 17 OL 4.0 0 4.0 0 Pin 13 output Hi level 13 OH 4.0 Pin 13 output Low level 13 OL 0 Pin 12 output Hi level 12 OH Pin 12 output Low level 12 OL 4.0 0 5.0 0.25 0.5 5.0 V V V V 1 1 1 1 1 1 1 1 2 2 2 2 1 1 1 1 0V 5V 2.5 V 5V 4 0V 5V 2.5 V 5V 4 0V 5V 2.5 V 5V 4 0V 5V 2.5 V 5V 4 6 6 6 6 50 kHz 1 µs 0.6 V P-P 50 kHz 1 µs 2 V P-P 50 kHz 1 µs 0.6 V P-P 50 kHz 1 µs 2 V P-P 50 kHz 1 µs 0.6 V P-P 50 kHz 1 µs 2 V P-P 15 17 1 0V 5V 2.5 V 5V 8 50 kHz 1 µs 2 V P-P 13 0.25 0.5 V 2 2 1 1 0V 5V 2.5 V 5V 8 50 kHz 1 µs 2 V P-P 13 0V 5V 2.5 V 5V 4 0V 5V 2.5 V 5V 4 0.25 0.5 Sync-Sep Sync SS-LV input signal Min. amplitude voltage 0.2 CLAMP SW V3H threshold voltage H 2.8 CLAMP SW V3L threshold voltage H variable 1.0 3.1 V 1 1 0.05 VP-P 1 3.4 VP-P V 1 2 1 1 2 2 1 1 6 6 V 2 4 50 kHz 1 µs 0.05 V P-P 14 15 17 2 2 1 0V 5V 2.5 V 5V 4 50 kHz 1 µs 0.2 V P-P 14 1 Vari- 5 V 3 2 17 1 2 1 Vari- 5 V 3 6 3.0 V 2 V Meas 0V 5V 2.5 V 5V 1 1 1 1 0 V Vari5 V able 6 8 10 DC voltage must be applied. 50 kHz 1 µs 2 V P-P 14, 17 DC voltage must be applied. 50 kHz 1 µs 2 V P-P 14, 17 50 kHz 1 µs 2 V P-P 50 kHz 1 µs 2 V P-P DC voltage must be applied. V Meas 12 1 able 2.5 12 2 6 1.6 50 kHz 1 µs 0.6 V P-P 50 kHz 1 µs 2 V P-P V Meas V Meas 2 able 1.3 50 kHz 1 µs 0.6 V P-P 50 kHz 1 µs 2 V P-P V Meas V Meas 1 V V Meas 17 2 5.0 Note V Meas 2 5.0 Output waveform 15 V 2.0 50 kHz 1 µs 0.6 V P-P 50 kHz 1 µs 2 V P-P Output pin 5.0 5.0 V10 5.0 0.25 0.5 Sync-Sep Sync SS-NV input signal Max. noise amplitude voltage V TIME GATE SW threshold voltage variable 5.0 Input Condition No pulse must be output. 50 kHz *3 *4 No pulse must be output in this portion. *5 15 *6 15 *7 14 15 Notes: 3. Must not operate when input amplitude is 0.05 VP-P or less. (Pseudo noise signal) 4. Must operate when the input amplitude is 0.2 VP-P or more. 5. Checking output pulse for output with a voltage of 5 VDC applied, decrease the DC voltage and then measure the voltage when the output pulse is not output. 6. Checking output pulse for output with a voltage of 0 VDC applied, increase the DC voltage and then measure the voltage when the output pulse is not output. 7. Checking output pulse for output with a voltage of 5 VDC applied, decrease the DC voltage and then measure the voltage when the output pulse becomes narrow. Rev.2.00 Sep 14, 2006 page 4 of 16 M52347SP/FP Electrical Characteristics (cont.) Item TP In Limits Relay Condition Condition put Symbol Min. Typ. Max. Unit 4 6 8 16 3 10 Pin HD+-delay time HD+-DA (A) HD+-delay time HD+-DB (B) 120 350 ns 1 1 2 1 0V 5V 5V 80 350 ns 1 1 2 1 0V 6 5V 5V HD+-delay time HD+-DC (C) 140 350 ns 1 1 2 4 4 6 1 2.5 V 5 V 4 6 HD+-delay time HD+-DD (D) 120 350 ns 1 1 2 1 2.5 V 5 V 4 6 HD−-delay time HD−-DA (A) 70 350 ns 1 1 2 1 0V 5V 5V HD−-delay time HD−-DB (B) 120 350 ns 1 1 2 1 0V 6 5V 5V HD−-delay time HD−-DC (C) 100 350 ns 1 1 2 4 4 6 1 2.5 V 5 V 4 6 HD−-delay time HD−-DD (D) 150 350 ns 1 1 2 1 2.5 V 5 V 4 6 CP+-delay time (A) CP+-DA 90 350 ns 1 1 2 1 0V 5V 4 6 CP+-delay time CP+-DB (B) 130 350 ns 1 1 2 1 2.5 V 5 V 4 6 CP+-delay time CP+-DC (C) 90 350 ns 1 1 2 1 5V 5V 4 6 CP+-PULSEWIDTH CP+-PW 250 400 550 VD+-delay time VD+-DA (A) VD+-delay time VD+-DB (B) 100 350 ns ns 1 2 1 2 2 1 1 1 70 350 ns 2 2 1 1 V Sync-Sep V11H threshold voltage H 3.0 3.5 4.0 V 2 1 2 1 V Sync-Sep V11L threshold voltage L 1.3 2.3 V 2 1 2 1 50 kHz 1 µs 0.6 V P-P 50 kHz 1 µs 2 V P-P 50 kHz 1 µs 0.6 V P-P 50 kHz 1 µs 2 V P-P 50 kHz 1 µs 0.6 V P-P 50 kHz 1 µs 2 V P-P 50 kHz 1 µs 0.6 V P-P 50 kHz 1 µs 2 V P-P Output pin 14 14 14 14 15 50 kHz 1 µs 0.6 V P-P 50 kHz 1 µs 2 V P-P 15 50 kHz 1 µs 0.6 V P-P 50 kHz 1 µs 2 V P-P 15 50 kHz 1 µs 0.6 V P-P 50 kHz 1 µs 2 V P-P 50 kHz 1 µs 0.6 V P-P 50 kHz 1 µs 2 V P-P 50 kHz 1 µs 0.6 V P-P 50 kHz 1 µs 2 V P-P 50 kHz 1 µs 0.6 V P-P 50 kHz 1 µs 2 V P-P 15 17 17 17 50 kHz 1 µs 2 V P-P 13 6 50 kHz 1 µs 2 V P-P 14 5V Input 4 (50%) Time Meas Output 14 (50%) Input 6 (50%) Time Meas Input 6 (50%) Time Meas Output 15 (50%) Input 4 (50%) Time Meas Input 4 (50%) Time Meas Output 15 (50%) Input 6 (50%) Time Meas Input 4 (50%) Time Meas Input 6 (50%) Time Meas Time Meas 17 Output 17 (50%) 13 Input 8 (50%) Time Meas Output 13 (50%) 11 0V Time Meas Output 17 (50%) 8 0V Input 4 (50%) Output 17 (50%) 0V 5V 2.5 V 5V 0V Time Meas Output 14 (50%) Output 17 (50%) 8 0V Input 6 (50%) Output 15 (50%) 0V 5V 2.5 V 5V 50 kHz 1 µs 2 V P-P Time Meas Output 15 (50%) 4 6 Note Output 14 (50%) 50 kHz 1 µs 0.6 V P-P 50 kHz 1 µs 2 V P-P 50 kHz 1 µs 0.6 V P-P 50 kHz 1 µs 2 V P-P Output waveform Input 6 (50%) Output 14 (50%) 0V 5V 2.5 V 5V 5V 1.8 Input Condition 6 11 DC voltage must be applied. 50 kHz 1 µs 2 V P-P DC voltage must be applied. Input 8 (50%) Time Meas Output 13 (50%) *8 15 14 *9 15 Notes: 8. Checking output pulse for output with a voltage of 0 VDC applied, increase the DC voltage and then measure the voltage when the output pulse is not output. 9. Checking output pulse for output with a voltage of 5 VDC applied, decrease the DC voltage and then measure the voltage when the output pulse is output. Rev.2.00 Sep 14, 2006 page 5 of 16 M52347SP/FP Test Circuit V11 100 p 11 V S/S IN V TIME 10 GATA SW 43 k V10 13 VD+ OUT TP13 V DET 9 V IN 8 + 10 µ 12 V S/S OUT 4.7 µ R8 2 1 COMP/H DET 7 TP15 15 HD− OUT COMP/H IN 6 4.7 µ R6 2 1 2 16 VCC GND 5 GREEN IN 4 1 R16 75 k + 5V 0.01 µ 47 µ TP17 + 14 HD+ OUT A TP14 0.0068 µ 17 CLAMP+ OUT 18 H.POL. TP18 3.3 µ CLAMP SW R4 2 1 3 V3 TP19 19 V.POL. V.STATE 2 TP2 CLAMP 20 TIMING H.STATE 1 TP1 4.3 k 220 p :5V Units Resistance: Ω Capacitance: F Rev.2.00 Sep 14, 2006 page 6 of 16 M52347SP/FP Pin Description Pin No. Name 1 H.STATE 2 V.STATE 3 CLAMP SW DC Voltage (V) Peripheral Circuit 0 VDC or 5 VDC Function Logic output pin for horizontal synchronous signal When pin 6 input signal is POSI, outputs "H"; when NON, outputs "L"; and when NEG, outputs "H". 20 kΩ 1 0 VDC or 5 VDC Same as pin 1 2.2 V when open Logic output pin for vertical synchronous signal When pin 8 input signal is POSI, outputs "H"; when NON, outputs "L"; and when NEG, outputs "H". 0.1 mA 28 kΩ 3.1 V 3 1.3 V This SW is available to change the generating position of clamp pulse for input signal. (See Table 2.) VTH L = 0 to 1 V VTH M = 1.6 to 2.8 V VTH H = 3.4 to 5 V 22 kΩ 20 kΩ 4 GREEN IN 20 kΩ 2.8 V when open 1 kΩ 1 kΩ 3.5 V 5 GND 6 COMP/H IN GREEN (SYNC ON VIDEO) input pin Input with negative sync. Comparison of pin 4 input signal and reference voltage within the IC performs synchronous separation. 4 2.5 V when open Grounding 1.5 kΩ 1.5 kΩ 20 kΩ 20 kΩ 6 10 kΩ 2.8 V 10 kΩ 2.5 V 0.3 mA 7 COMP/H DET 2.5 V when open (no signal) 10 kΩ 2.2 V 0.3 mA 12 kΩ 12 kΩ 75 kΩ 7 2.5 V 2.8 V 8 V IN 9 V DET 2.5 V when open 2.5 V when open (no signal) Rev.2.00 Sep 14, 2006 page 7 of 16 20 kΩ 20 kΩ Same as pin 6 Same as pin 7 2.2 V Composite sync/H sync input pin. Bias is approx. 2.5 V and impedance is 10 kΩ. The internal double threshold comparator is used for shaping waveform and detecting polarity. Optimum input amplitude is 0.6 VP-P at pin 6. Up to approx. 50% of duty, waveform shaping and polarity detection can be done. External capacitance is required as a filter pin for detecting polarity and detecting non-input. As the value is larger, the ripple is smaller and less malfunction occurs. However, this lowers the response speed of detection. V sync input pin Same as pin 6 Same as pin 7 M52347SP/FP Pin Description (cont.) Pin No. 10 Name DC Voltage (V) V.TIME GATE SW 3.2 V when open Peripheral Circuit Function 0.1 mA 2.5 V 10 30 kΩ 20 kΩ 11 V S/S IN 0.1 mA 4 kΩ 7.5 kΩ 11 1 kΩ 1 kΩ 5.5 kΩ 20 kΩ V S/S OUT 0.2 mA V S/S pulse output pin No problem occurs when current of approx. 6 mA flows to internal part of the IC. To improve the rising speed, connect a resistance between power supplies. 1 kΩ 12 + Same as pin 12 HD OUT + Same as pin 12 HD−OUT Same as pin 12 16 VCC 5V 17 CLAMP OUT Same as pin 12 18 H.POL. 0 VDC or 5 VDC Same as pin 1 19 V.POL. 0 VDC or 5 VDC Same as pin 1 20 CLAMP TIMING 13 VD OUT 14 15 + + VD pulse output pin Same as pin 12 + HD pulse output pin Same as pin 12 HD− pulse output pin Same as pin 12 Power supply + 3.0 V 4 kΩ 4 kΩ 3V 1.9 V 1.9 V 20 0.4 mA Rev.2.00 Sep 14, 2006 page 8 of 16 V S/S IN pin Inputs a signal of having externally integrated composite sync for V sync separation. 1.75 kΩ 0.2 mA 12 V TIME GATE SW pin Can select whether to output the pulse of VD portion from pin 14, 15 output pulse. The threshold voltage is approx. 2.5 V. VTH L = 0 to 2 V VTH H = 3 to 5 V 0.2 mA CLAMP pulse output pin Same as pin 12 Logic output pin for horizontal synchronous signal When pin 6 input signal is POSI, outputs "L"; when NON, outputs "L"; and when NEG, outputs "H". Logic output pin for vertical synchronous signal When pin 8 input signal is POSI, outputs "L"; when NON, outputs "L"; and when NEG, outputs "H". CLAMP TIMING pin The clamp pulse width is determined depending on the external resistance and capacitance. As the resistance value and capacitance value are larger, the clamp pulse width is wider. M52347SP/FP Table 1 Decorder Logic Output Pin 6 Input COMP/H Pin 8 Input V Output Pin POSI. NON POSI. NEG. 1 H H H 2 L H H 18 L L L 19 L L H NEG. NON POSI. NEG. NON POSI. NEG. H H H L L L L H H L H H H H H L L L L L H L L H NON. Table 2 Clamp Pulse Position Input Signal Table 3 Pin 17 Output Signal Pin 3 "M" Pin 4 Pin 6 Pin 3 "H" Ο Ο Χ Χ Ο Ο 4 trailing edge 6 leading edge 6 leading edge 4 trailing edge 4 trailing edge Χ Pin 3 "L" 4 trailing edge 6 trailing edge 6 trailing edge Output Priority Order Output Signal Input Signal Pin 4 Ο Ο Ο Ο Χ Χ Χ Χ Table 4 Pin 6 Χ Ο Χ Ο Χ Ο Χ Ο Pin 3 "H" "L" Pin 8 Χ Χ Ο Ο Χ Χ Ο Ο Pins 12, 14, 15, 17 4 6 4 6 Χ 6 Χ 6 Pin 3 "M" Pin 13 11 11 8 8 Χ 11 8 8 Pins 12, 14, 15, 17 4 4 4 4 Χ Χ Χ Χ Pin 13 11 11 8 8 Χ Χ 8 8 Allowable Input Amplitude Voltage Pin 4 input amplitude VV 0 to 2.1 (VP-P) fH = 10 Hz to 200 kHz VS 0.2 to 0.6 (VP-P) f = 10 Hz to 200 Hz V Pin 6 input amplitude VS 0.5 to 2.5 (VP-P) fH = 10 Hz to 200 kHz Pin 8 input amplitude VS 0.5 to 2.5 (VP-P) fV = 10 Hz to 200 Hz Rev.2.00 Sep 14, 2006 page 9 of 16 M52347SP/FP Application Method 1. Input Block 1) GREEN (SYNC ON VIDEO) IN (Pin 4) Input with sync negative polarity. Comparison of pin 4 input signal and the reference voltage of the inside of the IC performs the synchronous separation. When the input at pin 4 is less than or equal to the reference voltage (2.8 V) and the flowing current is more than or equal to the input sensitivity current (200 µA or more), the signal is separated. When only a synchronous signal is input into pin 4, the operatable amplitude and the duty are as shown in Figure 1. If the IC does not operate normally with the video signal input, change the value of external resistance R to make the current optimum. But, when capacity value is too big, output response becomes bad. 2) COMP/H IN, VIN (pins 6 and 8) The composite sync input is connected to pin 6. H and V of the separate sync input are connected to pins 6 and 8, respectively. For each of pins 6 and 8, the bias is 2.5 V and the impedance is 10 k. The internal double threshold converter is used for shaping waveform and for detecting polarity. Average DC voltage of input signal is 2.5 V. Each threshold voltage is set at a voltage 0.3 V away from this voltage. If the duty ratio at pin 6 is small as shown in Figure 2, the optimum value is approx. 0.3 VP-P. If the duty ratio is large, the optimum value is approx. 0.6 VP-P. Figure 3 shows the allowable input amplitude and the reference value of duty test. Only 5 V TTL input, decrease the amplitude by resistor splitting. In addition, Figure 4 shows an example for improving the capability of the allowable duty when the input amplitude is 0.7 VP-P or more. To use the IC out of the standard value, remove the filter from pins 7 and 9, observe the waveform and check for a match with the waveform shown in Figure 5. Operatable Maximum Duty (%) 30 R = 56 kΩ 25 20 15 R = 75 kΩ 10 3.3 µ f = 100 kHz 5 4 R 0 0 0.2 0.4 0.6 0.8 1.0 Input Amplitude (VP-P) Figure 1 ≈ 2.8 V ≈ 2.5 V ≈ 2.2 V Small POSI Duty Large NEG Duty Figure 2 Rev.2.00 Sep 14, 2006 page 10 of 16 M52347SP/FP Operatable Maximum Duty (%) 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 Input Amplitude (VP-P) Figure 3 18 kΩ pin 6 or pin 8 Input signal 100 Ω 3 kΩ This additional circuit (limiter) limits the amplitude to 0.6 VP-P. :5V Figure 4 ≈ 4.5 V NEG input ≈ 2.5 V ≈ 2.5 V POSI input ≈ 0.5 V Figure 5 Rev.2.00 Sep 14, 2006 page 11 of 16 M52347SP/FP 3) Polarity detection and non-input detection (pins 7 and 8) External capacitance is required as a filter pin to detect polarity and non-input. As the value is larger, the ripple is smaller and less malfunction occurs. However, the response speed for detection is lower. A sufficient external capacitance is 0.05 µF with input of 15 kHz and 10 µF with input of 60 kHz. However, check the frequency of the input signal in use and the filter pin waveform with the duty ratio conditions, and then check that the value is 3.1 V or more (2.8 V in capability) with positive polarity input and 1.9 V or less (2.2 V in capability) with negative polarity input. 4) V S/S IN (pin 11) Input a signal of having externally integrated composite sync for V sync separation. Composite sync input into pin 6 is output to pin 12. Output at 12 is externally integrated and is input into pin 11 for V sync separation. With the waveform at pin 11, check that the H element has been fully dropped. The threshold levels of sync separation, given hysteresis, are 3.5 V and 1.8 V. Input waveform at pin 6 Waveform at pin 11 VTH = 3.5 V VTH = 1.8 V Output waveform at pin 13 2. Clamp Pulse 1) Clamp pulse width CLAMP TIMING (Pin 20) The clamp pulse width is determined by the external resistance and the capacitance. As the resistance value and capacitance value are larger, the clamp pulse width is wider. The time constant is determined by the current flowing out of pin 20 and the capacitance value of the timing pin. The flow current at pin 20 is determined by the pin voltage and external resistance value. When the external resistance is 4.3 (that is 700 µA) and the external capacitance is 220 pF, the pulse width is 0.4 µs. 2) Clamp pulse position CLAMP SW (pin 3) When pin 3 is "M" or "L", fixing a higher-priority signal to the trailing edge results in occurrence of a clamp pulse. When pin 3 is "H", and only GREEN is input, clamp pulse occurs at the trailing edge. A clamp pulse also occurs at the leading edge when COMP/H only is input or when both COMP/H and GREEN are input. 8 Clamp Pulse Width (µs) 7 6 5 4 R = 10 kΩ 3 2 R = 4.3 kΩ 1 0 10 100 1000 10000 Clamp Timing Capacitance at Pin 20 (pF) Rev.2.00 Sep 14, 2006 page 12 of 16 M52347SP/FP 3. Sampling Pulse from VD Portion V TIME GATE SW (Pin 10) Whether to output the pulse of VD portion from pins 14 and 15 can be selected. When pin 10 is "H" or OPEN, pulse of the VD portion is output. When pin 10 is "L", the pulse of the VD portion is not output. Output at pin 14 when pin 10 is "H" or OPEN VD portion Output at pin 14 when pin 10 is "L" Output at pin 15 when pin 10 is "H" or OPEN VD portion Output at pin 15 when pin 10 is "L" 4. Output Stage 1) Logic output (pins 1, 2, 18 and 19) The output format is as shown in the diagram below. When the internal load resistance of the IC is 20 kΩ, a current of approx. 3 mA flows to the inside of the IC, no problem will occur. 20 kΩ 2) Pulse output (pins 12, 13, 14, 15 and 17) The output format is as shown in the diagram below. When the internal load resistance of the IC is 1 kΩ, a current of approx. 6 mA flows to the inside of the IC, no problem will occur. To improve the rising speed, connect a resistance between power supplies. Note that the low level of the output pulse goes up. 1 kΩ k Rev.2.00 Sep 14, 2006 page 13 of 16 M52347SP/FP Output Low Level (V) 0.8 0.6 0.4 0.2 0 0 2 6 4 8 10 ∞ External Resistance (kΩ) Typical Characteristics Thermal Derating (Maximum Rating) Power Dissipation Pd (mW) 1400 1237.6 1200 1000 SP 827.8 800 643.6 FP 600 430.5 400 200 0 −25 0 25 50 75 85 100 125 150 Ambient Temperature Ta (°C) Rev.2.00 Sep 14, 2006 page 14 of 16 M52347SP/FP Application Example (fH = 50 kHz, fV = 80 Hz) (POSI NON NEG) (POSI NON NEG) VCC 5 V 220 p 0.01 µ + 4.3 k CLAMP TIMING V.POL. 20 19 43 k 47 µ HD− HD+ OUT OUT H.POL. CLAMP+ OUT 18 17 16 15 V S/S OUT 13 12 V.TIME GATE EDGE SW CLAMP GEN 14 VD+ OUT 100 p V S/S IN 11 V.SYNC SEP LOGIC LOGIC SYNC SEP 1 H.STATE 2 V.STATE (POSI NON NEG) (POSI NON NEG) 3 4 5 6 4.7 µ CLAMP SW H M L H SHAPE 56 k 1.0 µ GND 0.01 µ Note: GREEN IN 9 V DET + 4.7 µ 0.01 µ 100 V DET 10 µ 4.7 µ 18 k 18 k V SHAPE 7 8 COMP/H + 4.7 µ DET 0.068 µ 3k :5V Units Resistance: Ω Capacitance: F H DET 10 V TIME GATE SW H L 100 3k COMP/H IN V IN External circuit for input of pins 6 and 8 When amplitude of up to 5 VP-P is entered into this circuit, can be kept constant at approx. 0.6 VP-P. When the duty of input signal at pins 6 and 8 changes, the most broad support range is obtained with amplitude of 0.6 VP-P. Rev.2.00 Sep 14, 2006 page 15 of 16 M52347SP/FP Package Dimensions RENESAS Code PRDP0020BA-A Previous Code 20P4B MASS[Typ.] 1.0g 11 1 10 c *1 E 20 e1 JEITA Package Code P-SDIP20-6.3x19-1.78 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. *2 A A2 D Reference Symbol L A1 e1 D E A A1 A2 bp b3 c *3 b 3 e bp SEATING PLANE e L JEITA Package Code P-SOP20-5.3x12.6-1.27 RENESAS Code PRSP0020DA-A Previous Code 20P2N-A Dimension in Millimeters Min Nom Max 7.32 7.62 7.92 18.8 19.0 19.2 6.15 6.3 6.45 4.5 0.51 3.3 0.38 0.48 0.58 0.9 1.0 1.3 0.22 0.27 0.34 0° 15° 1.528 1.778 2.028 3.0 MASS[Typ.] 0.3g 20 E *1 HE 11 F 1 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 10 c Index mark *2 A2 D A1 L A Reference Symbol *3 e bp y Detail F D E A2 A1 A bp c HE e y L Rev.2.00 Sep 14, 2006 page 16 of 16 Dimension in Millimeters Min Nom Max 12.5 12.6 12.7 5.2 5.3 5.4 1.8 0.1 0.2 0 2.1 0.35 0.4 0.5 0.18 0.2 0.25 0° 8° 7.5 7.8 8.1 1.12 1.27 1.42 0.1 0.4 0.6 0.8 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. 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