HD26LS32 Quadruple Differential Line Receivers With 3 State Outputs REJ03D0295–0200Z (Previous ADE-205-577 (Z)) Rev.2.00 Jul.16.2004 Description The HD26LS32 features quadruple line receivers designed to meet the specs of EIA standard RS-422A and RS-423. This device operates from a single 5 V power supply. The enable function is common to all four receivers and offers a choice of active high or active low input. Fail safe design ensures that if the inputs are open, the outputs will always be high. Features • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD26LS32P DILP-16 pin (JEITA) DP-16E, -16FV P — HD26LS32FPEL SOP-16 pin (JEITA) FP-16DAV FP EL (2,000 pcs/reel) Note: Please consults the sales office for the above package availability. Logic Diagram 1A 1B 2A 2B 3A 3B 4A 4B Enable G Enable G Rev.2.00, Jul.16.2004, page 1 of 14 1Y 2Y 3Y 4Y HD26LS32 Pin Arrangement 1B 1 16 VCC 1A 2 15 4B 1Y 3 14 4A Enable G 4 13 4Y 2Y 5 12 Enable G 2A 6 11 3Y 2B 7 10 3A GND 8 9 3B (Top view) Function Table Differential Input A–B Enable G Output Y G VID≥ V TH H X X L H H VTL < VID < VTH H X H X L X L X L H ? ? L L Z VID≤ V TL X H L X ? Z : : : : : High level Low level Immaterial Irrelevant High impedance Rev.2.00, Jul.16.2004, page 2 of 14 HD26LS32 Absolute Maximum Ratings Item Symbol Ratings Unit Supply Voltage In Phase Input Voltage VCC*1 VIC 7.0 ±25 V V Differential Input Voltage Enable Input Voltage VID*2 VIN ±25 7 V V Output Sink Current Continuous Total Dissipation Iout PT 50 1 mA W Operating Temperature Range Storage Temperature Range Topr Tstg 0 to +70 –65 to 150 °C °C Notes: 1. All voltage values except for differential input voltage are with respect to network ground terminal. 2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting onput. 3. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Symbol Min Typ Max Unit Supply Voltage In Phase Input Voltage VCC VIC 4.75 — 5.00 — 5.25 ±7.0 V V Output Current IOH IOL — — — — –440 8 µA mA Operating Temperature Topr 0 — 70 °C Rev.2.00, Jul.16.2004, page 3 of 14 HD26LS32 Electrical Characteristics (Ta = 0 to +70°C) Item Differential Input High Threshold Voltage Differential Input Low Min Typ*1 Max Unit Symbol VTH — — 0.2 V Conditions VIC = –7 to +7 V VOH = 2.7 V, IOH = –440 µA VTL — — –0.2 VOL = 0.4 V, IOL = 4 mA — 30 –0.2 — VOL = 0.45 V, IOL = 8 mA VTH – VTL — — Enable Input Voltage VIH VIL 2.0 — — — — 0.8 Enable Input Clamp Voltage Output Voltage VIK — — 1.5 VCC = 4.75 V, IIN = –18 mA VOH 2.7 — — VCC = 4.75 V VID = 1 V, IOH = –440 µA VOL — — — — 0.4 0.45 VIL (G) = 0.8 V VID = –1 V, IOL = 4 mA VID = –1 V, IOL = 8 mA Off State (High Impedance) Output Current IOZ — — — — 20 –20 µA VCC = 5.25 V VO = 2.4 V VO = 0.4 V Line Input Current II — — — — 2.3 2.8 mA VI = 15 V, Other Inputs –10 to +15 V VI = –15 V, Other Inputs –15 to +10 V Enable Input Current II (EN) IIH — — — — 100 20 µA VI = 5.5 V VI = 2.7 V IIL ri — 6 — 9.8 –0.36 mA — kΩ VI = 0.4 V VIC = –15 to +15 V (Other Inputs AC GND) IOS*3 –15 — –85 VCC = 5.25 V ICC — 52 70 Threshold Voltage Input Hysteresis*2 Input Resistance Short Circuit Output Current Supply Current mV V mA VCC = 5.25 V, VI = 0 V (All Outputs Disable) Notes: 1. All typical values are at VCC = 5 V, Ta = 25°C,VIC = 0. 2. Hysteresis is the differential between the positive going input threshold voltage and the negative going input threshold voltage. 3. Not more than one output should be shorted at a time. Switching Characteristics (VCC = 5 V, Ta = 25°C) TItem Propagation Delay Time Symbol tPLH, tPHL — 17 Max 25 Output Enable Time Output Disable Time tZH, tZL tHZ — — 15 15 22 22 tLZ — 20 30 Rev.2.00, Jul.16.2004, page 4 of 14 Min typ Unit ns Conditions CL = 15 pF CL = 5 pF HD26LS32 1. tPLH, tPHL Test circuit VCC Input Output 2 kΩ Pulse Generator CL *1 *2 5 kΩ *3 2V Waveforms 2.5 V Input A 0V 0V –2.5 V 2.5 V Input B 0V 0V –2.5 V t PLH t PHL VOH Output 1.3 V 1.3 V VOL Rev.2.00, Jul.16.2004, page 5 of 14 HD26LS32 2. tHZ, tZH Test circuit VCC Output 2 kΩ S1 2.5 V CL *2 Input 5 kΩ *3 Pulse Generator *1 *4 2V Waveforms 3V Enable G 1.3 V 1.3 V 0V 3V 1.3 V 1.3 V Enable G 0V S1 : Open t ZH Output Rev.2.00, Jul.16.2004, page 6 of 14 1.3 V S1 : Closed t HZ 0.5 V VOH 1.4 V 0V HD26LS32 3. tLZ, tZL Test circuit VCC Output 2 kΩ –2.5 V CL 5 kΩ Input Pulse Generator S2 2V Waveforms 3V Enable 1.3 V 1.3 V 0V 3V 1.3 V 1.3 V Enable G 0V S2 : Open t ZL S2 : Closed t LZ VOH Output 1.4 V 1.3 V 0.5 V Notes: 1. The pulse generator has the following characteristics : PRR = 1 MHz, 50 % duty cycle, tr≤ 15 ns, t f≤ 6 ns, Zout = 50 Ω. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074 (H) 4. To test G input,ground G input and apply an inverted input waveform. Rev.2.00, Jul.16.2004, page 7 of 14 VOL HD26LS32 HD26LS32 Line Receiver Applications The HD26LS32 is a line receiver that meets the EIA RS-422A and RS-423A conditions. It has a high in-phase input voltage range, both positive and negative, enabling highly reliable transmission to be performed even in noisy environments. Its main features are listed below. • • • • • • Operates on a single 5 V power supply. Three-state output On-chip fail-safe circuit ±7 V in-phase input voltage range ±200 mV input sensitivity Minimum 6 kΩ input resistance A block diagram is shown in figure 1. The enable function is common to all four drivers, and either active-high or active-low input can be selected. When exchange is carried out using a party line system, it is better to keep the receiver input bias current constituting the driver load small, as this allows more receivers to be connected. Consequently, whereas an input resistance of 4 kΩ or above is stipulated in RS-422A and RS-423A, the HD26LS32 has been designed to allow a greater margin, with a minimum resistance of 6 kΩ. Figure 2 shows the input current characteristics of the HD26LS32. The shaded areas in the graph indicate the input current allowable range stipulated in RS-422A and RS-423A. HD26LS32 output is LS-TTL compatible and has a three-state function, enabling the output to be placed in the highimpedance state, and so making the device suitable for bus line type applications. With an in-phase input voltage range of ±7 V and a ±200 mV input sensitivity, the HD26LS32 can withstand use in noisy environments. Also, since signals sent over a long-distance transmission line require a long transition time, it also takes a long time to cross the receiver’s input threshold level. Therefore, the input is provided with hysteresis of around 30 mV to prevent receiver output misoperation due to noise. An example of input hysteresis is shown in figure 3. The fail-safe function consists of resistances R connecting input A to VCC and input B to GND, as shown in figure 4. This circuit provides for the receiver input section to be pulled up or down by a high resistance that prevents it from becoming a driver load so that the output goes high in the event of a transmission line breakage or connector detachment. When the input pin is placed in the open state by the pull-up/pull-down resistance, the differential input voltage VID is as follows: VID: (VIA – VIB)≥ 0.2 V and the output is fixed high. However, if the receiver-side termination resistance remains connected despite a line breakage or connector detachment, the output will be undetermined (figure 5). Rev.2.00, Jul.16.2004, page 8 of 14 HD26LS32 1A 1Y 1B 2A 2Y 2B 3A 3Y 3B 4A 4Y 4B Enable G Enable G Figure 1 HD26LS32 Block Diagram 5 Input Current Iin (mA) 4 +3.25 mA Ta = 25°C 3 C VC 2 = C 1 5V 5.2 VC –10 V –3 V 0 = 0V +3 V +10 V –1 –2 –3 –3.25 mA –4 –5 –25 –20 –15 –10 –5 0 5 10 15 20 25 Input Voltage Vin (V) Figure 2 Input Voltage vs. Input Current Characteristics Output Voltage Vout (V) 5 VCC = 5 V, Ta = 25°C Input applied to pin A, with pin B as reference 4 3 VIC = –7 V 2 VIC = 0 V VIC = +7 V 1 0 –100 –80 –60 –40 –20 0 20 40 60 80 100 Differential Input Voltage VID (mV) Figure 3 Differential Input Voltage vs. Output Voltage Characteristics VCC A B R Y R Figure 4 Fail-Safe Function Rev.2.00, Jul.16.2004, page 9 of 14 HD26LS32 This is because, since the termination resistance is normally matched to the transmission line characteristic impedance, the value falls to several tens of hundreds of ohms, and the differential input pins are shorted by this termination resistance. That is, the differential input voltage VID comes within the range VID: –0.2 V < VIA – VIB < 0.2 V and the output becomes undetermined. To prevent this, resistance R1 is inserted in series with the transmission line as shown in figure 6, minimizing the effect of the termination resistance. Resistance R2 is added to increase the current flowing between the termination resistance and R1, enabling the value of R1 to be kept small. Inserting resistances R1 and R2 in this way provides for the differential input voltage VID to become 200 mV or higher, but the following points must be noted. • Smallest possible R1 value If this value is large, the receiver input sensitivity will fall. • Largest possible R2 value If this value is small, the load on the driver will be large. Figure 7 shows experimental differential input voltages for variations in R1 and R2. Undetermined RT "H" RT Figure 5 Examples of Transmission Line Disconnection R1 Driver VCC R2 Receiver RT R1 R2 Ω 0k 50 =3 Ω 0k 300 kΩ R2 = ∞ VCC 2 0.5 10 R Differential Input Voltage VID (V) 0.6 kΩ Figure 6 Method of Enhancing Fail-Safe Function VCC = 5 V Ta = 25°C R1 0.4 100 Ω 0.3 VID R1 0.2 0.1 0 5 10 15 R1 (kΩ) Figure 7 R1, R2 vs. Differential Input Voltage Rev.2.00, Jul.16.2004, page 10 of 14 R2 R2 HD26LS32 RS-442A Interface Standard Applications Figure 9 shows sample operation waveforms at various points with 1200 m and 12 m cable lengths. 1. Unidirectional Transmission (1 : 1 Configuration) Driver B Data A input D F Data output RT C Receiver E Figure 8 1 : 1 Unidirectional Transmission Line : 1200 m Frequency : 100 kHz Duty : 50% RT : 100 Ω A D GND GND B GND H : 5 µs/div V : 2 V/div E GND C F GND GND Line : 12 m Frequency : 10 MHz Duty : 50% RT : 100 Ω A D GND GND E GND B GND C F GND GND Figure 9 Sample Transmission Waveforms Rev.2.00, Jul.16.2004, page 11 of 14 H : 50 ns/div V : 2 V/div HD26LS32 2. Unidirectional Transmission (1 : n Configuration) Driver Data input RT Data output RT Enable Data output Receiver Data output Data output Figure 10 1 : n Unidirectional Transmission With this connection method, n receivers are connected for one driver. In the RS-422A standard, ten receivers can be connected simultaneously for one driver. Conversely, it is also possible to connect one receiver for n drivers. 3. Bidirectional Transmission Driver Data I/O Receiver RT Data I/O RT Enable Enable Receiver Driver Figure 11 Bidirectional Transmission When bidirectional data exchange is performed using a combination of the HD26LS31 and HD26LS32, since either high or low output control is possible, using complementary enable inputs for the driver and receiver makes it easy to configure the kind of combination illustrated in figure 11 . Extending this combination makes it possible to exchange n-bit data simultaneously, and handle a party line system. Rev.2.00, Jul.16.2004, page 12 of 14 HD26LS32 Package Dimensions As of January, 2003 Unit: mm 19.2 20.32 Max 9 6.3 7.4 Max 16 1 8 0.48 ± 0.1 2.54 ± 0.25 2.54 Min 5.06 Max 0.51 Min 1.3 0.89 7.62 + 0.1 0.25 – 0.05 0˚ – 15˚ Package Code JEDEC JEITA Mass (reference value) DP-16E Conforms Conforms 1.05 g Unit: mm 19.2 20.32 Max 9 6.3 7.4 Max 16 1 8 *0.48 ± 0.08 2.54 Min 5.06 Max 2.54 ± 0.25 1.3 0.51 Min 0.89 7.62 *0.25 ± 0.06 0˚ – 15˚ *NI/Pd/AU Plating Rev.2.00, Jul.16.2004, page 13 of 14 Package Code JEDEC JEITA Mass (reference value) DP-16FV Conforms Conforms 1.05 g HD26LS32 As of January, 2003 Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.40 ± 0.06 0.10 ± 0.10 0.80 Max *0.20 ± 0.05 2.20 Max 5.5 16 0.20 7.80 +– 0.30 1.15 0 ˚ – 8˚ 0.70 ± 0.20 0.15 0.12 M *Ni/Pd/Au plating Rev.2.00, Jul.16.2004, page 14 of 14 Package Code JEDEC JEITA Mass (reference value) FP-16DAV — Conforms 0.24 g Sales Strategic Planning Div. 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