HD151011 Dual BCD Programmable Counter with Synchronous Preset Enable REJ03D0298–0200Z (Previous ADE-205-100 (Z)) Rev.2.00 Jul.16.2004 Description The HD151011 has BCD decimal two digits down counter and D-type Flip Flop. The counter can set up to max 99 counts and synchronous preset (SPE) input can preset the data. When the count value is 0, the next clock pulse presets the data to invert the output. D-type Flip Flop takes the counter output as clock pulse, whose data is transferred to output at the rise edge. It is applied to generate AC signal for STN type liquid crystal and general-use divider. Features • High speed operation tpd (CLK or CLK to Q) = 35 ns (typ) • High output current Fanout of 10 LS TTL Loads • Wide operating voltage VCC = 2 to 6 V • Low supply current (Ta = 25°C) ICC (Static) = 4 µA (max) • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD151011FPEL SOP-20 pin (JEITA) FP-20DAV FP EL (2,000 pcs/reel) HD151011TELL TSSOP-20 pin T ELL (2,000 pcs/reel) TTP-20DAV Note: Please consults the sales office for the above package availability. Rev.2.00, Jul.16.2004, page 1 of 13 HD151011 Function Table Control Inputs CLR SPE H H X Mode Generally count Operation Description Down count at the rise edge of clock (CLK) Down count at the fall edge of clock (CLK) X X L X Synchronous preset — — — H — Jn data is preset at the rise of clock (CLK), the fall of clock (CLK) Clock inputs (CLK, CLK) is CMOS level — L — H — — L — — Initialize of Q output Clock inputs (CLK, CLK) is TTL level Initialize of Q = “L” H L — — Initialize of Q output Initialize of Q = “H” Note: H L X — : : : : PR C/T T H 1. 2. 3. 4. Synchronous preset (SPE) input can set max 99 down counts. When the count value is 0, the next clock pulse presets the data to invert the output. CLR and PR inputs initialize output state. Clock inputs (CLK, CLK) is selectable CMOS level (VCC = 2.0 to 6.0 V) and TTL level (VCC = 4.5 to 5.5V) (Jn, C/T, PR, CLR and SPE inputs are CMOS level) Don't set data exceeding 99 to Jn. (J0 : LSB, J7 : MSB) High level Low level Immaterial Irrespective of condition Pin Arrangement CO 1 20 VCC J0 2 19 (Test 1) * J1 3 18 (Test 2) * J2 4 17 C / T J3 5 16 CLK J4 6 15 CLK J5 7 14 Q J6 8 13 PR J7 9 12 SPE GND 10 11 CLR (Top view) Rev.2.00, Jul.16.2004, page 2 of 13 HD151011 Pin Description Pin Name Input pins Output pins Pin Description J0 to J7 C/T Count data input for option Level change input for CLK, CLK (CMOS level or TTL level) CLK, CLK Clock inputs SPE Preset input for Jn data PR CLR Preset input for D-type Flip Flop (Initialize “L” at Q output) Clear input for D-type Flip Flop (Initialize “H” at Q output) CO Q Output for BCD decimal counter Output for D-type Flip Flop CLK : Rise edge trigger CLK : Fall edge trigger Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage Input/output voltage VCC VIN/VOUT –0.5 to 7.0 –0.5 to VCC +0.5 V V VCC, GND current Output current/pin ICC, IGND IOUT ±50 ±25 mA mA Power dissipation Storage temperature PT Tstg 757 –65 to 150 mW °C Input diode current IIK ±20 mA Output diode current IOK ±20 mA Notes: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 2. All voltage values except for differential input voltage are with respect to network ground terminal. Recommended Operating Conditions Item Symbol Supply voltage Input/output voltage Operating temperature Input rise/fall time*1 VCC = 2.5 V Typ Max Unit 2 0 — — 6 VCC V V Topr tr, tf –40 0 — — +85 1000 °C ns 0 0 — — 500 400 VCC = 4.5 V VCC = 5.5 V Note: Min VCC VIN/OUT 1. This item guarantees maximum limit when one input switches. Logic Diagram C/T J0 J1 J1 J2 J2 J3 J3 J4 J4 J5 J5 J6 J6 J7 J7 CLK CLK BCD decimal counter J0 CLK CO PR PR CO SPE D Q CK Q Q CLR SPE CLR Rev.2.00, Jul.16.2004, page 3 of 13 HD151011 Electrical Characteristics SymItem High level input bol VIH voltage Low level input voltage High level output VIL VOH voltage Low level output voltage VOL Ta = 25°C Ta = –40 to 85°C VCC 2.0 Min Typ Max Min Max Unit 1.5 — — 1.5 — V J0 to J7 4.5 6.0 3.15 4.2 — — — — 3.15 4.2 — — C/T, SPE PR, CLR 2.0 4.5 1.5 3.15 — — — — 1.5 3.15 — — CLK, CLK 6.0 4.2 4.5 to 2.0 5.5 — — — — 4.2 2.0 — — 2.0 4.5 — — — — 0.5 1.35 — — 0.5 1.35 6.0 2.0 — — — — 1.8 0.5 — — 1.8 0.5 4.5 6.0 — — — — 1.35 1.8 — — 1.35 1.8 — 0.8 — 0.8 Test Conditions C/T = VIH C/T = VIL V J0 to J7 C/T, SPE PR, CLR CLK, CLK C/T = VIH 4.5 to — 5.5 2.0 1.9 2.0 — 1.9 — 4.5 6.0 4.4 5.9 4.5 6.0 — — 4.4 5.9 — — 4.5 6.0 4.18 5.68 4.31 5.80 — — 4.13 5.63 — — 2.0 4.5 — — 0.0 0.0 0.1 0.1 — — 0.1 0.1 6.0 4.5 — — 0.0 0.17 0.1 0.26 — — 0.1 0.33 — — 0.18 — 0.26 ±0.1 — — 0.33 ±1.0 µA IOL = 5.2 mA VIN = VCC or GND — — 4.0 — 40.0 µA VIN = VCC or GND Input capacitance IIN 6.0 6.0 Supply current ICC 6.0 Rev.2.00, Jul.16.2004, page 4 of 13 C/T = VIL V VIN = IOH = –20 mA VIH or VIL IOH = –4 mA IOH = –5.2 mA V VIN = VIH or VIL IOL = 20 mA IOL = 4 mA HD151011 Switching Characteristics (CL = 50 pF, tr = tf = 6 ns) SymItem Maximum clock bol fmax frequency Ta = 25°C Ta = –40 to 85°C VCC Min Typ Max Min Max Unit 2.0 — — 4 — 3 MHz 4.5 6.0 — — 36 — 20 24 — — 16 19 tTLH tTHL 2.0 4.5 — — 30 8 75 15 — — 95 19 Propagation delay time tPLH 6.0 2.0 — — 7 — 13 250 — — 16 318 tPHL 4.5 6.0 — — 30 — 50 45 — — 63 53 tPLH tPHL 2.0 4.5 — — — 35 300 60 — — 380 75 tPLH 6.0 2.0 — — — — 53 150 — — 65 185 tPHL 4.5 6.0 — — 18 — 30 25 — — 38 32 Pulse width (CLK, CLK, PR, CLR) tw 2.0 4.5 80 16 — — — — 100 20 — — Setup time ts 6.0 2.0 14 100 — — — — 17 125 — — 4.5 6.0 20 17 — — — — 25 21 — — 2.0 4.5 15 10 — — — — 15 10 — — 6.0 — 5 — — 5 — 10 5 — — 10 Output rise/fall time (Jn - CLK, CLK) (SPE, CLK, CLK) Hold time (Jn - CLK, CLK) (SPE, CLK, CLK) Input capacitance th CIN Test Conditions ns ns CLK or CLK to CO CLK or CLK to Q PR or CLK to Q ns ns ns pF Power dissipation CPD — — 48 — — — pF capacitance*1 Note: 1. CPD is equivalent capacitance inside of the IC calculated from the operating current without load (see test circuit). The average operating current without load is calculated according to the expression below. ICC (opr) = CPD • VCC • fIN + ICC Rev.2.00, Jul.16.2004, page 5 of 13 HD151011 Test Circuit VCC VCC Input J0 J1 Pulse generator See Function Table Zout = 50 Ω Input Pulse generator Zout = 50 Ω Output Q Output J7 CO C/T CLK CLK CL SPE CL PR CLR Note: 1. CL includes probe and jig capacitance. Waveforms – 1 tw tw 6 ns 6 ns CLK CLK VIH 90 % 90 % *1 *1 V ref V ref 10 % 10 % t PLH GND t PHL 50 % 50 % 10 % t THL 10 % t TLH t PLH 90 % t TLH 1. In case of C/T = "L", CLK, CLK is VIH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is VIH = VCC, Vref is VCC × 50% Rev.2.00, Jul.16.2004, page 6 of 13 VOH 90 % 10 % Note: VOL t PHL 50 % CO VOH 90 % 90 % Q *1 50 % 10 % t THL VOL HD151011 Waveforms – 2 6 ns 90 % Jn VCC 90 % 50 % 10 % 10 % GND ts CLK *1 90 % VIH 10 % 6 ns GND *1 V ref 10 % CLK F/F Output VOH *2 50 % VOL Internal delay Waveforms – 3 6 ns 90 % Jn 90 % VCC 50 % 10 % 10 % th CLK GND *1 90 % VIH 10 % 6 ns GND *1 V ref 10 % CLK VOH *2 50 % F/F Output Internal delay Notes: 1. In case of C/T = "L", CLK, CLK is VIH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is VIH = VCC, Vref is VCC × 50% 2. F/F output is internal signal of IC. Rev.2.00, Jul.16.2004, page 7 of 13 VOL HD151011 Waveforms – 4 6 ns 90 % SPE VCC 90 % 50 % 10 % 10 % GND ts CLK *1 90 % VIH 10 % 6 ns GND *1 V ref 10 % CLK F/F Output VOH *2 50 % VOL Internal delay Waveforms – 5 6 ns 90 % SPE 90 % VCC 50 % 10 % 10 % th CLK GND *1 90 % VIH 10 % 6 ns GND *1 V ref 10 % CLK VOH *2 50 % F/F Output Internal delay Notes: 1. In case of C/T = "L", CLK, CLK is VIH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is VIH = VCC, Vref is VCC × 50% 2. F/F output is internal signal of IC. Rev.2.00, Jul.16.2004, page 8 of 13 VOL HD151011 Waveforms – 6 tf tr VCC 90 % 90 % CLR 50 % 50 % 10 % 10 % GND tw tf tr 90 % 90 % VCC PR 50 % 50 % 10 % 10 % GND tw t PHL t PLH VOH Q 50 % 50 % VOL Rev.2.00, Jul.16.2004, page 9 of 13 HD151011 Timing Chart CLK SPE J0 J1 J2 J3 J4 J5 J6 J7 (CO=SPE) CLR (Initialize of CLR) Q PR (Initialize of PR) Q Count 5 Rev.2.00, Jul.16.2004, page 10 of 13 4 3 2 1 0 3 2 1 0 23 22 HD151011 Example of Application Circuit AC Signal Generator for STN Type Liquid Crystal Panel CLK (CLK) : Initialize counter Note: CMOS level input : 32 CO V CC J0 (Test 1) NC J1 (Test 2) NC J2 C/T J3 CLK J4 CLK J5 Q J6 PR J7 SPE GND CLR When initializing output D-F/F apply "L" Rev.2.00, Jul.16.2004, page 11 of 13 * * HD151011 Timing Chart Example of AC Signal Generator 1 2 3 32 31 30 31 32 33 34 35 65 66 67 68 CLK SPE J0 J1 1digit=2 J2 J3 J4 J5 2digits=3 J6 J7 (CO=SPE) CLR Q PR Q Count Rev.2.00, Jul.16.2004, page 12 of 13 2 1 0 32 31 1 0 32 31 HD151011 Package Dimensions As of January, 2003 Unit: mm 12.6 13 Max 11 1 10 5.5 20 *0.20 ± 0.05 2.20 Max 1.15 0˚ – 8 ˚ 0.10 ± 0.10 0.80 Max 0.20 7.80 +– 0.30 1.27 *0.40 ± 0.06 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-20DAV — Conforms 0.31 g As of January, 2003 Unit: mm 6.50 6.80 Max 11 1 10 4.40 20 0.65 *0.20 ± 0.05 1.0 0.13 M 6.40 ± 0.20 *Ni/Pd/Au plating Rev.2.00, Jul.16.2004, page 13 of 13 0.07 +0.03 –0.04 0.10 *0.15 ± 0.05 1.10 Max 0.65 Max 0˚ – 8˚ 0.50 ± 0.10 Package Code JEDEC JEITA Mass (reference value) TTP-20DAV — — 0.07 g Sales Strategic Planning Div. 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