Class D Amplifier Design Basics II 02/19/2009 Rev 1.0 1 Contents Chapter 1 Getting Familiar with Class D Audio Amplifier Chapter 2 Latest Class D Audio Amplifier Technology Trend Chapter 3 Identifying Problems ~ Performance Measurement of Class D Amplifier Chapter 4 Reducing Distortion ~Dead-time ~ LPF Designs Chapter 5 Reducing Noise ~ Isolation Technique ~ PCB Design APPENDIX Simulation of a Simple Class D Amplifier 2 Chapter 1: Getting Familiar with Class D Audio Amplifier Audio Amplifier Market Trend • More Channels • Smaller Box • Lighter Weight A Wire with Gain • More Functions (Digital Input, Diag) Device Technology • Smaller Size • Lower Cost Control Technology • Audio Performance 4 Why Class D Now? Audio Market Trend • More Channels Class AB • Smaller Size • Smaller Size IR Class D • Higher Performance Device Technology • MOSFET • High Speed HVIC 5 Basic Concept of Class D Audio Amplifier COMP Analog signal Î PWM Class D Switching Stage Amplify LPF PWM Î Analog signal VOUT = B (2D-1) In concept, Class D amplifier is linear; i.e. 0% distortion. 6 PWM: Heart of Class D Operation PWM Î Audio signal 10 10 5 5 0 0 V V Audio signal Î PWM -5 -5 -10 -10 60 Time/uSecs 80 100 120 140 20uSecs/div 60 Time/uSecs 80 100 120 140 20uSecs/div 7 Class AB vs. D Energy Point of View Similar to a variable resistor Class AB IIN = IOUT PLOSS depends on output power factor Similar to a transformer with variable turn ratio Class D VIN x IIN = VOUT x IOUT Bi-directional energy flow Note that input current and output current are not equal. 8 Class AB vs. D Characteristic Comparison (1/2) Feature Class D Advantage Superior efficiency Efficiency can be improved with device technology Efficiency Energy flow Drivability Suitable to drive lower impedance load Can drive reactive load without significant degradation of efficiency Requires smaller power supply Bi-directional energy flow; any energy reflected from the load is recycled to the power supply. Suitable to drive highly reactive load, such as woofer, speaker system with dividing network, piezo speaker, etc. Class AB Efficiency is fixed. Extremely inefficient when driving lower impedance load. Extremely inefficient when driving reactive load. All the reflected energy from reactive components and back EMF are consumed dissipating heat The output device has high impedance, ~tens of k ohm. Inherently has low output impedance (m ohm range) With a strong voltage feedback, Class AB can achieve low output impedance. Power supply current = load current. For a given output Lower impedance loading does not burden power supply. power with decreased load (Power supply current) ≠ (load current). impedance, the supply current and heat dissipation in the output device increase. Cross conduction limits high Wide power bandwidth; no extra effort to drive high frequency rated power. frequency power bandwidth. 9 Class AB vs. D Characteristic Comparison (2/2) Feature Class D Advantage Topology is inherently linear without feedback Linearity Cross over distortion is not in zero crossing area Stability Thermally stable; gain of the Class D stage, bandwidth, loop-gain are independent of output device temperature. Class AB Output device is non-linear; exponential in BJT, quadratic in MOSFET. Strong feedback is necessary to achieve good linearity. Cross over distortion is at where load current crosses zero, which is most critical point of operation. Output devices in linear operating mode has strong temperature coefficient in gain. Loop-gain is changing dynamically with output power. No bias-current thermal compensation Noise immunity Inherently immune to incoming noise; low drive impedance, inductor between the load and amplifier. Reliability Higher reliability from less heat. Less metal fatigue in solder joints. Because of strong non-linearity in device and 'exposed' feedback node, weak to RF noise. 10 Class AB vs D Comparison Loss Loss in Class AB 2 Pc = 0.2 ⋅ π 1 Vcc (1 − K sin ω ⋅ t ) Vcc K sin ω ⋅ t • dω ⋅ t PC = ⋅∫ 2 ⋅π 0 2 2 ⋅ RL Vcc 2 = 8π ⋅ RL ⎛ 2K K 2 ⎞ ⎟⎟ ⋅ ⎜⎜ − 2 ⎠ ⎝ π VCC 8 ⋅ RL Note that this is independent to device parameters. K=2/π K=1 Loss Loss in Class D Efficiency can be improved further! PTOTAL = Psw + Pcond + Pgd Pcond = RDS (ON ) RL ⋅ Po Psw = COSS ⋅ VBUS ⋅ f PWM 2 Pgd = 2 ⋅ Qg ⋅ Vgs ⋅ f PWM K=1 K is a ratio of Vbus and output voltage. To learn more about power losses in Class D, refer to AN-1070 Class D Amplifier Performance Relationship to MOSFET Parameters. 11 Practical Class D Amplifier Perturbation Supply impedance Bus Pumping Limited Gain & BW Noise Figure Audio source PWM Nonlinear inductance / Capacitance DC Resistance +VCC Gate Driver F/B -VCC 1. Non-linearity in the switching stage due to timing errors added, such as dead-time, ton/toff, and tr/tf Finite RDS(on) Vth and Qg Body diode recovery Stray inductances Dead-time 2. Limited amount of error collection capability due to limited gain and bandwidth in PWM modulator 3. Audio frequency band noise added in PWM modulator 4. Unwanted characteristics in the switching devices, such as finite ON resistance, finite switching speed or body diode characteristics. 5. Parasitic components that cause ringing on transient edges 6. Power supply voltage fluctuations due to its finite output impedance and reactive power flowing through the DC bus 7. RDS(ON) ON delay OFF delay Note that 0.01% of nonlinearity corresponds to10mV out of 100V DC bus, or 0.25ns in 400kHz! Finite dV/dt Non-linearity in the output LPF. 12 MOSFET Basics A MOSFET is a device to switch electronic current. A driving MOSFET charges/discharges a capacitor (Gate to Source, Gate to Drain). In switching transition, stray impedance in each terminal slows down switching and generates unwanted rings. A MOSFET does not require any energy to keep it on-state. To learn more about power MOSFETs, refer to AN-1084 Power MOSFET Basics. 13 Driving MOSFET for PWM • Only one side, either high-side or lowside, MOSFET is ON at a time. • The ratio of ON time between the highside and low-side MOSFETs determines the output voltage. High-side ON Driving a high-side MOSFET • A floating power supply that referenced to switching node drives the gate of the high-side MOSFET Alternating at Switching Frequency Low-side ON • The floating power supply is charged when the low-side MOSFET is ON. (Bootstrap power supply) Driving a low-side MOSFET • A bias voltage that refers to negative bus voltage –B drives the gate of the low-side MOSFET. NOTE: In a practical design, a dead-time where both high- and low-side MOSFETs are off is inserted to prevent simultaneous ON state. Refer to chapter 4 for more details. 14 Bootstrap High Side Power Supply High-side ON Low-side ON • I4 turns off the low-side MOSFET. Then, I5 turns on the high-side MOSFET, lifting VS up to +B. As long as the high side is ON, bootstrap diode DBS isolates the floating power supply VBS and bootstrap capacitor CBS retains VBS voltage. • After the high-side MOSFET ON state, I1 turns off the high-side MOSFET, then I2 turns on the low side MOSFET. As soon as switching node VS reaches negative supply –B, the bootstrap diode DBS turns on and starts charging bootstrap capacitor CBS with current I3 from VCC. • Note that VBS = VCC – (forward drop voltage of DBS). 15 Example of a 100W Class D Amplifier Optional switching noise filter VAA supply Feedback resistor High-side OCP Input resistor Bootstrap floating supply charging path ENABLE 20 V R8 4.7 Ω 6V Startup resister Bootstrap floating supply capacitor C11 10 µF 6V DC blocking capacitor VSS supply Demodulation LPF 20 V 2nd order integrator Low-side OCP Dead-time 16 Chapter 2: Latest Class D Audio Amplifier Technology Trend Class D Amplifier Innovations Device Technologies • MOSFET FOM (Figure of Merit) improvements • Higher voltage capability • Faster and accurate switching time • High gain low noise process Packaging Technology Signal Processing Technologies • Smaller • Feedback techniques • Low stray inductance • Self-oscillating topologies • Surface mount • Dual sided cooling • Digital domain PWM processing • Hybrid module • Multi chip module • High GBW (Gain BandWidth) process Higher Performance + Smaller Size + Lower Cost At The Same Time ! 18 1. MOSFET Technology Trend A MOSFET has inherent trade-offs between ON resistance and gate charge, RDS(on) vs Qg. In device design, this translates into Conduction loss vs Switching loss trade-off. International Rectifier Mosfet R*Qg Trend 1.2 Planar Stripe Technology 1.1 1 The objective of optimization for Class D applications is to achieve minimal power loss. Normalized R*Qg 0.9 0.8 0.7 Trench Technology IR Mosfet Technology Constant Improvement 0.6 0.5 0.4 0.3 Newer platforms show better FOM (Figure of Merit) 0.2 2000 2001 2002 2003 2004 2005 Fiscal Year Î This is what makes Class D keep improving! 19 MOSFET Evolution The latest trench MOSFET technology shows 7 times better figure of merit. Higher cell density Planar MOSFET Structure Trench MOSFET Structure IRF540 IRF6665 100 V 100 V 66m ohms 50 nC RDS(on) x Qg=3300 53m ohms RDS(on) x Qg=445 8.4 nC 20 Trade-offs in MOSFET Design There is a best die size for a given output power. Optimum die size for minimal PLOSS depends on load impedance, rated power and switching frequency. Optimal MOSFET die size ⇒Optimal MOSFET Parameters Total Loss = Conduction Loss + Switching Loss Total Loss A more advanced platform with better FOM acheives lower PLOSS. Optimal MOSFET Die Size Conduction Loss Switching Loss To learn more about MOSFET selection, refer to AN-1070 Class D Amplifier Performance Relationship to MOSFET Parameters. 21 Importance of Packaging How the package affects the design? 1. Amplifier size • Increase efficiency • Increase current capability • Improve the MOSFET thermal efficiency To utilize benefits from a newer generation MOSFET, new package with reduced stray inductance is necessary. D1 G1 G2 D2/S1 2. EMI considerations • Better control of current and voltage transients S2 ⇒ TO-220 Full-Pak 5 PIN 3. Amplifier linearity • Decrease switching times • Narrow the MOSFET parameter distribution 22 Stray Inductance A MOSFET has capacitive elements. Stray inductance is where excessive energy is stored, causing over/under shoots and rings. Stray inductance in Source returns feedback voltage to gate, slowing down switching speed significantly. The smaller the parasitic components the better performance! To learn more about MOSFET switching behavior, refer to AN-947 Understanding HEXFET Switching Performance. 23 Package Comparison • Lower inductance at frequency than SO-8, D-Pak, MLP and D-Pak • TO-220 inductance package is ~ 12nH • DirectFET® is 0.4nH 24 EMI Comparison • DirectFET® amplifier shows better EMI performance than TO-220 amplifier • Over 2MHz, DirectFET amplifier shows approximately 9dBuV lower Peak, Quasi-Peak and Average noise than TO-220 amplifier • Both PCB’s meet audio amplifier EMI standards limits (CISPR13) DirectFET Frequency (MHz) TO-220 (w/DirectFET die) Frequency (MHz) CISPR13 CISPR13 Quasi-Peak Limits Quasi-Peak Limits Average Limits Average Limits 25 2: Gate Driver IC Technology Trend • More integration to realize smaller footprint Gate driving Analog signal processing Power switching Level shifting Feed back AUDIO SIGNAL PWM Level Shift Down Level Shift Up Dead Time Speaker Shut Down Over Current Protection Control Logic Protection functions 26 What The Gate Driver IC Does? Four Essential Functions in Gate Driver IC • Level Shift • Gate Drive • Deadtime Generation • Under Voltage Lockout Gate Driver IC To learn more about High Voltage Gate Driver IC, refer to AN-978 HV Floating MOS-Gate Driver ICs. 27 How Internal High Voltage Level Shifter Works Operation Principle A pair of SET and RESET signals are generated at the PULSE GEN block. The SET and RESET pulses drive the high voltage MOSFET to send these signals to circuitries in a floating highside well. Pulse Gen Waveform Example HIN The high-side circuitry reconstructs PWM from SET and RESET pulses. SET RESET HO This method minimizes power dissipation in the high voltage MOSFETs in level shifter. 28 Floating Well and Noise Isolation INPUT SECTION HIGH SIDE GATE DRIVE LOW SIDE GATE DRIVE LEVEL SHIFTERS Note • Translate PWM signal to different voltage potential • Level shifter rates supply voltage ranges • Isolate circuit blocks that are in different voltage potentials • Level shifting is useful to drive high-side the MOSFET whose source is tied to switching node. • Level shifting blocks switching noise coming into sensitive input section. 29 Dead-time Generation With Dead-time Dead-time (or blanking time) is a period of time intentionally inserted in between the ON states of high- and low-side MOSFETs. This is necessary because the MOSFET is a capacitive load to the gate driver that delays switching time and causes simultaneous ON. NO DEADTIME Without Dead-time Lack of dead-time results in lower efficiency, excessive heat and potential thermal failure. INPUT HIGH-SIDE Usually, dead-time is realized by delaying turn on timing. LOW-SIDE SIMULTANEOUS ON 30 Under Voltage Lockout • Under voltage lockout (UVLO) prevents the MOSFET from entering the “half-ON” region when the gate bias voltage is reduced. • During the UVLO, gate drive stage keeps HO/LO low in order to prevent unintentional turn-on of the MOSFETs. • The “half-ON” condition of the MOSFET creates excessive power loss due to increased RDS(on) that could lead to MOSFET failure, therefore must be avoided. • UVLO in VCC resets shutdown logic and causes CSD recycling to start over the power up sequence. CSH UV DETECT • The IR Class D audio gate driver family is designed to accept any power sequence. VB HIGH SIDE CS UV Q HO HV LEVEL SHIFT FLOATING HIGH SIDE HV LEVEL SHIFT VS UVLO of VBS shuts down HO and disable high-side current sensing 31 Inside of High Voltage Gate Driver IRS2092 High Voltage Isolation FLOATING INPUT CLICK NOISE ELLIMINATION VAA VB 6.5V ` IN- VAA+VSS 2 OTA ENABLE GND ` Q COMP PWM MODULATOR HV LEVEL SHIFT COMP UV DETECT 6.5V UV HIGH SIDE CS 20.4V PWM Modulation Pop Noise Elimination CSH UV DETECT HV LEVEL SHIFT FLOATING HIGH SIDE High Speed, Low Distortion VCC Level Shift VS HV LEVEL SHIFT 5V REG UV DETECT VSS HO DEAD TIME LO SD DT CHARGE/ DISCHARGE HV LEVEL SHIFT PROTECTION CONTROL HV LEVEL SHIFT Dead Time Control 20.4V Shut down Recycle Control CSD COM Over Current Sensing OCSET VREF LOW SIDE CS DT 32 3. PWM and Feedback Technologies PWM modulator’s functions Demands • Convert analog or digital audio signal (PCM) to PWM that has reasonable switching frequency for power MOSFET • Feedback to reduce DC offset, • Error corrections to improve audio performance distortion and noise floor • Larger loop gain for lower distortion, higher power supply rejection ratio (PSRR) • Post filter feedback for higher damping factor • Switching frequency control for reduced EMI 33 Natural PWM vs. Self Oscillating PWM Natural PWM • Open loop or closed loop • Fixed frequency Optional feedback Self-oscillating PWM • Closed loop • Frequency changes with modulation • High loop gain • Fewer components 34 Modern PWM Topologies Self-oscillating PWM with 2nd order integration Global feedback from speaker output Self-oscillating PWM with pulse width control Inductor-less PWM 35 IRAUDAMP5 Functional Block Diagram Typical IR audio evaluation board based on self-oscillating PWM with 2nd order integration * FEEDBACK IRF6645 DirectFET VOLUME IC CS3310 INPUT + ERROR AMP + * + PWM COMP. DT Micro controller LPF L/S L /S * SD * CS IRS2092 - OTP DCP PROTECTION LOGIC PROTECTION CONTROL 36 Chapter 3: Identifying Problems ~ Performance Measurement of Class D Amplifier Identifying Problems • Proper audio performance measurement is crucial to identify potential problems. • Frequency response and THD+N are the minimum basic measure of audio performance. Problem Possible Causes Low frequency response Audio input, feedback network High frequency response Audio input, feedback network, LPF design High harmonic distortion Shoot-through, dead-time, switching noise coupling High noise floor Analog input, switching noise coupling 38 1. Frequency Response • Use resistive dummy load. • Set reference voltage level to 1W output power at 1kHz. • Sweep sinusoidal signal from 20Hz to 100kHz. • Take frequency response with various load impedances and without loading. International Rectifier A-A FREQUENCY RESPONSE 08/15/06 10:56:54 +1 +0.5 +0 d B r A -0.5 -1 Reference 1kHz=0dB, usually set to 1W output power -1.5 -2 -2.5 -3 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k Hz Sweep Trace Color Line Style Thick Data Axis Comment 1 1 Red Solid 1 Anlr.Level A Left 8Ohm, 1W, 80kHz BW Frequency Response from 20k to 20 Hz. F4 first to set 0 dBr at 1kHz. The 2 Ch Ampl Function Reading meter BW is set to <10 Hz & >500kHz so the bandwidth is the same as the Level meter. Optimize for detail. A-A FREQ RESP.at2 39 Check for.. R117 3.3k 1w R17 R22 75k R18 10K U1 CSH 16 10k CP6 22uF 2 GND VB 22uF R2 3 3.3k 10uF 1nF 1nF R3 C7 100R CP3 HO VS1 4 5 COMP VS High Frequency 4 L1 22uH R24 CSD VCC 6 VSS LO R13 D3 12 20R VREF COM 8 OCSET IRS2092S DIP DT 9 R30 R31 10, 1W 2.2k + CH1 - 2 R25 10 10k R12 8.7k C12 0.47uF, 400V 4.7R 11 SPKR1 1 2 R20 -B 7 CH_OUT 3 13 10uF CP2 22uF R118 3.3k 1w IN- 20R 14 C6 C4 SD D1 1nF CP8 470uF,100V FET1 15 270R CP1 0.1uF,100V 5 R11 VAA C13 0.1uF, 400V -B 1 RCA1 1 R8 100k C11 D4 9.6k R19 CP4 Low Frequency +B R26 R21 R23 10R 4.7K 10k R27 10k CP5 22uF LED1 Blue C14 0.1uF CP7 470uF,100V VCC -B 40 2: THD+N • THD+N is a sum of harmonic distortion components and noise, i.e. anything except fundamental spectrum. Fundamental THD 2nd order harmonic 3rd order harmonic • THD is a measure of linearity. frequency Î Refer to Chapter 4 • Noise is a measure of added errors not depending on the input signal Î Refer to Chapter 5 Fundamental THD+N 2nd order harmonic 3rd order harmonic Noise frequency 41 What is Distortion? • THD is a simple way to measure non-linearity of the amplifier. • If the amplifier is not linear, it generates harmonics. Any repetitive waveforms can be expressed as a sum of sinusoidal signal as Harmonic distortion is a ratio of rms value of the harmonic component and the original waveform. Total harmonic distortion is a ratio of rms value of sum of the all harmonic component and the original waveform. 42 How to Read THD+N vs. Power 100 T IRAUDAMP4 THD+N ±30 V 10 ±25 V 1 % ±35 V 0.1 out noise floor, distortion and output power in a shot. • Noise floor dominant part has 20dB/dec slope. • Reading above noise floor 0.01 0.001 100m • THD+N vs. Power spells slope is dominated by harmonic distortion. 200m 500m 1 2 5 10 20 50 W Noise floor Distortion Clipping 100 200 • To trouble shoot, better to start with single channel operation. 43 Check for.. R117 3.3k 1w R17 R22 75k R18 10K U1 9.6k R19 CP4 1 10k CP6 22uF 2 GND VB IN- HO 3 3.3k 1nF 1nF R3 C7 COMP VS 100R CP3 VS1 4 5 CSD VCC 6 VSS LO R13 L1 22uH R24 VREF COM D3 12 R12 8.7k C12 0.47uF, 400V 20R OCSET IRS2092S DIP DT 9 R30 R31 10, 1W 2.2k + CH1 - 2 R25 10 SPKR1 1 2 R20 4.7R 11 10k 8 CH_OUT 3 -B 7 CP8 470uF,100V LPF 4 13 10uF CP2 22uF R118 3.3k 1w 20R 14 C6 C4 SD D1 1nF 0.1uF,100V FET1 22uF R2 10uF dead-time 15 270R CP1 C11 D4 C13 0.1uF, 400V -B 1 RCA1 R11 CSH 16 5 R8 100k Ceramic? VAA +B R26 R21 R23 10R 4.7K 10k R27 10k CP5 22uF LED1 Blue C14 0.1uF CP7 470uF,100V VCC -B Switching noise coupling 44 Audio Measurement Setup Amplifier Output 20KHz LPF Amplifier Output Filtered Amplifier Input For more information on Class D audio measurement, refer to white paper, Measuring Switch-mode Power Amplifiers by Bruce Hofer, from //ap.com 45 Audio Measurement Setup with IRAUDAMP7D Audio Precision System Two with AES-17 Filter 46 AP Substitute • Old audio analyzers are not designed to tolerate high frequency noise that is from carrier signal residual from a Class D amplifier. • Place a 3rd order LPF to remove the switching carrier ingredients in front of the audio analyzer • Check measurements are correct by changing scaling range manually An Example of an additional pre-LPF for HP8903B 8 R4 470 680 1K R1 R2 R3 4.7n C1 2.2n C2 1n C3 To HP8903B Dummy Load 47 Chapter 4: Reducing Distortion ~dead-time ~ LPF Designs Trade-off 1: Dead-time and Distortion 34 40 30 1 Positive half cycle: Hard Switching 20 10 Vout( t ) 2 0 10 20 4 Cross over region: ZVS 3 Negative half cycle: Hard Switching 30 − 34 40 0 0 5 .10 4 0.001 0.0015 t 0.002 0.0021 • Dead-time reduces volt-second therefore voltage gain. • There is a region that dead-time does not affect around zero crossing (regions 2 and 4). • The smaller the dead-time, the lower the distortion. • Too narrow dead-time could cause shoot-through from unit-to-unit, temperature and production variations, that could seriously affect product reliability. • Audio performance and reliability is NOT a trade-off. 49 Gate Drive and Switching Output ZVS Region Hard Switching Region Turning off of the previous MOSFET dictates transition in switching waveform. Turning on dictates output switching waveform. High-side VGS Low-side VGS Switching Node VS 50 PWM Switching Cycle 1 High Side ON +B +B VBS -B VCC 2 Dead-time 4 Dead-time ? ? +B VBS VBS -B VCC -B VCC -B VBS VCC +B +B -B 3 Low Side ON 51 During Dead-time 1 2 4 3 • Polarity of IL is always toward the load • VS follows high side switch status • Polarity of IL alternates • VS follows turning off edges of both high and low sides • ZVS Î No influence from dead-time insertion • Polarity of IL is always toward the amp • VS follows low side switch status Note: Dead-time insertion reduces volt-second of VS. Dead-time inserted in the rising edge of the high side affects the operating region 1. Dead-time inserted in the rising edge of the low side affects the operating region 3. As a result, output voltage gets lower than it should be, causing non-linearity in the output stage. 52 Trade-off 2: Inductor and Distortion • The quality of the output inductor is crucial to achieve not only the target audio performance but also efficiency. THD characteristic with various inductors 100 TTT T TTTT 10 1 % • Inductance changes with load current, which causes distortion. 0.1 0.01 • Core saturation increase inductor 0.001 ripple significantly that can trigger over current protection. 0.0001 100m 200m 500m 1 2 5 10 20 50 100 200 W Inductance Soft saturation core Hard saturation core Load current Frequency characteristic of IRAUDAMP4 53 LPF Design • Set corner frequency according to the bandwidth requirement. • Design LC-LPF with Q=0.7 for a nominal load impedance to attain flat frequency response. Inductance and inductor ripple I L PP = Vbus L ⋅ f SW Inductor ripple current dictates ZVS region Note that Lower Switching Frequency - The higher the corner frequency the higher the switching carrier leakage - The lower the corner frequency the bigger the inductance size Higher Ripple Current Higher Corner Frequency Higher Ripple Current 54 LPF Design 1. Decide the order of the filter based on the attenuation of the switching frequency given by: 2nd order LPF ⎧⎪ ⎛ f ⎞ 2 N ⎫⎪ At = 10 ⋅ log ⎨1 + ⎜⎜ ⎟⎟ ⎬ ⎪⎩ ⎝ f C ⎠ ⎪⎭ 3rd order LPF 4th order LPF 2. Design Butterworth filter # of Order Ln = RL Lk n 2 ⋅ π ⋅ fC Cn = Ck n 2 ⋅ π ⋅ f C ⋅ RL Lk1 Ck1 Lk2 Ck2 2 1.414214 0.707107 - - 3 1.5000 1.3333 0.5000 - 4 1.530734 1.577161 1.082392 0.382683 3. Design Zobel network 55 Choosing Inductor for LPF Air Coil Large, High DCR, Low distortion, Leakage flux Drum Core Small, Leakage Flux, Low DCR (Ferrite, Open Circuit) Drum Core (Ferrite, Closed Circuit) Toroidal Core Small, Hard saturation, Low DCR Soft saturation, Lower iron loss (Iron Powder) NOTE • Ferrite core is suitable for smaller size • Iron powder is suitable for high power • Determine IRMS rating for temperature rise condition with 1/8 rated power • Determine peak current (ISAT) based on maximum load current 56 Choosing Capacitor for LPF Polyester film, winding Small, High ESR Ceramic High dielectric type has large distortion, lower AC ratings Polyester, non-inductive Small, lower AC voltage rating Polypropylene, non-inductive Low dissipation factor, large size, low distortion NOTE • Do not use winding structure types. Use stacked structure. • Check AC voltage ratings at highest audio frequency. 57 LPF Design Example + 4 Corner frequency: 40kHz + 2 8Ω + d 0 Load impedance: 4 ohms B Output power: 250W (32Vrms, 11Apeak) r 2 A 4 4 Ω 6 22uH 8 10 2 0 0.1uF 5 0 10 0 20 0 50 0 1 2 k Hz k 5 k 10 k 20 k 50 k 200 k 4 0.47uF 10 Sagami 7G17B220 EPCOS B32652A4474J 22µH, 13A, 10mΩ Polypropylene, 0.47µF, 400VDC Ferrite, closed circuit with inner gap 58 Chapter 5: Reducing Noise ~ Noise Isolation Technique ~ PCB Design Sources of Noise in Class D Amplifier Switching noise Audio noise Switching noise is generated by the output MOSFET switching in wide range of frequency spectrum above the audible range. The amount of switching noise depends on: Audio noise is a noise ingredient in audible frequency range in the speaker output. Major causes of audio noise includes: • Switching speed • Noise figure (NF) in the front-end error amplifier • Size of the MOSFET • Jitter in switching time • Load current • RFI noise from switching noise injection • PCB layout • Locations and quality of bypass capacitors • Thermal noise from resistors • Hum noise (AC line 60Hz and its harmonics) from ground loop 60 Noise Reduction Strategy 1. Minimize noise source in switching stage 2. Maximize noise immunity in analog stage 3. Minimizing noise coupling from switching stage to analog stage 61 1: Minimizing Noise Source Self-commutation at idling. If rings, check for shoot-through, check dead time. Reverse recovery charge, Qrr, causes hard switching that triggers resonance in stray reactance. Idling (ZVS) Hard-switching Rings triggered by Qrr Qrr is a function of di/dt, drain current and die temperature. Slower switching helps to reduce Qrr. Stray inductance is where excessive energy is stored. Look for optimum trace layouts to minimize stray inductance. Low dV/dt driven by inductor and Coss High dV/dt driven by MOSFET turn on Careful component selection is key to minimize stray reactance. 62 Reducing Noise with RC Snubber RC voltage snubber is used to suppress voltage spikes in switching and power supply nodes. Resistor in RC snubber absorbs energy from reactance by damping resonance. To maximize effectiveness of a snubber - Resistance should be close to impedance of resonant element. - Capacitance should be larger than resonant capacitor. - Capacitance should be small enough not to cause too much dissipation in the resistor. Power dissipation from the resistor P= 2*f*(½CV2) 63 Snubber and THD Adding snubber usually improves THD+N. Change should be in hard switching region. Basic approach: Make all efforts to minimize stray inductances and current loop areas (minimize resonant energy), then tailor snubber values. 1 0.5 Pay attention to dissipation at snubber. 0.2 0.1 0.05 % 0.02 0.01 0.005 0.002 0.001 100m 200m 500m 1 2 5 10 20 50 100 300 W Sweep Trace Color Line Style Thick Data Axis Comment 1 2 1 1 Red Blue Solid Solid 2 2 Anlr.THD+N Ratio Anlr.THD+N Ratio Left Left original+150p+10ohighside original (low side snubber onl 64 2: Maximizing Noise Immunity NOTE Input RF Filter • Filter out HF noise and reduce node impedance at high frequency Feedback LPF Differential Input RFI Filter • Prevent RFI causing audio frequency interferences from switching rings • Weed out high frequency spectrum to avoid TIM distortion in the error amplifier • Ground can be a route of noise injection to error amplifier 65 RFI Analog stage uses non-linear components such as diode, BJT and FET. Diode amplitude detector When a non-linear component receives high frequency components, it detects envelop information that could fall into audio frequency range (amplitude modulation envelop detector). When non-linear components receives high frequency components along with audio signal, it could shift operating bias point and cause distortion in audio signal. 66 3: Minimizing Noise Coupling There are functional blocks that generate noise. There are functional blocks that are sensitive to noise. The PCB designer should identify them and find out the best combination of the placement based on these facts and mechanical and thermal requirements. Noise Sensitive Nodes Noise sensitive functions: - The audio input circuitry - The PWM control circuitry - Noise generating functions - The gate driver stage Noise Generating Nodes - The switching stage 67 Switching Noise Injection Example Noise Coupling from VS Insufficient Bypass Cap Original Design (IRAUDAMP7D) 68 PCB Design Tips The first and most important step for PCB designers is to group components dedicated to a common purpose, such as: Key Components Layout Example (IRAUDAMP7D) - the audio input circuitry - the PWM control circuitry - the gate driver stage - the switching stage By identifying which components belong together, place the remaining circuitry by coupling them appropriately into open areas of the board. PWM GATE DRIVE MOSFET LPF Placement Determines Maximum Performance ! 69 PCB Layout Example Audio Input, Error Amplifier Note that • Separation between analog and switching sections • Minimized trace impedances with planes in power section • No overlap between switching nodes and analog nodes Analog Section Gate Drive Section Switching Nodes Load Current Paths Power Section 70 APPENDIX Simulation of a Simple Class D Amplifier (SIMetrix) Feedback 0 IC 47k R1 1n 1n C1 C2 E2-N 10u 3.3k C8 R8 AC 1 0 Sine(0 1 5k 0 0) V5 220 R2 10k 2.5*(1+tanh(1e4*v(n1,n2))) ARB1 DELAY N1OUT ARB1-OUT N2 HC04D HC04D U1 U2 U5 250n E3 HO S1 LO D3 IDEAL 50 V4 18u L1 470n C3 S2 Integrator Comparator Delay sp out D4 IDEAL Gate Driver Note • Disable initial DC operating point analysis 4 R6 LPF 50 V1 MOSFET Simulation set up with SIMetrix • Add initial value in the feedback loop to start off oscillation • Get into further work once basic ideal model is confirmed Trial version of SIMetrix can be downloaded from: http://www.catena.uk.com/ 72 Simulation Result Example 100 80 Switching Node 60 V 40 20 Gate and other internal nodes 0 -20 Speaker Output -40 150 T im e / µ S e c s 200 250 300 350 400 450 5 0 µ S e c s / d iv 73 END February 19, 2009