IRF IRAUDAMP5

IRAUDAMP5
120W x 2 Channel Class D Audio Power Amplifier
Using the IRS2092S and IRF6645
By
Jun Honda, Manuel Rodríguez and Jorge Cerezo
Fig 1
CAUTION: International Rectifier suggests the following guidelines for
safe operation and handling of IRAUDAMP5 Demo Board;
• Always wear safety glasses whenever operating Demo Board
• Avoid personal contact with exposed metal surfaces when operating
Demo Board
• Turn off Demo Board when placing or removing measurement probes
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IRAUDAMP5 REV 3.0
Table of Contents
Page
Introduction…………………………………………………………………..
2
Specifications…………………………………………………………………
3
Connection Setup……………………………………………………….……
4
Test Procedure………………………………………………………………...
5
Typical Performance………………………………………………………….
5-9
Theory of Operation………………………………………………………….
9-10
IRS2092S System Overview…………………………………………………
10-11
Selectable Dead Time…………………………………………………………
11-12
Protection Features……………………………………………………………
12-17
Efficiency……………………………………………………………………..
17-18
Thermal Considerations………………………………………………………
18
Click and Pop Noise Control………………………………………………….
18-19
Startup and Shutdown Sequencing……………………………………………
19-21
PSRR………………………………………………………………………….
21-22
Bus Pumping…………………………………………………………………..
22-23
Input/Output Signal and Volume Control…………………………………….
23-26
Self Oscillating PWM Modulator……………………………………………..
27
Switches and Indicators……………………………………………………….
28
Frequency Lock, Synchronization Feature……………………………………
29
Schematics…………………………………………………………………….
32-36
Bill of Materials………………………………………………………………
37-40
Hardware……………………………………………………………………… 41
PCB specifications…………………………………………………………….
42
Assembly Drawings…………………………………………………………...
43-49
END…………………………………………………………………………...
49
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IRAUDAMP5 REV 3.0
Page 1 of 49
Introduction
The IRAUDAMP5 reference design is a two-channel, 120W half-bridge Class D audio power
amplifier. This reference design demonstrates how to use the IRS2092S Class D audio controller
and gate driver IC, implement protection circuits, and design an optimum PCB layout using the
IRF6645 DirectFET MOSFETs. The resulting design requires no heatsink for normal operation
(one-eighth of continuous rated power). The reference design provides all the required
housekeeping power supplies for ease of use. The two-channel design is scalable for power and
the number of channels.
Applications
AV receivers
Home theater systems
Mini component stereos
Powered speakers
Sub-woofers
Musical Instrument amplifiers
Automotive after market amplifiers
Features
Output Power:
Residual Noise:
Distortion:
Efficiency:
Multiple Protection Features:
PWM Modulator:
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120W x 2 channels,
Total Harmonic Distortion (THD+N) = 1%, 1 kHz
170µV, IHF-A weighted, AES-17 filter
0.005% THD+N @ 60W, 4Ω
96% @ 120W, 4Ω, single-channel driven, Class D stage
Over-current protection (OCP), high side and low side
Over-voltage protection (OVP),
Under-voltage protection (UVP), high side and low side
DC-protection (DCP),
Over-temperature protection (OTP)
Self-oscillating half-bridge topology with optional clock
synchronization
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Specifications
General Test Conditions (unless otherwise noted)
Supply Voltage
±35V
Load Impedance
8-4Ω
Self-Oscillating Frequency
400kHz
Gain Setting
26dB
Notes / Conditions
No input signal, Adjustable
1Vrms input yields rated power
Electrical Data
IR Devices Used
Typical
Notes / Conditions
IRS2092S Audio Controller and Gate-Driver,
IRF6645 DirectFET MOSFETs
Modulator
Self-oscillating, second order sigma-delta modulation, analog input
Power Supply Range
± 25V to ±35V
Bipolar power supply
Output Power CH1-2: (1% THD+N)
120W
1kHz
Output Power CH1-2: (10% THD+N)
170W
1kHz
Rated Load Impedance
8-4Ω
Resistive load
Standby Supply Current
±100mA
No input signal
Total Idle Power Consumption
7W
No input signal
Channel Efficiency
96%
Single-channel driven,
120W, Class D stage
.
Audio Performance
Demodulator
Class D
Output
THD+N, 1W
THD+N, 10W
THD+N, 60W
THD+N, 100W
0.009%
0.003%
0.003%
0.008%
0.01%
0.004%
0.005%
0.010%
Dynamic Range
101dB
101dB
Residual Noise, 22Hz - 20kHzAES17
170µV
170µV
2000
95dB
85dB
75dB
N/A
170
90dB
80dB
65dB
±1dB
±3dB
Damping Factor
Channel Separation
Frequency Response : 20Hz-20kHz
: 20Hz-35kHz
Thermal Performance
Idling
2ch x 15W (1/8 rated power)
2ch x 120W (Rated power)
Physical Specifications
Dimensions
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*Before
Typical
TC =30°C
TPCB=37°C
TC =54°C
TPCB=67°C
TC =80°C
TPCB=106°C
Notes / Conditions
1kHz, Single-channel driven
A-weighted, AES-17 filter,
Single-channel operation
Self-oscillating – 400kHz
1kHz, relative to 4Ω load
100Hz
1kHz
10kHz
1W, 4Ω - 8Ω Load
Notes / Conditions
No signal input, TA=25°C
Continuous, TA=25°C
At OTP shutdown @ 150 sec,
TA=25°C
5.8”(L) x 5.2”(W)
IRAUDAMP5 REV 3.0
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Note: Class D Specifications are typical
*Before demodulator refers to audio performance measurements of the Class D output power
stage only, with preamp and output filter bypassed this means performance measured before the
low pass filter.
Connection Setup
35V, 5A DC supply
35V, 5A DC supply
250W, Non-inductive Resistors
4 Ohm
4 Ohm
G
J3
CH1
Output
LED
J4
TP1
S1
CH2
Output
J7
J9
TP2
Protection
CH1
Input
J8
J5
J6
CH2
Input
Normal
S2
S3
Volume
R113
Audio Signal Generator
Typical Test Setup
Fig 2
Connector Description
CH1 IN
CH2 IN
POWER
CH1 OUT
CH2 OUT
EXT CLK
DCP OUT
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J6
J5
J7
J3
J4
J8
J9
Analog input for CH1
Analog input for CH2
Positive and negative supply (+B / -B)
Output for CH1
Output for CH2
External clock sync
DC protection relay output
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Test Procedures
1. Connect 4Ω, 250W load to both output connectors, J3 and J4 and Audio Precision
analyzer (AP).
2. Connect Audio Signal Generator to J6 and J5 for CH1 and CH2 respectively (AP).
3. Connect a dual power supply to J7, pre-adjusted to ±35V, as shown in Figure 2 above.
4. Set switch S3 to middle position (self oscillating).
5. Set volume level knob R108 fully counter-clockwise (minimum volume).
6. Turn on the power supply. Note: always apply or remove the ±35V at the same time.
7. Orange LED (Protection) should turn on almost immediately and turn off after about 3s.
8. Green LED (Normal) then turns on after orange LED is extinguished and should stay on.
9. One second after the green LED turns on; the two blue LEDS on the Daughter Board
should turn on and stay on for each channel, indicating that a PWM signal is present at
LO
10. With an Oscilloscope, monitor switching waveform at test points TP1 and TP2 of CH1
and CH2 on Daughter Board.
11. If necessary, adjust the self-oscillating switching frequency of AUDAMP5 to 400KHz
±5kHz using potentiometer R29P. For IRAUDAMP5, the self-oscillating switching
frequency is pre-calibrated to 400KHz. To modify the AUDAMP5 frequency, change the
values of potentiometers R21 and R22 for CH1 and CH2 respectively.
12. Quiescent current for the positive supply should be 70mA ±10mA at +35V.
13. Quiescent current for the negative supply should be 100mA ±10mA at –35V.
14. Push S1 switch, (Trip and Reset push-button) to restart the sequence of LEDs indicators,
which should be the same as noted above in steps 6-9.
Audio Tests:
15. Apply 1 V RMS at 1KHz from the Audio Signal Generator
16. Turn control volume up (R108 clock-wise) to obtain an output reading of 100Watts for
all subsequent tests as shown on the Audio Precision graphs below, where measurements
are across J3 and J2 with an AES-17 Filter
Typical Performance
The tests below were performed under the following conditions:
±B supply = ±35V, load impedance = 4Ω resistive load, 1kHz audio signal,
Self oscillator @ 400kHz and internal volume-control set to give required output with 1Vrms
input signal, with AES-17 Filter, unless otherwise noted.
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IRAUDAMP5 REV 3.0
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THD versus Power:
10
5
2
1
0.5
0.2
0.1
%
0.05
0.02
0.01
0.005
0.002
0.001
100m
200m
500m
1
2
5
10
20
50
100
200
W
Blue, CH1 - 4 Ohm
Red, CH2 - 4 Ohm
Figure 18. Total Harmonics Distortion + Noise (THD+N) versus power output
Fig 3
+4
+3
+2
+1
-0
-1
d
B
r
A
-2
-3
-4
-5
-6
-7
-8
-9
-10
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k 200k
Hz
Frequency Response:
Red
Blue
CH1 - 4 Ohm, 2V Output
CH1 - 8 Ohm, 2V Output
Frequency Characteristics vs. Load Impedance
Fig 4
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IRAUDAMP5 REV 3.0
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.
THD versus Frequency:
100
50
10
5
1
0.1
0.05
%
0.01
0.001
0.0005
0.0001
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Pink
Blue
Cyan
Green
CH1, 1W Output
CH1, 10W Output
CH1, 50W Output
CH1, 100W Output
THD+N Ratio vs. Frequency
Fig 5
.
Frequency Spectrum :
+0
-10
-20
-30
-40
d
B
V
-50
-60
-70
-80
-90
-100
-110
10
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Red
Blue
CH1, 1V, 1kHz, Self Oscillator @ 400kHz
CH2, 1V, 1kHz, Self Oscillator @ 400kHz
Fig 6
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Frequency Spectrum
IRAUDAMP5 REV 3.0
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.
Floor Noise:
+20
+0
-20
-40
d
B
V
-60
-80
-100
-120
-140
10
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Red
Blue
CH1 - ACD, No signal, Self Oscillator @ 400kHz
CH2 - ACD, No signal, Self Oscillator @ 400kHz
Fig 7 Residual Noise (ACD)
.
Channel Separation:
+0
-10
-20
-30
-40
-50
d
B
-60
-70
-80
-90
-100
-110
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Red
Blue
CH1 – CH2, 60W
CH2 – CH1, 60W
Fig 8 Channel Separation vs. Frequency
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IRAUDAMP5 REV 3.0
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.
Clipping Characteristics:
Red Trace: Total Distortion + Noise Voltage
Green Trace: Output Voltage
60W / 4Ω, 1kHz, THD+N=0.008%
174W / 4Ω, 1kHz, THD+N=10%
Measured Output and Distortion Waveforms
Fig 9
.
IRAUDAMP5 Theory of Operation
Referring to Fig 10 below, the input error amplifier of the IRS2092S forms a front-end secondorder integrator with C1, C21, C23 and R21. This integrator also receives a rectangular feedback
waveform from R31, R33 and C17 into the summing node at IN- from the Class D power stage
switching node (connection of DirectFET Q3 and DirectFET Q4). The quadratic oscillatory
waveform of the switch node serves as a powered carrier signal from which the audio is
recovered at the speaker load through a single-stage LC filter. The modulated signal is created by
the fluctuations of the analog input signal at R13 that shifts the average value of this quadratic
waveform through the gain relationship between R13 and R31 + R33 so that the duty cycle varies
according to the instantaneous signal level of the analog input signal at R13.
R33 and C17 act to immunize the rectangular waveform from possible narrow noise spikes that
may be created by parasitic impedances on the power output stage. The IRS2092S input
integrator then processes the signal from the summing node to create the required triangle wave
amplitude at the COMP output. The triangle wave then is converted to Pulse Width Modulation,
or PWM, signals that are internally level-shifted Down and Up to the negative and positive
supply rails. The level shifted PWM signals are called LO for low output, and HO for high
output, and have opposite polarity. A programmable amount of dead time is added between the
gate signals to avoid cross conduction between the power MOSFETs. The IRS2092S drives two
IRF6645 DirectFET MOSFETs in the power stage to provide the amplified PWM waveform. The
amplified analog output is reconstructed by demodulating the powered PWM at the switch node,
called VS. (Show as VS on the schematic)This is done by means of the LC low-pass filter (LPF)
formed by L1 and C23A, which filters out the Class D switching carrier signal, leaving the audio
powered output at the speaker load. A single stage output filter can be used with switching
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IRAUDAMP5 REV 3.0
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frequencies of 400 kHz and greater; lower switching frequencies may require additional filter
components.
+VCC is referenced to –B and provides the supply voltage to the LO gate driver. D6 and C5 form
a bootstrap supply that provides a floating voltage to the HO gate driver. The VAA and VSS
input supplies are derived from +B and -B via R52 and C18, and R50 and C12, respectively.
Thus, a fully functional Class D PWM amplifier plus driver circuit is realized in an SO16
package with just a few small components.
.
R33
C17
R31
R52
+B
C18
0V
IRS2092S
DirectFet
VB
R32
HO
IN-
Modulator
and
Shift level
-
.
+
GND
VS
VCC
IRF6645
LP Filter
0V
L1
R30
LO
Integrator
0V
Q3
C5
R13
COMP
D6
INPUT
R21
0V
C23
C1
C21
+VAA
Q4
C23A
.
IRF6645
DirectFet
COM
C3
-VSS
+VCC
C12
-B
R50
.
Simplified Block Diagram of IRAUDAMP5 Class D Amplifier
Fig 10
System overview
IRS2092S Gate Driver IC
The IRAUDAMP5 uses the IRS2092S, a high-voltage (up to 200V), high-speed power MOSFET
PWM generator and gate driver with internal dead-time and protection functions specifically
designed for Class D audio amplifier applications. These functions include OCP and UVP. Bidirectional current protection for both the high-side and low-side MOSFETs are internal to the
IRS2092S, and the trip levels for both MOSFETs can be set independently. In this design, the
dead time can be selected for optimized performance by minimizing dead time while preventing
shoot-through. As a result, there is no gate-timing adjustment on the board. Selectable dead time
through the DT pin voltage is an easy and reliable function which requires only two external
resistors, R11 and R9 as shown on Fig11 below.
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IRAUDAMP5 REV 3.0
Page 10 of 49
.
+B
CSH
VAA
HO
.
LO
VREF
COM
CSLO
DT
R13
VSS
R19
VS
VCC
CSD
R18
CH1
VB
INCOMP
AUDIO_INPUT
Feedback
.
GND
IRS2092S
+VCC
R5
-B
.
System-level View of Class D Controller and Gate Driver IRS2092S
Fig 11
Selectable Dead-Time
The dead time of the IRS2092S is based on the voltage applied to the DT pin. (Fig 12) An
internal comparator determines the programmed dead time by comparing the voltage at the DT
pin with internal reference voltages. An internal resistive voltage divider based on different ratios
of VCC negates the need for a precise reference voltage and sets threshold voltages for each of
the four programmable settings. Shown in the table below are component values for
programmable dead times between 15 and 45 ns. To avoid drift from the input bias current of the
DT pin, a bias current of greater than 0.5mA is suggested for the external resistor divider circuit.
Resistors with up to 5% tolerance can be used.
Selectable Dead-Time
Dead-time mode
DT1
DT2
DT3
DT4
Dead time
~15ns
~25ns
~35ns
~45ns
R5
3.3k
5.6k
8.2k
open
R13
8.2k
4.7k
3.3k
<10k
DT voltage
0.71 x Vcc
0.46 x Vcc
0.29 x Vcc
0 x Vcc
Default
Operational Mode
Default
15nS
25nS
Dead-time
35nS
45nS
Shutdown
0.23xVcc
0.36xVcc
0.57xVcc
0.89xVcc Vcc
VDT
Fig 12 Dead-time Settings vs. VDT Voltage
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IRAUDAMP5 REV 3.0
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Over-Current Protection (OCP)
In the IRAUDAMP5, the IRS2092S gate driver accomplishes OCP internally, a feature discussed
in greater detail in the “Protection” section.
Offset Null (DC Offset)
The IRAUDAMP5 is designed such that no output-offset nullification is required, thanks to
closed loop operation. DC offsets are tested to be less than ±20mV.
Protection
The IRAUDAMP5 has a number of protection circuits to safeguard the system and speaker as
shown in the figure 13 below, which fall into one of two categories – internal faults and external
faults, distinguished by the manner in which a fault condition is treated. Internal faults are only
relevant to the particular channel, while external faults affect the whole board. For internal faults,
only the offending channel is stopped. The channel will hiccup until the fault is cleared. For
external faults, the whole board is stopped using the shutdown sequencing described earlier. In
this case, the system will also hiccup until the fault is cleared, at which time it will restart
according to the startup sequencing described earlier.
.
CSH
D1
R43
+B
VB
1.2V
R25
+
R41
BAV19
Q3
R32
HO
IRF6645
10R
LP Filter
.
CSD
VS
.
CSD
OCSET
VCC
OCREF
5.1V
D4
OCREF
Green
Yellow
LEDs
Q4
R30
LO
IRF6645
10R
R19
R18
OCSET
Trip
RESET
-B
COM
UVP
OVP
OTP
DCP
To next channel
Functional Block Diagram of Protection Circuit Implementation
Fig 13
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IRAUDAMP5 REV 3.0
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Internal Faults
OCP and OTP are considered internal faults, which will only shutdown the particular channel by
pulling low the relevant CSD pin. The channel will shutdown for about one-half a second and
will hiccup until the fault is cleared.
Over-Temperature Protection (OTP, Fig 14)
A separate PTC resistor is placed in close proximity to the high-side IRF6645 DirectFET
MOSFET for each of the amplifier channels. If the resistor temperature rises above 100°C, the
OTP is activated. The OTP protection will only shutdown the relevant channel by pulling the
CSD pin low and will recover once the temperature at the PTC has dropped sufficiently. This
temperature protection limit yields a PCB temperature at the MOSFET of about 100°C, which is
limited by the PCB material and not by the operating range of the MOSFET.
Rp1 is thermally connected with Q3
Rp1
100K
100C
Q7
C28
47nF
OTP1
-B
R47
R48
100K
1K
Q3
2
2
3
3
1
-B
R31
IRF6645
OTP CH1
Fig 14
Over-Current Protection (OCP)
The OCP internal to the IRS2092S shuts down the IC if an OCP is sensed in either of the output
MOSFETs. For a complete description of the OCP circuitry, please refer to the IRS2092S
datasheet. Here is a brief description:
Low-Side Current Sensing
Fig 15 shows the low side MOSFET as is protected from an overload condition by measuring the
low side MOSFET drain-to-source voltage during the low side MOSFET on state, and will shut
down the switching operation if the load current exceeds a preset trip level. The voltage setting on
the OCSET pin programs the threshold for low-side over-current sensing. Thus, if the VS voltage
during low-side conduction is higher than the OCSET voltage, the IRS2092S will trip and CSD
goes down. It is recommended to use VREF to supply a reference voltage to a resistive divider
(R19 and R18 for CH1) to generate a voltage to OCSET; this gives better variability against VCC
fluctuations. For IRAUDAMP5, the low-side over-current trip level is set to 0.65V. For IRF6645
DirectFET MOSFETs with a nominal RDS-ON of 28mOhms at 25°C, this results in a ~23A
maximum trip level. Since the RDS-ON is a function of temperature, the trip level is reduced to
~15A at 100°C.
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IRAUDAMP5 REV 3.0
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.
CSH
D1
R43
+B
VB
1.2V
R25
+
R41
BAV19
R32
HO
10R
Q3
IRF6645
LP Filter
.
VS
CSD
.
CSD
OCSET
VCC
OCREF
5.1V
OCREF
R19
LO
R30
10R
R18
Q4
IRF6645
-B
OCSET
COM
Simplified Functional Block Diagram of High-Side and Low-Side Current Sensing (CH1)
Fig 15
High-Side Current Sensing (Fig15)
The high-side MOSFET is protected from an overload condition and will shutdown the switching
operation if the load current exceeds a preset trip level. High-side over-current sensing monitors
detect an overload condition by measuring the high side MOSFET’s drain-to-source voltage
(VDS) through the CSH and VS pins. The CSH pin detects the drain voltage with reference to the
VS pin, which is the source of the high-side MOSFET. In contrast to the low-side current sensing,
the threshold of CSH pin to engage OC protection is internally fixed at 1.2V. An external
resistive divider R43+R25 and R41 (for Ch1) can be used to program a higher threshold. An
additional external reverse blocking diode (D1 for CH1) is required to block high voltage feeding
into the CSH pin during low-side conduction. By subtracting a forward voltage drop of 0.6V at
D1, the minimum threshold which can be set for the high-side is 0.6V across the drain-to-source.
For IRAUDAMP5, the high-side over-current trip level is set to 0.6V across the high-side
MOSFET. For the IRF6645 MOSFETs with a nominal RDS-ON of 28 mOhms at 25°C, this results
in a ~21A maximum trip level. Since the RDS-ON is a function of temperature, the trip level is
reduced to ~14A at 100°C.
For a complete description of calculating and designing the over-current trip limits, please refer to
the IRS2092S datasheet.
Positive and Negative Side of Short Circuit, versus switching output shut down:
The plots below show the speed that the IRS2092S responds to a short circuit condition. Notice
that the envelope behind the sine wave output is actually the switching frequency ripple. Bus
pumping naturally affects this topology.
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IRAUDAMP5 REV 3.0
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Positive and Negative side of Short Circuit, versus switching output shut down:
CSD pin
CSD pin
VS pin
VS pin
Load current
CSD pin
Load
current
CSD
pin
VS pin
VS pin
Load current
Load current
OCP Waveforms Showing Load Current and Switch Node Voltage (VS)
Fig 16
.
Short Circuit Response:
CSD pin
CSD pin
VS pin
VS pin
Load current
Load current
OCP Waveforms Showing CSD Trip and Hiccup
Fig 17
External Faults
OVP, UVP and DCP are considered external faults. In the event that any external fault condition
is detected, the shutdown circuit will disable the output for about three seconds, during which
time the orange AUDAMP5 “Protection” LED will turn on. If the fault condition has not cleared,
the protection circuit will hiccup until the fault is removed. Once the fault is cleared, the green
“Normal” LED will turn on. There is no manual reset option.
Over-Voltage Protection (OVP Fig 18)
OVP will shut down the amplifier if the bus voltage between GND and -B exceeds 40V. The
threshold is determined by the voltage sum of the Zener diode Z105, R140, and VBE of Q109. As
a result, it protects the board from hazardous bus pumping at very low audio signal frequencies
by shutting down the amplifier. OVP will automatically reset after three seconds. Since the +B
and –B supplies are assumed to be symmetrical (bus pumping, although asymmetrical in time,
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IRAUDAMP5 REV 3.0
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will pump the bus symmetrically in voltage level over a complete audio frequency cycle), it is
sufficient to sense only one of the two supply voltages for OVP. It is therefore up to the user to
ensure that the power supplies are symmetrical.
SD
Q109 Over-Voltage Protection (OVP)
R139
D105
R140
10k
47k
OT
Z107
18V
R149
47K
Z105
R145
47K
39V
1N4148
OT
DCP
R144
UVP
10k
Q109
Q110
MMBT5551
R141
47k
MMBT5551
-B
R146
47K
S1
SW-PB
C119
0.1uF, 50V
Trip and restart
OVP
Q110 Under-Voltage Protection (UVP)
Fig 18
Under-Voltage Protection (UVP, Fig18)
UVP will shutdown the amplifier if the bus voltage between GND and -B falls below 20V. The
threshold is determined by the voltage sum of the Zener diode Z107, R145 and VBE of Q110. As
with OVP, UVP will automatically reset after three seconds, and only one of the two supply
voltages needs to be monitored.
Speaker DC-Voltage Protection (DCP, Fig 19)
DCP is provided to protect against DC current flowing into the speakers. This abnormal condition
is rare and is likely caused when the power amplifier fails and one of the high-side or low-side
IRF6645 DirectFET MOSFETs remain in the ON state. DCP is activated if either of the outputs
has more than ±4V DC offset (typical). Under this fault condition, it is normally required to
shutdown the feeding power supplies. Since these are external to the reference design board, an
isolated relay P1 is provided for further systematic evaluation of DC-voltage protection. This
condition is transmitted to the power supply controller through connector J9, whose pins are
shorted during a fault condition.
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IRAUDAMP5 REV 3.0
Page 16 of 49
+B
R125
10K
Q106
R126
100K
MMBT5401
Q105
MMBT5551
R130
47K
To DCP
DC protection
DCP
R131
47K
R128
6.8k
R124
10k
Q104
C116
100uF, 16V
R123
R122
1K
47k
MMBT5401
R129
6.8k
R121
R127
6.8k
47k
From CH1 Output
CH1 O
CH2 O
From CH2 Output
-B
Fig 19
Efficiency
Figs 20 demonstrate that IRAUDAM5 is highly efficient, due to two main factors:
a.) DirectFETs offer low RDS(ON) and very low input capacitance, and b). The PWM operates as
Pulse Density Modulation.
100.0%
90.0%
Power Stage Efficiency (%)
80.0%
70.0%
60.0%
50.0%
40.0%
30.0%
20.0%
10.0%
0.0%
0
20
40
60
80
100
120
140
160
180
Output Power (W)
Efficiency vs. Output Power, 4Ω Single Channel Driven, ±B supply = ±35V, 1kHz Audio Signal
Fig20
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IRAUDAMP5 REV 3.0
Page 17 of 49
Thermal Considerations
The daughter-board design can handle one-eighth of the continuous rated power, which is
generally considered to be a normal operating condition for safety standards. Without the addition
of a heatsink or forced air-cooling, the daughter board cannot handle fully rated continuous
power. A thermal image of the daughter board is as shown in Fig 21 below.
Thermal Distribution
67°C
54°C
67°C
54°C
Thermal image of Daughter-Voard
Two-Channel x 1/8th Rated Power (15W) in Operation, TC = 54°C at Steady State
±B supply = ±35V, 4Ω Load, 1kHz audio signal, Temp ambient = 25°C
Fig 21
Click and POP noise:
One of the most important aspects of any audio amplifier is the startup and shutdown procedures.
Typically, transients occurring during these intervals can result in audible pop- or click-noise
from the output speaker. Traditionally, these transients have been kept away from the speaker
through the use of a series relay that connects the speaker to the audio amplifier only after the
startup transients have passed and disconnects the speaker prior to shutting down the amplifier.
Thanks to the click and pop elimination function in the IRS2092S, IRAUDAMP5 does not use
any series relay to disconnect the speaker from the audible transient noise.
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IRAUDAMP5 REV 3.0
Page 18 of 49
Click-Noise Reduction Circuit (Solid-State Shunt)
IRS2092S controller is relatively quiet with respect to class AB, but for additional click or POP
noise reduction you may add a shunt circuit that further attenuates click or pop transients during
turn on sequencing. The circuit is not populated on the present demo board; for implementation
details, please refer to the IRAUDAMP4 user’s manual at http://www.irf.com/technicalinfo/refdesigns/audiokits.html
Startup and Shutdown Sequencing (Fig 22)
The IRAUDAMP5 sequencing is achieved through the charging and discharging of the CStart
capacitor C117. Along with the charging and discharging of the CSD voltage (C10 on daughter
board for CH1) of the IRS2092S, this is all that is required for complete sequencing. The startup
and shutdown timing diagrams are show in Figure 22A below:
CStart Ref2
CStart Ref1
CStart Ref1
CStart Ref2
CSD= 2/3VDD
CSD
CStart
Time
External trip
Reset
CHx_O
SP MUTE
Audio MUTE
Music shutdown
Class D shutdown
Class D startup
Music startup
Click Noise Reduction Sequencing at Trip and Reset
Fig 22A
For startup sequencing, the control power supplies start up at different intervals depending on the
±B supplies. As the +/-B supplies reach +5 volts and -5 volts respectively, the +/-5V control
supplies for the analog input start charging. Once +B reaches ~16V, VCC charges. Once –B
reaches -20V, the UVP is released and CSD and CStart (C117) start charging. The Class D
amplifier is now operational, but the preamp output remains muted until CStart reaches Ref2. At
this point, normal operation begins. The entire process takes less than three seconds.
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IRAUDAMP5 REV 3.0
Page 19 of 49
For Shutdown (Fig22B) sequencing is initiated once UVP is activated. As long as the supplies do
not discharge too quickly, the shutdown sequence can be completed before the IRS2092S trips
UVP. Once UVP is activated, CSD and CStart are discharged at different rates. In this case,
threshold Ref2 is reached first and the preamp audio output is muted. It is then possible to
shutdown the Class D stage (CSD reaches two-thirds VDD). This process takes less than 200ms.
+B
CStart Ref2
CStart Ref1
CSD= 2/3VDD
CSD
CStart
+5V
Time
-5V
Vcc
-B
[email protected]
CHx_O
SP MUTE
Audio MUTE
Class D shutdown
Music shutdown
Conceptual Shutdown Sequencing of Power Supplies and Audio Section Timing
Fig22B
For any external fault condition (OTP, OVP, UVP or DCP – see “Protection”) that does not lead
to power supply shutdown, the system will trip in a similar manner as described above. Once the
fault is cleared, the system will reset (similar sequence as startup).
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IRAUDAMP5 REV 3.0
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Power Supplies
The IRAUDAMP5 has all the necessary housekeeping power supplies onboard and only requires
a pair of symmetric power supplies ranging from ±25V to ±35V (+B, GND, -B) for operation.
The internally-generated housekeeping power supplies include a ±5V supply for analog signal
processing (preamp etc.), while a +12V supply (VCC), referenced to –B, is included to supply the
low and high side Class D gate-driver stages.
For the externally-applied power, a regulated power supply is preferable for performance
measurements, but is not always necessary. The bus capacitors, C31 and C32 on the motherboard,
along with high-frequency bypass-caps C14, C15; C32 and C33 on the daughter board, address
the high-frequency ripple current that results from switching action. In designs involving
unregulated power supplies, the designer should place a set of external bus capacitors having
enough capacitance to handle the audio-ripple current. Overall regulation and output voltage
ripple for the power supply design are not critical when using the IRAUDAMP5 Class D
amplifier as the power supply rejection ratio (PSRR) of the IRAUDAMP5 is excellent, as shown
on Figure 23 below.
Power Supply Rejection Ratio
Green: IRAUDAMP5, Cyan: VAA/VSS are fed by Vbus
Fig 23
Bus Pumping (Fig24)
Since the IRAUDAMP5 is a half-bridge configuration, bus pumping does occur. Under normal
operation during the first half of the cycle, energy flows from one supply through the load and
into the other supply, thus causing a voltage imbalance by pumping up the bus voltage of the
receiving power supply. In the second half of the cycle, this condition is reversed, resulting in
bus pumping of the other supply.
These conditions worsen bus pumping:
1. Lower frequencies (bus-pumping duration is longer per half cycle)
2. Higher power output voltage and/or lower load impedance (more energy transfers
between supplies)
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IRAUDAMP5 REV 3.0
Page 21 of 49
3. Smaller bus capacitors (the same energy will cause a larger voltage increase)
The IRAUDAMP5 has protection features that will shut down the switching operation if the bus
voltage becomes too high (>40V) or too low (<20V). One of the easiest countermeasures is to
drive both of the channels in a stereo configuration out of phase so that one channel consumes the
energy flow from the other and does not return it to the power supply. Bus voltage detection is
only done on the –B supply, as the effect of the bus pumping on the supplies is assumed to be
symmetrical in amplitude (although opposite in phase) with the +B supply.
Bus Pumping Figure:
Cyan = Positive Rail voltage (+B)
Green = Speaker Output
Pink = Negative Rail voltage (-B)
Fig 24
Input Signal
A proper input signal is an analog signal below 20 kHz, up to ±3.5V peak, having a source
impedance of less than 600 ohms. A 30-60 kHz input signal can cause LC resonance in the output
LPF, resulting in an abnormally large amount of reactive current flowing through the switching
stage (especially at 8 ohms or higher impedance towards open load), and causing OCP activation.
The IRAUDAMP5 has an RC network (Fig25), or Zobel network (R47 and C25 [CH1]), to
dampen the resonance and protect the board in such an event, but is not thermally rated to handle
continuous supersonic frequencies. These supersonic input frequencies therefore should be
avoided. Separate mono RCA connectors provide input to each of the two channels. Although
both channels share a common ground, it is necessary to connect each channel separately to limit
noise and crosstalk between channels.
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IRAUDAMP5 REV 3.0
Page 22 of 49
.
LP Filter
0V
L1
C23A
0V
.
R47
.
C25
.
Zobel Filter and Output filter demodulator
Fig 25
Output
Both outputs for the IRAUDAMP5 are single-ended and therefore have terminals labeled (+) and
(-), with the (-) terminal connected to power ground. Each channel is optimized for a 4-Ohm
speaker load for a maximum output power (120W), but is capable of operating with higher load
impedances (at reduced power), at which point the frequency response will have a small peak at
the corner frequency of the output LC low pass filter. The IRAUDAMP5 is stable with
capacitive-loading; however, it should be noted that the frequency response degrades with heavy
capacitive loading of more than 0.1µF.
Gain Setting / Volume Control
The IRAUDAMP5 has an internal volume control (potentiometer R108 labeled, ”VOLUME”, Fig
26) for gain adjustment. Gain settings for both channels are tracked and controlled by the volume
control IC (U_2), setting the gain from the microcontroller IC (U_1). The maximum volume
setting (clockwise rotation) corresponds to a total gain of +37.9dB (78.8V/V). The total gain is a
product of the power-stage gain, which is constant (+23.2dB), and the input-stage gain that is
directly-controlled by the volume adjustment. The volume range is about 100dB, with minimum
volume setting to mute the system with an overall gain of less than -60dB. For best performance
in testing, the internal volume control should be set to a gain of 21.9V/V, such that 1Vrms input
will result in rated output power (120W into 4Ω), allowing for a >11dB overdrive.
+5V
C109
+5V
R108
CT2265-ND
C107
4.7uF, 16V
8
7
6
C108
10nF, 50V
5
VSS
VDD
VR0
CS
VR1
SDATA
CLK
Audio in
4.7uF, 16V
U_2
U_1
1
ZCEN
R7
2 CS
4
SIMUL
47R
CS
3 SDATAI
R8
SDATAI AOUTL
C1
10uF, 50V
SCLK R10
47R
MUTE
100R
Level OUT 1
100K
R1
10R
+5V
3310S06S
J5
R3
AGNDL
47R
R9
Control Volume
AINL
R11
47R
VD+
VA-
-5V
DGRD
VA+
+5V
SCLK
AOUTR
Level OUT 2
R2
SDATAOAGNDR
MUTE
CS3310
AINR
R4
100R
100K
J6
Audio in
Fig 26 Digital volume Control
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IRAUDAMP5 REV 3.0
Page 23 of 49
Bridged Output
The IRAUDAMP5 is not intended for a bridge-tied-load, or BTL configuration. However, BTL
operation can be achieved by feeding out-of-phase audio input signals to the two input channels
as shown in the figure 27 below. In BTL operation, minimum load impedance is 8 Ohms and
rated power is 240W non-clipping. The installed clamping diodes D5 – D8 are required for BTL
operation, since reactive energy flowing from one output to the other during clipping can force
the output voltage beyond the voltage supply rails if not clamped.
.
R33
C17
R31
+VAA
+B
COMP
C1
R13
INPUT
HO
INCH1
GND
Modulator
and
Shift level
+
+B
VS
L1
VCC
10k 1%
LO
.
10k 1%
COM
R34
Q4
-B
IRF6645
-B
.
C18
1
IRF6645
LP Filter
Integrator
R32
0V
Q3
D5
.
VB
IRS2092S
D7
C23
R21
C21
+VAA
+B
COMP
VB
IRS2092S
HO
R14
INCH2
GND
IRF6645
+B
LP Filter
+
Modulator
and
Shift level
D6
.
0V
Q6
VS
L2
VCC
Integrator
LO
COM
Q5
D8
C24
C2
C22
-B
IRF6645
-B
Bridged configuration
Fig 27
Output Filter Design, Preamplifier and Performance
The audio performance of IRAUDAMP5 depends on a number of different factors. The section
entitled, “Typical Performance” presents performance measurements based on the overall system,
including the preamp and output filter. While the preamp and output filter are not part of the
Class D power stage, they have a significant effect on the overall performance.
Output filter
Since the output filter is not included in the control loop of the IRAUDAMP5, the reference
design cannot compensate for performance deterioration due to the output filter. Therefore, it is
important to understand what characteristics are preferable when designing the output filter:
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IRAUDAMP5 REV 3.0
Page 24 of 49
1) The DC resistance of the inductor should be minimized to 20 mOhms or less.
2) The linearity of the output inductor and capacitor should be high with respect to load
current and voltage.
Preamplifier (Fig 28)
The preamp allows partial gain of the input signal, and controls the volume in the IRAUDAMP5.
The preamp itself will add distortion and noise to the input signal, resulting in a gain through the
Class D output stage and appearing at the output. Even a few micro-volts of noise can add
significantly to the output noise of the overall amplifier.
C5
10uF, 50V
R13
3.3K
Audio in
R55
0.0
R1 J5
1
2
3
4
5
6
7
8
R3
100R
100K
U_?
ZCEN
CS
AINL
AGNDL
SDATAI AOUTL
VD+
VA-
DGRD
VA+
SCLK
AOUTR
SDATAOAGNDR
MUTE
CS3310
AINR
R2
100K
J6
Audio in
R71
OPEN
+5V
16
Feedback
IN-1
R31
CH1 IN
4
5
6
1
2
3
R33
47k 1%
1K
C17
150pF, 500V
OC
-5V
J1A
15
C2
10uF, 50V
R5
14
13
4.7R 4.7R
12
+5V
R6
11
IRS2092S MODULE
-5V
J1B
C3
10uF, 50V
10
9
R4
100R
C6
10uF, 50V
R14
-5V
10
11
12
CH2 IN
3.3K
R72
OPEN
7
8
9
IN-2
VCC
SD
R56
0.0
VCC
Feedback
R32
R34
47k 1%
1K
Preamplifier
Fig28
It is possible to evaluate the performance without the preamp and volume control, by moving
resistors R13 and R14 to R71 and R72, respectively. This effectively bypasses the preamp and
connects the RCA inputs directly to the Class D power stage input. Improving the selection of
preamp and/or output filter components will improve the overall system performance,
approaching that of the stand-alone Class D power stage. In the “Typical Performance” section,
only limited data for the stand-alone Class D power stage is given. For example, Fig 20 below
shows the results for THD+N vs. Output Power are provided, utilizing a range of different
inductors. By changing the inductor and repeating this test, a designer can quickly evaluate a
particular inductor.
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IRAUDAMP5 REV 3.0
Page 25 of 49
I
IRAUDAMP5 can be used as output inductors evaluation tool
100
TTTTTTT
10
1
%
0.1
0.01
0.001
0.0001
100m
200m
500m
1
2
5
10
20
50
100
200
W
Results of THD+N vs. Output Power with Different Output Inductors
Fig 29
Self-Oscillating PWM Modulator
The IRAUDAMP5 Class D audio power amplifier features a self-oscillating type PWM
modulator for the lowest component count, highest performance and robust design. This topology
represents an analog version of a second-order sigma-delta modulation having a Class D
switching stage inside the loop. The benefit of the sigma-delta modulation, in comparison to the
carrier-signal based modulation, is that all the error in the audible frequency range is shifted to
the inaudible upper-frequency range by nature of its operation. Also, sigma-delta modulation
allows a designer to apply a sufficient amount of correction.
The self-oscillating frequency (Fig 30) is determined by the total delay time inside the control
loop of the system. The delay of the logic circuits, the IRS2092S gate-driver propagation delay,
the IRF6645 switching speed, the time-constant of front-end integrator (e.g.R13, R33, R31, R21,
P1, C17, C21, C23 and C1 for CH1) and variations in the supply voltages are critical factors of
the self-oscillating frequency. Under nominal conditions, the switching-frequency is around
400kHz with no audio input signal and a +/-35V supply.
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IRAUDAMP5 REV 3.0
Page 26 of 49
.
R33
P1
C17
R31
+B
R21
C23
COMP
IRS2092S
. INPUT
R13
0V
Q3
IRF6645
LP Filter
INCH1
VB
HO
C1
C21
-
GND
+
Modulator
and
Shift level
Integrator
VS
.
VCC
LO
Q4
IRF6645
COM
-B
Self Oscillating determined components
Fig 30
Adjustments of Self-Oscillating Frequency
The PWM switching frequency in this type of self-oscillating switching scheme greatly impacts
the audio performance, both in absolute frequency and frequency relative to the other channels. In
absolute terms, at higher frequencies distortion due to switching-time becomes significant, while
at lower frequencies, the bandwidth of the amplifier suffers. In relative terms, interference
between channels is most significant if the relative frequency difference is within the audible
range. Normally, when adjusting the self-oscillating frequency of the different channels, it is best
to either match the frequencies accurately, or have them separated by at least 25kHz. With the
installed components, it is possible to change the self-oscillating frequency from about 300kHz
up to 450kHz, as shown on Fig 30
Switches and Indicators
There are four different indicators on the reference design as shown in the figure 31 below:
1. An orange LED, signifying a fault / shutdown condition when lit.
2. A green LED on the motherboard, signifying conditions are normal and no fault
condition is present.
3. A blue LED on the daughter board module, signifying there are HO pulses for CH1
4. A blue LED on the daughter board module signifying there are HO pulses for CH2
There are three switches on the reference design:
1. Switch S1 is a trip and reset push-button. Pushing this button has the same effect as a
fault condition. The circuit will restart about three seconds after the shutdown button is
released.
2. Switch S2 is an internal clock-sync frequency selector. This feature allows the designer
to modify the switching frequency in order to avoid AM radio interference. With S3 set
to INT, the two settings “H” and “L” will modify the internal clock frequency by about
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IRAUDAMP5 REV 3.0
Page 27 of 49
20 kHz to 40 kHz, either higher “H” or lower “L.” The actual internal frequency is set
by potentiometer R113 - “INT FREQ.”
3. Switch S3 is an oscillator selector. This three-position switch is selectable for internal
self oscillator (middle position – “SELF”), or either internal (“INT”) or external
(“EXT”) clock synchronization.
I
E
S
SW-3WAY_A-B
S3A
SW
S2
R109
1K
D103
C110
R110
100k
C112
1200pF, 50V
100pF, 50V
C111
1N4148
1nF, 50V
1
2
SW_H-L
R111
10K
+5V
R120
100R
R112
820R
U_3
1A
VCC
1Y
6A
2A
6Y
2Y
5A
3A
5Y
3Y
4A
GND
4Y
Q103
C113
MMBT5551
100pF, 50V
R113
5K POT
S
E
I
SW-3WAY_A-B
S3B SW
R116
47R
R114
100R
C114
10nF, 50V
CLK
CLK
R115
47R
74HC14
+5V
J8
BNC
A24497
R118
1k
EXT. CLK
NORMAL
R119
1k
MUTE
PROTECTION
MUTE R117
47R
LED, Switches and Sync frequencies
Fig 31
Switching Frequency Lock / Synchronization Feature
For single-channel operation, the use of the self-oscillating switching scheme will yield the best
audio performance. The self-oscillating frequency, however, changes with the duty ratio. This
varying frequency can interfere with AM radio broadcasts, where a constant-switching frequency
with its harmonics shifted away from the AM carrier frequency is preferred. In addition to AM
broadcasts, multiple channels can also reduce audio performance at low power, and can lead to
increased residual noise. Clock frequency locking/synchronization can address these unwanted
characteristics.
Please note that the switching frequency lock / synchronization feature is not possible for all
frequencies and duty ratios, and operates within a limited frequency and duty-ratio range around
the self-oscillating frequency (Figure 32 below).
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IRAUDAMP5 REV 3.0
Page 28 of 49
600
Suggested clock frequency
for maximum locking range
Locking range
Operating Frequency (kHz)
500
Self-oscillating frequency
400
300
200
Self-oscillating frequency
100
0
10%
20%
30%
40%
50%
60%
70%
80%
90%
Duty Cycle
Typical Lock Frequency Range vs. PWM Duty Ratio
(Self-oscillating frequency set to 400 kHz with no input)
Fig 32
The output power range, for which frequency-locking is successful, depends on what the locking
frequency is with respect to the self-oscillating frequency. As illustrated in Figure 33, the locking
frequency is lowered (from 450kHz to 400kHz to 350kHz and then 300kHz) as the output power
range (where locking is achieved) is extended. Once locking is lost, however, the audio
performance degrades, but the increase in THD seems independent from the clock frequency.
Therefore, a 300 kHz clock frequency is recommended, as shown on Fig 34
It is possible to improve the THD performance by increasing the corner frequency of the high
pass filter (HPF) (R17 and C15 for Ch1 Fig 33) that is used to inject the clock signal, as shown in
Figure 33 below.
This drop in THD, however, comes at the cost of reducing the locking range. Resistor values of
up to 100 kOhms and capacitor values down to 10pF may be used.
.
+VAA
+B
C15
SYNC
0V
.
33pF
INPUT
R22
COMP
IRS2092S
VB
HO
22k
R13
INCH1
GND
0V
Q3
IRF6645
LP Filter
+
Modulator
and
Shift level
Integrator
VS
VCC
LO
COM
.
Q4
IRF6645
-B
Switching Frequency Lock / Synchronization Feature
Fig 33
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IRAUDAMP5 REV 3.0
Page 29 of 49
In IRAUDAMP5, this switching frequency lock/synchronization feature (Fig 31 and Fig 33) is
achieved with either an internal or external clock input (selectable through S3). If an internal
(INT) clock is selected, an internally-generated clock signal is used, adjusted by setting
potentiometer R113 “INT FREQ.” If external (EXT) clock signal is selected, a 0-5V squarewave (~50% duty ratio) logic signal must be applied to BNC connector J17.
10
5
2
1
0.5
0.2
%
0.1
0.05
0.02
0.01
0.005
0.002
0.001
100m
200m
500m
1
2
5
10
20
50
100
200
W
Red
Pink
Blue
Cyan
CH1, = Self Oscillator @ 400kHz
CH1, = Sync Oscillator @ 400kHz
CH1, = Sync Oscillator @ 450kHz
CH1, = Sync Oscillator @ 350kHz
THD+N Ratio vs. Output Power for Different Switching Frequency Lock/Synchronization Conditions
Fig 34
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IRAUDAMP5 REV 3.0
Page 30 of 49
OC
SD
4
5
6
VSS
D4
R7
R1
IN-1
10R
10R
100R
R3
A26568-ND
1
2
3
www.irf.com
.
VSS
J1A
GND1
VAA
-5V
3.01k
VAA
R46
10nF
C30
+5V
CH1
10uF
P1
R50
open
C23
R17
1.2k
8.2k
R19
1nF
C1
Audio Gnd 1
1nF,250V
1K
8
7
6
5
4
3
2
1
-35V Bus
IRS2092S
OCSET
VREF
VSS
CSD
COMP
IN-
GND
VAA
U1
IRAUDAMP5 REV 3.0
3.3uF
C12
C10
C21
1nF,250V
SD
1k
R21
3.3uF
C18
R52
open
DT
COM
LO
VCC
VS
HO
VB
CSH
+35V Bus
9
10
11
12
13
14
15
16
VCC
D1
Page 31 of 49
10uF
10R
3.3K
R13
8.2K
R9
R5
4.7R
R26
D6
22uF
10k
C5
0.0
R41
R43
C3
33k
R40
R32
10R
4.7K
R12
R30
10R
R25
10K
OTP1
100K
1
D-FET2
IRF6645
1
D-FET1
IRF6645
-B
R47
100C
100K
Q7
Rp1
R31
2
2
3
3
2
2
DS1
3
3
-B
13
14
15
16
-35V Bus -B
CH1 Output to LPF1
A26570-ND
9
10
11
12
TP1
CH1 O J2A
CH1
C14
0.1uF,100V
C32
0.1uF,100V
+35V Bus +B
Drawing by: M.Rodriguez [email protected]
R37
1R
C17
0.1uF
1K
R48
C28
47nF
Rp1 is thermally connected with Q3
Class D, Daughter Board IRS2092S Module CH1 Schematic
OTP CH1
+B
SD
7
8
9
10
11
12
VSS
D3
CH2
10R
100R
R4
R2
VCC
Q1
SD
-B
-5V
+5V
R36
10K
R34
100K
OTP1
3.01k R53
10R
R8
A26568-ND IN-2
www.irf.com
.
PWM2
VSS
J1B
VAA
OC
10nF,50V
MMBT5551
10uF
R49
open
C24
1
R18
1.2k
8.2k
R20
1nF
C2
8
7
6
5
4
3
Audio Gnd 2 2
1nF,1250V
P2 1K
3.3uF
C19
R51
open
DT
COM
LO
VCC
VS
HO
VB
CSH
+35V Bus
-35V Bus
IRS2092S
OCSET
VREF
VSS
CSD
COMP
IN-
GND
VAA
U2
IRAUDAMP5 REV 3.0
D7
3.3uF
C16
C11
C22
1nF,250V
SD
1k
R22
C29
47nF
R11
100K
OTP2
9
10
11
12
13
14
15
16
VCC
D2
Page 32 of 49
10uF
10R
3.3K
R14
8.2K
R10
R6
4.7R
R23
D5
22uF
10k
C6
0.0
R42
R44
C4
33k
R39
R27
10R
4.7K
R45
R28
10R
R29
10K
100K
R35
1K
1
D-FET4
IRF6645
1
DS2
5
6
7
8
-35V Bus -B
CH2 Output to LPF2
A26570-ND
1
2
3
4
TP2
CH2 O J2B
CH2
C15
0.1uF,100V
C33
0.1uF,100V
+35V Bus +B
-B
Drawing by: M.Rodriguez [email protected]
R38
1R
C13
0.1uF
R24
C9
47nF
Rp2 is thermally connected with Q5
100K
100C
Rp2
R33
D-FET3
IRF6645
-B
MMBT5401
Q2
OTP2
-B
Class D, Daughter Board IRS2092S Module CH2 Schematic
C31
2
2
3
3
2
2
3
3
OTP CH2
www.irf.com
4
5
6
10
11
12
D4
SD
IN-2
CH2
-5V
D3
VAA
10R
OC
10R
100R
R4
R2
3.01k
10nF
C30
+5V
-B
+5V
R36
10K
C29
47nF
10uF
3.3uF
C19
R17
1.2k
8.2k
R19
R49
open
C24
R18
1.2k
8.2k
R20
1nF,1250V
P2 1K
R50
open
C23
1nF,250V
1K
3.3uF
C18
1nF
C2
1nF
C1
8
7
6
5
4
3
2
1
DT
COM
LO
VCC
VS
HO
VB
CSH
9
10
11
12
13
14
15
16
DT
COM
LO
VCC
VS
HO
VB
CSH
+35V Bus
-35V Bus
IRS2092S
OCSET
VREF
VSS
CSD
COMP
IN-
GND
VAA
U2
-35V Bus
IRS2092S
OCSET
VREF
VSS
CSD
COMP
IN-
GND
VAA
U1
R51
open
8
7
6
5
4
3
2
1
R52
open
IRAUDAMP5 REV 3.0
D7
3.3uF
C16
C11
C22
1nF,250V
SD
1k
R22
P1
10uF
R11
100K
OTP2
3.3uF
C12
C10
C21
1nF,250V
SD
1k
R21
R34
100K
OTP1
-5V
Q1
-5V
SD R53
10R
R8
100R
R3
R1
3.01k
VAA
R46
Audio Gnd 1
10R
VCC
IN-1
IR_Logo
VSS
A26568-ND
7
8
9
SD
A26568-ND
1
2
3
J1A
J1B
Audio Gnd 2
VSS
GND2
VSS
OC
VAA
MMBT5551
GND1
R7
CH1
C31
+35V Bus
9
10
11
12
13
14
15
16
VCC
R32
10R
1
100K
R35
DS1
R27
10R
4.7K
R45
R28
1K
1
D-FET4
IRF6645
1
DS2
-35V Bus -B
CH1 Output to LPF1
C9
47nF
5
6
7
8
-35V Bus -B
CH2 Output to LPF2
A26570-ND
1
2
3
4
CH2
TP2
CH2 O J2B
C15
0.1uF,100V
C33
0.1uF,100V
+35V Bus +B
-B
+B
Drawing by: M.Rodriguez [email protected]
R38
1R
C13
0.1uF
R24
100K
100C
Rp2
13
14
15
16
A26570-ND
9
10
11
12
TP1
CH1 O J2A
CH1
C14
0.1uF,100V
C32
0.1uF,100V
+35V Bus +B
Rp2 is thermally connected with Q5
R37
1R
C17
0.1uF
1K
R48
C28
47nF
R33
D-FET3
IRF6645
-B
MMBT5401
Q2
1
D-FET2
IRF6645
10R
R29
10K
100K
R47
D-FET1
IRF6645
-B
OTP2
-B
4.7K
R12
R30
10R
R25
10K
D2
VCC
D1
100C
100K
OTP CH1
Rp1 is thermally connected with Q3
Rp1
R31
MMBT5401DICT-ND
Q7
OTP1
-B
Page 33 of 49
10uF
10R
3.3K
R14
8.2K
R10
R6
4.7R
R23
D5
22uF
10k
C6
0.0
R42
R44
C4
33k
R39
10uF
10R
3.3K
R13
8.2K
R9
R5
4.7R
R26
D6
22uF
10k
C5
0.0
R41
R43
C3
33k
R40
Class D, Daughter Board IRS2092S Module Schematic
10nF,50V
2
2
3
3
2
2
3
3
2
2
3
3
2
2
3
3
OTP CH2
MMBT5401
5
CS
VDD
U_2
SIMUL
SDATA
3310S06S
CLK
VR1
VR0
VSS
+5V
+5V
MUTE
47R
10uF, 50V
47R
R11
SCLK R10
4
Z104
24V
Q102
VCC UVP
15V
C106
10uF, 50V
Q101
FX941
10R
+B
-B
8
7
6
5
4
CLK
C1
3
2
1
CLK
C105
10uF, 50V
VCC
VA-
AOUTR
VA+
AINR
J6
100K
R2
9
10
11
12
13
14
15
16
U4
470
R40
33pF
C16
+5V
R71
OPEN
33pF
C2
10uF, 50V
R5
22k
R18
3.3K
R14
+B
R101
IN-2
-5V
+5V
10
11
12
1
2
3
-5V
C101
47R, 1W
R102
C17
150pF, 500V
1K
R33
CH1 O
VCC
47k 1%
C102
+5V
10uF, 50V
Vout
MC78M05
Page 34 of 49
Vin
U_4
C18
150pF, 500V
1K
R34
-B
J2B
C23
C24
-B
D7
-B
-B
D8
D6
+B
R104
47R, 1W
47R, 1W
4.7V
C103
10uF, 50V
IN
U_5
MC79M05
R50
2.2k
-5V
C104
10uF, 50V
OUT
C32
1000uF,50V
C31
1000uF,50V
OPEN
1
2
J4
2
1
3
J7
1
2
J3
+
CH2
-
+35V
Gnd
-35V
+
CH1
-
D102
MA2YD2300
OPEN
C28
CH2 OUT
R49
2.2k
C27
CH1 OUT
C34
OPEN
C33
OPEN
0.1uF, 400V
C26
10, 1W
R48
R57
100K
R58
100K
+B
C25
0.1uF, 400V
10, 1W
R47
D5
+B
-5V Power Supply
0.47uF, 400V
22uH
Chassis Gnd
Trace under J7
+B
0.47uF, 400V
22uH
R103
L2
-B
L1
Z102
CH2 O
1
2
3
4
5
6
7
8
13
14
15
16
J2A
9
10
11
12
ZM4732ADICT
D101
MA2YD2300
CH2 Feedback
R32
R56
0.0
VCC
SD
IRS2092S_ MODULE
OC
+5V Power Supply
CH2 IN
7
8
9
J1B
J1A
4
5
6
47k 1%
R31
CH1 Feedback
CH1 IN
10uF, 50V
R55
0.0
IN-1
4.7V 47R, 1W
ZM4732ADICT
Z101
C6
10uF, 50V
C3
10uF, 50V
R6
+5V
-5V
C5
10uF, 50V
4.7R 4.7R
3.3K
R13
22k
R17
IRAUDAMP5 REV 3.0
HS1
+5V
C15
OPEN
R72
R4
100R
R3
100R
U3
470
R39
Heat Sink
74AHC1G04
47R
R28
2.2uF,16V
C20
Audio in
CS3310
MUTE
SDATAOAGNDR
SCLK
DGRD
VD+
SDATAI AOUTL
CS
AINL
AGNDL
100K
R1 J5
Audio in
74AHC1G04
47R
R27
2.2uF,16V
C19
ZCEN
U_?
VCC Power Supply
Vout
U_6
MC78M12
Vin
4.7K
R106
47K
R105
R107
Z103
10R
47R
R8
R9
47R
R7
4.7uF, 16V
C109
3 SDATAI
2 CS
1
+5V
Drawing by: M.Rodriguez [email protected]
C108
10nF, 50V
6
7
8
C107
4.7uF, 16V
www.irf.com
.
R108
Control Volume
GND
Class D, Mother Board Control Volume and Power Supplies Schematic
GND
.
GND
S3B
Q103
SW
EXT. CLK
J8
BNC
A24497
MUTE
CLK
CLK
R116
47R
GND
+5V
-5V
Z109
8.2V
R151
47k
+B
PROTECTION
NORMAL
4Y
C114
10uF, 50V
C115
+5V
Q112
MMBT5551
47k
R150
10nF, 50V
R120
100R
+5V
MMBT5401
Q111
IRAUDAMP5 REV 3.0
47R
1k
R119
1k
R118
74HC14
4A
5Y
3A
3Y
5A
2Y
6Y
6A
1Y
2A
VCC
1A
U_3
MUTE R117
5K POT
R113
R112
820R
C112
1200pF, 50V
Drawing by: M.Rodriguez [email protected]
R115
47R
R114
100R
100pF, 50V
C113
100pF, 50V
C111
MMBT5551
R111
10K
1
2
SW_H-L
S2
SW-3WAY_A-B
100k
R110
D103
1N4148
www.irf.com
1nF, 50V
C110
R109
1K
SW
I
E
S
SW-3WAY_A-B
S3A
SP MUTE
MMBT5551
S
E
I
+B
-B
MMBT5551
47k
R137
Q107
R133
47k
R142
68k
R131
47K
DCP
R129
6.8k
R128
6.8k
1
2
3
1N4148
4.7k
P1
PVT412
6
5
4
R139
OVP
2
1
J9
R124
10k
100uF, 16V
C116
1K
R123
Q110
MMBT5551
R141
47k
10k
R144
39V
Z105
R140
10k
DC protection
DCP
OT
47k
-B
MMBT5551
MMBT5401
Q104
Q105
R126
100K
R125
10K
MMBT5551
Q109
OT
D105
R138
R127
6.8k
Page 35 of 49
R132
47k
Q106
+B
Z106
18V
MMBT5401
R130
47K
R135
82k
R136
68k
D107
C117
1N4148 100uF, 16V
D106
1N4148
+5V
10K
-5V
R134
10k
Z108
8.2V
CStart
D104
1N4148
Q108
R148
10k
R147
47k
R143
R149
47K
R122
47k
CH1 O
SD
Class D, Mother Board Clock and House Keeping Schematic
R146
47K
Trip and restart
S1
C119
SW-PB
0.1uF, 50V
UVP
R145
47K
Z107
18V
DC_PS
R121
47k
CH2 O
Direct Fet SJ
0805
0805
0805
D-FET1, D-FET2, D-FET3, D-FET4
R1, R2
R3,R4,R9,R10,R15,R16,R27,R28,R30,R32,R8
R5, R6
IRAUDAMP5 REV 3.0
SOT23-BCE
Q2, Q7
www.irf.com
805
TAN-A
TAN-B
0805
TAN-B
TAN-B
0805
1206
0805
0805
SOD-323
SOD-323
SMA
SMA
805
CON EISA31
CON EISA31
CON_POWER
CON_POWER
SOT23-BCE
Footprint
3.3K
10R
100R
IRF6645
MMBT5401-7
2
11
2
4
2
6
2
2
3
2
4
2
3
1
2
2
2
2
1
2
1
1
1
1
1
Quantity
Page 36 of 49
1nF,250V,COG
10uF, 16V, Tan
10uF, 16V, Tan
47nF,50V, X7R
10uF, 16V, Tan
3.3uF, 16V, X7R
0.1uF,100V, X7R
0.1uF,100V, X7R
open
10nF,50V, X7R
BAV19WS-7-F
1N4148WS-7-F
MURA120T3G
ES1D
LTST-C171TBKT
CON EISA31
CON EISA31
CON_POWER
CON_POWER
MMBT5551
PartType
Amp5_DB_2092_Rev 3.0_BOM
C1, C2, C21,C22,C23,C24
C3, C4
C5, C6
C9, C28, C29
C10, C11
C12, C16, C18, C19
C13, C17
C14, C15, C32, C33
C20
C30, C31
D1, D2
D3, D4
D5, D6
D7
DS1, DS2
J1A
J1B
J2A
J2B
Q1
Designator
Class D, Daughter Board:
IRAUDAMP5 Bill of Materials
PART NO
445-2325-1-ND
495-2236-1-ND
399-3706-1-ND
PCC1836CT-ND
399-3706-1-ND
445-1432-1-ND
399-3486-1-ND
PCC2239CT-ND
open
PCC103BNCT-ND
BAV19WS-FDICT-ND
1N4148WS-FDICT-ND
MURA120T3GOSCT-ND
ES1DFSCT-ND
160-1645-1-ND
A26568-ND
A26568-ND
A26570-ND
A26570-ND
MMBT5551FSCT-ND
MMBT5401DICT-ND
IRF6645
P100ACT-ND
P10ACT-ND
P3.3KACT-ND
DIGI KEY
DIGI KEY
DIGI KEY
IR
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
VENDER
0805
0805
0805
805
0805
0805
0805
0805
0805
0805
1206
805
ST-32 3mm SQ
805
SOIC16
R12, R45
R13, R14,R19,R20
R24, R48
R7,R18
R21, R22
R23, R26
R25, R29,R36,R41, R42
R37, R38
R39, R40
R43, R44
R49, R50, R51, R52,
Rp1, Rp2
P1,P2
R46,R53
U1, U2
IRAUDAMP5 REV 3.0
0805
R11, R31, R33, R34, R35, R47
www.irf.com
1206
R7
IR Driver
3.01k
1k
100C
open
0
33K
1R
10K
4.7R
1k
1.2k
1K
8.2K
4.7K
100K
10R
Page 37 of 49
3
3
3
3
3
3
5
2
2
2
2
2
2
1
ST32ETB102TR-ND
RHM3.01KCCT-ND
IRS2092S
P10ECT-ND
P100KACT-ND
P4.7KACT-ND
P8.2KACT-ND
P1.0KACT-ND
RHM1.2KARCT-ND
P1.0KACT-ND
P4.7ACT-ND
P10KACT-ND
P1.0ACT-ND
RHM33KARCT-ND
RHM0.0ARCT-ND
open
594-2322-675-21007
IR
DIGI KEY
DIGI KEY
MOUSER
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
DIGI KEY
Class D Motherboard:
IRAUDAMP5 MOTHERBOARD BILL OF MATERIAL
NO
1
2
3
4
5
6
7
8
9
10
11
Designator
C1, C5, C6, C101, C102, C103, C104, C105,
C106, C115
C2, C3
C7, C8, C9, C10
C11, C12, C13, C14
C15, C16
C17, C18
C19, C20
C119
C23, C24
#
Footprint
Part Type
Part No
Vender
10
RB2/5
10uF, 50V
565-1106-ND
Digikey
2
4
4
2
2
2
1
2
RB2/5
open
open
805
AXIAL0.19R
1206
1206
CAP MKP
2.2uF, 50V
565-1103-ND
Digikey
33pF
150pF, 500V
2.2uF, 16V
0.1uF, 50V
0.47uF, 400V
478-1281-1-ND
338-1052-ND
PCC1931CT-ND
PCC104BCT-ND
495-1315-ND
Digikey
Digikey
Digikey
Digikey
Digikey
495-1311-ND
Digikey
14
15
16
17
18
19
20
21
22
23
24
25
26
27
C25, C26
C27, C28, C29, C30, C40, C41, C42, C43,
C44, C45, C46, C47
R29, R30, R55, R56, R60, R61, R62, R63,
R64, R65, R66, R67, R71, R72
C31, C32
C33, C34, C48, C49
C107, C109
C108, C114
C110
C111, C113
C112
C116, C117
D103, D104, D105, D106, D107
D5, D6, D7, D8
D101, D102
HS1
J1A, J1B
J2A, J2B
28
J3, J4
2
MKDS5/2-9.5
29
J5, J6
2
Blue RCA
RCJ-055
30
J7
1
J HEADER3
277-1272
277-1272-ND or 651-1714984
31
32
J8
J9
1
1
L1, L2
2
P13504-ND
Digikey
34
35
36
37
38
NORMAL
P1
PROTECTION
Q101
Q102, Q104, Q106, Q111
Q103, Q105, Q107, Q108, Q109, Q110,
Q112
R1, R2, R57, R58, R110, R126
R3, R4, R114
R5, R6
R7, R8, R10, R11, R27, R28, R115, R116,
R117
R9, R105
R13, R14
R17, R18
R106, R121, R122, R130, R131, R132,
R133, R137, R139, R141, R145, R146,
R147, R149, R150, R151
R152
R55, R56
R39, R40
R21, R22, R23, R24
R120
R29P, R30P
R31, R32
R33, R34
R109, R118, R119, R123
R47, R48
R49, R50
R68, R69
1
1
1
1
4
BNC
ED1567
ETQA21ZA220 or
ETQA17B220
404-1106-ND
PVT412
404-1109-ND
FX941
A32248-ND
ED1567
33
BNC_RA CON
ED1567
Inductor from
Panasonic
Led rb2/5
DIP-6
Led rb2/5
SOT89
SOT23-BCE
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey or
Mouser
Digikey
Digikey or
Mouser
Digikey
Digikey
160-1143-ND
PVT412-ND
160-1140-ND
FCX491CT-ND
MMBT5401-7-F
MMBT5401-FDICT-ND
7
SOT23-BCE
MMBT5551
MMBT5551-7DICT-ND
Digikey
6
3
2
805
805
1206
100K
100R
4.7R
P100KACT-ND
P100ACT-ND
P4.7ECT-ND
Digikey
Digikey
Digikey
9
805
47R
P47ACT-ND
Digikey
2
2
2
805
805
805
10R
3.3K, 1%
22k
P10ACT-ND
P3.3KZCT-ND
P22KACT-ND
Digikey
Digikey
Digikey
16
805
47k
P47KACT-ND
Digikey
1
2
2
4
1
2
2
2
4
2
2
2
805
805
805
open
1206
open
2512
1206
805
2512
1206
AXIAL-0.3
OPEN
0.0 Ohms
470R
P0.0ACT-ND
P470ACT-ND
Digikey
Digikey
Digikey
100R
P100ECT-ND
Digikey
47K, 1%
1K
1K
10, 1W
2.2k
OPEN
PT47KAFCT-ND
P1.0KECT-ND
P1.0KACT-ND
PT10XCT
P2.2KECT-ND
-
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
12
13
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
www.irf.com
2
CAP MKPs
0.1uF, 400V
12
805
OPEN
14
805
OPEN
2
4
2
2
1
2
1
2
5
4
2
1
2
2
RB5/12_5
AXIAL0.1R
805
805
805
805
805
rb2/5
SOD-123
SMA
SOD-123
Heat_S6in1
CON EISA-31
CON_POWER
1000uF,50V
OPEN
4.7uF, 16V
10nF, 50V
1nF, 50V
100pF, 50V
1200pF, 50V
100uF, 16V
1N4148W-7-F
1N4148W-FDICT-ND
MURA120T3G
MA2YD2300
HEAT SINK
CON EISA31
CON_POWER
MURA120T3GOSCT-ND
MA2YD2300LCT-ND
294-1086-ND
A26453-ND
A26454-ND
277-1022
277-1271-ND or 651-1714971
CP-1422-ND
IRAUDAMP5 REV 3.0
565-1114-ND
PCC2323CT-ND
PCC103BNCT-ND
PCC102CGCT-ND
PCC101CGCT-ND
478-1372-1-ND
565-1037-ND
Page 38 of 49
Digikey
Digikey
Digikey
Digikey
Digikey
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
R101, R102, R103, R104
R107, R138
R108
R111, R124, R125, R134, R140, R143,
R144, R148
R112
R113
R127, R128, R129
R135
R136, R142
S1
S2
S3
U1, U2
U3, U4
U7, U8
U9, U10
U_1
4
2
1
8
1
1
3
1
2
1
1
1
2
2
2
2
1
U_2
1
U_3
U_4
U_5
U_6
Z1, Z2, Z103
Z101, Z102
Z104
Z105
Z106, Z107
Z108, Z109
Volume Knob
Thermalloy TO-220 mounting kit with screw
1/2" Standoffs 4-40
4-40 Nut
No. 4 Lock Washer
1
1
1
1
3
2
1
1
2
2
1
3
5
5
5
2512
805
V_Control
47R, 1W
4.7K
CT2265
PT47XCT-ND
P4.7KACT-ND
CT2265-ND
Digikey
Digikey
Digikey
805
10K
P10KACT-ND
Digikey
805
POTs
1206
805
805
Switch
SW-EG1908-ND
SW-EG1944-ND
open
SOT25
MINI5
SO-8
SOIC16
820R
5K POT
6.8k
82k
68k
SW-PB
SW_H-L
SW-3WAY
P820ACT-ND
P6.8KECT-ND
P82KACT-ND
P68KACT-ND
P8010S-ND
EG1908-ND
EG1944-ND
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
74AHC1G04
open
open
CS3310
296-1089-1-ND
open
open
73C8016 or 72J5420
N8A
3310S06S
3310-IR01
M14A
TO-220
TO-220
TO-220
SOD-123
SMA
SOD-123
SOD-123
SOD-123
SOD-123
Blue Knob
Kit screw, ROHS
Standoff
100 per bag
100 per bag
74HC14
296-1194-1-ND
MC78M05CTG
LM79M05CT
LM78M12CT
MC78M05CTGOS-ND
LM79M05CT-ND
LM78M12CT-ND
15V
4.7V
24V
39V
18V
8.2V
MC21060
AAVID 4880G
BZT52C15-FDICT-ND
1SMA5917BT3GOSCT-ND
BZT52C24-FDICT-ND
BZT52C39-13-FDICT-ND
BZT52C18-FDICT-ND
BZT52C8V2-FDICT-ND
10M7578
82K6096
8401K-ND
H724-ND
H729-ND
3362H-502LF-ND
*Tachyonix Corporation, 14 Gonaka Jimokuji Jimokuji-cho, Ama-gun Aichi, JAPAN 490-1111 http://www.tachyonix.co.jp
[email protected]
www.irf.com
IRAUDAMP5 REV 3.0
Page 39 of 49
Digikey
Newark
*Tachyonix
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Newark
Newark
Digikey
Digikey
Digikey
IRAUDAMP5 Hardware
Voltage regulator mounting:
Item Description
7
8
1
Insulator Thermalfilm
2
Shoulder Washer
3
Flat Washer #4
4
No. 4-40 UNC-2B Hex Nut
5
No. 4-40 UNC-2A X 1/2 Long Phillips
Pan Head Screw
6
Lockwasher, No.4
7
Heatsink
8
PCB
Item Description
7
8
www.irf.com
1
Insulator Thermalfilm
2
Shoulder Washer
3
Flat Washer #4
4
No. 4-40 UNC-2B Hex Nut
5
No. 4-40 UNC-2A X 1/2 Long Phillips
Pan Head Screw
6
Lockwasher, No.4
7
Heatsink
8
PCB
IRAUDAMP5 REV 3.0
Page 40 of 49
IRAUDAMP5 PCB Specifications
Figure 34. Motherboard and Daughter-board Layer Stack
Daughter board:
Material:
FR4, UL 125°C
Layer Stack:
2 Layers, 1 oz. Cu each, Through-hole plated
Dimensions:
3.125” x 1.52” x 0.062”
Solder Mask:
LPI Solder mask, SMOBC on Top and Bottom Layers
Plating:
Silkscreen:
Open copper solder finish
On Top and Bottom Layers
Motherboard:
Material:
FR4, UL 125°C
Layer Stack:
2 Layers, 1 oz. Cu
Dimensions:
5.2” x 5.8” x 0.062”
Solder Mask:
LPI Solder mask, SMOBC on Top and Bottom Layers
Plating:
Open copper solder finish
Silkscreen:
On Top and Bottom Layers
www.irf.com
IRAUDAMP5 REV 3.0
Page 41 of 49
IRAUDAMP5 PCB layers
Class D, Daughter-board:
Figure 40. PCB Layout – Top-Side Solder-Mask and Silkscreen
www.irf.com
IRAUDAMP5 REV 3.0
Page 42 of 49
Figure 41. PCB Layout – Bottom Layer and Pads and bottom silk screen
www.irf.com
IRAUDAMP5 REV 3.0
Page 43 of 49
Figure 39. PCB Layout Motherboard:
Top Layer
www.irf.com
IRAUDAMP5 REV 3.0
Page 44 of 49
Top silk screen
www.irf.com
IRAUDAMP5 REV 3.0
Page 45 of 49
Bottom
www.irf.com
IRAUDAMP5 REV 3.0
Page 46 of 49
www.irf.com
IRAUDAMP5 REV 3.0
Page 47 of 49
4.0
4.0
Bottom Silkscreen
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 7/27/2007
www.irf.com
IRAUDAMP5 REV 3.0
Page 48 of 49