IRS20957S functional description

Application Note AN-1144
IRS20957S Functional Description
By Jun Honda, Xiao-chang Cheng
Table of Contents
Floating PWM Input .................................................................................................................................................. 2
Over-Current Protection (OCP) ................................................................................................................................ 3
Protection Control ..................................................................................................................................................... 5
Self Reset Protection................................................................................................................................................ 5
Designing Ct.............................................................................................................................................................. 5
Shutdown Input......................................................................................................................................................... 6
Latched Protection.................................................................................................................................................... 6
Interfacing with System Controller............................................................................................................................ 6
Programming OCP Trip Level .................................................................................................................................. 7
Low-side Over-Current Sensing ............................................................................................................................... 7
Low-Side Over-Current Setting ................................................................................................................................ 8
High-Side Over-Current Sensing.............................................................................................................................. 9
High-Side Over-Current Setting.............................................................................................................................. 10
Choosing the Right Reverse Blocking Diode ......................................................................................................... 10
Deadtime Generator ............................................................................................................................................... 11
How to Determine Optimal Deadtime..................................................................................................................... 11
Programming Deadtime.......................................................................................................................................... 11
Supplying VDD ......................................................................................................................................................... 12
Charging VBS Prior to Start ..................................................................................................................................... 13
Start-up Sequence (UVLO) .................................................................................................................................... 14
Power-down Sequence .......................................................................................................................................... 14
Power Supply Decoupling ...................................................................................................................................... 14
VSS Negative Bias Clamping................................................................................................................................... 14
Junction Temperature Estimation........................................................................................................................... 15
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IRS20957S General Description
Note: The IRS20957S is an improved version of the IRS20955S. The IRS20955S is no longer recommended for
new designs. For details, refer to application note AN-1141, IRS20955S and IRS20957S Comparison.
The IRS20957 is a high voltage, high speed MOSFET driver with a floating PWM input designed for Class D
audio amplifier applications. Bi-directional current sensing detects over current conditions during positive and
negative load currents without any external shunt resistors. A built-in protection control block provides a secure
protection sequence against over-current conditions and a programmable reset timer. The internal dead-time
generation block enables accurate gate switching and optimum dead-time setting for better audio performance,
such as lower THD and lower audio noise floor.
For the convenience of half bridge configuration, the PWM input and protection logic are constructed on a floating
well.
Typical Implementation
The following explanations are based on a typical application circuit with self-oscillating PWM topology shown in
Figure 1. For further information, refer to the IRAUDAMP4 reference design.
Figure 1. IRS20957 Typical Application Circuit
Floating PWM Input
The IRS20957 accepts floating inputs, enabling easy half-bridge implementation. VDD, CSD and IN refer to VSS.
As a result, the PWM input signal can directly feed into IN while referencing VSS, which is typically the midpoint
between the positive and negative DC bus voltages in a half-bridge configuration.
The IRS20957 also accepts a non-floating input when VSS is tied to COM.
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VDD
HV
LEVEL
SHIFT
CSD
10.2V
IN
PROTECTION
VSS
Floating Input Isolation
Floating Bias
0V – 200V
COM
Figure 2. Floating PWM Input Structure
Over-Current Protection (OCP)
The IRS20957 features over-current protection to protect the power MOSFETs during abnormal load conditions.
The IRS20957 starts a sequence of events when it detects an over-current condition during either high-side or
low-side turn on of a pulse.
As soon as either the high-side or low-side current sensing block detects over-current:
1. The OC Latch (OCL) flips logic states and shutdowns the outputs LO and HO.
2. The CSD pin starts discharging the external capacitor Ct.
3. When VCSD, the voltage across Ct, falls below the lower threshold Vth2, an output signal from COMP2
resets OCL.
4. The CSD pin starts charging the external capacitor Ct.
5. When VCSD goes above the upper threshold Vth1, the logic on COMP1 flips and the IC resumes operation.
As long as the over-current condition exists, the IC will repeat the over-current protection sequence at a repetition
rate dependent upon capacitance in CSD pin.
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Figure 3. Over-Current Protection Timing Chart
VDD
Vth1
`
COMP1
CSD
OC
S
Q
UVLO(VB)
`
COMP2
Ct
R
OC DET (H)
Vth2
VSS
HV
LEVEL
SHIFT
FLOATING INPUT
HV
LEVEL
SHIFT
HV
LEVEL
SHIFT
FLOATING HIGH SIDE
LOW SIDE
OC DET (L)
UVLO(VCC)
SD
PWM
HO
DEAD TIME
`
LO
Figure 4. Shutdown Functional Block Diagram
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Protection Control
The internal protection control block dictates the operational mode, normal, or shutdown, using the input of the
CSD pin. In shutdown mode, the IC forces LO and HO to output 0V with respect to COM and VS respectively to
turn off the power MOSFETs.
The CSD pin provides five functions.
1. Power up delay timer
2. Self-reset timer
3. Shutdown input
4. Latched protection configuration
5. Shutdown status output (host I/F)
Self Reset Protection
By putting a capacitor between CSD and VSS, the IRS20957 resets itself after entering the shutdown mode.
Figure 5. Self Reset Protection Configuration
Designing Ct
The timing capacitor, Ct, is used to program tRESET and tSU.
• tRESET, is the amount of time that elapses from when the IC enters the shutdown mode to the time when
the IC resumes operation. tRESET should be long enough to avoid over heating the MOSFET from the
repetitive sequence of shutting down and resuming operation during over-current conditions. In most
applications, the minimum recommended time for tRESET is 0.1 second.
• tSU is the amount of time between powering up the IC in the shutdown mode to the moment the IC
releases shutdown to begin normal operation.
The values chosen for tRESET and tSU will determine the capacitance of Ct using the given equations:
The Ct determines tRESET and tSU as following equations:
t RESET =
t SU =
Ct ⋅ VDD
1.1 ⋅ I CSD
Ct ⋅ VDD
0.7 ⋅ I CSD
[s]
[s]
where ICSD = the charge/discharge current at the CSD pin
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VDD = the floating input supply voltage with respect to VSS.
Shutdown Input
The IRS20957 can be shut down by an external shutdown signal SD. Figure 6 shows how to add an external
discharging path to shutdown the PWM.
Figure 6. Shutdown Input
Latched Protection
Connecting CSD to VDD through a 10k Ω or less resistor configures the over-current protection latch. The latch
locks the IC in shutdown mode after over-current is detected. An external reset switch can be used to bring CSD
below the lower threshold Vth2 for a minimum of 200 ns to properly reset the latch. After the power up sequence,
a reset signal to the CSD pin is required to release the IC from the latched shutdown mode.
<10k
SD
1
VDD
CSH
16
2
CSD
VB
15
3
IN
HO
14
4
VSS
VS
13
5
NC
NC
12
VCC
11
LO
10
COM
9
6
VREF
7
OCSET
8
DT
Figure 7. Latched Protection Configuration
Interfacing with System Controller
The IRS20957 can communicate with an external system controller through a simple interfacing circuit shown in
Figure 8. A generic PNP transistor U1 detects the sink current at the CSD pin during an OCP event and outputs a
shutdown signal to an external system controller. Another generic NPN transistor U2 can then reset the internal
protection logic by pulling the CSD voltage below the lower threshold Vth2 for a minimum of 200 ns. Note that the
CSD pin is configured to operate in latched OCP. After the power up sequence, a reset signal to the CSD pin is
required to release the IC from the shutdown mode.
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U1
SD
<10k
RESET
1
VDD
CSH
16
2
CSD
VB
15
3
IN
HO
14
4
VSS
VS
13
5
NC
NC
12
6
VREF
VCC
11
7
OCSET
LO
10
8
DT
COM
9
U2
Figure 8. Interfacing with Host Controller
Programming OCP Trip Level
In a Class D audio amplifier, the direction of the load current alternates with the audio input signal. An overcurrent condition can therefore occur during either a positive current cycle or a negative current cycle. The
IRS20957 uses the RDS(ON) of the output MOSFETs as current sensing resistors. Due to the structural constraints
of high voltage ICs, current sensing is implemented differently for high side and low side. If the measured current
exceeds a predetermined threshold, the OCP block outputs a signal to the protection block, focing HO and LO
low and protecting the MOSFETs.
D1
R2
+B
CSH
UV
DETECT
R1
VB
UV
HIGH
SIDE
CS
Q
Dbs
R3
HO
Q1
Cbs
OUT
HV
LEVEL
SHIFT
FLOATING HIGH SIDE
5V REG
VS
HV
LEVEL
SHIFT
Vcc
VCC
UV
DETECT
DEAD TIME
Q2
LO
SD
-B
COM
R5
LOW SIDE CS
OCSET
R4
VREF
Figure 9. Bi-Directional Over-Current Protection
Low-side Over-Current Sensing
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For negative load currents, low-side over-current sensing monitors the load condition and shuts down switching
operation if the load current exceeds the preset trip level.
Low-side current sensing is based on the measurement of VDS across the low side MOSFET during low-side turn
on. In order to avoid triggering OCP from overshoot, a blanking interval inserted after LO turn on disables overcurrent detection for 450 ns.
The OCSET pin is used to program the threshold for low-side over-current sensing. When the VDS measured
across the low-side MOSFET exceeds the voltage at the OCSET pin with respect to COM, the IRS20957 begins
the OCP sequence described earlier.
Note that programmable OCSET range is 0.5V to 5.0V. To disable low side OCP, connect OCSET to VCC
directly.
To program the trip level for over current, the voltage at OCSET can be calculated using the equation below.
VOCSET = VDS(LOW SIDE) = ITRIP+ x RDS(ON)
In order to minimize the effect of the input bias current at the OCSET pin, select resistor values for R4 and R5
such that the current through the voltage divider is 0.5 mA or more.
* Note: Using VREF to generate an input to OCSET through a resistive divider provides improved immunity from
fluctuations in VCC.
+B
Q1
OC
REF
OCREF
5.1V
R4
R5
OUT
VS
0.5mA
-
OCSET
OC
+
OC Comparator
COM
LO
LO
Q2
IRS20957
-B
Figure 10. Low-Side Over-Current Sensing
Low-Side Over-Current Setting
Assume that the low side MOSFET has RDS(on) of 100mΩ. VOCSET to set the current trip level at 30A is given by:
VOCSET = ITRIP+ x RDS(ON) = 30 A x 100 mΩ = 3.0 V
Choose R4+R5=10 kΩ to properly load the VREF pin.
R5 =
=
VOCSET
⋅ 10 kΩ
VREF
3.0 V
⋅ 10 kΩ
5.1 V
= 5.8 kΩ
where VREF = 5.1 V
Based on the E-12 series of resistor values, choose R5 to be 5.6 kΩ and R4 to be 3.9 kΩ to complete the design.
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In general, RDS(ON) has a positive temperature coefficient that needs to be considered when setting the threshold
level. Also, variations in RDS(ON) will affect the selection of external or internal component values.
High-Side Over-Current Sensing
For positive load currents, high-side over-current sensing also monitors the load condition and shuts down the
switching operation if the load current exceeds the preset trip level.
High-side current sensing is based on the measurement of VDS across the high-side MOSFET during high-side
turn on through pins CSH and VS. In order to avoid triggering OCP from overshoot, a blanking interval inserted
after HO turn on disables over-current detection for 450 ns.
In contrast to low-side current sensing, the threshold at which the CSH pin engages OC protection is internally
fixed at 1.2V. An external resistive divider R2 and R3 can be used to program a higher threshold.
An external reverse blocking diode, D1, is required to block high voltages from feeding into the CSH pin while the
high-side is off. Due to a forward voltage drop of 0.6V across D1, the minimum threshold required for high-side
over-current protection is 0.6V.
VCSH =
R3
⋅ (V DS ( HIGHSIDE ) + V F ( D1) )
R 2 + R3
where VDS(HIGH SIDE) = the drain to source voltage of the high-side MOSFET during high-side turn on
VF(D1) = the forward drop voltage of D1
Since VDS(HIGH SIDE) is determined by the product of drain current ID and RDS(ON) of the high-side MOSFET. VCSH
can be rewritten as:
VCSH =
R3
⋅ (RDS ( ON ) ⋅ I D + VF ( D1) )
R 2 + R3
The reverse blocking diode D1 is forward biased by a 10 kΩ resistor R1.
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Figure 1. Programming High-Side Over-Current Threshold
High-Side Over-Current Setting
Figure 11 demonstrates the typical circuitry used for high-side current sensing. In the following
example, the over-current protection level is set to trip at 30A using a MOSFET with an RDS(ON) of
100 mΩ. The component values of R2 and R3 can be calculated using the following formula:
Let R2 + R3=10 kΩ.
VthOCH
R3 = 10 kΩ ⋅
VDS + VF
where Vth,OCL = 1.2V
VF = the forward voltage of reverse blocking diode D1 = 0.6V.
[email protected]=30A = the voltage drop across the high-side MOSFET when the MOSFET current
is 30 A.
Therefore, [email protected]=30A = ID x RDS(ON) = 30A x 100 mΩ = 3V
Based on the formulas above, R2 = 6.8 kΩ and R3 = 3.3 kΩ.
Choosing the Right Reverse Blocking Diode
The selection of the appropriate reverse blocking diode D1 depends on its voltage rating and
speed. To effectively block bus voltages, the reverse voltage must be higher than the voltage
difference between +B and -B and the reverse recovery time must be as fast as the bootstrap
charging diode. A diode such as the NXP BAV21 W, a 200V, 50 ns high-speed switching diode, is
more than sufficient.
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Deadtime Generator
Deadtime is the blanking period inserted between either high-side Turn-OFF and low-side TurnON, or low-side Turn-OFF and high-side Turn-ON. Its purpose is to prevent shoot through, or a
rush of current through both MOSFETs. In the IRS20924(S), an internal deadtime generation
block allows the user to select the optimum deadtime from a range of preset values. Selecting a
preset deadtime through the DT pin voltage can easily be done through an external voltage
divider. This way of setting deadtime prevents outside noise from modulating the switching timing,
which is critical to the audio performance.
How to Determine Optimal Deadtime
The effective deadtime in an actual application differs from the deadtime specified in this
datasheet due to the switching fall time, tf.. The deadtime value in this datasheet is defined as the
time period between the beginning of turn-off on one side of the switching stage and the
beginning of turn-on on the other side as shown in Figure 12. The fall time of the MOSFET gate
voltage must be subtracted from the deadtime value in the datasheet to determine the effective
deadtime of a Class D audio amplifier.
(Effective deadtime) = (Deadtime in datasheet) – tf.
90%
HO (or LO)
Effective dead - time
10%
tf
LO (or HO)
Dead-time
in
datasheet
10%
Figure 12. Effective Deadtime
A longer deadtime period is required for a MOSFET with a larger gate charge value because of
the longer tf.. Although a shorter effective deadtime setting is beneficial to achieving better
linearity in Class D amplifiers, the likelihood of shoot-through current increases with narrower
dead-time settings. Negative values of effective dead-time may cause excessive heat dissipation
in
the
MOSFETs,
leading
to
potentially
serious
damage.
To calculate the optimal deadtime in a given application, the fall time tf for both HO and LO in the
actual circuit needs to be taken into account. In addition, variations in temperature and device
parameters could also affect the effective deadtime in the actual circuit. Therefore, a minimum
effective deadtime of 10 ns is recommended to avoid shoot-through current over the range of
operating temperatures and supply voltages.
Programming Deadtime
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The IRS20957 selects the deadtime from a range of preset deadtime values based on the voltage
applied at the DT pin. An internal comparator translates the DT input to a predetermined deadtime by comparing the input with internal reference voltages. These internal reference voltages
are set in the IC through a resistive voltage divider using VCC. The relationship between the
operation mode and the voltage at DT pin is illustrated in the Figure13 below.
Dead- time
15nS
25nS
35nS
45nS
0.23 xVcc
0.36 xVcc
0.57 xVcc
Vcc
VDT
Figure 2. Deadtime vs. VDT
Table 1 suggests pairs of resistor values used in the voltage divider for selecting deadtime.
Resistors with up to 5% tolerance are acceptable when using these values.
IRS20957
>0.5mA
Vcc
R1
DT
R2
COM
Figure 3. External Voltage Divider
Table 1 Recommended Resistor Values for Deadtime Selection
Deadtime Mode
DT1
DT2
DT3
DT4
R1
<10 kΩ
5.6 kΩ
8.2 kΩ
Open
R2
Open
4.7 kΩ
3.3 kΩ
<10 kΩ
DT Voltage
VCC
0.46(VCC)
0.29(VCC)
COM
Supplying VDD
VDD is designed to be supplied with an internal Zener diode clamp. IDD, the supply current for VDD,
can be estimated by:
IDD ≈ 1.5 mA x 300 x 10-9 x switching frequency + 0.5 mA + 0.5 mA
(Dynamic power consumption)
(Static) (Zener bias)
The value of RDD used to supply IDD should meet the following requirement:
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RDD ≤
V+ B − 10.2 V
I DD
[Ω]
Example: In the case where the average PWM switching frequency is 400kHz, the required IDD is
1.18 mA. Based on this calculation, a 50V power supply voltage would require RDD to be 33 kΩ or
less.
Furthermore, make sure IDD is below the maximum Zener diode bias current, IDDZ, during static
state conditions.
I DDZ ≥
V+ B − 10.2 V
− 0.5 mA
Rdd
Figure 4. Supplying VDD
Charging VBS Prior to Start
The high-side bootstrap capacitor can be charged through a resistor from the positive supply bus
to the VB pin by utilizing an internal 15.3V Zener diode between VB and VS. This scheme provides
proper PWM start-up with self-oscillating topologies.
The value of this charging resistor is subject to several constraints:
- The minimum value of RCHARGE is limited by the leakage current of the bootstrap voltage
supply through RCHARGE, which would limit the maximum PWM modulation index of the
system.
- The maximum value of RCHARGE is limited by the current charge capability of the resistor
during startup:
I CHARGE > I QBS
where ICHARGE = the current through RCHARGE
IQBS = the high side quiescent current.
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Figure 16. Boot Strap Supply Pre-charging
Start-up Sequence (UVLO)
The protection control block in the IRS20957 monitors the status of VDD and VCC to ensure that
both voltage supplies are above the UVLO (under- voltage lockout) threshold before beginning
normal operation. If either VDD or VCC is below the under voltage threshold, LO and HO are
disabled in shutdown mode until both VDD and VCC rise above the voltage threshold.
Power-down Sequence
As soon as VDD or VCC falls below the UVLO threshold, protection logic in the IRS20957 turns off
LO and HO, shutting off the power MOSFETs.
Figure 5. IRS20957 UVLO Timing Chart
Power Supply Decoupling
Ceramic capacitors of 0.1 µF or more should be placed close to the power supply pins of the IC
on the board. Please refer to the application note AN-978 for general design considerations of a
high voltage gate driver IC.
VSS Negative Bias Clamping
VSS can go below COM when a negative supply is missing in a dual supply configuration. In this
case, excessive negative VSS voltage with respect to COM could damage the IRS20957. Having
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a diode to clamp potential negative biases to VSS is recommended to protect the IC. A standard
recovery diode with a current rating of 1A such as the 1N4002 is sufficient for this purpose.
1
VDD
CSH
16
2
CSD
VB
15
3
IN
HO
14
4
VSS
VS
13
5
NC
NC
12
6
VREF
VCC
11
7
OCSET
LO
10
8
DT
COM
9
-B
Figure 6. Negative VSS Clamping
Junction Temperature Estimation
The power dissipation in the IRS20957 is dominated by the following items:
- PMID: Power dissipation of the floating input logic and protection circuitry
- PLSM: Power dissipation of the input level shifter
- PLOW: Power dissipation in low-side
- PLSH: Power dissipation of the high-side level shifter
- PHIGH: Power dissipation in high-side
1. PMID: Power Dissipation of the Floating Input Logic and Protection Circuitry
The power dissipation of the floating input section is given by:
PMID = PZDD + PLDD ≈
V+ BUS − VDD
⋅VDD
RDD
where
PZDD = the power dissipation from the internal Zener diode clamping VDD
PLDD = the power dissipation from the internal logic circuitry
V+BUS = the positive bus voltage feeding VDD
RDD = the resistor feeding VDD from V+BUS
*For obtaining the value of RDD, refer to the section “Supplying VDD.”
2. PLSM: Power Dissipation of the Input Level Shifter
PLSM = 2 nC x fsw x VSS,BIAS
where
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fSW = the PWM switching frequency
VSS,BIAS = the bias voltage of VSS with respect to COM
3. PLOW: Power Dissipation in Low-Side
The power dissipation in low-side comes from the losses of the logic circuitry and the losses
of driving LO.
PLOW = PLDD + PLO
⎛
⎞
RO
⎟
= (I QCC ⋅ VCC ) + ⎜Vcc ⋅ Qg ⋅ f SW ⋅
⎜
⎟
+
+
R
R
R
O
g
g
(int)
⎝
⎠
where
PLDD = the power dissipation from the internal logic circuitry
PLO = the power dissipation from the gate drive stage to LO
RO = the output impedance of LO, typically 10 Ω for the IRS20957
Rg(int) = the internal gate resistance of the low side MOSFET driver, typically 10 Ω for the
IRS20957
Rg = the external gate resistance of the low side MOSFET
Qg = total gate charge of the low side MOSFET
4. PLSH: Power Dissipation of the High-Side Level Shifter
PLSH = 0.4 nC x fsw x VBUS
where
fSW = the PWM switching frequency
VBUS = the difference between the positive bus voltage and negative bus voltage
5. PHIGH: Power Dissipation in High-side
The power dissipation in high-side comes from the losses of the logic circuitry and the losses
of driving LO.
PHIGH = PLDD + PHO
⎛
⎞
RO
⎟
= (I QBS ⋅ VBS ) + ⎜VBS ⋅ Qg ⋅ f SW ⋅
⎜
RO + Rg + Rg (int) ⎟⎠
⎝
where
PLDD = the power dissipation from the internal logic circuitry
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PLO = the power dissipation from the gate drive stage to HO
RO = equivalent output impedance of HO, typically 10 Ω for the IRS20957
Rg(int) = the internal gate resistance of the high-side MOSFET driver, typically 10 Ω for the
IRS20957
Rg = external gate resistance of the high-side MOSFET
Q g = total gate charge of the high- side MOSFET
Total power dissipation, Pd, is given by
Pd = PMID + PLSM + PLOW + PHSM + PHIGH .
Tj: Junction Temperature
Given Rth,JA, the thermal resistance between the ambient and junction temperature, TJ, the
junction temperature, can be calculated from the formula provided below.
TJ = Rth , JA ⋅ Pd + TA < 150 °C
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Revision History
Date
Xx/xx/2007
September
16th, 2008
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Change
Initial online release
Updated for IRS20957S. IRS20955S is not recommended for new
design.
Charging VBS Prior to Start: Vbs Zener diode clamping voltage from
20.4V to 15.3V.
Other minor language corrections.
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