12V Multi-phase Controller & PowIRStage® IR3565B CORE 1.025V Boot Voltage / 80A (VDD) VID ± 12.5mV -- read FUSESR (via I2C) for optimum Vcore for setting [ accuracy of IR3565 is ±5mV] +IR3550 (4 phase) + IR3550 (2 phase) LDO 1.5V / 40A I2C BUS DDR3 Freescale QorIQ T4240 VTT VCC_GVDD_S_P1V5: DDR3, DDR cntrl, Serdes POL Regulators SupIRBuck® IR3897 POL Regulators SupIRBuck® IR3897 POL Regulators SupIRBuck® IR3897 5V OVDD 1.89V FUSE (PROG_SFP, PROG_MTR) International Rectifier is Proven Power Partner of Freescale DVDD 2.5V (LVDD) Core, Enet, Bus, GPIO OVDD 1.8V X1234 1.35V (XnVDD Serdes Xmit) POL Regulators SupIRBuck® IR3897 S1234 1.00V (XnVDD Serdes Rcvr) KEY CORE, PLATFORM, SERDES RAILS XFI SFP also: CPLD, Thermal Monitors PHY 1.20V P2V5_R LDO Vitesse 1G PHY & Serdes P1V8 SGMII EMI1 VCC_3.3 Utility 3.3V rail various other locations Core Voltage ± 3% Accuracy DC/AC - IR3565B Meets Accuracy specs through all Dhrystone Code test over temperature and worst load. Load Step: T4240: 20A for 12 cores T4160: 15A for 8 cores T4080: 10A for 4 cores Slew rate: 12A/µs Power Dissipation Range: 32 to 64W worst case Core+SVDD, for 1.5 to 1.6GHz also: CPLD, Thermal Monitors LDO LDO Cortina Quad 10G PHY CDR CS4340 eSHDC, eSPI, DMA, MPIC, CPLD, SPI / SDHC GPIO, clocking, debug, PLL filter, NOR Flash system control and pwr mgt, SD Card IFC, DDRCLK supply, JTAG I/O voltage POL Regulators SupIRBuck® IR3897 POL Regulators SupIRBuck® IR3897 4 Port 10G CDR + PHY Quad Port 10/100/1000BASE-T PHY, SERDES http://www.irf.com/reference-designs/design-family/_/N~1njcj9#tab-tab1 SERDES Voltage Supplies SnVdd and XnVdd ( schematic as X1234 and X1234) Absolute peak ripple/noise should not exceed 10mV when measured from 50kHz to 500MHz. IR implemented special filters to meet these specs.