HT1382 I2C/3-Wire Real Time Clock

HT1382
I2C/3-Wire Real Time Clock
Feature
Applications
• Real Time Clock/Calendar Functions
–– Includes: Sec, Minutes, Hours, Day, Date,
Month, and year in BCD format
• Utility meters
• Clock operating voltage: 2.0V~5.5V
• Wireless equipment
• Consumer electronics
• Portable equipment
• Supply voltage VDD=2.7V~5.5V
• POS equipment
• Automatic leap year correction, valid until year
2099
• Computer products
• Other industrial/Medical/Automotive applications
• Automatic supply switch over
• Integrated oscillator load capacitors – CL=12.5pF
General Description
• Clock compensation
The HT1382 is a low power real time clock device
with two serial interface: I2C or 3-wire. The interface
mode is selected by the chosen chip version. The
device provides both clock and calendar information
in BCD format and also includes alarm functions. The
calendar is accurate until the year 2099 and includes
automatic leap year correction.
• Programmable alarm and interrupt function
• 15 selectable frequency outputs
• 4 Bytes EEPROM for user
• Serial commutation via I2C or 3-wire interface
• 8-pin DIP, SOP and MSOP package for I2C
interface
An external 32768Hz crystal is used as the device
oscillator for device timing for which is provided
an integrated crystal load capacitance of 12.5pF.
The device includes a crystal oscillator temperature
compensation function and internal power control
circuitry detects power failures and automatically
switches to the battery supply when a power failure
occurs.
• 10-pin MSOP package for 3-wire interface
Rev. 1.50
1
July 24, 2014
HT1382
Block Diagram
Internal
power supply
VDD
VCOMP
＋
－
Switch
RTC Register
VBAT
X1
Oscillator
Compensation
Crystal
Oscillator
X2
Control & Status
Register
Divider
Circuit
Alarm Register
CE
IRQ /FOUT
2
I C or 3-wire
Interface
SCL/SCLK
SDA/I/O
DT & USER
EEPROM
IFS
VSS
Note: IFS pin is used for selecting I2C interface or 3-wire interface.
I2C interface is selected when IFS is unconnected.
3-wire interface is selected when IFS is connected to VSS.
Pin Assignment
I2 C
3 -W ir e In te r fa c e
In te r fa c e
X 1
X 1
2
7
3
6
4
5
X 2
8
V B A T
V S S
V D D
1
IR Q /F O U T
C E
S D A
V S S
H T 1 3 8 2
8 D IP -A /S O P -A /M S O P -A
Rev. 1.50
9
IR Q /F O U T
8
S C L K
7
I/O
6
N C
2
V B A T
S C L
V D D
1 0
1
X 2
3
4
5
H T 1 3 8 2
1 0 M S O P -A
2
July 24, 2014
HT1382
Pad Assignment
(0 ,0 )
X 1
1
X 2
V B A T
C E
2
8
5
S C L K
7
6
V D D
IR Q /F O U T
9
4
IF S
V S S
1 0
3
S D A
Chip size: 1245 × 1520 (μm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Pad Coordinates
Pad No.
Unit: mm
X
Y
Pad No.
X
Y
1
−520.005
-161.460
6
−520.005
−646.610
2
−520.005
-256.460
7
521.000
−625.000
3
−520.005
-360.130
8
521.000
−530.000
4
−520.005
−455.130
9
521.000
−425.300
5
−520.005
−550.130
10
516.450
-288.400
Pin Description
Pad No.
Pin Name
I/O
Description
1
X1
I
32768Hz crystal input pin
2
X2
O
32768Hz crystal output pin
3
VBAT
—
Battery power supply
4
CE
I
Not used for I2C interface
Chip Enable for 3-Wire interface
5
IFS
I
Interface selection pin.
I2C interface is selected when IFS is unconnected, 3-wire interface
is selected when IFS is connected to VSS.
6
VSS
—
Negative power supply, ground
7
SDA/I/O
I/O
Serial Data Input/Output for I2C and 3wire interfaces
8
SCL/SCLK
I/O
Serial Clock input for I2C and 3-wire interfaces
9
IRQ/FOUT
O
Interrupt/Frequency Output, this pin is open drain output
10
VDD
—
Positive power supply
Rev. 1.50
3
July 24, 2014
HT1382
Approximate Internal Connections
IFS, CE
SCL, SCLK
SDA, I/O
VDD
VDD
VDD
GND
GND
X1, X2
GND
IRQ/FOUT
X2
X1
GND
GND
Absolute Maximum Ratings
Supply Voltage .......................... VSS-0.3V to VSS+6.0V
Storage Temperature ............................ -50˚C to 125˚C
Input Voltage............................. VSS-0.3V to VDD+0.3V
Operating Temperature........................... -40˚C to 85˚C
Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device
reliability.
Rev. 1.50
4
July 24, 2014
HT1382
D.C. Characteristics
Symbol
Parameter
Ta=-40˚C~85˚C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
V
VDD
Supply Voltage
―
―
2.7
―
5.5
VBAT
Battery Supply Voltage
―
―
2.0
―
5.5
V
ISTB
Standby Current
―
VBAT=3V, "CH"=1
―
―
0.1
μA
IBAT
Battery Supply Current
―
VBAT=3V, "CH"=0
―
0.8
1.2
μA
SCL/SCLK=0Hz,
"LPM"=1
―
5
15
―
15
30
―
50
100
―
70
150
3V
μA
IDD1
Supply Current (Low Power Mode)
IDD2
Supply Current
IDD3
Supply Current with I2C Active
IDD4
Supply Current with 3-wire Active
VIH
“H” Input Voltage
―
―
0.7VDD
―
―
V
VIL
“L” Input Voltage
―
―
―
―
0.3VDD
V
3V
IOH1=-1.5mA
2.7
―
―
5V
IOH1=-3.0mA
4.5
―
―
3V
IOL1=3.0mA
0
―
0.4
5V
IOL1=6.0mA
0
―
0.4
3V
IOL2=1.5mA
0
―
0.4
5V
IOL2=3.0mA
0
―
0.4
VOH
I/O High Level Output Voltage
VOL1
I/O, SCL and SDA Low Level
Output Voltage
VOL2
IRQ Low Level Output Voltage
VCOMP
VBATHYS
Rev. 1.50
5V
3V
5V
3V
5V
SCL/SCLK=0Hz,
"LPM"=0
SCLK=400kHz
―
80
150
―
150
300
3V
SCLK=1MHz
―
100
200
5V
SCLK=2MHz
―
300
500
μA
μA
μA
V
V
V
VBAT Mode Compared Voltage
―
―
2.40
2.55
2.70
V
Hysteresis
―
―
―
25
―
mV
VBAT Hysteresis
―
―
―
40
―
mV
5
July 24, 2014
HT1382
A.C. Characteristics
Power-Down Timing
VDD=2.7V~5.5V, Ta=-40˚C~85˚C
Symbol
tFSR
Parameter
Conditions
Min.
Typ.
Max.
Unit
―
―
―
10
V/ms
VDD Falling Slew Rate
Note: In order to ensure proper timekeeping, the tFSR specification must be followed.
I2C Interface
Symbol
Parameter
Remark
Min.
Typ.
Max.
Unit
fSCL
Clock frequency
―
―
―
400
kHz
tHIGH
Clock High Time
―
600
―
―
ns
tLOW
Clock Low Time
―
1300
―
―
ns
tr
SDA and SCL Rise Time
Note
―
―
300
ns
tf
SDA and SCL Fall Time
Note
―
―
300
ns
tHD:STA
START Condition Hold Time
After this period, the first clock pulse
is generated.
600
―
―
ns
tSU:STA
START Condition Setup Time
Only relevant for repeated START
condition.
600
―
―
ns
tHD:DAT
Data Input Hold Time
―
0
―
―
ns
tSU:DAT
Data Input Setup Time
―
100
―
―
ns
tSU:STO
STOP Condition Setup Time
―
600
―
―
ns
tAA
Output Valid from Clock
―
―
―
900
ns
1300
―
―
ns
―
―
50
ns
tBUF
Bus Free Time
Time in which the bus must be free
before a new transmission can start
tSP
Input Filter Time Constant
(SDA and SCL Pins)
Noise suppression time
Note: These parameters are periodically sampled but not 100% tested.
Rev. 1.50
6
July 24, 2014
HT1382
3-Wire Interface
Ta=-40˚C~85 ˚C
Symbol
Parameter
fSCLK
Serial Clock
tDC
Data to Clock Setup
tCDH
Clock to Data Hold
tCDD
Clock to Data Delay
tCL
Clock Low Time
tCH
Clock High Time
tr
tf
Clock Rise and Fall time
tCC
CE to Clock Setup
tCCH
Clock to CE Hold
tCWH
CE Inactive Time
tCDZ
CE to I/O High Impedance
Rev. 1.50
Test Conditions
Conditions
VDD
Min.
Typ.
Max.
3V
―
―
―
1
5V
―
―
―
2
3V
―
100
―
―
5V
―
50
―
―
3V
―
140
―
―
5V
―
70
―
―
3V
―
―
―
400
5V
―
―
―
200
3V
―
500
―
―
5V
―
250
―
―
3V
―
500
―
―
5V
―
250
―
―
3V
―
―
―
1000
5V
―
―
―
500
3V
―
2
―
―
5V
―
1
―
―
3V
―
120
―
―
5V
―
60
―
―
3V
―
2
―
―
5V
―
1
―
―
3V
―
―
―
140
5V
―
―
―
70
7
Unit
MHz
ns
ns
ns
ns
ns
ns
μs
ns
μs
ns
July 24, 2014
HT1382
Timing Diagrams
Power-Down Timing
I2C Interface
SDA
tBUF
tSU:DAT
tf
tLOW
tHD:STA
tr
tSP
SCL
tHD:SDA
tHD:DAT
S
tHIGH
tSU:STA
tAA
tSU:STO
P
Sr
S
SDA
OUT
3-Wire Interface
Read Data Transfer
Write Data Transfer
tC W H
C E
S C L K
tC D H
tD C
I/O
7
0
tC C H
tf
tC L
7
0
C o m m a n d B y te
Rev. 1.50
tr
tC H
tC C
In p u t D a ta B y te
8
July 24, 2014
HT1382
Crystal Specifications
Symbol
Battery Backup Mode (VBAT) to Normal Mode (VDD)
To switch from the V BAT to V DD mode, one of the
following conditions must be valid:
Parameter
Min.
Typ.
Max. Unit
f0
Nominal Frequency
―
32.768
―
kHz
VDD>VBAT+VBATHYS or VDD>VCOMP+VCOMPHYS
ESR
Series Resistance
―
35
50
kΩ
CL
Load Capacitance
―
12.5
―
pF
The power control situation is illustrated graphically
below:
Note: 1. It is strongly recommended to use a crystal
with load capacitance 12.5pF.
Battery
Backup
Mode
VDD
2. The oscillator selection can be optimized
using a high quality resonator with small
ESR value. Refer to crystal manufacturer for
more details: www.microcrystal.com
VCOMP
VBAT
VBAT-VBATHYS
2.55V
2.0V
VBAT+VBATHYS
Note: Battery switchover when VBAT < VCOMP
Functional Description
Battery Backup
Mode
VDD
VBAT
VCOMP
The HT1382 is a low power real time clock device
which provides full date and time functions. Communication with the device is provided through two
integral serial interfaces, I2C or 3-wire. The device
version selects the type of interface. The clock and
calendar information is generated in BCD format and
also has alarm features. The calendar is accurate until
the year 2099, with automatic leap year correction.
VCOMP
3.0V
2.55V
VCOMP+VCOMPHYS
Note: Battery switchover when VBAT > VCOMP
Low Power Mode
In normal mode, the HT1382 switched into battery
backup mode when the VDD power is lost. This will
ensure that the device can accept a wide range of
backup voltages from many types of sources while
reliably switching into backup mode. Another mode,
called Low Power Mode, is available to allow direct
switching from VDD to VBAT without requiring VDD to
drop below VCOMP. The power switchover circuit is
disabled and less power is used while operating from
VDD. The Low Power Mode is activated using the
LPM bit.
Basic timing is provided using an external 32768Hz
crystal, for which the device includes load capacitances
of 12.5pF. An oscillator compensation function is provided to compensate for crystal oscillator temperatures.
With fully integrated power control circuitry which
can detect power failures, the device can automatically
switch to a reserve battery supply when a power failure
occurs.
Power Control Function
The Low Power Mode is useful when VDD is normally
higher than VBAT. The device will switch from VDD to
VBAT when VDD drops below VBAT, with about 40mV
of hysteresis to prevent any switchback of VDD after
switchover. In a system with VDD=5V and VBAT= 3V,
the Low Power Mode can be used. However, it is
not recommended to use the Low Power Mode in
VDD = 3.3V±10%, VBAT≥3V.
The internal battery switchover circuit continually
monitors the main power supply on the VDD pin and
automatically switches to the backup battery supply
when a power failure condition is detected.
In the battery backup mode, the interface is disabled
to minimise power consumption. The interface inputs
will not be recognised which prevents extraneous data
being written to the device. The interface outputs are
high-impedance. All RTC functions are operational
when the device is in the battery backup mode.
Normal Mode (VDD) to Battery Backup Mode (VBAT)
To switch from the VDD to VBAT mode, both of the
following conditions must be valid:
VDD<VBAT-VBATHYS and VDD<VCOMP
Rev. 1.50
9
July 24, 2014
HT1382
Clock Compensation
Set FO3~FO0= “1010”, the FOUT pin will have 1Hz
clock pulse output. Measure the FOUT frequency
using a high-accuracy frequency counter with 7 or
more digits. The correction value is calculated using
the formula shown below.
The device includes a digital trimming method for
clock error correction due to temperature variations
of the crystal oscillator. This can be implemented as
manufacturing calibration or user active calibration.
The crystal accuracy to temperature characteristic is
similar to that shown in the accompanying diagram.
Correction value = integral value
1Hz − (measured value)
minimum resolution (3.052ppm or 1.014ppm)
When clock compensation is used, set FO3~FO0=
“1010”, and the FOUT pin will have 1Hz clock pulse
output. The cycle changes once in 10 seconds or in 30
seconds as shown below. In the diagram “a” denotes a
non-correctional cycle, and “b” denotes a correctional
cycle. Measure “a” and “b” using a high-accuracy
frequency counter of 7 or more digits. Calculate the
average frequency based on the measured result.
For DTS = 0, the average period = (a × 9 + b) ÷ 10
For DTS = 1, the average period = (a × 29 + b) ÷ 30
The Digital Trimming Register, DT, is used for
clock compensation. Correction is performed once
every 10 seconds or 30 seconds. The minimum
resolution is 3.052ppm or 1.017ppm and the device
has a correction in the range of ±192.276ppm or
±64.071ppm.
a
a
a
9 times or 29 times
Rev. 1.50
b
a
Once
10
July 24, 2014
HT1382
Register Description
The device includes 16 registers which are used to control functions such as the RTC, Status, Alarm, Frequency
output etc. There are also five bytes of EEPROM which contain the clock compensation settings and stored user
data. The RTC and Alarm register data is stored in BCD format, while other data is stored in binary format. The
register map shows the address definitions for the I2C interface. The command byte and R/W bit are used for the
3-wire interface.
Address
Register Definition
D7
D6
D5
D4
D3
D2
D1
D0
Register Range
Bit Command
Default
Name
Data
R/W
Byte
00H
CH
10 SEC
SEC
Seconds 00~59
80H
W
R
10000000
10000001
01H
0
10 MIN
MIN
Minutes
00~59
00H
W
R
10000010
10000011
02H
12/
24
0
0
HR
HR
HOUR
Hours
01~12
00~23
12H
W
R
10000100
10000101
03H
0
0
10 DATE
DATE
Date
01~31
01H
W
R
10000110
10000111
04H
0
0
0
10M
MONTH
Month
01~12
01H
W
R
10001000
10001001
05H
0
0
0
0
Day
01~07
01H
W
R
10001010
10001011
Year
00~99
00H
W
R
10001100
10001101
06H
AP
10
0
DAY
10 YEAR
YEAR
07H
WP
0
0
0
0
0
0
0
ST
—
80H
W
R
10001110
10001111
08H
ARE
0
0
EWE
EB
AI
BE
0
ST
—
00H
W
R
10010000
10010001
09H
IME
AE
INT
—
00H
W
R
10010010
10010011
0AH
SECEN
AL. 10SEC
AL. SEC
Seconds
00~59
Alarm
00H
W
R
10010100
10010101
0BH
MINEN
AL. 10MIN
AL. MIN
Minutes
Alarm
00~59
00H
W
R
10010110
10010111
0CH
HREN
0
AL. 10HR
AL. HOUR
Hours
Alarm
01~12
00~23
00H
W
R
10011000
10011001
0DH
DTEN
0
AL. 10DT
AL. DATE
Date
Alarm
01~31
00H
W
R
10011010
10011011
0EH
MOEN
0
0
AL.
10M
AL. MONTH
Month
Alarm
01~12
00H
W
R
10011100
10011101
0FH
DAYEN
0
0
0
Day
Alarm
01~07
00H
W
R
10011110
10011111
DT
—
—
W
R
10100000
10100001
LPM OEOBM FO3 FO2 FO1 FO0
0
AL. DAY
EEPROM Data
10H
DTS
DT6 DT5
DT4
DT3 DT2 DT1 DT0
11H
EEPROM User Data
USR
—
—
W
R
10100010
10100011
12H
EEPROM User Data
USR
—
—
W
R
10100100
10100101
13H
EEPROM User Data
USR
—
—
W
R
10100110
10100111
14H
EEPROM User Data
USR
—
—
W
R
10101000
10101001
Rev. 1.50
11
July 24, 2014
HT1382
Real Time Clock Register
EEPROM Write Enable Bit – EWE
The RTC register stores the Year, Day, Month, Date,
Hours, Minutes and Second data inBCDformat.
When EWE is cleared to “0”, the EEPROM is read
only, and the user can not write data to the EEPROM.
When EWE is set to “1”, the user can write data to the
EEPROM. Before writing data to the EEPROM, this
bit must be set to “1”.
12/24 Hour Mode
Bit D7 of the hour register is defined as the 12-hour
or 24-hour mode select bit. If the bit is “1”, the RTC
uses a 24-hour format. If “0”, the RTC uses a 12-hour
format. The default value is “0.
EEPROM Busy Status Bit – EB
This bit is set to “1” when a write operation to the
EEPROM has not completed. When this bit is set to
“1”, reading data from the EEPROM or writing data
to the EEPROM is invalid. After an EEPROM write
operation has finished, this bit will be cleared to “0”
and the user can read data from the EEPROM or write
data to the EEPROM.
AM/PM Mode
There are two function for the D5 bit in the hour
register which is determined by the D7 bit. In the 12hour mode the bit is used for AM/PM selection. When
D5 is “1”, it will be PM, otherwise it will be AM. In
the 24-hour mode, the bit is used to set the second 10hour bit (20~23 hours).
Output Enable On Battery Mode Bit – OEOBM
Leap Years
This bit enables/disables the IRQ/FOUT pin in the
battery mode. When the OEOBM bit is set to “1”, the
IRQ/FOUT pin is disabled in the battery mode and
the frequency output and alarm function are disabled.
When the OEOBMbit is cleared to “0”, the IRQ/
FOUT pin is enabled in the battery mode.
Leap years add an extra day for February 29 and are
defined as those years that are divisible by 4. The device will provide automatic correction for leap years
until the year 2099.
Clock HALT Bit – CH
Low Power Mode Bit – LPM
This bit enables/disables the oscillator. The CH bit is
set high to disable the oscillator and cleared to zero is
enable it. The default value is defined as “1”.
This bit enables/disables the Low Power Mode. When
the LPM bit is cleared to “0”, the device will be in the
normal mode and will use the VBAT supply when VDD
< VBAT and VDD < VCOMP. When the LPM bit is set to
“1”, the device is in the Low Power Mode and uses
the VBAT supply when VDD < VBAT.
Write Protect Bit – WP
TheWP bit is set high to prevent data writes and
cleared to zero to allow data to be written. The default
value is define as “1”.
Frequency Output Bits – FO3~FO0
Battery Enable Bit – BE
These bits enable/disable the frequency output function and select the output frequency at the FOUT pin.
The frequency selection table is shown below. It overrides the alarm mode. The 1, 1/2, 1/4, 1/8, 1/16, 1/32
frequency outputs are compensated.
When the device enters the battery backup mode, the
BE bit is set to “1”. This bit can be cleared to “0”
either manually by the user or automatically reset by
the ARE pin. Only a “0” an be written to this bit, not a
“1”.
Alarm Interrupt Bit – AI
When the RTC register values match the alarm
register values, the AI bit will be set to “1”. This bit
can be reset to “0” either manually by the user or
automatically reset by the ARE pin. Only a “0” an be
written to this bit, not a “1”. The AI bit will be set by
an alarm occurring during a read operation ad will
remain set until after the read operation is complete.
Auto Reset Enable Bit – ARE
FOUT (Hz)
FO3
FO2
FO1
―
0
0
0
FO0
0
32768
0
0
0
1
4096
0
0
1
0
1024
0
0
1
1
64
0
1
0
0
32
0
1
0
1
16
0
1
1
0
8
0
1
1
1
4
1
0
0
0
2
This bit enables/disables the automatic reset of the
BE and AI status bits only. When ARE is set to “1”,
BE and AI will be reset to “0” after reading these
registers. When ARE is cleared to “0”, the user must
manually reset the BE and AI bits.
1
0
0
1
1
1
0
1
0
1/2
1
0
1
1
Alarm Enable Bit – AE
1/4
1
1
0
0
1/8
1
1
0
1
1/16
1
1
1
0
1/32
1
1
1
1
This bit enables/disables the alarm function. When
the AE bit is set to “1”, the alarm function is enabled.
When the AE bit is cleared to “0”, the alarm function
is disabled.
Rev. 1.50
12
July 24, 2014
HT1382
Interrupt Mode Enable Bit − IME
EEPROM User Data
This bit enables/disables the interrupt mode of the
alarm function. When the IME bit is set to “1”, the
interrupt mode is enabled and when the IME bit is
cleared to “0”, the interrupt mode is disabled and the
alarm operates in single mode.
The HT1382 provides 4 bytes EEPROM for user. The
EEPROM will continue to operate in battery backup
mode. However, it should be noted that the I2C/3-wire
interface is disabled in battery backup mode. User
must detect the status of EB bit before reading data
or writing data. If the EB bit is “0”, it is valid to read
data or write data. If the EB bit is “1”, it is invalid to
read data or write data.
Alarm Register
The addresses of alarm registers are 0Bh to 10h. The
data is stored in the BCD format. The MSB of each
alarm register is an enable bit. (enable=“1”). These
enable bits specify which alarm registers are used to
make the comparison between the alarm registers and
the RTC registers. There is no alarm byte for year.
When a compare match condition exists, the AI bit is
set to “1”, and the IRQ pin is activated.
Digital Trimming Setting Bits − DTS
This bit sets the digital trimming resolution and
adjustment time. The user must detect the status of the
EB bit before reading data or writing data. If the EB
bit is “0”, it is valid to read data or write data. If the
EB bit is “1”, it is invalid to read data or write data.
To clear an alarm, the AI bit must be cleared to “0”. If
the ARE bit is set to “1”, the AI bit will automatically
be cleared when the status register is read.
Digital Trimming Bits − DT6~DT0
This digital trimming bit, DT6, is the sign bit. A “0”
indicates positive calibration and a “1” indicates
negative calibration. DT5~DT0 are the calibration
values and the adjustable range is -63 ~ +63. If DTS is
cleared to “0”, the correction range is -192.276ppm to
+192.276ppm and if DTS is set to “1”, the correction
range is -64.071ppm to +64.071ppm. The user must
detect the status of EB bit before reading data or
writing data. If the EB bit is “0”, it is valid to read
data or write data. If the EB bit is “1”, it is invalid to
read data or write data.
There are two alarm operation modes: Single mode
and Interrupt Mode.
Single mode: set the AE bit to “1”, the IME bit to
“0”, and disable the frequency output. When the
RTC register values match the alarm registers values,
the AI bit will be set to “1” and the alarm condition
activates the IRQ pin. The IRQ pin will remain low
until the AI bit is cleared to “0”.
Interrupt mode: set the AE bit to “1”, the IME bit to
“1”, and disable the frequency output. When the RTC
registers values match the alarm registers values, the
IRQ pin will be pulled low for 250ms and the AI bit
will be set to “1”. This mode allows for a repetitive
or recurring alarm function. When the alarm is set,
the device will continue to activate an alarm for each
match of the alarm and the present time. For example,
if only the seconds are set, it will activate an alarm
every minute, if only the minutes are set, it will
activate an alarm every hour.
Rev. 1.50
13
July 24, 2014
HT1382
DTS = “0”
DTS = “1”
Adjustment time
Every 10 seconds
Every 30 seconds
Minimum resolution
3.052ppm
1.017ppm
Correction range
-192.276ppm to +192.276ppm
-64.071ppm to + 64.071ppm
Correction Value (ppm)
DT6
DT5
DT4
DT3
DT2
DT1
DT0
Value
DTS=“0”
DTS=“1”
0
1
1
1
1
1
1
+63
+192.276
+64.071
0
1
1
1
1
1
0
+62
+189.224
+63.054
0
1
1
1
1
0
1
+61
+186.172
+62.037
0
1
1
1
1
0
0
+60
+183.120
+61.020
:
:
:
:
:
:
0
0
0
0
0
1
1
+3
+9.156
+3.051
0
0
0
0
0
1
0
+2
+6.104
+2.034
0
0
0
0
0
0
1
+1
+3.052
+1.017
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
-1
-3.052
-1.07
1
0
0
0
0
1
0
-2
-6.104
-2.034
1
0
0
0
0
1
1
-3
-9.156
-3.051
:
:
:
:
:
:
1
1
1
1
1
0
0
-60
-183.120
-61.020
1
1
1
1
1
0
1
-61
-186.172
-62.037
1
1
1
1
1
1
0
-62
-189.224
-63.054
1
1
1
1
1
1
1
-63
-192.276
-64.071
Rev. 1.50
14
July 24, 2014
HT1382
I2C Serial Interface
Acknowledge
Each bytes of eight bits is followed by one
acknowledge bit. This acknowledge bit is a low
level placed on the bus by the receiver. The master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge (ACK) after the reception of each byte.
The HT1382 includes an I C serial interface. The I C
bus is used for bidirectional, two-line communication
between multiple I2C devices. The two lines of the
interface are the serial data line (SDA) and the serial
clock line (SCL). Both lines are connected to the positive supply via a pull-up resistor externally.
2
2
The acknowledging device must first pull down the
SDA line during the acknowledge clock pulse so
that it remains LOW during the HIGH period of this
clock pulse. Amaster receiver must signal an end of
data to the slave by generating a not-acknowledge
(NACK) bit on the last byte that has been clocked
out of the slave. In this case, the master receiver must
leave the data line HIGH during the 9th pulse to not
acknowledge. The master will generate a STOP or
repeated START condition.
When the bus is free, both lines will be high. The
output stages of the devices connected to the bus
must have open-drain or open-collector output types
to implement the wired-AND function necessary for
connection. Data transfer is initiated only when the
bus is not busy.
Data Validity
The data on the SDAline must be stable during the
HIGH period of the clock. The HIGH or LOWstate of
the data line can only change when the clock signal
on the SCL line is LOW.
DATA OUTPUT
BY TRANSMITER
not acknowledge
SDA
DATA OUTPUT
BY RECEIVER
SCL
SCL FROM
MASTER
acknowledge
Data line stable; Change of data
Data valid
allowed
START and STOP Conditions
2
7
8
9
clk pulse for
acknowledgement
Device Addressing
A HIGH to LOWtransition on the SDA line while
SCL is HIGH defines a START condition. A LOW
to HIGH transition on the SDA line while SCL is
HIGH defines a STOP condition. START and STOP
conditions are always generated by the master.
The bus is considered to be busy after the START
condition. The bus is considered to be free again a
certain time after the STOP condition. The bus stays
busy if a repeated START(Sr) is generated instead
of a STOP condition. In this respect, a START(S)
and repeated START(Sr) conditions are functionally
identical.
The slave address byte is the first byte received
following the START condition from the master
device. The first seven bits of the first byte make
up the slave address. The eighth bit defines a read
or write operation to be performed. When this R/W
bit is “1”, then a read operation is selected. A “0”
selects a write operation. The device address bits
are “1101000”. When an address byte is sent, the
device compares the first seven bits after the START
condition. If they match, the device outputs an
acknowledge on the SDA line.
MSB
LSB
SDA
SDA
1
SCL
SCL
S
STOP condition
SDA
Rev. 1.50
2
7
8
9
ACK
1
2
3-8
1
0
0
0 R/W
• Byte Write Operation
A byte write operation requires a START condition,
a slave address with R/W bit, a valid Register
Address, the required Data and a STOP condition.
After each of the three byte transfers, the device
responds with an ACK.
Every byte put on the SDA line must be 8-bits long.
The number of bytes that can be transmitted per
transfer is unrestricted. Each byte has to be followed
by an acknowledge bit. Data is transferred with the
most significant bit (MSB) first.
1
0
Write Operation
Byte Format
S
or
Sr
1
The first byte after the START
P
START condition
SCL
1
S
START
condition
9
ACK
P
Slave Address
Sr
S 1 1 0 1 0 0 0 0
P
or
Sr
Write
15
Register Address (An)
Data (n)
P
ACK
ACK
ACK
July 24, 2014
HT1382
Byte Write Sequence
R/W Signal
The LSB of the Command Byte determines whether
the data in the register is to be read or be written to. If
it is “0” then this means that it is a write cycle. If it is
“1” then this means that it is a read cycle.
• Page Write Operation
Following a START condition and slave address,
a R/W bit is placed on the bus which indicates to
the addressed device that a Register Address will
follow which is to be written to the address pointer.
The data to be written to the memory follows next
and the internal address pointer is incremented
to the next address location on the reception of
an acknowledge clock. After reaching memory
location 0Fh, the pointer will be reset to 00h.
Slave Address
Register Address(An)
Data(n)
Data(n+1)
When the Command Byte is 10111110 or 10111111,
the device is configured in the burst mode. In this
mode, the address of registers from 00h to 0Fh can be
written or read in series, starting with bit 0 of register
address 0.
Data(n+x)
Data Input and Data Out
P
S1 1 0 1 0 0 0 0
Write
Burst Mode
ACK
ACK
ACK
ACK
ACK
In writing a data byte, R/W is cleared to “0” in the
Command Byte and is then followed by the corresponding data register address on the rising edge of
the next eight SCLK. Additional SCLK cycles are
ignored. Data inputs are entered starting with bit 0. In
reading data from the register, the R/W is set to “1”
in the Command Byte. The data bits are output on the
falling edge of the next eight SCLK cycles. Note that
the first data bit to be transmitted on the first falling
edge after the last bit of the read command byte is
written. Additional SCLK cycles re-transmit the data
bytes as long as CE remains at high level. Data outputs are read starting with bit 0.
ACK
Page Write Sequence
Read Operation
In this mode, the master reads the device data after
setting the slave address. Following the R/W bit
(=“0”) and the acknowledge bit, the register address
(An) is written to the address W pointer. Next the
START condition and slave address are repeated
followed by the R/W bit (=“1”). The data which was
addressed is then transmitted. The address pointer is
only incremented on reception of an acknowledge
clock. The device will then place the data at address
An+1 on the bus. The master reads and acknowledges
the new byte and the address pointer is incremented
to “An+2”. After reaching the memory location
0Fh, the pointer will be reset to 00h. This cycle of
reading consecutive addresses will continue until the
master sends a STOP condition. This cycle of reading
consecutive addresses will continue until the master
sends a STOP condition.
Slave Address
0
I/O
A 0
2
3
4
5
A 1
A 2
A 3
A 4
6
0
7
0
1
2
3
4
5
6
7
1
C o m m a n d B y te
D a ta I/O
• Burst Mode Transfer
S C L K
ACK
Data(n)
Data(n+1)
C E
Data(n+x)
0
P
S 1 1 0 1 0 0 0 1
ACK
R /W
1
P
ACK
Slave Address
Read
C E
Register Address(An)
S 1 1 0 1 0 0 0 0
Write
• Single Byte Transfer
S C L K
ACK
ACK
ACK
I/O
ACK
R /W
1
2
1
3
1
4
1
1
5
1
C o m m a n d B y te
Read Sequence
6
0
7
0
7
0
7
1
D a ta B y te 0
D a ta B y te 1 5
3-wire Serial Interface
The device also support a 3-wire serial interface. The
CE pin is used to identify the transmitted data. The
transmission is controlled by the active HIGH signal
CE. Each data transfer is a byte, with the LSB sent
first. The first byte transmitted is the Command Byte.
Command Byte
For each data transfer, a Command Byte is initiated
to specify which register is accessed. This is to
determine whether a read or write cycle is operational
and whether a single byte or burst mode transfer is to
occur.
Rev. 1.50
16
July 24, 2014
HT1382
Application Circuit
I2C Serial Interface
V
C 1
V
R 2
D D
V D D
B A T
V B A T
4 .7 k S C L
V
0 .1 F
V
D D
R 3
D D
X 1
4 .7 k V
R 1
S D A
3 2 7 6 8 H z
X 2
D D
4 .7 k V S S
IR Q /F O U T
3-wire Serial Interface
V
C 1
0 .1 F
V
D D
V D D
B A T
V B A T
C E
S C L K
I/O
V
R 1
X 1
D D
4 .7 k IR Q /F O U T
Rev. 1.50
17
3 2 7 6 8 H z
X 2
V S S
July 24, 2014
HT1382
Package Information
Note that the package information provided here is for consultation purposes only. As this information may be
updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package
information.
Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be
transferred to the relevant website page.
• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• Packing Meterials Information
• Carton information
Rev. 1.50
18
July 24, 2014
HT1382
8-pin DIP (300mil) Outline Dimensions
Symbol
Min.
Nom.
Max.
A
0.355
0.365
0.400
B
0.240
0.250
0.280
C
0.115
0.130
0.195
D
0.115
0.130
0.150
E
0.014
0.018
0.022
F
0.045
0.060
0.070
G
—
0.100 BSC
—
H
0.300
0.310
0.325
I
—
—
0.430
Symbol
Rev. 1.50
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
10.16
A
9.02
9.27
B
6.10
6.35
7.11
C
2.92
3.30
4.95
D
2.92
3.30
3.81
E
0.36
0.46
0.56
F
1.14
1.52
1.78
G
—
2.54 BSC
—
H
7.26
7.87
8.26
I
—
—
10.92
19
July 24, 2014
HT1382
8-pin SOP (150mil) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
—
0.236 BSC
—
B
—
0.154 BSC
—
0.020
C
0.012
—
C'
—
0.193 BSC
—
D
—
—
0.069
E
—
0.050 BSC
—
F
0.004
—
0.010
G
0.016
—
0.050
H
0.004
—
0.010
α
0°
—
8°
Symbol
Rev. 1.50
Dimensions in mm
Min.
Nom.
Max.
A
—
6.00 BSC
—
B
—
3.90 BSC
—
C
0.31
—
0.51
C'
—
4.90 BSC
—
D
—
—
1.75
E
—
1.27 BSC
—
F
0.10
—
0.25
G
0.40
—
1.27
H
0.10
—
0.25
α
0°
―
8°
20
July 24, 2014
HT1382
8-pin MSOP Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
—
—
0.043
A1
0.000
—
0.006
A2
0.030
0.033
0.037
B
0.009
—
0.015
C
0.003
—
0.009
D
—
0.118 BSC
—
E
—
0.193 BSC
—
E1
—
0.118 BSC
—
e
—
0.026 BSC
—
L
0.016
0.024
0.031
L1
—
0.037 BSC
—
y
—
0.004
—
θ
0°
—
8°
Symbol
Rev. 1.50
Dimensions in mm
Min.
Nom.
Max.
A
—
—
1.10
A1
0.00
—
0.15
A2
0.75
0.85
0.95
B
0.22
—
0.38
C
0.08
—
0.23
D
—
3.00 BSC
—
E
—
4.90 BSC
—
E1
—
3.00 BSC
—
e
—
0.65 BSC
—
L
0.40
0.60
0.80
L1
—
0.95 BSC
—
y
—
0.10
—
θ
0°
—
8°
21
July 24, 2014
HT1382
10-pin MSOP Outline Dimensions
Symbol
Nom.
Max.
A
—
—
0.043
A1
0.000
—
0.006
A2
0.030
0.033
0.037
B
0.007
—
0.013
C
0.003
—
0.009
D
—
0.118 BSC
—
E
—
0.193 BSC
—
E1
—
0.118 BSC
—
e
—
0.020 BSC
—
L
0.016
0.024
0.031
L1
—
0.037 BSC
—
y
—
0.004
—
θ
0°
—
8°
Symbol
Rev. 1.50
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
—
—
1.10
A1
0.00
—
0.15
A2
0.75
0.85
0.95
B
0.17
—
0.33
C
0.08
—
0.23
D
—
3.00 BSC
—
E
—
4.90 BSC
—
E1
—
3.00 BSC
—
e
—
0.50 BSC
—
L
0.40
0.60
0.80
L1
—
0.95 BSC
—
y
—
0.10
—
θ
0°
—
8°
22
July 24, 2014
HT1382
Copyright© 2014 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw.
Rev. 1.50
23
July 24, 2014