TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM HT67F30/HT67F40/HT67F50/HT67F60 Revision: V1.80 Date: August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Table of Contents Features.............................................................................................................. 7 CPU Features.......................................................................................................................... 7 Peripheral Features.................................................................................................................. 7 General Description........................................................................................... 8 Selection Table................................................................................................... 9 Block Diagram.................................................................................................. 10 Pin Assignment................................................................................................ 10 Absolute Maximum Ratings............................................................................ 22 D.C. Characteristics......................................................................................... 22 A.C. Characteristics......................................................................................... 27 ADC Characteristics........................................................................................ 28 Comparator Electrical Characteristics.......................................................... 29 Power-on Reset Characteristics..................................................................... 29 LCD D.C. Characteristics ............................................................................... 30 System Architecture........................................................................................ 31 Clocking and Pipelining.......................................................................................................... 31 Program Counter.................................................................................................................... 32 Stack...................................................................................................................................... 33 Arithmetic and Logic Unit – ALU............................................................................................ 33 Flash Program Memory................................................................................... 34 Structure................................................................................................................................. 34 Special Vectors...................................................................................................................... 34 Look-up Table......................................................................................................................... 35 Table Program Example......................................................................................................... 35 In Circuit Programming.......................................................................................................... 35 RAM Data Memory................................................................................................................. 37 Structure................................................................................................................................. 37 Special Function Register Description.......................................................... 43 Indirect Addressing Registers – IAR0, IAR1.......................................................................... 43 Memory Pointers – MP0, MP1............................................................................................... 43 Bank Pointer – BP.................................................................................................................. 44 Accumulator – ACC................................................................................................................ 45 Program Counter Low Register – PCL................................................................................... 45 Look-up Table Registers – TBLP, TBHP, TBLH...................................................................... 46 Status Register – STATUS..................................................................................................... 46 EEPROM Data Memory......................................................................................................... 48 EEPROM Data Memory Structure......................................................................................... 48 EEPROM Registers............................................................................................................... 48 Reading Data from the EEPROM.......................................................................................... 51 Rev. 1.80 2 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Writing Data to the EEPROM................................................................................................. 51 Write Protection...................................................................................................................... 51 EEPROM Interrupt................................................................................................................. 51 Programming Considerations................................................................................................. 52 Oscillator.......................................................................................................... 53 Oscillator Overview................................................................................................................ 53 System Clock Configurations................................................................................................. 53 External Crystal/ Ceramic Oscillator – HXT........................................................................... 54 External RC Oscillator – ERC................................................................................................ 55 Internal RC Oscillator – HIRC................................................................................................ 56 External 32.768kHz Crystal Oscillator – LXT......................................................................... 56 LXT Oscillator Low Power Function....................................................................................... 57 Internal 32kHz Oscillator – LIRC............................................................................................ 57 External Clock – EC............................................................................................................... 57 Supplementary Oscillators..................................................................................................... 57 Operating Modes and System Clocks........................................................... 58 System Clocks....................................................................................................................... 58 System Operation Modes....................................................................................................... 60 Control Register..................................................................................................................... 61 Fast Wake-up......................................................................................................................... 62 Operating Mode Switching and Wake-up............................................................................... 64 NORMAL Mode to SLOW Mode Switching............................................................................ 64 SLOW Mode to NORMAL Mode Switching............................................................................ 66 Entering the SLEEP0 Mode................................................................................................... 66 Entering the SLEEP1 Mode................................................................................................... 66 Entering the IDLE0 Mode....................................................................................................... 67 Entering the IDLE1 Mode....................................................................................................... 67 Standby Current Considerations............................................................................................ 67 Wake-up................................................................................................................................. 68 Programming Considerations................................................................................................. 68 Watchdog Timer............................................................................................... 69 Watchdog Timer Clock Source............................................................................................... 69 Watchdog Timer Control Register.......................................................................................... 69 Watchdog Timer Operation.................................................................................................... 70 Reset and Initialisation........................................................................................................... 71 Reset Functions..................................................................................................................... 71 Reset Initial Conditions.......................................................................................................... 74 Input/Output Ports........................................................................................... 85 Pull-high Resistors................................................................................................................. 88 Port A Wake-up...................................................................................................................... 90 I/O Port Control Registers...................................................................................................... 90 Pin-remapping Functions....................................................................................................... 92 Pin-remapping Registers........................................................................................................ 92 I/O Pin Structures................................................................................................................... 98 Programming Considerations................................................................................................. 98 Rev. 1.80 3 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Timer Modules – TM........................................................................................ 99 Introduction............................................................................................................................ 99 TM Operation....................................................................................................................... 100 TM Clock Source.................................................................................................................. 100 TM Interrupts........................................................................................................................ 100 TM External Pins.................................................................................................................. 100 TM Input/Output Pin Control Registers................................................................................ 101 Programming Considerations............................................................................................... 109 Compact Type TM.................................................................................................................110 Compact TM Operation.........................................................................................................110 Compact Type TM Register Description...............................................................................111 Compact Type TM Operating Modes....................................................................................114 Compare Match Output Mode...............................................................................................114 Timer/Counter Mode.............................................................................................................115 PWM Output Mode................................................................................................................116 Standard Type TM – STM.............................................................................. 118 Standard TM Operation.........................................................................................................118 Standard Type TM Register Description...............................................................................119 Standard Type TM Operating Modes................................................................................... 124 Compare Output Mode......................................................................................................... 124 Timer/Counter Mode............................................................................................................ 126 PWM Output Mode............................................................................................................... 126 Single Pulse Mode............................................................................................................... 128 Capture Input Mode............................................................................................................. 129 Enhanced Type TM – ETM............................................................................. 131 Enhanced TM Operation...................................................................................................... 131 Enhanced Type TM Register Description............................................................................. 132 Enhanced Type TM Operating Modes................................................................................. 137 Compare Output Mode......................................................................................................... 138 Timer/Counter Mode............................................................................................................ 140 PWM Output Mode............................................................................................................... 140 Single Pulse Mode............................................................................................................... 144 Capture Input Mode............................................................................................................. 146 Analog to Digital Converter.......................................................................... 148 A/D Overview....................................................................................................................... 148 A/D Converter Register Description..................................................................................... 148 A/D Converter Data Registers – ADRL, ADRH.................................................................... 149 A/D Converter Control Registers – ADCR0, ADCR1, ACERL, ACERH............................... 149 A/D Operation...................................................................................................................... 154 A/D Input Pins...................................................................................................................... 155 Summary of A/D Conversion Steps...................................................................................... 156 Programming Considerations............................................................................................... 157 A/D Transfer Function.......................................................................................................... 157 A/D Programming Example.................................................................................................. 157 Rev. 1.80 4 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Comparators.................................................................................................. 159 Comparator Operation......................................................................................................... 159 Comparator Registers.......................................................................................................... 159 Comparator Interrupt............................................................................................................ 159 Programming Considerations............................................................................................... 160 Serial Interface Module – SIM....................................................................... 162 SPI Interface........................................................................................................................ 162 SPI Registers....................................................................................................................... 164 SPI Communication............................................................................................................. 167 I2C Interface......................................................................................................................... 169 I2C Bus Communication....................................................................................................... 175 I2C Bus Start Signal.............................................................................................................. 176 Slave Address...................................................................................................................... 176 I2C Bus Read/Write Signal................................................................................................... 176 I2C Bus Slave Address Acknowledge Signal........................................................................ 176 I2C Bus Data and Acknowledge Signal................................................................................ 177 Serial Interface – SPIA ........................................................................................................ 178 SPIA Interface Operation..................................................................................................... 179 SPIA Registers..................................................................................................................... 180 SPIA Communication.................................................................................... 182 Peripheral Clock Output................................................................................ 184 Peripheral Clock Operation.................................................................................................. 184 Interrupts........................................................................................................ 185 Interrupt Registers................................................................................................................ 185 Interrupt Operation............................................................................................................... 193 External Interrupt.................................................................................................................. 197 Comparator Interrupt............................................................................................................ 197 Multi-function Interrupt......................................................................................................... 197 A/D Converter Interrupt........................................................................................................ 198 Time Base Interrupts............................................................................................................ 198 Serial Interface Module Interrupt.......................................................................................... 200 External Peripheral Interrupt................................................................................................ 200 Serial Interface Interrupt....................................................................................................... 200 EEPROM Interrupt............................................................................................................... 201 LVD Interrupt........................................................................................................................ 201 TM Interrupts........................................................................................................................ 201 Interrupt Wake-up Function.................................................................................................. 202 Programming Considerations............................................................................................... 202 Power Down Mode and Wake-up.................................................................. 203 Entering the IDLE or SLEEP Mode...................................................................................... 203 Standby Current Considerations.......................................................................................... 203 Wake-up............................................................................................................................... 203 Rev. 1.80 5 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Low Voltage Detector – LVD......................................................................... 204 LVD Register........................................................................................................................ 204 LVD Operation...................................................................................................................... 205 LCD Driver...................................................................................................... 205 LCD Memory........................................................................................................................ 207 LCD Registers...................................................................................................................... 209 LCD Reset Function............................................................................................................. 210 Clock Source........................................................................................................................ 210 LCD Driver Output................................................................................................................ 210 LCD Voltage Source and Biasing......................................................................................... 212 LCD Waveform Timing Diagrams ........................................................................................ 213 Programming Considerations............................................................................................... 220 Configuration Options.......................................................................................................... 221 Application Circuits....................................................................................... 223 Instruction Set................................................................................................ 224 Introduction.......................................................................................................................... 224 Instruction Timing................................................................................................................. 224 Moving and Transferring Data.............................................................................................. 224 Arithmetic Operations........................................................................................................... 224 Logical and Rotate Operations............................................................................................. 224 Branches and Control Transfer............................................................................................ 225 Bit Operations...................................................................................................................... 225 Table Read Operations........................................................................................................ 225 Other Operations.................................................................................................................. 225 Instruction Set Summary.............................................................................. 226 Table conventions................................................................................................................ 226 Instruction Definition..................................................................................... 228 Package Information..................................................................................... 238 48-pin LQFP (7mmx7mm) Outline Dimensions................................................................... 238 64-pin LQFP (7mmx7mm) Outline Dimensions................................................................... 239 80-pin LQFP (10mmx10mm) Outline Dimensions............................................................... 240 100-pin LQFP (14mmx14mm) Outline Dimensions............................................................. 241 Rev. 1.80 6 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Features CPU Features ●● Operating Voltage: fSYS= 4MHz: 2.2V~5.5V fSYS= 8MHz: 2.4V~5.5V fSYS= 12MHz: 2.7V~5.5V fSYS= 16MHz: 4.5V~5.5V ●● Up to 0.25us instruction cycle with 16MHz system clock at VDD=5V ●● Power down and wake-up functions to reduce power consumption ●● Six oscillators: External Crystal - HXT External 32.768kHz Crystal - LXT External RC - ERC External Clock - EC Internal RC - HIRC Internal 32kHz RC - LIRC ●● Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP ●● Fully integrated internal 4MHz, 8MHz and 12MHz oscillator requires no external components ●● All instructions executed in one or two instruction cycles ●● Table read instructions ●● 63 powerful instructions ●● Up to 12-level subroutine nesting ●● Bit manipulation instruction Peripheral Features ●● Flash Program Memory: 2Kx15 ~ 12Kx16 ●● RAM Data Memory: 128x8 ~ 640x8 ●● EEPROM Memory: 64x8 ~ 256x8 ●● Watchdog Timer function ●● Up to 64 bidirectional I/O lines ●● LCD driver function ●● Multiple pin-shared external interrupts ●● Multiple Timer Module for time measure, input capture, compare match output, PWM output or single pulse output function ●● Serial Interfaces Module with Dual SPI and I2C interfaces ●● Single Serial SPI Interface ●● Dual Comparator functions ●● Dual Time-Base functions for generation of fixed time interrupt signals ●● Multi-channel 12-bit resolution A/D converter ●● Low voltage reset function ●● Low voltage detect function ●● Wide range of available package types Rev. 1.80 7 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● Flash program memory can be re-programmed up to100,000 times ●● Flash program memory data retention > 10 years ●● EEPROM data memory can be re-programmed up to 1,000,000 times ●● EEPROM data memory data retention > 10 years General Description The HT67FXX series of devices are Flash Memory A/D with LCD type 8-bit high performance RISC architecture microcontrollers, designed for applications that interface directly to analog signals and which require an LCD interface. Offering users the convenience of Flash Memory multiprogramming features, these devices also include a wide range of functions and features. Other memory includes an area of RAM Data Memory as well as an area of EEPROM memory for storage of non-volatile data such as serial numbers, calibration data etc. Analog features include a multi-channel 12-bit A/D converter and dual comparator functions. Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM generation functions. Communication with the outside world is catered for by including fully integrated SPI or I2C interface functions, two popular interfaces which provide designers with a means of easy communication with external peripheral hardware. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of HXT, LXT, ERC, HIRC and LIRC oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. The inclusion of flexible I/O programming features, Time-Base functions along with many other features ensure that the devices will find excellent use in applications such as electronic metering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. Rev. 1.80 8 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Selection Table Most features are common to all devices, the main feature distinguishing them are Memory capacity, I/O count, TM features, stack capacity, LCD driver and package types. The following table summarises the main features of each device. Part No. VDD Program Memory Data Memory Data EEPROM I/O Ext. Interrupt LCD HT67F30 2.2V~5.5V 2Kx15 128x8 64x8 32 2 20x4 21x3 21x2 HT67F40 2.2V~5.5V 4Kx15 256x8 128x8 44 2 32x4 33x3 33x2 HT67F50 2.2V~5.5V 8Kx16 384x8 256x8 52 2 40x4 41x3 41x2 HT67F60* 2.2V~5.5V 12Kx16 640x8 256x8 64 4 56x4 57x3 57x2 Part No. A/D Timer Module Interface SPI Stack Package HT67F30 12-bitx8 10-bit CTMx1, 10-bit ETMx1 SPI/I2C, SPI √ 4 48 LQFP HT67F40 12-bitx8 10-bit CTMx1, 10-bit ETMx1, 16-bit STMx1 SPI/I2C, SPI √ 8 48/64 LQFP HT67F50 12-bitx8 10-bit CTMx2, 10-bit ETMx1, 16-bit STMx1 SPI/I2C, SPI √ 8 48/64/80 LQFP HT67F60* 12-bitx12 10-bit CTMx2, 10-bit ETMx1, 16-bit STMx1 SPI/I2C, SPI √ 12 48/64/80 LQFP 100 LQFP Note: * Under development, available in 2Q, 2011. Rev. 1.80 9 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Block Diagram Low Voltage Detect Watchdog Timer Reset Circuit Low Voltage Reset Interrupt Controller Stack Flash/EEPROM Programming Circuitry (ICP) Flash Program Memory 8-bit RISC MCU Core EEPROM Data Memory ERC/EC/HXT Oscillator HIRC Oscillator RAM Data Memory TB0/TB1 LIRC/LXT Oscillator 12-Bit A/D Converter Comparators I/O LCD Driver SPI TM0 SIM TM1 TMn Pin Assignment Rev. 1.80 10 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM 11 Rev. 1.80 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Rev. 1.80 12 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM 13 August 08, 2012 Rev. 1.80 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Rev. 1.80 14 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Pin Description The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. ●● HT67F30 Pin Name Rev. 1.80 Function OP I/T O/T Pin-Shared Mapping PA0~PA7 Port A PAWU PAPU ST CMOS — PB0~PB5 Port B PBPU ST CMOS — PC0~PC1 Port C PCPU ST CMOS — PD0~PD7 Port D PDPU ST CMOS — PE0~PE7 Port E PEPU ST CMOS — AN0~AN7 ADC input ACERL AN — PA0~PA7 VREF ADC reference input ADCR1 AN — PB5 C0-, C1- Comparator 0, 1 input AN — PA3, PC1 C0+, C1+ Comparator 0, 1 input AN — PA2, PC0 C0X, C1X Comparator 0, 1 output — CMOS PA0, PA5 or PE2, PE6 or PE3,PE7 TCK0, TCK1 TM0, TM1 input — ST — PA2, PA4 or PE0,PE1 TP0_0, TP0_1 TM0 I/O TMPC0 ST CMOS PA0, PA7or PD0, PD1 TP1A TM1 I/O TMPC0 ST CMOS PA1 or PD2 TP1B_0, TP1B_1 TM1 I/O TMPC0 ST CMOS PC0, PC1 or PD3, PD4 INT0, INT1 Ext. interrupt 0, 1 — ST — PA3, PA4 or PE4,PE5 PINT Peripheral interrupt — ST — PA4 PCK Peripheral clock output — — CMOS PA5 SDI SPI data input — ST — PC0 SDO SPI data output — — CMOS PC1 SCS SPI slave select — ST CMOS PA6 SCK SPI serial clock — ST CMOS PA7 CP0C CP1C PRM0 SCL I C clock — ST NMOS PA7 SDA I2C data — ST NMOS PC0 SDIA SPIA data input — ST — PA2 2 SDOA SPIA data output — — CMOS PA3 SCSA SPIA slave select — ST CMOS PA0 SCKA SPIA serial clock — ST CMOS PA1 OSC1 HXT/ERC pin CO HXT — PB1 OSC2 HXT pin CO — HXT PB2 XT1 LXT pin CO LXT — PB3 XT2 LXT pin CO — LXT PB4 RES Reset input CO ST — PB0 VDD Power supply * — PWR — — AVDD ADC power supply * — PWR — — VSS Ground ** — PWR — — AVSS ADC ground ** — PWR — — VLCD LCD power supply — PWR — — 15 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Pin Name OP I/T O/T Pin-Shared Mapping VMAX IC maximum voltage, connect to VDD, VLCD1 or V1 Function — PWR — — V1,V2,C1,C2 LCD voltage pump — — — — SEG0~7 LCD segment output — — CMOS PD0~PD7 SEG8~15 LCD segment output — — CMOS PE0~PE7 SEG16~19, 24 LCD segment output — — CMOS — COM0~3 — — CMOS — LCD common output Note: I/T: Input type; O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option; ST: Schmitt Trigger input CMOS: CMOS output; NMOS: NMOS output AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator *: VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded together internally with VDD. **: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together internally with VSS. As the Pin Description Summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. ●● HT67F40 Pin Name Rev. 1.80 Function OP I/T O/T Pin-Shared Mapping PAWU PAPU ST CMOS — PA0~PA7 Port A PB0~PB5 Port B PBPU ST CMOS — PC0~PC5 Port C PCPU ST CMOS — PD0~PD7 Port D PDPU ST CMOS — PE0~PE7 Port E PEPU ST CMOS — PF0~PF7 Port F PFPU ST CMOS — AN0~AN7 ADC input ACERL AN — PA0~PA7 VREF ADC reference input ADCR1 AN — PB5 AN — PA3, PC3 C0-, C1- Comparator 0, 1 input CP0C CP1C C0+, C1+ Comparator 0, 1 input CP0C CP1C AN — PA2, PC2 C0X, C1X Comparator 0, 1 output CP0C CP1C PRM0 — CMOS PA0, PA5 or PE2,PE6 or PE3, PE7 TCK0~TCK2 TM0~TM2 input PRM1 ST — PA2, PA4, PC2 or PE0, PE1, PE2 TP0_0, TP0_1 TM0 I/O TMPC0 PRM2 ST CMOS PA0, PC5 or PD0, PD1 TP1A TM1 I/O TMPC0 PRM2 ST CMOS PA1 or PD2 TP1B_0~TP1B_2 TM1 I/O TMPC0 PRM2 ST CMOS PC0, PC1, PC5 or PD3,PD4,PD5 16 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Pin Name Function OP I/T O/T Pin-Shared Mapping TMPC1 PRM2 ST CMOS PC3, PC4 or PD6, PD7 TP2_0, TP2_1 TM2 I/O INT0, INT1 Ext. Interrupt 0, 1 PRM1 ST — PA3, PA4 or PE4, PE5 PINTB Peripheral Interrupt PRM0 ST — PA4 or PC0 PCK Peripheral Clock output PRM0 — CMOS PA5 or PC1 SDI SPI Data input PRM0 ST — PC0 or PC4 SDO SPI Data output PRM0 — CMOS PC1 or PC5 SCS SPI Slave Select PRM0 ST CMOS PA6 or PC2 SCK SPI Serial Clock PRM0 ST CMOS PA7 or PC3 SCL I C Clock PRM0 ST NMOS PA7 or PC3 SDA I2C Data PRM0 ST NMOS PC0 or PC4 SDIA SPIA Data input — ST — PA2 SDOA SPIA Data output — — CMOS PA3 SCSA SPIA Slave Select — ST CMOS PA0 SCKA SPIA Serial Clock — ST CMOS PA1 OSC1 HXT/ERC pin CO HXT — PB1 2 OSC2 HXT pin CO — HXT PB2 XT1 LXT pin CO LXT — PB3 XT2 LXT pin CO — LXT PB4 RES Reset input CO ST — PB0 VDD Power supply * — PWR — — AVDD ADC power supply * — PWR — — VSS Ground ** — PWR — — AVSS ADC ground ** — PWR — — VLCD LCD power supply — PWR — — VMAX IC maximum voltage, connect to VDD, VLCD1 or V1 — PWR — — V1,V2,C1,C2 LCD voltage pump — — — — SEG0~7 LCD segment output — — CMOS PD0~PD7 SEG8~15 LCD segment output — — CMOS PE0~PE7 SEG16~23 LCD segment output — — CMOS PF0~PF7 SEG24~32 LCD segment output — — CMOS — COM0~3 LCD common output — — CMOS — Note: I/T: Input type; O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option; ST: Schmitt Trigger input CMOS: CMOS output; NMOS: NMOS output AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator *: VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded together internally with VDD. **: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together internally with VSS. Rev. 1.80 As the Pin Description Summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. 17 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● HT67F50 Pin Name PA0~PA7 Rev. 1.80 Function Port A OP I/T O/T Pin-Shared Mapping PAWU PAPU ST CMOS — PB0~PB7 Port B PBPU ST CMOS — PC0~PC5 Port C PCPU ST CMOS — PD0~PD7 Port D PDPU ST CMOS — PE0~PE7 Port E PEPU ST CMOS — PF0~PF7 Port F PFPU ST CMOS — PG0~PG5 Port G PGPU ST CMOS — AN0~AN7 ADC input ACERL AN — PA0~PA7 VREF ADC reference input ADCR1 AN — PB5 AN — PA3, PC3 C0-, C1- Comparator 0, 1 input CP0C CP1C C0+, C1+ Comparator 0, 1 input CP0C CP1C AN — PA2, PC2 C0X, C1X Comparator 0, 1 output CP0C CP1C PRM0 — CMOS PA0, PA5 or PE2,PE6 or PE3, PE7 TCK0~TCK3 TM0~TM3 input PRM1 ST — PA2, PA4, PC2, PC4 or PE0, PE1, PE2, TP0_0, TP0_1 TM0 I/O TMPC0 PRM2 ST CMOS PA0, PC5 or PD0,PD1 TP1A TM1 I/O TMPC0 PRM2 ST CMOS PA1 or PD2 TP1B_0~TP1B_2 TM1 I/O TMPC0 PRM2 ST CMOS PC0, PC1, PC5 or PD3, PD4, PD5 TP2_0, TP2_1 TM2 I/O TMPC1 PRM2 ST CMOS PC3, PC4 or PD6,PD7 TP3_0, TP3_1 TM3 I/O TMPC1 PRM2 ST CMOS PG0, PG3 or PF0,PF1 INT0, INT1 Ext. Interrupt 0, 1 PRM1 ST — PA3, PA4 or PE4,PE5 PINTB Peripheral Interrupt PRM0 ST — PA4 or PC0 or PG0 PCK Peripheral Clock output PRM0 — CMOS PA5 or PC1 or PG1 SDI SPI Data input PRM0 ST — PC0 or PC4 or PG4 SDO SPI Data output PRM0 — CMOS PC1 or PC5 or PG5 SCS SPI Slave Select PRM0 ST CMOS PA6 or PC2 or PG2 SCK SPI Serial Clock PRM0 ST CMOS PA7 or PC3 or PG3 SCL I C Clock PRM0 ST NMOS PA7 or PC3 or PG3 SDA I2C Data PRM0 ST NMOS PC0 or PC4 or PG4 PA2 2 SDIA SPIA Data input — ST — SDOA SPIA Data output — — CMOS PA3 SCSA SPIA Slave Select — ST CMOS PA0 SCKA SPIA Serial Clock — ST CMOS PA1 OSC1 HXT/ERC pin CO HXT — PB1 PB2 OSC2 HXT pin CO — HXT XT1 LXT pin CO LXT — PB3 XT2 LXT pin CO — LXT PB4 18 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM OP I/T O/T Pin-Shared Mapping RES Pin Name Reset input Function CO ST — PB0 VDD Power supply * — PWR — — AVDD ADC power supply * — PWR — — VSS Ground ** — PWR — — AVSS ADC ground ** — PWR — — VLCD LCD power supply — PWR — — VMAX IC maximum voltage, connect to VDD, VLCD1 or V1 — PWR — — V1,V2,C1,C2 LCD voltage pump — — — — SEG0~7 LCD segment output — — CMOS PD0~PD7 SEG8~15 LCD segment output — — CMOS PE0~PE7 SEG16~23 LCD segment output — — CMOS PF0~PF7 SEG24~40 LCD segment output — — CMOS — COM0~3 LCD common output — — CMOS — Note: I/T: Input type; O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option; ST: Schmitt Trigger input CMOS: CMOS output; NMOS: NMOS output AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator *: VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded together internally with VDD. **: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together internally with VSS. Rev. 1.80 As the Pin Description Summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. 19 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● HT67F60 Pin Name PA0~PA7 Rev. 1.80 Function Port A OP I/T O/T Pin-Shared Mapping PAWU PAPU ST CMOS — PB0~PB7 Port B PBPU ST CMOS — PC0~PC7 Port C PCPU ST CMOS — PD0~PD7 Port D PDPU ST CMOS — PE0~PE7 Port E PEPU ST CMOS — PF0~PF7 Port F PFPU ST CMOS — PG0~PG7 Port G PGPU ST CMOS — PH0~PH7 Port H PHPU ST CMOS — AN0~AN11 ADC input ACERH AN — PA0~PA7, PH0~PH3 VREF ADC reference input ADCR1 AN — PB5 AN — PA3, PC3 C0-, C1- Comparator 0, 1 input CP0C CP1C C0+, C1+ Comparator 0, 1 input CP0C CP1C AN — PA2, PC2 C0X, C1X Comparator 0, 1 output CP0C CP1C PRM0 — CMOS PA0, PA5 or PE2, PE6 or PE3, PE7 TCK0~TCK3 TM0~TM3 input PRM1 ST — PA2, PA4, PC2, PC4 or PE0, PE1, PE2, TP0_0, TP0_1 TM0 I/O TMPC0 PRM2 ST CMOS PA0, PC5 or PD0,PD1 TP1A TM1 I/O TMPC0 PRM2 ST CMOS PA1 or PD2 TP1B_0~TP1B_2 TM1 I/O TMPC0 PRM2 ST CMOS PC0, PC1, PC5 or PD3,PD4,PD5 TP2_0, TP2_1 TM2 I/O TMPC1 PRM2 ST CMOS PC3, PC4 or PD6,PD7 TP3_0, TP3_1 TM3 I/O TMPC1 PRM2 ST CMOS PG3, PG0 or PF0,PF1 INT0~INT3 Ext. Interrupt 0~3 PRM1 ST — PA3, PA4, PC4, PC5 or,PE4,PE5,PE6 PINTB Peripheral Interrupt PRM0 ST — PA4 or PC0 or PG0 PCK Peripheral Clock output PRM0 CMOS PA5 or PC1 or PG1 SDI SPI Data input PRM0 ST — PC0 or PC4 or PG4 SDO SPI Data output PRM0 — CMOS PC1 or PC5 or PG5 SCS SPI Slave Select PRM0 ST CMOS PA6 or PC2 or PG2 SCK SPI Serial Clock PRM0 ST CMOS PA7 or PC3 or PG3 SCL I2C Clock PRM0 ST NMOS PA7 or PC3 or PG3 SDA I C Data PRM0 ST NMOS PC0 or PC4 or PG4 SDIA SPIA Data input — ST — PA2 2 SDOA SPIA Data output — — CMOS PA3 SCSA SPIA Slave Select — ST CMOS PA0 SCKA SPIA Serial Clock — ST CMOS PA1 OSC1 HXT/ERC pin CO HXT — PB1 OSC2 HXT pin CO — HXT PB2 XT1 LXT pin CO LXT — PB3 20 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM OP I/T O/T Pin-Shared Mapping XT2 Pin Name LXT pin Function CO — LXT PB4 RES Reset input CO ST — PB0 VDD Power supply * — PWR — — AVDD ADC power supply * — PWR — — VSS Ground ** — PWR — — AVSS ADC ground ** — PWR — — VLCD LCD power supply — PWR — — VMAX IC maximum voltage, connect to VDD, VLCD1 or V1 — PWR — — V1,V2,C1,C2 LCD voltage pump — — — — SEG0~7 LCD segment output — — CMOS PD0~PD7 SEG8~15 LCD segment output — — CMOS PE0~PE7 SEG16~23 LCD segment output — — CMOS PF0~PF7 SEG24~31 LCD segment output — — CMOS PH6~PH7, PB6~PB7, PG6~PG7, PC6~PC7 SEG32~56 LCD segment output — — CMOS — COM0~3 LCD common output — — CMOS — Note: I/T: Input type; O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option; ST: Schmitt Trigger input CMOS: CMOS output; NMOS: NMOS output AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator *: VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded together internally with VDD. **: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together internally with VSS. Rev. 1.80 As the Pin Description Summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. 21 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Absolute Maximum Ratings Supply Voltage .................................................................................................VSS-0.3V to VSS+6.0V Input Voltage ...................................................................................................VSS-0.3V to VDD+0.3V IOL Total ....................................................................................................80mA Total Power Dissipation ......................................................................................................... 500mW Storage Temperature ................................................................................................... -50°C to 125°C Operating Temperature ................................................................................................. -40°C to 85°C IOH Total...................................................................................................-80mA Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol VDD IDD1 IDD2 Parameter Operating Voltage (HXT, ERC, HIRC) Operating Current (Crystal OSC, fSYS=fH, fS=fSUB=fLXT or fLIRC) Operating Current (ERC OSC, fSYS=fH, fS=fSUB=fLXT or fLIRC) Ta=25°C VDD — 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 5V IDD3 Rev. 1.80 Operating Current (HIRC OSC, fSYS=fH, fS=fSUB=fLXT or fLIRC) 3V 5V 3V 5V 3V 5V Test Conditions Conditions fSYS=4MHz fSYS=8MHz fSYS=12MHz (HIRC, Crystal) fSYS=12MHz (Resonator) fSYS=16MHz (Crystal) No load, fH=455kHz, ADC off, WDT enable No load, fH=1MHz, ADC off, WDT enable No load, fH=4MHz, ADC off, WDT enable No load, fH=8MHz, ADC off, WDT enable No load, fH=12MHz, ADC off, WDT enable No load, fH=16MHz, ADC off, WDT enable No load, fH=455kHz, ADC off, WDT enable No load, fH=1MHz, ADC off, WDT enable No load, fH=4MHz, ADC off, WDT enable No load, fH=8MHz, ADC off, WDT enable No load, fH=12MHz, ADC off, WDT enable No load, fH=16MHz, ADC off, WDT enable No load, fH=4MHz, ADC off, WDT enable No load, fH=8MHz, ADC off, WDT enable No load, fH=12MHz, ADC off, WDT enable 22 Min. Typ. Max. Unit 2.2 2.4 2.7 4.5 4.5 — — — — — — — — — — — — — — — — — — — — — — — — — — — 100 300 240 480 400 0.8 0.8 1.6 1.2 2.4 1.6 3.2 120 240 200 400 500 1 1 2 1.5 3.0 5.5 5.5 5.5 5.5 5.5 150 450 360 720 600 1.2 1.2 2.4 1.8 3.6 2.4 4.8 180 360 300 600 750 1.5 1.5 3.0 2.75 4.5 V V V V V µA µA µA µA µA mA mA mA mA mA mA mA µA µA µA µA µA mA mA mA mA mA — 4.0 6.0 µA — — — — — — 400 0.8 0.8 1.6 1.2 2.4 600 1.2 1.2 2.4 1.8 3.6 µA mA mA mA mA mA August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Symbol IDD4 IDD5 Parameter Operating Current (EC Mode, fSYS=fH, fS=fSUB=fLXT or fLIRC) Operating Current (Crystal OSC, fSYS=fL, fS=fSUB=fLXT or fLIRC) VDD 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V IDD6 Operating Current (Crystal OSC, fSYS=fL, fS=fSUB=fLXT or fLIRC) 5V 3V 5V 3V IDD7 Operating Current (Crystal OSC, fSYS=fL, fS=fSUB=fLXT or fLIRC) 5V 3V 5V IDD8 IDD8a IDD9 Rev. 1.80 Operating Current (RTC OSC, fSYS=fL=fLXT, fS=fSUB=fLXT) (Except HT67F50, HT67F60) Operating Current (RTC OSC, fSYS=fL=fLXT, fS=fSUB=fLXT) (HT67F50, HT67F60) Operating Current (LIRC OSC, fSYS=fL=fLIRC, fS=fSUB=fLIRC) (Except HT67F50, HT67F60) 3V 5V 3V 5V 3V 5V 3V 5V Test Conditions Conditions No load, fH=4MHz, ADC off, WDT enable No load, fH=8MHz, fL=fH/2, ADC off, WDT enable No load, fH=8MHz, fL=fH/4, ADC off, WDT enable No load, fH=8MHz, fL=fH/8, ADC off, WDT enable No load, fH=8MHz, fL=fH/16, ADC off, WDT enable No load, fH=8MHz, fL=fH/32, ADC off, WDT enable No load, fH=8MHz, fL=fH/64, ADC off, WDT enable No load, fH=4MHz, fL=fH/2, ADC off, WDT enable No load, fH=4MHz, fL=fH/2, ADC off, WDT enable No load, fH=4MHz, fL=fH/4, ADC off, WDT enable No load, fH=4MHz, fL=fH/4, ADC off, WDT enable No load, fH=12MHz, fL=fH/2, ADC off, WDT enable No load, fH=12MHz, fL=fH/2, ADC off, WDT enable No load, fH=12MHz, fL=fH/4, ADC off, WDT enable No load, fH=12MHz, fL=fH/4, ADC off, WDT enable No load, ADC off, WDT enable, QOSC=0 No load, ADC off, WDT enable, QOSC=1 No load, ADC off, WDT enable, QOSC=0 No load, ADC off, WDT enable, QOSC=1 3V Min. Typ. Max. Unit — 360 480 µA — 720 1080 µA — — — — — — — — — — — — 500 1 350 0.7 300 600 280 560 250 500 230 440 750 1.5 525 1.05 450 900 420 840 375 750 345 660 µA mA µA mA µA µA µA µA µA µA µA µA — 300 600 µA — 600 900 µA — 200 300 µA — 400 600 µA — 0.8 1.2 mA — 1.6 2.4 mA — 0.5 0.75 mA — 1 1.5 mA — 10 15 µA — 20 30 µA — 10 15 µA — 20 30 µA — 20 30 µA — 40 60 µA — 20 30 µA — 40 60 µA — 10 15 µA — 20 30 µA No load, ADC off, WDT enable 5V 23 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Symbol IDD9a IDD10 IDD10a ISTB1 ISTB2 ISTB3 ISTB4 ISTB5 ISTB7 ISTB8 ISTB9 Rev. 1.80 Parameter Operating Current (LIRC OSC, fSYS=fL=fLIRC, fS=fSUB=fLIRC) (HT67F50, HT67F60) Operating Current (RTC+LIRC OSC, fSYS=fL=fLXT, fS=fSUB=fLIRC) (Except HT67F50, HT67F60) Operating Current (RTC+LIRC OSC, fSYS=fL=fLXT, fS=fSUB=fLIRC) (HT67F50, HT67F60) Stanby Current (Idle) (Crystal OSC, fSYS=fH, fS=fSUB=fLXT or fLIRC) Stanby Current (Idle) (Crystal OSC, fSYS=off, fS=T1) Stanby Current (Idle) (Crystal OSC, fSYS=off, fS=fSUB=fLXT or fLIRC) Stanby Current (Idle) (ERC OSC, fSYS=off, fS=fSUB=fLXT) Stanby Current (Idle) (HIRC OSC, fSYS=off, fS=fSUB=fLIRC) Stanby Current (Idle) (Crystal OSC, fSYS=off, fS=fSUB=fLXT or fLIRC) Stanby Current (Idle) (RTC OSC, fSYS=fL=fLXT, fS=fSUB=fLXT) Stanby Current (Idle) (RTC OSC, fSYS=off, fS=T1) VDD Test Conditions Conditions 3V Min. Typ. Max. Unit — 20 30 µA — 40 60 µA — 10 15 µA — 20 30 µA — 15 30 µA — 0.3 0.5 mA — 0.5 0.8 mA — 1.5 3.0 μA — 2.5 5.0 μA — 1.5 3.0 μA — 2.5 5.0 μA — 1.5 3.0 μA — 2.5 5.0 μA — 1.5 3.0 μA — 2.5 5.0 μA — 1.5 3.0 μA — 2.5 5.0 μA — 1.9 4.0 μA — 3.3 7.0 μA — 1.5 3.0 μA — 2.5 5.0 μA No load, ADC off, WDT enable 5V 3V No load, ADC off, WDT enable, QOSC=0 5V 3V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V No load, ADC off, WDT enable, QOSC=0 No load, system HALT, ADC off, WDT enable, fSYS=8MHz, SPI or I2C on, PCK on, PCK=fSYS/8 No load, system HALT, ADC off, WDT enable, fSYS=8MHz No load, system HALT, ADC off, WDT enable, fSYS=8MHz No load, system HALT, ADC off, WDT enable, fSYS=8MHz No load, system HALT, ADC off, WDT enable, fSYS=8MHz No load, system HALT, ADC off, WDT enable, fSYS=8MHz/64 No load, system HALT, ADC off, WDT enable, fSYS=32768Hz No load, system HALT, ADC off, WDT enable, fSYS=32768Hz 24 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Symbol ISTB10 ISTB11 ISTB12 ISTB13 ISTB14 ISTB15 ISTB16 ISTB17 ISTB18 VIL1 VIH1 VIL2 VIH2 Rev. 1.80 Parameter Stanby Current (Idle) (RTC OSC, fSYS=off, fS=fSUB=fLXT) Stanby Current (Idle) (LIRC OSC, fSYS=off, fS=fSUB=fLIRC) Stanby Current (Idle) (RTC OSC, fSYS=off, fS=fSUB=fLIRC) Stanby Current (Sleep) (Crystal OSC, fSYS=off, fS=fSUB=fLXT or fLIRC) Stanby Current (Sleep) (Crystal OSC, fSYS=off, fS=fSUB=fLXT) Stanby Current (Sleep) (Crystal OSC, fSYS=off, fS=fSUB=fLIRC) Stanby Current (Sleep) (RTC OSC, fSYS=off, fS=fSUB=fLXT or fLIRC) Stanby Current (Sleep) (RTC OSC, fSYS=off, fS=fSUB=fLXT) Stanby Current (Sleep) (Crystal OSC, fSYS=off, fS=fSUB=fLXT or fLIRC) Input Low Voltage for I/O Ports, TMR and INTB Input High Voltage for I/O Ports, TMR and INTB Input Low Voltage (RES) Input High Voltage (RES) VDD 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V — Test Conditions Conditions No load, system HALT, ADC off, WDT enable, fSYS=32768Hz No load, system HALT, ADC off, WDT enable, fSYS=32kHz No load, system HALT, ADC off, WDT enable, fSYS=32768Hz No load, system HALT, ADC off, WDT disable, fSYS=12MHz No load, system HALT, ADC off, WDT enable, fSYS=12MHz No load, system HALT, ADC off, WDT enable, fSYS=12MHz No load, system HALT, ADC off, WDT disable, fSYS=32768Hz No load, system HALT, ADC off, WDT enable, fSYS=32768Hz No load, system HALT, ADC off, WDT disable, fSYS=12MHzHz, LVR enable and LVDEN=1 Min. Typ. Max. Unit — 1.5 3.0 μA — 2.5 5.0 μA — 1.5 3.0 μA — 2.5 5.0 μA — 1.5 3.0 μA — 2.5 5.0 μA — 0.1 1 μA — 0.3 2 μA — 1.5 3.0 μA — 2.5 5.0 μA — 1.5 3.0 μA — 2.5 5.0 μA — 0.1 1 μA — 0.3 2 μA — 1.5 3.0 μA — 2.5 5.0 μA — 20 30 μA — — 0 — 0.3VDD V — — 0.7VDD — VDD V — — 0 — 0.4VDD V — — 0.9VDD — VDD V 25 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Symbol Parameter VDD VLVR1 VLVR2 VLVR3 Min. LVR Enable, 2.1V option Low Voltage Reset Voltage — LVR Enable, 2.55V option LVR Enable, 3.15V option Low Voltage Reset Current — LVR Enable, LVDEN=0 Typ. Max. 2.1 -5%× Typ. LVR Enable, 4.2V option VLVR4 ILVR Test Conditions Conditions 2.55 3.15 V +5%× Typ. 4.2 — 20 Unit V V V 30 μA VLVD1 LVDEN = 1, VLVD = 2.0V 2.0 V VLVD2 LVDEN = 1, VLVD = 2.2V 2.2 V VLVD3 LVDEN = 1, VLVD = 2.4V 2.4 V VLVD4 LVDEN = 1, VLVD = 2.7V 2.7 VLVD5 Low Voltage Detector Voltage — LVDEN = 1, VLVD = 3.0V -5%× Typ. 3.0 +5%× Typ. V V VLVD6 LVDEN = 1, VLVD = 3.3V 3.3 V VLVD7 LVDEN = 1, VLVD = 3.6V 3.6 V VLVD8 LVDEN = 1, VLVD = 4.4V 4.4 V ILVD1 ILVD2 IOL Low Voltage Detector Current I/O Port Sink Current LVR disable, LVDEN = 1 — 20 30 μA LVR enable, LVDEN = 1 — 30 45 μA VOL=0.1VDD 4 8 — mA 5V VOL=0.1VDD 10 20 — mA VOH=0.9VDD -2 -4 — mA 5V VOH=0.9VDD -5 -10 — mA — 3V IOH I/O Port, Source Current 3V RPH Pull-high Resistance of I/O Ports 3V — 20 60 100 kΩ 5V — 10 30 50 kΩ AVDD Analog operating voltage — 2.7 — 5.5 V VBG Bandgap reference with buffer voltage — -3%× Typ. 1.19 +3%× Typ. V IBG Bandgap reference with buffer driving current — — 200 400 μA Rev. 1.80 VREF=AVDD — VBG is used, LVR disable, LVDEN=0 (OPA enabled) 26 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM A.C. Characteristics Ta=25°C Symbol fCPU fSYS fHIRC fERC Parameter Operating Clock System clock (HXT) System clock (HIRC) System clock (ERC) Test Conditions VDD — Min. Typ. Max. Unit 2.2~5.5V DC — 4 MHz 2.4~5.5V DC — 8 MHz 2.7~5.5V DC — 12 MHz Conditions 4.5~5.5V DC — 16 MHz 2.2~5.5V 0.4 — 4 MHz 2.2~5.5V 0.4 — 8 MHz 2.7~5.5V (Crystal) 0.4 — 12 MHz 4.5~5.5V (Resonator) 0.4 — 12 MHz 4.5~5.5V (Crystal) 0.4 — 16 MHz 3V/5V Ta=25°C -2% 4 +2% MHz 3V/5V Ta=25°C -2% 8 +2% MHz 5V Ta=25°C -2% 12 +2% MHz 3V/5V Ta=0~70°C -5% 4 +5% MHz 3V/5V Ta=0~70°C -5% 8 +5% MHz 5V — Ta=0~70°C -5% 12 +5% MHz 2.2V~3.6V Ta=0~70°C -10% 4 +10% MHz 3.0V~5.5V Ta=0~70°C -10% 4 +10% MHz 2.4V~3.6V Ta=0~70°C -7% 8 +7% MHz 3.0V~5.5V Ta=0~70°C -7% 8 +7% MHz 3.0V~5.5V Ta=0~70°C -7% 12 +7% MHz 2.2V~3.6V Ta=-40~85°C -10% 4 +10% MHz 3.0V~5.5V Ta=-40~85°C -10% 4 +10% MHz 2.4V~3.6V Ta=-40~85°C -10% 8 +10% MHz 3.0V~5.5V Ta=-40~85°C -10% 8 +10% MHz 3.0V~5.5V Ta=-40~85°C -10% 12 +10% MHz 5V Ta = 25°C External RERC = 150kΩ -2% 4 +2% MHz 5V Ta = 0~70°C External RERC = 150kΩ -5% 4 +5% MHz 5V Ta = -40~85°C External RERC = 150kΩ -7% 4 +7% MHz 3.0V~5.5V Ta = -40~85°C External RERC = 150kΩ -9% 4 +9% MHz 2.2V~5.5V Ta = -40~85°C External RERC = 150kΩ -12% 4 +12% MHz fSYS4 System Clock (32768 Crystal) — — — 32768 — Hz tRES External reset low pulse width — — 1 — — μs fSYS=XTAL or RTC OSC — 1024 1025 tSST System startup timer period (wake-up from HALT) fSYS=ERC or HIRC OSC — 15 17 fSYS=LIRC OSC — 1 3 Rev. 1.80 — 27 tSYS August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit tINT Interrupt pulse width — — 1 — — tSYS tLVR Low Voltage Width to Reset — — 120 240 480 μs tLVD Low Voltage Width to Interrupt — — 20 45 90 μs tLVDS LVDO stable time tBGS VBG turn on stable time tAD — For all VLVD, LVR disable 15 — — μs — For VLVD disable, LVR enable 25 — — μs — — 10 — — ms A/D Clock Period 2.7~5.5V — 0.5 — 100 μs tADC AD Conversion Time(note2) 2.7~5.5V — 16 — tAD tON2ST (#) ADC on to ADC start 2.7~5.5V — 2 — — μs tEERD EEPROM Read Time — — 1 2 4 tSYS tEEWR EEPROM Write Timet — — 1 2 4 ms 12 bit ADC ADC Characteristics Symbol Parameter Ta=25°C Test Conditions VDD Conditions Min. Typ. Max. Unit AVDD ADC Operating Voltage — — 2.7 — 5.5 V VADI AD Input Voltage — — 0 — VREF V VREF ADC Reference Voltage — 2 — AVDD V DNL Differential Non-linearity 5V — 1 2 LSB — tAD= 1.0μs INL Integral Non-linearity 5V tAD= 1.0μs — 2 4 LSB IADC Additional Power Consumption if A/D Converter is Used 3V No load, tAD= 0.5μs — 0.90 1.35 mA 5V No load, tAD= 0.5μs — 1.20 1.80 mA tADCK A/D Clock Period — 0.5 — 10 μs tADC A/D Conversion Time (Include A/D Sample and Hold Time) — — 16 — tADCK tSH A/D Sampling Time — — 4 — tADCK — 12-bit ADC — Note: 1. tSYS=1/fSYS 2. * For fERC, as the resistor tolerance will influence the frequency a precision resistor is recommended. 3. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor should be connected between VDD and VSS and located as close to the device as possible. Rev. 1.80 28 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Comparator Electrical Characteristics Symbol Ta=25°C Test Conditions Parameter Min. Typ. Max. Unit — 2.2 — 5.5 V 3V — — 37 56 A 5V — — 130 200 A VDD Conditions — VCMP Comparator Operating Voltage ICMP Comparator Operating Current VCMPOS Comparator Input Offset Voltage — — 10 — 10 mV VHYS Hysteresis Width — — 20 40 60 mV VCM Comparator Common Mode Voltage Range — — VSS — VDD-1.4V V AOL Comparator Open Loop Gain — — 60 80 — dB tPD Comparator Response Time — — 200 400 Ns With 100mV overdrive (Note) Note: Measured with comparator one input pin at VCM = (VDD -1.4)/2 while the other pin input transition from VSS to (VCM +100mV) or from VDD to (VCM -100mV). Power-on Reset Characteristics Symbol Ta=25°C Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV RRVDD VDD Raising Rate to Ensure Power-on Reset — — 0.035 — — V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — Ms Rev. 1.80 29 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM LCD D.C. Characteristics Symbol Parameter Ta=25°C VDD 3 ISTB1 Standby Current (Idle) (fSYS, fWDT off, fs= fSUB = 32768 or 32K RC OSC) ISTB2 Standby Current (Idle) (fSYS, fWDT off, fs= fSUB = 32768 or 32K RC OSC) ISTB3 Standby Current (Idle) (fSYS, fWDT off, fs= fSUB = 32768 or 32K RC OSC) ISTB4 Standby Current (Idle) (fSYS, fWDT off, fs= fSUB = 32768 or 32K RC OSC) ISTB5 Standby Current (Idle) (fSYS, fWDT off, fs= fSUB = 32768 or 32K RC OSC) ISTB6 Standby Current (Idle) (fSYS, fWDT off, *fs= fSUB = % 32768 or 32K RC OSC) ISTB7 Standby Current (Idle) (fSYS, fWDT off, fs= fSUB = 32768 or 32K RC OSC) ISTB8 Standby Current (Idle) (fSYS, fWDT off, fs= fSUB = 32768 or 32K RC OSC) ISTB9 Standby Current (Idle) (fSYS, fWDT off, fs= fSUB = 32768 or 32K RC OSC) ISTB10 Standby Current (Idle) (fSYS, fWDT off, fs= fSUB =32768 or 32K RC OSC) 5 IOL2 LCD Common and Segment Sink Current 5 IOH2 LCD Common and Segment Source Current 5 Rev. 1.80 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 3 3 Condition No load, system HALT, LCD on, WDT off, C type VLCD=VDD, 1/2 Bias, No load, system HALT, LCD on, WDT off, C type VLCD= VDD, 1/3 Bias, No load, system HALT, LCD on, WDT off, R type VLCD=VDD, 1/2 bias(IBIAS =7.5µA) No load, system HALT, LCD on, WDT off, R type VLCD=VDD, 1/2 bias(IBIAS =15µA) No load, system HALT, LCD on, WDT off, R type VLCD=VDD, 1/2 bias(IBIAS =45µA) No load, system HALT, LCD on, WDT off, R type VLCD=VDD, 1/2 bias(IBIAS =90µA) No load, system HALT, LCD on, WDT off, R type VLCD=VDD, 1/3 bias(IBIAS =7.5µA) No load, system HALT, LCD on, WDT off, R type VLCD=VDD, 1/3 bias(IBIAS =15µA) No load, system HALT, LCD on, WDT off, R type VLCD=VDD, 1/3 bias(IBIAS =45µA) No load, system HALT, LCD on, WDT off, R type VLCD=VDD, 1/3 bias(IBIAS =90µA) VOL=0.1VLCD VOH=0.9VLCD 30 Min. Typ. Max. Unit — 6 10 µA — 10 15 µA — 6 10 µA — 10 15 µA — 13.5 20 µA — 22.5 40 µA — 21 40 µA — 35 60 µA — 51 80 µA — 85 160 µA — 96 160 µA — 160 320 µA — 11 20 µA — 18.3 40 µA — 16 25 µA — 26.6 50 µA — 36 50 µA — 60 100 µA — 66 100 µA — 110 200 µA 210 420 — µA 350 700 — µA -80 -160 — µA -180 -360 — µA August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a HXT, LXT, HIRC, LIRC, EC or ERC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. System Clocking and Pipelining Rev. 1.80 31 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as “JMP” or “CALL” that demand a jump to a nonconsecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Program Counter Device Program Counter High Byte HT67F30 PC10~PC8 HT67F40 PC11~PC8 HT67F50 PC12~PC8 HT67F60 PC13~PC8 PCL Register PCL7~PCL0 Program Counter The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Rev. 1.80 32 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has multiple levels depending upon the device and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P ro g ra m T o p o f S ta c k S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k P o in te r B o tto m C o u n te r P ro g ra m M e m o ry S ta c k L e v e l 3 o f S ta c k S ta c k L e v e l N Device Stack Levels HT67F30 4 HT67F40/HT67F50 8 HT67F60 12 Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: ●● Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA ●● Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA ●● Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC ●● Increment and Decrement INCA, INC, DECA, DEC ●● Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Rev. 1.80 33 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device series the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, these Flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 2Kx15 bits to 12Kx16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. Device Capacity Banks HT67F30 2Kx15 0 HT67F40 4Kx15 0 HT67F50 8Kx16 0 HT67F60 12Kx16 0, 1 The HT67F60 has its Program Memory divided into two Banks, Bank 0 and Bank 1. The required Bank is selected using Bit 5 of the BP Register. Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. R e s e t R e s e t R e s e t R e s e t 0 0 2 C H In te rru p t V e c to r In te rru p t V e c to r In te rru p t V e c to r In te rru p t V e c to r 0 7 F F H 1 5 b its 0 0 0 0 H 0 0 0 4 H 0 0 3 C H 0 F F F H B a n k 0 1 5 b its 1 F F F H 1 6 b its 1 F F F H 2 0 0 0 H 2 F F F H 1 6 b its B a n k 1 Porgram Memory Structure Rev. 1.80 34 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the ”TABRD[m]” or ”TABRDL[m]” instructions, respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as0. The accompanying diagram illustrates the addressing data flow of the look-up table. A d d re s s L a s t p a g e o r T B H P R e g is te r T B L P R e g is te r D a ta 1 5 ~ 1 6 b its R e g is te r T B L H U s e r S e le c te d R e g is te r H ig h B y te L o w B y te Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is “700H” which refers to the start address of the last page within the 2K Program Memory of the HT67F30. The table pointer is setup here to have an initial value of “06H”. This will ensure that the first data read from the data table will be at the Program Memory address “706H” or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the “TABRD [m]” instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the “TABRD [m]” instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. In Circuit Programming The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a Rev. 1.80 35 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM 5-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. MCU Programming Pins Function PA0 Serial Data Input/Output PA2 Serial Clock RES Device Reset VDD Power Supply VSS Ground The Program Memory and EEPROM data memory can both be programmed serially in-circuit using this 5-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply and one line for the reset. The technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. During the programming process the RES pin will be held low by the programmer disabling the normal operation of the microcontroller and taking control of the PA0 and PA2 I/O pins for data and clock programming purposes. The user must there take care to ensure that no other outputs are connected to these two pins. Table Read Program Example tempreg1 db ? tempreg2 db ? : : mov a,06h address mov tblp,a mov a,07h tbhp,a : : tabrd tempreg1 pointer data at program TBLH ; temporary register #1 ; temporary register #2 dec tblp ; reduce value of table pointer by one ; initialise low table pointer - note that this ; is referenced ; initialise high table pointer ; transfers value in table referenced by table ; memory address 706H transferred to tempreg1 and tabrd tempreg2 ; pointer data at program ; TBLH in this ; and data 0FH to ; : : org 700h ; transfers value in table referenced by table memory address 705H transferred to tempreg2 and example the data 1AH is transferred to tempreg1 register tempreg2 sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : Rev. 1.80 36 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM W r ite r C o n n e c to r S ig n a ls M C U W r ite r _ V D D V D D R E S R E S D A T A P r o g r a m m in g P in s D A T A C L K C L K W r ite r _ V S S V S S * * * T o o th e r C ir c u it Note: * may be resistor or capacitor. The resistance of * must be greater than 1kΩ or the capacitance of * must be less than 1nF. Programmer Pin MCU Pins RES PB0 DATA PA0 CLK PA2 Programmer and MCU Pins RAM Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into three sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. The third area is reserved for the LCD Memory. This special area of Data Memory is mapped directly to the LCD display so data written into this memory area will directly affect the displayed data. The addresses of the LCD Memory area overlap those in the General Purpose Data Memory area. Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value. Rev. 1.80 37 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Structure The Data Memory is subdivided into several banks, all of which are implemented in 8-bit wide RAM. The Data Memory located in Bank 0 is subdivided into two sections, the Special Purpose Data Memory and the General Purpose Data Memory. The start address of the Data Memory for all devices is the address 00H. Registers which are common to all microcontrollers, such as ACC, PCL, etc., have the same Data Memory address. The LCD Memory is mapped into Bank 1. The Banks 2 to 5 contain only General Purpose Data Memory for those devices with larger Data Memory capacities. As the Special Purpose Data Memory registers are mapped into all bank areas, they can subsequently be accessed from any bank location. Device Capacity Banks HT67F30 128x8 0: 80H~FFH 1: 80H~98H HT67F40 256x8 0: 80H~FFH 1: 80H~A0H 2: 80H~FFH 384x8 0: 80H~FFH 1: 80H~A8H 2: 80H~FFH 3: 80H~FFH 640x8 0: 80H~FFH 1: 80H~B8H 2: 80H~FFH 3: 80H~FFH 4: 80H~FFH 5: 80H~FFH HT67F50 HT67F60 Data Memory Structure – HT67F30/40/50/60 Rev. 1.80 38 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM HT67F30 Special Purpose Data Memory Rev. 1.80 39 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM HT67F40 Special Purpose Data Memory Rev. 1.80 40 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM HT67F50 Special Purpose Data Memory Rev. 1.80 41 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM HT67F60 Special Purpose Data Memory Rev. 1.80 42 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section; however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of “00H” and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks according to BP register. Direct Addressing can only be used with Bank 0, all other Banks must be addressed indirectly using MP1 and IAR1. Note that for the HT67F30 device, bit 7 of the Memory Pointers is not required to address the full memory space. When bit 7 of the Memory Pointers for HT67F30 device is read, a value of “1” will be returned. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Indirect Addressing Program Example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov mov mov mov a,04h block,a a,offset adres1 mp0,a loop: clr inc sdz jmp IAR0 mp0 block loop ; setup size of block ; Accumulator loaded with first RAM address ; setup memory pointer with first RAM address ; clear the data at address defined by MP0 ; increment memory pointer ; check if last memory location has been cleared continue: The important point to note here is that in the example shown above, no reference is made to specific RAM addresses. Rev. 1.80 43 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Bank Pointer – BP Depending upon which device is used, the Program and Data Memory are divided into several banks. Selecting the required Program and Data Memory area is achieved using the Bank Pointer. Bit 5 of the Bank Pointer is used to select Program Memory Bank 0 or 1, while bits 0~2 are used to select Data Memory Banks 0~5. The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within any bank. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from banks other than Bank 0 must be implemented using Indirect addressing. As both the Program Memory and Data Memory share the same Bank Pointer Register, care must be taken during programming. Device HT67F30 Bit 7 6 5 4 3 2 1 0 — — — — — — — DMBP0 HT67F40 — — — — — — DMBP1 DMBP0 HT67F50 — — — — — — DMBP1 DMBP0 HT67F60 — — PMBP0 — — DMBP2 DMBP1 DMBP0 3 2 1 0 BP Registers List BP Register ●● HT67F30 Bit 7 6 5 4 Name — — — — — — — DMBP0 R/W — — — — — — — R/W POR — — — — — — — 0 Bit 7 ~ 3 Unimplemented, read as "0" Bit 0 DMBP0: Select Data Memory Banks 0: Bank 0 1: Bank 1 ●● HT67F40 Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name — — — — — — DMBP1 DMBP0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7 ~ 2 Unimplemented, read as "0" Bit 1 ~ 0 DMBP1, DMBP0: Select Data Memory Banks 00: Bank 0 01: Bank 1 10: Bank 2 11: Undefined 44 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● HT67F50 Bit 7 6 5 4 3 2 1 0 Name — — — — — — DMBP1 DMBP0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7 ~ 2 Unimplemented, read as "0" Bit 1 ~ 0 DMBP1, DMBP0: Select Data Memory Banks 00: Bank 0 01: Bank 1 10: Bank 2 11: Bank 3 ●● HT67F60 Bit 7 6 5 4 3 2 1 0 Name — — PMBP0 — — DMBP2 DMBP1 DMBP0 R/W — — R/W — — R/W R/W R/W POR — — 0 — — 0 0 0 Bit 7 ~ 6 Unimplemented, read as "0" Bit 5 PMBP0: Select Program Memory Banks 0: Bank 0, Program Memory Address is from 0000H ~ 1FFFH 1: Bank 1, Program Memory Address is from 2000H ~ 2FFFH Bit 4 ~ 3 Unimplemented, read as "0" Bit 2 ~ 0 DMBP2 ~ DMBP0: Select Data Memory Banks 000: Bank 0 001: Bank 1 010: Bank 2 011: Bank 3 100: Bank 4 101: Bank 5 110~111: Undefined Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Rev. 1.80 45 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the “INC” or “DEC” instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the “CLR WDT” or “HALT” instruction. The PDF flag is affected only by executing the ”HALT” or “CLR WDT” instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. ●● C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. ●● AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. ●● Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. ●● OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. ●● PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by executing the “HALT” instruction. ●● TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Rev. 1.80 46 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● STATUS Register Bit 7 6 5 4 3 2 1 Name — — TO PDF OV Z AC C R/W — — R R R/W R/W R/W R/W POR — — 0 0 x x x Rev. 1.80 0 x “X” unknown Bit 7, 6 Unimplemented, read as “0” Bit 5 TO: Watchdog Time-Out flag 0: After power up or executing the “CLR WDT” or “HALT” instruction 1: A watchdog time-out occurred. Bit 4 PDF: Power down flag 0: After power up or executing the “CLR WDT” instruction 1: By executing the “HALT” instruction Bit 3 OV: Overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2 Z: Zero flag 0: The result of an arithmetic or logical operation is not zeroT 1: The result of an arithmetic or logical operation is zero Bit 1 AC: Auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0 C: Carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction. 47 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM EEPROM Data Memory All devices contain an area of internal EEPROM Data Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of reprogrammable memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. EEPROM Data Memory Structure The EEPROM Data Memory capacity varies from 64x8 to 256x 8 bits, according to the device selected. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. Read and Write operations to the EEPROM are carried out in single byte operations using an address and data register in Bank 0 and a single control register in Bank 1. Device Capacity Address HT67F30 64x8 00H ~ 3FH HT67F40 128x8 00H ~ 7FH HT67F50/HT67F60 256x8 00H ~ FFH EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory. These are the address register, EEA, the data register, EED and a single control register, EEC. As both the EEA and EED registers are located in Bank 0, they can be directly accessed in the same was as any other Special Function Register. The EEC register however, being located in Bank1, cannot be directly addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register, IAR1. Because the EEC control register is located at address 40H in Bank 1, the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer register, BP, set to the value, 01H, before any operations on the EEC register are executed. EEPROM Register List ●● HT67F30 Name Bit 7 6 5 4 3 2 1 0 EEA — — D5 D4 D3 D2 D1 D0 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC — — — — WREN WR RDEN RD 7 6 5 4 3 2 1 0 EEA — D6 D5 D4 D3 D2 D1 D0 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC — — — — WREN WR RDEN RD ●● HT67F40 Name Rev. 1.80 Bit 48 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● HT67F50/HT67F60 Name Bit 7 6 5 4 3 2 1 0 EEA D7 D6 D5 D4 D3 D2 D1 D0 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC — — — — WREN WR RDEN RD Bit 7 6 5 4 3 2 1 0 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — x x x x x x EEA Register ●● HT67F30 “X” unknown Bit 7 ~ 6 Unimplemented, read as “0” Bit 5 ~ 0 Data EEPROM address Data EEPROM address bit 5 ~ bit 0 ●● HT67F40 Bit 7 6 5 4 3 2 1 0 Name — D6 D5 D4 D3 D2 D1 D0 R/W — R/W R/W R/W R/W R/W R/W R/W POR — x x x x x x x “X” unknown Bit 7 Unimplemented, read as “0” Bit 6 ~ 0 Data EEPROM address Data EEPROM address bit 6 ~ bit 0 ●● HT67F50/HT67F60 Bit 7 6 5 4 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x “X” unknown Bit 7 ~ 0 Rev. 1.80 3 Data EEPROM address Data EEPROM address bit 7 ~ bit 0 49 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● EEC Register Bit 7 6 5 4 3 2 1 0 Name — — — — WREN WR RDEN RD R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7 ~ 4 Unimplemented, read as “0” Bit 3 WREN: Data EEPROM Write Enable 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2 WR: EEPROM Write Control 0: Write cycle has finished 1: Activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high. Bit 1 RDEN: Data EEPROM Read Enable 0: Disable 1: Enablez This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations. Bit 0 RD: EEPROM Read Control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high. Note: The WREN, WR, RDEN and RD can not be set to “1” at the same time in one instruction. The WR and RD can not be set to “1” at the same time. Rev. 1.80 50 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Writing Data to the EEPROM To write data to the EEPROM, the write enable bit, WREN, in the EEC register must first be set high to enable the write function. The EEPROM address of the data to be written must then be placed in the EEA register and the data placed in the EED register. If the WR bit in the EEC register is now set high, an internal write cycle will then be initiated. Setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered-on the Write Enable bit in the control register will be cleared preventing any write operations. Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this adds a further measure of protection against spurious write operations. During normal program operation, ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. However as the EEPROM is contained within a Multi-function Interrupt, the associated multi-function interrupt enable bit must also be set. When an EEPROM write cycle ends, the DEF request flag and its associated multi-function interrupt request flag will both be set. If the global, EEPROM and Multifunction interrupts are enabled and the stack is not full, a jump to the associated Multi-function Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag will be automatically reset, the EEPROM interrupt flag must be manually reset by the application program. More details can be obtained in the Interrupt section. Rev. 1.80 51 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1 where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. Programming Examples ●● Reading data from the EEPROM – polling method MOV A, EEPROM_ADRES ; user defined address MOV EEA, A MOV A, 040H ; setup memory pointer MP1 MOV MP1, A ; MP1 points to EEC register MOV A, 01H ; setup Bank Pointer MOV BP, A SET IAR1.1 ; set RDEN bit, enable read operations SET IAR1.0 ; start Read Cycle - set RD bit BACK: SZ IAR1.0 ; check for read cycle end JMP BACK CLR IAR1 ; disable EEPROM read/write CLR BP MOV A, EEDATA ; move read data to register MOV READ_DATA, A ●● Writing Data to the EEPROM – polling method MOV A, EEPROM_ADRES ; user defined address MOV EEA, A MOV A, EEPROM_DATA ; user defined data MOV EED, A MOV A, 040H ; setup memory pointer MP1 MOV MP1, A ; MP1 points to EEC register MOV A, 01H ; setup Bank Pointer MOV BP, A SET IAR1.3 ; set WREN bit, enable write operations SET IAR1.2 ; start Write Cycle - set WR bit BACK: SZ IAR1.2 ; check for write cycle end JMP BACK CLR IAR1 ; disable EEPROM read/write CLR BP Rev. 1.80 52 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Oscillator Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. External oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. All oscillator options are selected through the configuration options. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/ power ratio, a feature especially important in power sensitive portable applications. Name Freq. Pins External Crystal Type HXT 400kHz~16MHz OSC1/OSC2 External RC ERC 8MHz OSC1 EC 400kHz~16MHz OSC1 HIRC 4, 8 or 12MHz — External Low Speed Crystal LXT 32.768kHz XT1/XT2 Internal Low Speed RC LIRC 32kHz — External Clock Internal High Speed RC Oscillator Types System Clock Configurations There are six methods of generating the system clock, three high speed oscillators and two low speed oscillators. The high speed oscillators are the external crystal/ceramic oscillator, external RC network oscillator, external clock and the internal 4MHz, 8MHz or 12MHz RC oscillator. The two low speed oscillators are the internal 32kHz RC oscillator and the external 32.768kHz crystal oscillator. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK bit and CKS2 ~ CKS0 bits in the SMOD register and as the system clock can be dynamically selected. Rev. 1.80 53 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM High Speed Oscillation HXT ERC fH 6-stage Prescaler HIRC fH/2 EC fH/4 fH/8 High Speed Oscillation Configuration Option fH/16 fH/32 Low Speed Oscillation LIRC fH/64 fSYS fL LXT HLCLK, CKS2~CKS0 bits Low Speed Oscillation Configuration Option fSUB Fast Wake -up from SLEEP Mode or IDLE Mode Control (for HXT only) System Clock Configurations The actual source clock used for each of the high speed and low speed oscillators is chosen via configuration options. The frequency of the slow speed or high speed system clock is also determined using the HLCLK bit and CKS2 ~ CKS0 bits in the SMOD register. Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection for either the high or low speed oscillator. External Crystal/ Ceramic Oscillator – HXT The External Crystal/Ceramic System Oscillator is one of the high frequency oscillator choices, which is selected via configuration option. For most crystal oscillator configurations, the simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. However, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer's specification. An additional configuration option must be setup to configure the device according to whether the oscillator frequency is high, defined as equal to or above 1MHz, or low, which is defined as below 1MHz. Rev. 1.80 54 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Crystal/Resonator Oscillator — HXT Crystal Oscillator C1 and C2 Values Crystal Frequency C1 C2 12MHz 0pF 0pF 8MHz 0pF 0pF 4MHz 0pF 0pF 1MHz 100pF 100pF 100pF 100pF 455kHz (see Note2) Note: 1. C1 and C2 values are for guidance only. 2. XTAL mode configuration option: 455kHz. Crystal Recommended Capacitor Values External RC Oscillator – ERC Using the ERC oscillator only requires that a resistor, with a value between 56kΩ and 2.4MΩ, is connected between OSC1 and V DD, and a capacitor is connected between OSC1 and ground, providing a low cost oscillator configuration. It is only the external resistor that determines the oscillation frequency; the external capacitor has no influence over the frequency and is connected for stability purposes only. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a resistance/frequency reference point, it can be noted that with an external 120kΩ resistor connected and with a 5V voltage power supply and temperature of 25°C degrees, the oscillator will have a frequency of 8MHz within a tolerance of 2%. Here only the OSC1 pin is used, which is shared with I/O pin PB1, leaving pin PB2 free for use as a normal I/O pin. External RC Oscillator — ERC Rev. 1.80 55 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Internal RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has three fixed frequencies of either 4MHz, 8MHz or 12MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of either 3V or 5V and at a temperature of 25°C degrees, the fixed oscillation frequency of 4MHz, 8MHz or 12MHz will have a tolerance within 2%. Note that if this internal system clock option is selected, as it requires no external pins for its operation, I/O pins PB1 and PB2 are free for use as normal I/O pins. External 32.768kHz Crystal Oscillator – LXT The External 32.768kHz Crystal System Oscillator is one of the low frequency oscillator choices, which is selected via configuration option. This clock source has a fixed frequency of 32.768kHz and requires a 32.768kHz crystal to be connected between pins XT1 and XT2. The external resistor and capacitor components connected to the 32.768kHz crystal are necessary to provide oscillation. For applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. During power-up there is a time delay associated with the LXT oscillator waiting for it to start-up. When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the SLEEP or IDLE Mode. To do this, another clock, independent of the system clock, must be provided. However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer┬ specification. The external parallel feedback resistor, Rp, is required. Some configuration options determine if the XT1/XT2 pins are used for the LXT oscillator or as I/O pins. ●● If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/O pins. ●● If the LXT oscillator is used for any clock source, the 32.768kHz crystal should be connected to the XT1/XT2 pins. External LXT Oscillator Rev. 1.80 56 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM LXT Oscillator C1 and C2 Values Crystal Frequency C1 C2 32.768kHz 10pF 10pF Note:1. C1 and C2 values are for guidance only. 2. RP=5M~10MΩ is recommended. 32.768kHz Crystal Recommended Capacitor Values LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power Mode. The mode selection is executed using the LXTLP bit in the TBC register. LXTLP Bit LXT Mode 0 Quick Start 1 Low-power After power on the LXTLP bit will be automatically cleared to zero ensuring that the LXT oscillator is in the Quick Start operating mode. In the Quick Start Mode the LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has fully powered up it can be placed into the Low-power mode by setting the LXTLP bit high. The oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the LXT oscillator start-up. In power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the LXTLP bit high about 2 seconds after power-on. It should be noted that, no matter what condition the LXTLP bit is set to, the LXT oscillator will always function normally, the only difference is that it will take more time to start up if in the Lowpower mode. Internal 32kHz Oscillator – LIRC The Internal 32kHz System Oscillator is one of the low frequency oscillator choices, which is selected via configuration option. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of 25°C degrees, the fixed oscillation frequency of 32kHz will have a tolerance within 10%. External Clock – EC The system clock can also be supplied by an externally supplied clock giving users a method of synchronizing their external hardware to the microcontroller operation. This is selected using a configuration option and supplying the clock on pin OSC1. Pin OSC2 should be left floating if the external oscillator is used. The internal oscillator circuit contains a filter circuit to reduce the possibility of erratic operation due to noise on the oscillator pin, however as the filter circuit consumes a certain amount of power, a oscillator configuration option exists to turn this filter off. Not using the internal filter should be considered in power sensitive applications and where the externally supplied clock is of a high integrity and supplied by a low impedance source. Supplementary Oscillators The low speed oscillators, in addition to providing a system clock source are also used to provide a clock source to two other device functions. These are the Watchdog Timer, the LCD driver and the Time Base Interrupts. Rev. 1.80 57 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The device has many different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock options using configuration options and register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency, fH, or low frequency, fL, source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from either an HXT, ERC, EC or HIRC oscillator, selected via a configuration option. The low speed system clock source can be sourced from internal clock fL. If fL is selected then it can be sourced by either the LXT or LIRC oscillators, selected via a configuration option. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. There are two additional internal clocks for the peripheral circuits, the substitute clock, fSUB, and the Time Base clock, f TBC. Each of these internal clocks are sourced by either the LXT or LIRC oscillators, selected via configuration options. The fSUB clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. Rev. 1.80 58 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM High Speed Oscillation HXT ERC fH HIRC 6-stage Prescaler fH/2 EC fH/4 fH/8 High Speed Oscillation Configuration Option fH/16 fH/32 Low Speed Oscillation LIRC fH/64 fSYS fL LXT HLCLK, CKS2~CKS0 bits Low Speed Oscillation Configuration Option fSUB Fast Wake -up from SLEEP Mode or IDLE Mode Control (for HXT only) fTBC fTB Time Base fSYS/4 TBCK fSUB fS fSYS/4 WDT Configuration Option fSUB fSUB fSYS ÷8 Clock Source Selection 4KHz LCD Driver SPI/SPIA System Clock Configurations Note: When the system clock source fSYS is switched to fL from fH, the high speed oscillation will stop to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use. Together with fSYS/4 it is also used as one of the clock sources for the Watchdog timer. The fTBC clock is used as a source for the Time Base interrupt functions and for the TMs. The fSUB is used as the LCD source. Rev. 1.80 59 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0, SLEEP1, IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power. Description Operation Mode CPU fSYS fSUB fS fTBC NORMAL Mode On fH~ fH/64 On On On SLOW Mode On fL On On On IDLE0 Mode Off Off On On/Off On IDLE1 Mode Off On On On On SLEEP0 Mode Off Off Off Off Off SLEEP1 Mode Off Off On On Off ●● NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. This mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the HXT, ERC, EC or HIRC oscillators. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. ●● SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from one of the low speed oscillators, either the LXT or the LIRC. Running the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW Mode, the fH is off. ●● SLEEP0 Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP0 mode the CPU will be stopped, and the fSUB and fS clocks will be stopped too, and the Watchdog Timer function is disabled. In this mode, the LVDEN is must set to "0". If the LVDEN is set to "1", it won't enter the SLEEP0 Mode. ●● SLEEP1 Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP1 mode the CPU will be stopped. However the fSUB and fS clocks will continue to operate if the LVDEN is "1" or the Watchdog Timer function is enabled and if its clock source is chosen via configuration option to come from the fSUB. ●● IDLE0 Mode The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the WDTC register is low. In the IDLE0 Mode the system oscillator will be inhibited from driving the CPU but some peripheral functions will remain operational such as the Watchdog Timer, TMs and LCD driver. In the IDLE0 Mode, the system oscillator will be stopped. In the IDLE0 Mode the Watchdog Timer clock, fS, will either be on or off depending upon the fS clock source. If the source is fSYS/4 then the fS clock will be off, and if the source comes from fSUB then fS will be on. Rev. 1.80 60 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the WDTC register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational such as the Watchdog Timer, TMs, LCD driver, SPIA and SIM. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. In the IDLE1 Mode the Watchdog Timer clock, fS, will be on. If the source is fSYS/4 then the fS clock will be on, and if the source comes from fSUB then fS will be on. Control Register A single register, SMOD, is used for overall control of the internal clocks within the device. ●● SMOD Register Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 FSTEN LTO HTO IDLEN HLCLK R/W R/W R/W R/W R/W R R R/W R/W POR 0 0 0 0 0 0 1 1 Bit 7~5 CKS2~CKS0: The system clock selection when HLCLK is "0" 000: fL (fLXT or fLIRC) 001: fL (fLXT or fLIRC) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which can be either the LXT or LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4 FSTEN: Fast Wake-up Control (only for HXT) 0: Disable 1: Enable This is the Fast Wake-up Control bit which determines if the f SUB clock source is initially used after the device wakes up. When the bit is high, the fSUB clock source can be used as a temporary system clock to provide a faster wake up time as the fSUB clock is available. Bit 3 LTO: Low speed system oscillator ready flag 0: Not ready 1: Ready This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. The flag will be low when in the SLEEP0 Mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if the LXT oscillator is used and 1~2 clock cycles if the LIRC oscillator is used. Bit 2 HTO: High speed system oscillator ready flag 0: Not ready 1: Ready 61 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to "0" by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as "1" by the application program after device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if the HXT oscillator is used and after 15~16 clock cycles if the ERC or HIRC oscillator is used. Bit 1 IDLEN: IDLE Mode control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. Bit 0 HLCLK: system clock selection 0: fH/2 ~ fH/64 or fL 1: fH This bit is used to select if the fH clock or the fH/2 ~ fH/64 or fL clock is used as the system clock. When the bit is high the fH clock will be selected and if low the fH/2 ~ fH/64 or fL clock will be selected. When system clock switches from the fH clock to the fL clock and the fH clock will be automatically switched off to conserve power. Fast Wake-up To minimise power consumption the device can enter the SLEEP or IDLE0 Mode, where the system clock source to the device will be stopped. However when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. To ensure the device is up and running as fast as possible a Fast Wake-up function is provided, which allows fSUB, namely either the LXT or LIRC oscillator, to act as a temporary clock to first drive the system until the original system oscillator has stabilised. As the clock source for the Fast Wake-up function is fSUB, the Fast Wake-up function is only available in the SLEEP1 and IDLE0 modes. When the device is woken up from the SLEEP0 mode, the Fast Wake-up function has no effect because the f SUB clock is stopped. The Fast Wake-up enable/disable function is controlled using the FSTEN bit in the SMOD register. If the HXT oscillator is selected as the NORMAL Mode system clock, and if the Fast Wake-up function is enabled, then it will take one to two tSUB clock cycles of the LIRC or LXT oscillator for the system to wake-up. The system will then initially run under the fSUB clock source until 1024 HXT clock cycles have elapsed, at which point the HTO flag will switch high and the system will switch over to operating from the HXT oscillator. If the ERC or EC or HIRC oscillators or LIRC oscillator is used as the system oscillator then it will take 15~16 clock cycles of the ERC or EC or HIRC or 1~2 cycles of the LIRC to wake up the system from the SLEEP or IDLE0 Mode. The Fast Wake-up bit, FSTEN will have no effect in these cases. Rev. 1.80 62 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM System Oscillator FSTEN Bit Wake-up Time (SLEEP0 Mode) Wake-up Time (SLEEP1 Mode) Wake-up Time (IDLE0 Mode) Wake-up Time (IDLE1 Mode) 1024 HXT cycles 1024 HXT cycles 1 1024 HXT cycles 1~2 fSUB cycles (System runs with fSUB first for 1024 HXT cycles 1~2 HXT cycles and then switches over to run with the HXT clock) ERC X 15~16 ERC cycles 15~16 ERC cycles 1~2 ERC cycles EC X 15~16 EC cycles 15~16 EC cycles 1~2 EC cycles HIRC X 15~16 HIRC cycles 15~16 HIRC cycles 1~2 HIRC cycles LIRC X 1~2 LIRC cycles 1~2 LIRC cycles 1~2 LIRC cycles LXT X 1024 LTX cycles 1024 LXT cycles 1~2 LXT cycles 0 HXT 1~2 HXT cycles Wake-Up Times Note that if the Watchdog Timer is disabled, which means that the LXT and LIRC are all both off, then there will be no Fast Wake-up function available when the device wakes-up from the SLEEP0 Mode. Rev. 1.80 63 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Operating Mode Switching and Wake-up The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the WDTC register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, fH, to the clock source, fH/2~fH/64 or fL. If the clock is from the fL, the high speed clock source will stop running to conserve power. When this happens it must be noted that the fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the TMs and the SIM. The accompanying flowchart shows what happens when the device moves between the various operating modes. NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the HLCLK bit to "0" and set the CKS2~CKS0 bits to "000" or "001" in the SMOD register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LXT or the LIRC oscillators and therefore requires these oscillators to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register. Rev. 1.80 64 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Rev. 1.80 65 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM SLOW Mode to NORMAL Mode Switching In SLOW Mode the system uses either the LXT or LIRC low speed system oscillator. To switch back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to "1" or HLCLK bit is "0", but CKS2~CKS0 is set to "010", "011", "100", "101", "110" or "111". As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. The amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. Entering the SLEEP0 Mode There is only one way for the device to enter the SLEEP0 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the WDT and LVD both off. When this instruction is executed under the conditions described above, the following will occur: ●● The system clock, WDT clock and Time Base clock will be stopped and the application program will stop at the "HALT" instruction. ●● The Data Memory contents and registers will maintain their present condition. ●● The WDT will be cleared and stopped no matter if the WDT clock source originates from the fSUB clock or from the system clock. ●● The I/O ports will maintain their present conditions. ●● In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the SLEEP1 Mode There is only one way for the device to enter the SLEEP1 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the WDT or LVD on. When this instruction is executed under the conditions described above, the following will occur: ●● The system clock and Time Base clock will be stopped and the application program will stop at the "HALT" instruction, but the WDT or LVD will remain with the clock source coming from the fSUB clock. ●● The Data Memory contents and registers will maintain their present condition. ●● The WDT will be cleared and resume counting if the WDT clock source is selected to come from the fSUB clock as the WDT is enabled. ●● The I/O ports will maintain their present conditions. ●● In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Rev. 1.80 66 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the FSYSON bit in WDTC register equal to "0". When this instruction is executed under the conditions described above, the following will occur: ●● The system clock will be stopped and the application program will stop at the "HALT" instruction, but the Time Base clock and fSUB clock will be on. ●● The Data Memory contents and registers will maintain their present condition. ●● The WDT will be cleared and resume counting if the WDT clock source is selected to come from the fSUB clock and the WDT is enabled. The WDT will stop if its clock source originates from the system clock. ●● The I/O ports will maintain their present conditions. ●● In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the FSYSON bit in WDTC register equal to "1". When this instruction is executed under the with conditions described above, the following will occur: ●● The system clock and Time Base clock and fSUB clock will be on and the application program will stop at the "HALT" instruction. ●● The Data Memory contents and registers will maintain their present condition. ●● The WDT will be cleared and resume counting if the WDT is enabled regardless of the WDT clock source which originates from the fSUB clock or from the system clock. ●● The I/O ports will maintain their present conditions. ●● In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the configuration options have enabled the LXT or LIRC oscillator. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. Rev. 1.80 67 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: ●● An external reset ●● An external falling edge on Port A ●● A system interrupt ●● A WDT overflow If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the "HALT" instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HALT" instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Programming Considerations The HXT and LXT oscillators both use the same SST counter. For example, if the system is woken up from the SLEEP0 Mode and both the HXT and LXT oscillators need to start-up from an off state. The LXT oscillator uses the SST counter after HXT oscillator has finished its SST period. ●● If the device is woken up from the SLEEP0 Mode to the NORMAL Mode, the high speed system oscillator needs an SST period. The device will execute first instruction after HTO is "1". At this time, the LXT oscillator may not be stability if fSUB is from LXT oscillator. The same situation occurs in the power-on state. The LXT oscillator is not ready yet when the first instruction is executed. ●● If the device is woken up from the SLEEP1 Mode to NORMAL Mode, and the system clock source is from HXT oscillator and FSTEN is "1" , the system clock can be switched to the LXT or LIRC oscillator after wake up. ●● There are peripheral functions, such as WDT, TMs and SPIA, LCD driver and SIM, for which the fSYS is used. If the system clock source is switched from fH to fL, the clock source to the peripheral functions mentioned above will change accordingly. ●● The on/off condition of fSUB and fS depends upon whether the WDT is enabled or disabled as the WDT clock source is selected from fSUB. Rev. 1.80 68 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal clock, fS, which is in turn supplied by one of two sources selected by configuration option: fSUB or fSYS/4. The fSUB clock can be sourced from either the LXT or LIRC oscillators, again chosen via a configuration option. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 215 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. The LXT oscillator is supplied by an external 32.768kHz crystal. The other Watchdog Timer clock source option is the fSYS/4 clock. The Watchdog Timer clock source can originate from its own internal LIRC oscillator, the LXT oscillator or fSYS/4. It is divided by a value of 28 to 215, using the WS2~WS0 bits in the WDTC register to obtain the required Watchdog Timer time-out period. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable operation. This register together with several configuration options control the overall operation of the Watchdog Timer. ●● WDTC Register Rev. 1.80 Bit 7 6 5 4 Name FSYSON WS2 WS1 WS0 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 1 1 1 0 1 0 WDTEN3 WDTEN2 WDTEN1 WDTEN0 Bit 7 FSYSON: fSYS Control in IDLE Mode 0: Disable 1: Enable Bit 6 ~ 4 WS2, WS1, WS0: WDT time-out period selection 000: 256/fS 001: 512/fS 010: 1024/fS 011: 2048/fS 100: 4096/fS 101: 8192/fS 110: 16384/fS 111: 32768/fS These three bits determine the division ratio of the Watchdog Timer source clock, which in turn determines the timeout period. Bit 3 ~ 0 WDTEN3, WDTEN2, WDTEN1, WDTEN0: WDT Software Control 1010: Disable Other: Enable 69 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unkown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. Some of the Watchdog Timer options, such as enable/disable, clock source selection and clear instruction type are selected using configuration options. In addition to a configuration option to enable/disable the Watchdog Timer, there are also four bits, WDTEN3~WDTEN0, in the WDTC register to offer an additional enable/disable control of the Watchdog Timer. To disable the Watchdog Timer, as well as the configuration option being set to disable, the WDTEN3~WDTEN0 bits must also be set to a specific value of "1010". Any other values for these bits will keep the Watchdog Timer enabled, irrespective of the configuration enable/disable setting. After power on these bits will have the value of 1010. If the Watchdog Timer is used it is recommended that they are set to a value of 0101 for maximum noise immunity. Note that if the Watchdog Timer has been disabled, then any instruction relating to its operation will result in no operation. WDT Configuration Option WDTEN3~WDTEN0 Bits WDT WDT Enable xxxx Enable WDT Disable Except 1010 Enable WDT Disable 1010 Disable Watchdog Timer Enable/Disable Control Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is an external hardware reset, which means a low level on the RES pin, the second is using the Watchdog Timer software clear instructions and the third is via a HALT instruction. There are two methods of using software instructions to clear the Watchdog Timer, one of which must be chosen by configuration option. The first option is to use the single "CLR WDT" instruction while the second is to use the two commands "CLR WDT1" and "CLR WDT2". For the first option, a simple execution of CLR WDT will clear the WDT while for the second option, both "CLR WDT1" and "CLR WDT2" must both be executed alternately to successfully clear the Watchdog Timer. Note that for this second option, if "CLR WDT1" is used to clear the Watchdog Timer, successive executions of this instruction will have no effect, only the execution of a "CLR WDT2" instruction will clear the Watchdog Timer. Similarly after the "CLR WDT2" instruction has been executed, only a successive "CLR WDT1" instruction can clear the Watchdog Timer. The maximum time out period is when the 215 division ratio is selected. As an example, with a 32.768kHz LXT oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 215 division ratio, and a minimum timeout of 7.8ms for the 28 division ration. If the fSYS/4 clock is used as the Watchdog Timer clock source, it should be noted that when the system enters the SLEEP or IDLE0 Mode, then the instruction clock is stopped and the Watchdog Timer may lose its protecting purposes. For systems that operate in noisy environments, using the fSUB clock source is strongly recommended. Rev. 1.80 70 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Watchdog Timer Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the is running. One example of this is where after power has been applied and the is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the registers remain unchanged allowing the to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the . All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are five ways in which a reset can occur, through events occurring both internally and externally: ●● Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the . As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Rev. 1.80 Power-On Reset Timing Chart Note: tRSTD is power-on delay, typical time=100ms 71 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● RES Pin As the reset pin is shared with PB.0, the reset function must be selected using a configuration option. Although the has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the will be inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer. For most applications a resistor connected between V DD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference. For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended. External RES Circuit Note: * It is recommended that this component is added for added ESD protection. ** It is recommended that this component is added in environments where power line noise is significant. More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website. Pulling the RES Pin low using external hardware will also execute a device reset. In this case, as in the case of other resets, the Program Counter will reset to zero and program execution initiated from this point. Rev. 1.80 RES Reset Timing Chart Note: tRSTD is power-on delay, typical time=100ms 72 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● Low Voltage Reset — LVR The contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a configuration option. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for greater than the value tLVR specified in the A.C. characteristics. If the low voltage state does not exceed tLVR, the LVR will ignore it and will not perform a reset function. One of a range of specified voltage values for VLVR can be selected using configuration options. Low Voltage Reset Timing Chart Note: tRSTD is power-on delay, typical time=100ms ●● Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to "1". WDT Time-out Reset during Normal Operation Timing Chart Note: tRSTD is power-on delay, typical time=100ms ●● Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for tSST details. WDT Time-out Reset during SLEEP or IDLE Timing Chart Note: The tSST is 15~16 clock cycles if the system clock source is provided by ERC or HIRC. The tSST is 1024 clock for HXT or LXT. The tSST is 1~2 clock for LIRC. Rev. 1.80 73 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 0 Power-on reset RESET Conditions u u RES or LVR reset during NORMAL or SLOW Mode operation 1 u WDT time-out reset during NORMAL or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation Note: "u" stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Program Counter Interrupts WDT Timer/Event Counter Input/Output Ports Stack Pointer Condition After RESET Reset to zero All interrupts will be disabled Clear after reset, WDT begins counting Timer Counter will be turned off I/O ports will be setup as inputs, and AN0~AN11 in as A/D input pin. Stack Pointer will point to the top of the stack The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation for the larger package type. Rev. 1.80 74 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● HT67F30 Register Register Rev. 1.80 Reset (Power On) RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (IDLE) MP0 1xxx xxxx 1xxx xxxx 1xxx xxxx 1 uuu uuuu MP1 1xxx xxxx 1xxx xxxx 1xxx xxxx 1 uuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH --xx xxxx - - uu uuuu - - uu uuuu - - uu uuuu TBHP ---- -xxx - - - - - uuu - - - - - uuu - - - - - uuu STATUS --00 xxxx - - uu uuuu - - 1 u uuuu - - 1 1 uuuu BP ---- -000 ---- -000 ---- -000 - - - - - uuu SMOD 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 uuuu uuuu INTEG ---- 0000 ---- 0000 ---- 0000 - - - - uuuu LVDC --00 -000 --00 -000 --00 -000 - - uu - uuu INTC0 -000 0000 -000 0000 -000 0000 - uuu uuuu INTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI0 --00 --00 --00 --00 --00 --00 - - uu - - uu MFI1 -000 -000 -000 -000 -000 -000 - uuu - uuu MFI2 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI3 -0-- -0-- -0-- -0-- -0-- -0-- -u-- -u-- PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PB - - 11 1111 - - 11 1111 - - 11 1111 - - uu uuuu PBC - - 11 1111 - - 11 1111 - - 11 1111 - - uu uuuu PC ---- --11 ---- --11 ---- --11 - - - - - - uu PCC ---- --11 ---- --11 ---- --11 - - - - - - uu PD 1111 1111 1111 1111 1111 1111 uuuu uuuu PDC 1111 1111 1111 1111 1111 1111 uuuu uuuu PE 1111 1111 1111 1111 1111 1111 uuuu uuuu PEC 1111 1111 1111 1111 1111 1111 uuuu uuuu ADRL(ADREF=0) xxxx ---- xxxx ---- xxxx ---- uuuu - - - - ADRL(ADREF=1) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRH(ADREF=0) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRH(ADREF=1) ---- xxxx ---- xxxx ---- xxxx - - - - uuuu ADCR0 0 11 0 - 0 0 0 0 11 0 - 0 0 0 0 11 0 - 0 0 0 uuuu - uuu ADCR1 00-0 -000 00-0 -000 00-0 -000 uu - u - uuu ACERL 1111 1111 1111 1111 1111 1111 uuuu uuuu WDTC 0 111 1 0 1 0 0 111 1 0 1 0 0 111 1 0 1 0 uuuu uuuu TBC 0 0 11 0 111 0 0 11 0 111 0 0 11 0 111 uuuu uuuu EEA --00 0000 --00 0000 --00 0000 - - uu uuuu EED 0000 0000 0000 0000 0000 0000 uuuu uuuu EEC ---- 0000 ---- 0000 ---- 0000 - - - - uuuu SIMC0 111 0 0 0 0 - 111 0 0 0 0 - 111 0 0 0 0 - uuuu uuu - 75 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Register Reset (Power On) RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (IDLE) SIMC1 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMA/SIMC2 0000 0000 0000 0000 0000 0000 uuuu uuuu SPIAC0 111 - - - 0 - 111 - - - 0 - 111 - - - 0 - uuu - - - u - SPIAC1 --00 0000 --00 0000 --00 0000 - - uu uuuu SPIAD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu PAWU 0000 0000 0000 0000 0000 0000 uuuu uuuu PAPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PBPU --00 0000 --00 0000 --00 0000 - - uu uuuu PCPU ---- --00 ---- --00 ---- --00 uuuu uuuu PDPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PEPU 0000 0000 0000 0000 0000 0000 uuuu uuuu CP0C 1000 0--1 1000 0--1 1000 0--1 uuuu u - - u CP1C 1000 0--1 1000 0--1 1000 0--1 uuuu u - - u TMPC0 1-01 --01 1-01 --01 1-01 --01 u - uu - - uu PRM0 0000 ---- 0000 ---- 0000 ---- uuuu - - - - PRM1 -00- 0000 -00- 0000 -00- 0000 - uu - uuuu PRM2 ---- -000 ---- -000 ---- -000 - - - - - uuu TM0C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DH ---- --00 ---- --00 ---- --00 - - - - - - uu TM0AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0AH ---- --00 ---- --00 ---- --00 - - - - - - uu TM1C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DH ---- --00 ---- --00 ---- --00 - - - - - - uu TM1AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1AH ---- --00 ---- --00 ---- --00 - - - - - - uu TM1BL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1BH ---- --00 ---- --00 ---- --00 - - - - - - uu LCDCTRL 000- 0000 000- 0000 000- 0000 uuu - uuuu LCDOUT0 1111 1111 1111 1111 1111 1111 uuuu uuuu LCDOUT1 1111 1111 1111 1111 1111 1111 uuuu uuuu Note: “ * ” stands for “warm reset”, “ - ” not implement “ u ” stands for “unchanged” “ x ” stands for “unknown” Rev. 1.80 76 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● HT67F40 Register Rev. 1.80 Register Reset (Power On) RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (IDLE) MP0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu MP1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH -xxx xxxx - uuu uuuu - uuu uuuu - uuu uuuu TBHP ---- xxxx - - - - uuuu - - - - uuuu - - - - uuuu STATUS --00 xxxx - - uu uuuu - - 1 u uuuu - - 1 1 uuuu BP ---- --00 ---- --00 ---- --00 - - - - - - uu SMOD 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 uuuu uuuu INTEG ---- 0000 ---- 0000 ---- 0000 - - - - uuuu LVDC --00 -000 --00 -000 --00 -000 - - uu - uuu INTC0 -000 0000 -000 0000 -000 0000 - uuu uuuu INTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI0 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI1 -000 -000 -000 -000 -000 -000 - uuu - uuu MFI2 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI3 -0-- -0-- -0-- -0-- -0-- -0-- -u-- -u-- PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PB - - 11 1111 - - 11 1111 - - 11 1111 - - uu uuuu PBC - - 11 1111 - - 11 1111 - - 11 1111 - - uu uuuu PC - - 11 1111 - - 11 1111 - - 11 1111 - - uu uuuu PCC - - 11 1111 - - 11 1111 - - 11 1111 - - uu uuuu PD 1111 1111 1111 1111 1111 1111 uuuu uuuu PDC 1111 1111 1111 1111 1111 1111 uuuu uuuu PE 1111 1111 1111 1111 1111 1111 uuuu uuuu PEC 1111 1111 1111 1111 1111 1111 uuuu uuuu PF 1111 1111 1111 1111 1111 1111 uuuu uuuu PFC 1111 1111 1111 1111 1111 1111 uuuu uuuu ADRL(ADREF=1) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRH(ADREF=0) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRH(ADREF=1) ---- xxxx ---- xxxx ---- xxxx - - - - uuuu ADCR0 0 11 0 - 0 0 0 0 11 0 - 0 0 0 0 11 0 - 0 0 0 uuuu - uuu ADCR1 00-0 -000 00-0 -000 00-0 -000 uu - u - uuu ANCSR 1111 1111 1111 1111 1111 1111 uuuu uuuu WDTC 0 111 1 0 1 0 0 111 1 0 1 0 0 111 1 0 1 0 uuuu uuuu TBC 0 0 11 0 111 0 0 11 0 111 0 0 11 0 111 uuuu uuuu EEA -000 0000 -000 0000 -000 0000 - uuu uuuu EED 0000 0000 0000 0000 0000 0000 uuuu uuuu EEC ---- 0000 ---- 0000 ---- 0000 - - - - uuuu SIMC0 111 0 0 0 0 - 111 0 0 0 0 - 111 0 0 0 0 - uuuu uuu - SIMC1 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMA/SIMC2 0000 0000 0000 0000 0000 0000 uuuu uuuu SPIAC0 111 - - - 0 - 111 - - - 0 - 111 - - - 0 - uuu - - - u - 77 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Register Reset (Power On) RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (IDLE) SPIAC1 --00 0000 --00 0000 --00 0000 - - uu uuuu SPIAD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu PAWU 0000 0000 0000 0000 0000 0000 uuuu uuuu PAPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PBPU --00 0000 --00 0000 --00 0000 - - uu uuuu PCPU --00 0000 --00 0000 --00 0000 - - uu uuuu PDPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PEPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PFPU 0000 0000 0000 0000 0000 0000 uuuu uuuu CP0C 1000 0--1 1000 0--1 1000 0--1 uuuu u - - u CP1C 1000 0--1 1000 0--1 1000 0--1 uuuu u - - u TMPC0 1001 --01 1001 --01 1001 --01 uuuu - - uu TMPC1 ---- --01 ---- --01 ---- --01 - - - - - - uu PRM0 0000 0000 0000 0000 0000 0000 uuuu uuuu PRM1 000- 0000 000- 0000 000- 0000 uuu - uuuu PRM2 --00 0000 --00 0000 --00 0000 - - uu uuuu TM0C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DH ---- --00 ---- --00 ---- --00 - - - - - - uu TM0AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0AH ---- --00 ---- --00 ---- --00 - - - - - - uu TM1C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DH ---- --00 ---- --00 ---- --00 - - - - - - uu TM1AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1AH ---- --00 ---- --00 ---- --00 - - - - - - uu TM1BL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1BH ---- --00 ---- --00 ---- --00 - - - - - - uu TM2C0 0000 0--- 0000 0--- 0000 0--- uuuu u - - - TM2C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2DH 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2AH 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2RP 0000 0000 0000 0000 0000 0000 uuuu uuuu LCDCTRL 000- 0000 000- 0000 000- 0000 uuu - uuuu LCDOUT0 1111 1111 1111 1111 1111 1111 uuuu uuuu LCDOUT1 1111 1111 1111 1111 1111 1111 uuuu uuuu LCDOUT2 1111 1111 1111 1111 1111 1111 uuuu uuuu Note: “ * ” stands for “warm reset”, “ - ” not implement “ u ” stands for “unchanged” “ x ” stands for “unknown” Rev. 1.80 78 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● HT67F50 Register Register RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (IDLE) MP0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu MP1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBHP ---x xxxx - - - u uuuu - - - u uuuu - - - u uuuu STATUS --00 xxxx - - uu uuuu - - 1 u uuuu - - 1 1 uuuu BP ---- --00 ---- --00 ---- --00 - - - - - - uu SMOD 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 uuuu uuuu INTEG ---- 0000 ---- 0000 ---- 0000 - - - - uuuu LVDC --00 -000 --00 -000 --00 -000 - - uu - uuu INTC0 -000 0000 -000 0000 -000 0000 - uuu uuuu INTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI0 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI1 -000 -000 -000 -000 -000 -000 - uuu - uuu MFI2 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI3 -000 -000 -000 -000 -000 -000 - uuu - uuu PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 uuuu uuuu 11 1111 11 1111 11 1111 uu uuuu PC PCC 11 1111 11 1111 11 1111 uu uuuu PD 1111 1111 1111 1111 1111 1111 uuuu uuuu PDC 1111 1111 1111 1111 1111 1111 uuuu uuuu PE 1111 1111 1111 1111 1111 1111 uuuu uuuu PEC 1111 1111 1111 1111 1111 1111 uuuu uuuu PF 1111 1111 1111 1111 1111 1111 uuuu uuuu PFC 1111 1111 1111 1111 1111 1111 uuuu uuuu uu uuuu PG 11 1111 11 1111 11 1111 PGC 11 1111 11 1111 11 1111 uu uuuu xxxx ---- xxxx ---- xxxx ---- uuuu ---- ADRL(ADREF=0) Rev. 1.80 Reset (Power On) ADRL(ADREF=1) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRH(ADREF=0) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRH(ADREF=1) ---- xxxx ---- xxxx ---- xxxx - - - - uuuu ADCR0 0 11 0 - 0 0 0 0 11 0 - 0 0 0 0 11 0 - 0 0 0 uuuu - uuu ADCR1 00-0 -000 00-0 -000 00-0 -000 uu - u - uuu ACERL 1111 1111 1111 1111 1111 1111 uuuu uuuu WDTC 0 111 1 0 1 0 0 111 1 0 1 0 0 111 1 0 1 0 uuuu uuuu TBC 0 0 11 0 111 0 0 11 0 111 0 0 11 0 111 uuuu uuuu 79 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Register Rev. 1.80 RES or LVR Reset Reset (Power On) WDT Time-out (Normal Operation) WDT Time-out (IDLE) EEA 0000 0000 0000 0000 0000 0000 uuuu uuuu EED 0000 0000 0000 0000 0000 0000 uuuu uuuu EEC ---- 0000 ---- 0000 ---- 0000 - - - - uuuu SIMC0 111 0 0 0 0 - 111 0 0 0 0 - 111 0 0 0 0 - uuuu uuu - SIMC1 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMA/SIMC2 0000 0000 0000 0000 0000 0000 uuuu uuuu SPIAC0 111 - - - 0 - 111 - - - 0 - 111 - - - 0 - uuu - - - u - SPIAC1 --00 0000 --00 0000 --00 0000 - - uu uuuu SPIAD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu PAWU 0000 0000 0000 0000 0000 0000 uuuu uuuu PAPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PBPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PCPU 00 0000 00 0000 00 0000 uu uuuu PDPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PEPU 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu PFPU 0000 0000 0000 0000 0000 0000 PGPU 00 0000 00 0000 00 0000 uu uuuu CP0C 1000 0--1 1000 0--1 1000 0--1 uuuu u - - u CP1C 1000 0--1 1000 0--1 1000 0--1 uuuu u - - u TMPC0 1001 --01 1001 --01 1001 --01 uuuu - - uu TMPC1 --01 --01 --01 --01 --01 --01 - - uu - - uu PRM0 0000 0000 0000 0000 0000 0000 uuuu uuuu PRM1 000- 0000 000- 0000 000- 0000 uuu - uuuu PRM2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DH ---- --00 ---- --00 ---- --00 - - - - - - uu TM0AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0AH ---- --00 ---- --00 ---- --00 - - - - - - uu TM1C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DH ---- --00 ---- --00 ---- --00 - - - - - - uu TM1AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1AH ---- --00 ---- --00 ---- --00 - - - - - - uu TM1BL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1BH ---- --00 ---- --00 ---- --00 - - - - - - uu TM2C0 0000 0--- 0000 0--- 0000 0--- uuuu u - - - TM2C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2DL 0000 0000 0000 0000 0000 0000 uuuu uuuu 80 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Register Reset (Power On) RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (IDLE) TM2DH 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2AH 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2RP 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3DH ---- --00 ---- --00 ---- --00 - - - - - - uu TM3AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3AH ---- --00 ---- --00 ---- --00 - - - - - - uu LCDCTRL 000- 0000 000- 0000 000- 0000 uuu - uuuu LCDOUT0 1111 1111 1111 1111 1111 1111 uuuu uuuu LCDOUT1 1111 1111 1111 1111 1111 1111 uuuu uuuu LCDOUT2 1111 1111 1111 1111 1111 1111 uuuu uuuu Note: “ * ” stands for “warm reset”, “ - ” not implement “ u ” stands for “unchanged” “ x ” stands for “unknown” Rev. 1.80 81 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● HT67F60 Register Rev. 1.80 Register Reset (Power On) RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (IDLE) MP0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu MP1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBHP --xx xxxx - - uu uuuu - - uu uuuu - - uu uuuu STATUS --00 xxxx - - uu uuuu - - 1 u uuuu - - 1 1 uuuu BP --0- -000 --0- -000 --0- --000 - - u - - uuu SMOD 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 uuuu uuuu INTEG 0000 0000 0000 0000 0000 0000 uuuu uuuu LVDC --00 -000 --00 -000 --00 -000 - - uu - uuu INTC0 -000 0000 -000 0000 -000 0000 - uuu uuuu INTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC3 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI0 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI1 -000 -000 -000 -000 -000 -000 - uuu - uuu MFI2 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI3 -000 -000 -000 -000 -000 -000 - uuu - uuu PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 uuuu uuuu PC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC 1111 1111 1111 1111 1111 1111 uuuu uuuu PD 1111 1111 1111 1111 1111 1111 uuuu uuuu PDC 1111 1111 1111 1111 1111 1111 uuuu uuuu PE 1111 1111 1111 1111 1111 1111 uuuu uuuu PEC 1111 1111 1111 1111 1111 1111 uuuu uuuu PF 1111 1111 1111 1111 1111 1111 uuuu uuuu PFC 1111 1111 1111 1111 1111 1111 uuuu uuuu PG 1111 1111 1111 1111 1111 1111 uuuu uuuu PGC 1111 1111 1111 1111 1111 1111 uuuu uuuu PH 1111 1111 1111 1111 1111 1111 uuuu uuuu PHC 1111 1111 1111 1111 1111 1111 uuuu uuuu ADRL(ADREF=0) xxxx ---- xxxx ---- xxxx ---- uuuu - - - - ADRL(ADREF=1) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRH(ADREF=0) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRH(ADREF=1) ---- xxxx ---- xxxx ---- xxxx - - - - uuuu ADCR0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 uuuu uuuu ADCR1 00-0 -000 00-0 -000 00-0 -000 uu - u - uuu 82 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Register Rev. 1.80 Reset (Power On) RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (IDLE) ACERL 1111 1111 1111 1111 1111 1111 uuuu uuuu ACERH - - - - 1111 - - - - 1111 - - - - 1111 - - - - uuuu WDTC 0 111 1 0 1 0 0 111 1 0 1 0 0 111 1 0 1 0 uuuu uuuu TBC 0 0 11 0 111 0 0 11 0 111 0 0 11 0 111 uuuu uuuu EEA 0000 0000 0000 0000 0000 0000 uuuu uuuu EED 0000 0000 0000 0000 0000 0000 uuuu uuuu EEC ---- 0000 ---- 0000 ---- 0000 - - - - uuuu SIMC0 111 0 0 0 0 - 111 0 0 0 0 - 111 0 0 0 0 - uuuu uuu - SIMC1 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMA/SIMC2 0000 0000 0000 0000 0000 0000 uuuu uuuu SPIAC0 111 - - - 0 - 111 - - - 0 - 111 - - - 0 - uuu - - - u - SPIAC1 --00 0000 --00 0000 --00 0000 - - uu uuuu SPIAD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu PAWU 0000 0000 0000 0000 0000 0000 uuuu uuuu PAPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PBPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PCPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PDPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PEPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PFPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PGPU ---- --00 ---- --00 ---- --00 - - - - - - uu CP0C 1000 0--1 1000 0--1 1000 0--1 uuuu u - - u CP1C 1000 0--1 1000 0--1 1000 0--1 uuuu u - - u TMPC0 1001 --01 1001 --01 1001 --01 uuuu - - uu TMPC1 --01 --01 --01 --01 --01 --01 - - uu - - uu PRM0 0000 0000 0000 0000 0000 0000 uuuu uuuu PRM1 0000 0000 0000 0000 0000 0000 uuuu uuuu PRM2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DH ---- --00 ---- --00 ---- --00 - - - - - - uu TM0AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0AH ---- --00 ---- --00 ---- --00 - - - - - - uu TM1C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DH ---- --00 ---- --00 ---- --00 - - - - - - uu TM1AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1AH ---- --00 ---- --00 ---- --00 - - - - - - uu TM1BL 0000 0000 0000 0000 0000 0000 uuuu uuuu 83 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Register Reset (Power On) RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (IDLE) TM1BH ---- --00 ---- --00 ---- --00 - - - - - - uu TM2C0 0000 0--- 0000 0--- 0000 0--- uuuu u - - - TM2C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2DH 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2AH 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2RP 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3DH ---- --00 ---- --00 ---- --00 - - - - - - uu TM3AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3AH ---- --00 ---- --00 ---- --00 - - - - - - uu LCDCTRL 000- 0000 000- 0000 000- 0000 uuu - uuuu LCDOUT0 1111 1111 1111 1111 1111 1111 uuuu uuuu LCDOUT1 1111 1111 1111 1111 1111 1111 uuuu uuuu LCDOUT2 1111 1111 1111 1111 1111 1111 uuuu uuuu LCDOUT3 1111 1111 1111 1111 1111 1111 uuuu uuuu Note: “ * ” stands for “warm reset”, “ - ” not implement “ u ” stands for “unchanged” “ x ” stands for “unknown” Rev. 1.80 84 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port names PA~PH These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction “MOV A, [m]”, where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. I/O Register List ●● HT67F30 Rev. 1.80 Bit Register Name 7 6 5 4 3 2 1 0 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PBPU — — D5 D4 D3 D2 D1 D0 PB — — D5 D4 D3 D2 D1 D0 PBC — — D5 D4 D3 D2 D1 D0 PCPU — — — — — — D1 D0 PC — — — — — — D1 D0 PCC — — — — — — D1 D0 PDPU D7 D6 D5 D4 D3 D2 D1 D0 PD D7 D6 D5 D4 D3 D2 D1 D0 PDC D7 D6 D5 D4 D3 D2 D1 D0 PEPU D7 D6 D5 D4 D3 D2 D1 D0 PE D7 D6 D5 D4 D3 D2 D1 D0 PEC D7 D6 D5 D4 D3 D2 D1 D0 85 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● HT67F40 Bit Register Name 7 6 5 4 3 2 1 0 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PBPU — — D5 D4 D3 D2 D1 D0 PB — — D5 D4 D3 D2 D1 D0 PBC — — D5 D4 D3 D2 D1 D0 PCPU — — D5 D4 D3 D2 D1 D0 PC — — D5 D4 D3 D2 D1 D0 PCC — — D5 D4 D3 D2 D1 D0 PDPU D7 D6 D5 D4 D3 D2 D1 D0 PD D7 D6 D5 D4 D3 D2 D1 D0 PDC D7 D6 D5 D4 D3 D2 D1 D0 D0 PEPU D7 D6 D5 D4 D3 D2 D1 PE D7 D6 D5 D4 D3 D2 D1 D0 PEC D7 D6 D5 D4 D3 D2 D1 D0 PFPU D7 D6 D5 D4 D3 D2 D1 D0 PF D7 D6 D5 D4 D3 D2 D1 D0 PFC D7 D6 D5 D4 D3 D2 D1 D0 ●● HT67F50 Rev. 1.80 Bit Register Name 7 6 5 4 3 2 1 0 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 D0 PAC D7 D6 D5 D4 D3 D2 D1 PBPU D7 D6 D5 D4 D3 D2 D1 D0 PB D7 D6 D5 D4 D3 D2 D1 D0 PBC D7 D6 D5 D4 D3 D2 D1 D0 PCPU — — D5 D4 D3 D2 D1 D0 PC — — D5 D4 D3 D2 D1 D0 PCC — — D5 D4 D3 D2 D1 D0 PDPU D7 D6 D5 D4 D3 D2 D1 D0 PD D7 D6 D5 D4 D3 D2 D1 D0 PDC D7 D6 D5 D4 D3 D2 D1 D0 PEPU D7 D6 D5 D4 D3 D2 D1 D0 D0 PE D7 D6 D5 D4 D3 D2 D1 PEC D7 D6 D5 D4 D3 D2 D1 D0 PFPU D7 D6 D5 D4 D3 D2 D1 D0 PF D7 D6 D5 D4 D3 D2 D1 D0 PFC D7 D6 D5 D4 D3 D2 D1 D0 PGPU — — D5 D4 D3 D2 D1 D0 PG — — D5 D4 D3 D2 D1 D0 PGC — — D5 D4 D3 D2 D1 D0 86 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● HT67F60 Rev. 1.80 Bit Register Name 7 6 5 4 3 2 1 0 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PBPU D7 D6 D5 D4 D3 D2 D1 D0 PB D7 D6 D5 D4 D3 D2 D1 D0 PBC D7 D6 D5 D4 D3 D2 D1 D0 PCPU D7 D6 D5 D4 D3 D2 D1 D0 PC D7 D6 D5 D4 D3 D2 D1 D0 PCC D7 D6 D5 D4 D3 D2 D1 D0 PDPU D7 D6 D5 D4 D3 D2 D1 D0 PD D7 D6 D5 D4 D3 D2 D1 D0 PDC D7 D6 D5 D4 D3 D2 D1 D0 PEPU D7 D6 D5 D4 D3 D2 D1 D0 PE D7 D6 D5 D4 D3 D2 D1 D0 PEC D7 D6 D5 D4 D3 D2 D1 D0 PFPU D7 D6 D5 D4 D3 D2 D1 D0 PF D7 D6 D5 D4 D3 D2 D1 D0 PFC D7 D6 D5 D4 D3 D2 D1 D0 PGPU D7 D6 D5 D4 D3 D2 D1 D0 PG D7 D6 D5 D4 D3 D2 D1 D0 PGC D7 D6 D5 D4 D3 D2 D1 D0 PHPU D7 D6 D5 D4 D3 D2 D1 D0 PH D7 D6 D5 D4 D3 D2 D1 D0 PHC D7 D6 D5 D4 D3 D2 D1 D0 87 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU~PHPU, and are implemented using weak PMOS transistors. PAPU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 PBPU Register ●● HT67F30/HT67F40 Bit 7 6 5 4 3 2 1 0 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as “0” ●● HT67F50/HT67F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PCPU Register ●● HT67F30 Bit Name — — — — — — D1 D0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 4 3 2 1 0 Bit 7~2 Unimplemented, read as “0” ●● HT67F40/HT67F50 Bit 7 6 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 5 Unimplemented, read as “0” ●● HT67F60 Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 88 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM PDPU Register ●● HT67F30/HT67F40/HT67F50/HT67F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 PEPU Register ●● HT67F30/HT67F40/HT67F50/HT67F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 PFPU Register ●● HT67F40/HT67F50/HT67F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 PGPU Register ●● HT67F50 Bit 7 6 5 4 3 2 1 0 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 ●● HT67F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 PHPU Register ●● HT67F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.80 I/O Port bit 7 ~ bit 0 Pull-High Control 0: Disable 1: Enable 89 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. ●● PAWU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 PAWU: Port A bit 7 ~ bit 0 Wake-up Control 0: Disable 1: Enable I/O Port Control Registers Each I/O port has its own control register known as PAC~PHC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a “1”. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a “0”, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. PAC Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 PBC Register ●● HT67F30/HT67F40 Bit 7 6 5 4 3 2 1 0 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 1 1 1 1 1 1 Bit 7~6 “—” Unimplemented, read as “0” ●● HT67F50/HT67F60 Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 90 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM PCC Register ●● HT67F30 Bit 7 6 5 4 3 2 1 0 Name — — — — — — D1 D0 R/W — — — — — — R/W R/W POR — — — — — — 1 1 Bit 7~2 “–” Unimplemented, read as “0” ●● HT67F40 Bit 7 6 5 4 3 2 1 0 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 1 1 1 1 1 1 Bit 7~6 “–” Unimplemented, read as “0” ●● HT67F50 Bit 7 6 5 4 3 2 1 0 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 1 1 1 1 1 1 Bit 7~6 “–” Unimplemented, read as “0” ●● HT67F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 PDC Register ●● HT67F30/HT67F40/HT67F50/HT67F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 PEC Register ●● HT67F30/HT67F40/HT67F50/HT67F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 PFC Register ●● HT67F40/HT67F50/HT67F60 Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 91 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM PGC Register ●● HT67F50 Bit 7 6 5 4 3 2 1 0 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 1 1 1 1 1 1 Bit 7~6 “–” Unimplemented, read as “0” ●● HT67F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 PHC Register ●● HT67F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~0 I/O Port bit 7 ~ bit 0 Input/Output Control 0: Output 1: Input Pin-remapping Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. The way in which the pin function of each pin is selected is different for each function and a priority order is established where more than one pin function is selected simultaneously. Additionally there are a series of PRM0, PRM1 and PRM2 registers to establish certain pin functions. Pin-remapping Registers The limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. However by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. Some devices include PRM0, PRM1 or PRM2 registers which can select the functions of certain pins. Pin-remapping Register List ●● HT67F30 Register Name PRM0 Rev. 1.80 Bit 7 6 1XPS1 C1XPS0 5 4 3 2 1 0 C0XPS1 C0XPS0 — — — — PRM1 — TCK1PS TCK0PS — INT1PS INT0PS PRM2 — — — — — TP1APS 92 TP1B1PS TP1B0PS TP01PS TP00PS August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● HT67F40 Bit Register Name 7 6 5 4 3 2 1 0 PRM0 C1XPS1 C1XPS0 C0XPS1 C0XPS0 SIMPS1 SIMPS0 PCKPS1 PCKPS0 PRM1 TCK2PS TCK1PS TCK0PS — INT1PS INT0PS TP1B1PS TP1B0PS PRM2 — — TP21PS Register Name 7 6 5 4 3 2 1 0 PRM0 C1XPS1 C1XPS0 C0XPS1 C0XPS0 SIMPS1 SIMPS0 PCKPS1 PCKPS0 PRM1 TCK2PS TCK1PS TCK0PS — INT1PS INT0PS TP1B1PS TP1B0PS PRM2 TP31PS TP30PS TP21PS Register Name 7 6 5 4 3 2 1 0 PRM0 C1XPS1 C1XPS0 C0XPS1 C0XPS0 SIMPS1 SIMPS0 PCKPS1 PCKPS0 PRM1 TCK2PS TCK1PS TCK0PS INT2PS INT1PS INT0PS TP1B1PS TP1B0PS PRM2 TP31PS TP30PS TP21PS TP20PS TP1B2PS TP1APS 7 6 TP20PS TP1B2PS TP1APS TP01PS TP00PS ●● HT67F50 Bit TP20PS TP1B2PS TP1APS TP01PS TP00PS ●● HT67F60 Bit TP01PS TP00PS PRM0 Register ●● HT67F30 Bit Name Rev. 1.80 1XPS1 C1XPS0 5 4 3 2 1 0 C0XPS1 C0XPS0 — — — — R/W R/W R/W R/W R/W — — — — POR 0 0 0 0 — — — — Bit 7~6 C1XPS1, C1XPS0: C1X Pin Remapping Control 00: C1X on PA5 01: C1X on PE6 10: C1X on PE7 11: Undefined Bit 5~4 C0XPS1, C0XPS0: C0X Pin Remapping Control 00: C0X on PA0 01: C0X on PE2 10: C0X on PE3 11: Undefined Bit 3~0 Unimplemented, read as “0” 93 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM PRM0 Register ●● HT67F40 Bit 7 6 5 4 3 2 1 0 Name C1XPS1 C1XPS0 C0XPS1 C0XPS0 SIMPS1 SIMPS0 PCKPS1 PCKPS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 1 PCKPS1 R/W 0 0 PCKPS0 R/W 0 Bit 7~6 C1XPS1, C1XPS0: C1X Pin Remapping Control 00: C1X on PA5 01: C1X on PE6 10: C1X on PE7 11: Undefined Bit 5~4 C0XPS1, C0XPS0: C0X Pin Remapping Control 00: C0X on PA0 01: C0X on PE2 10: C0X on PE3 11: Undefined Bit 3~2 SIMPS1, SIMPS0: SIM Pin Remapping Control 00: SDO on PC1; SDI/SDA on PC0; SCK/SCL on PA7; SCS on PA6 01: SDO on PC5; SDI/SDA on PC4; SCK/SCL on PC3; SCS on PC2 10: Undefined 11: Undefined Bit 1~0 PCKPS1, PCKPS0: PCK and PINTB Pin Remapping Control 00: PCK on PA5; PINTB on PA4 01: PCK on PC1; PINTB on PC0 10: Undefined 11: Undefined PRM0 Register ●● HT67F50/HT67F60 Bit Name R/W POR Rev. 1.80 7 C1XPS1 R/W 0 6 C1XPS0 R/W 0 5 C0XPS1 R/W 0 4 C0XPS0 R/W 0 3 SIMPS1 R/W 0 2 SIMPS0 R/W 0 Bit 7~6 C1XPS1, C1XPS0: C1X Pin Remapping Control 00: C1X on PA5 01: C1X on PE6 10: C1X on PE7 11: Undefined Bit 5~4 C0XPS1, C0XPS0: C0X Pin Remapping Control 00: C0X on PA0 01: C0X on PE2 10: C0X on PE3 11: Undefined Bit 3~2 SIMPS1, SIMPS0: SIM Pin Remapping Control 00: SDO on PC1; SDI/SDA on PC0; SCK/SCL on PA7; SCS on PA6 01: SDO on PC5; SDI/SDA on PC4; SCK/SCL on PC3; SCS on PC2 10: SDO on PG5; SDI/SDA on PG4; SCK/SCL on PG3; SCS on PG2 11: Undefined Bit 1~0 PCKPS1, PCKPS0: PCK and PINTB Pin Remapping Control 00: PCK on PA5; PINTB on PA4 01: PCK on PC1; PINTB on PC0 10: PCK on PG1; PINTB on PG0 11: Undefined 94 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM PRM1 Register ●● HT67F30 Bit 7 6 5 4 3 2 Name — TCK1PS TCK0PS — INT1PS INT0PS R/W — R/W R/W — R/W R/W R/W R/W POR — 0 0 — 0 0 0 0 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 0 TP1B1PS TP1B0PS Unimplemented, read as “0” TCK1PS: TCK1 Pin Remapping Control 0: TCK1 on PA4 1: TCK1 on PE1 TCK0PS: TCK0 Pin Remapping Control 0: TCK0 on PA2 1: TCK0 on PE0 Unimplemented, read as “0” INT1PS: INT1B Pin Remapping Control 0: INT1B on PA4 1: INT1B on PE5 INT0PS: INT0B Pin Remapping Control 0: INT0B on PA3 1: INT0B on PE4 TP1B1PS: TP1B_1 Pin Remapping Control 0: TP1B_1 on PC1 1: TP1B_1 on PD4 TP1B0PS: TP1B_0 Pin Remapping Control 0: TP1B_0 on PC0 1: TP1B_0 on PD3 ●● HT67F40/HT67F50 Bit 7 6 5 4 3 2 Name TCK2PS TCK1PS TCK0PS — INT1PS INT0PS R/W R/W R/W R/W — R/W R/W R/W R/W POR 0 0 0 — 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev. 1.80 TP1B1PS TP1B0PS TCK2PS: TCK2 Pin Remapping Control 0: TCK2 on PC2 1: TCK2 on PE2 TCK1PS: TCK1 Pin Remapping Control 0: TCK1 on PA4 1: TCK1 on PE1 TCK0PS: TCK0 Pin Remapping Control 0: TCK0 on PA2 1: TCK0 on PE0 Unimplemented, read as “0” INT1PS: INT1B Pin Remapping Control 0: INT1B on PA4 1: INT1B on PE5 INT0PS: INT0B Pin Remapping Control 0: INT0B on PA3 1: INT0B on PE4 TP1B1PS: TP1B_1 Pin Remapping Control 0: TP1B_1 on PC1 1: TP1B_1 on PD4 TP1B0PS: TP1B_0 Pin Remapping Control 0: TP1B_0 on PC0 1: TP1B_0 on PD3 95 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM PRM1 Register ●● HT67F60 Bit 7 6 5 4 3 2 Name TCK2PS TCK1PS TCK0PS INT2PS INT1PS INT0PS R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 TCK2PS: TCK2 Pin Remapping Control 0: TCK2 on PC2 1: TCK2 on PE2 Bit 6 TCK1PS: TCK1 Pin Remapping Control 0: TCK1 on PA4 1: TCK1 on PE1 Bit 5 TCK0PS: TCK0 Pin Remapping Control 0: TCK0 on PA2 1: TCK0 on PE0 Bit 4 INT2PS: INT2 Pin Remapping Control 0: INT2 on PC4 1: INT2 on PE6 Bit 3 INT1PS: INT1B Pin Remapping Control 0: INT1B on PA4 1: INT1B on PE5 Bit 2 INT0PS: INT0B Pin Remapping Control 0: INT0B on PA3 1: INT0B on PE4 Bit 1 TP1B1PS: TP1B_1 Pin Remapping Control 0: TP1B_1 on PC1 1: TP1B_1 on PD4 Bit 0 TP1B0PS: TP1B_0 Pin Remapping Control 0: TP1B_0 on PC0 1: TP1B_0 on PD3 1 0 TP1B1PS TP1B0PS PRM2 Register ●● HT67F30 Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name — — — — — TP1APS TP01PS TP00PS R/W — — — — — R/W R/W R/W POR — — — — — 0 0 0 Bit 7~3 Unimplemented, read as “0” Bit 2 TP1APS: TP1A Pin Remapping Control 0: TP1A on PA1 1: TP1A on PD2 Bit 1 TP01PS: TP0_1 Pin Remapping Control 0: TP0_1 on PA7 1: TP0_1 on PD1 Bit 0 TP00PS: TP0_0 Pin Remapping Control 0: TP0_0 on PA0 1: TP0_0 on PD0 96 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● HT67F40 Bit 7 6 5 Name — — TP21PS 4 R/W — — R/W R/W R/W POR — — 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5 TP21PS: TP2_1 Pin Remapping Control 0: TP2_1 on PC4 1: TP2_1 on PD7 TP20PS: TP2_0 Pin Remapping Control 0: TP2_0 on PC3 1: TP2_0 on PD6 TP1B2PS: TP1B_2 Pin Remapping Control 0: TP1B_2 on PC5 1: TP1B_2 on PD5 TP1APS: TP1A Pin Remapping Control 0: TP1A on PA1 1: TP1A on PD2 TP01PS: TP0_1 Pin Remapping Control 0: TP0_1 on PC5 1: TP0_1 on PD1 TP00PS: TP0_0 Pin Remapping Control 0: TP0_0 on PA0 1: TP0_0 on PD0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3 2 1 0 TP01PS TP00PS R/W R/W R/W 0 0 0 0 3 2 TP20PS TP1B2PS TP1APS ●● HT67F50/HT67F60 Bit 7 6 5 Name TP31PS TP30PS TP21PS R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev. 1.80 4 1 0 TP01PS TP00PS R/W R/W R/W 0 0 0 TP20PS TP1B2PS TP1APS TP31PS: TP3_1 Pin Remapping Control 0: TP3_1 on PG0 1: TP3_1 on PF1 TP30PS: TP3_0 Pin Remapping Control 0: TP3_0 on PG3 1: TP3_0 on PF0 TP21PS: TP2_1 Pin Remapping Control 0: TP2_1 on PC4 1: TP2_1 on PD7 TP20PS: TP2_0 Pin Remapping Control 0: TP2_0 on PC3 1: TP2_0 on PD6 TP1B2PS: TP1B_2 Pin Remapping Control 0: TP1B_2 on PC5 1: TP1B_2 on PD5 TP1APS: TP1A Pin Remapping Control 0: TP1A on PA1 1: TP1A on PD2 TP01PS: TP0_1 Pin Remapping Control 0: TP0_1 on PC5 1: TP0_1 on PD1 TP00PS: TP0_0 Pin Remapping Control 0: TP0_0 on PA0 1: TP0_0 on PD0 97 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers, PAC~PHC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA~PH, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the “SET [m].i” and “CLR [m].i” instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Generic Input/Output Structure Rev. 1.80 98 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions each device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has either two or three individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Compact, Standard and Enhanced TM sections. Introduction The devices contain from two to four TMs depending upon which device is selected with each TM having a reference name of TM0, TM1, TM2 and TM3. Each individual TM can be categorised as a certain type, namely Compact Type TM, Standard Type TM or Enhanced Type TM. Although similar in nature, the different TM types vary in their feature complexity. The common features to all of the Compact, Standard and Enhanced TMs will be described in this section, the detailed operation regarding each of the TM types will be described in separate sections. The main features and differences between the three types of TMs are summarised in the accompanying table. CTM STM ETM Timer/Counter Function √ √ √ I/P Capture — √ √ Compare Match Output — √ √ PWM Channels 1 1 2 Single Pulse Output — 1 2 Edge Edge Edge & Centre Duty or Period Duty or Period Duty or Period PWM Alignment PWM Adjustment Period & Duty TM Function Summary Each device in the series contains a specific number of either Compact Type, Standard Type and Enhanced Type TM units which are shown in the table together with their individual reference name, TM0~TM3. Device TM0 TM1 TM2 TM3 HT67F30 10-bit CTM 10-bit ETM — — HT67F40 10-bit CTM 10-bit ETM 16-bit STM — HT67F50 10-bit CTM 10-bit ETM 16-bit STM 10-bit CTM HT67F60 10-bit CTM 10-bit ETM 16-bit STM 10-bit CTM TM Name/Type Reference Rev. 1.80 99 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM TM Operation The three different types of TM offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the TnCK2~TnCK0 bits in the TM control registers. The clock source can be a ratio of either the system clock fSYS or the internal high clock fH, the fTBC clock source or the external TCKn pin. Note that setting these bits to the value 101 will select a reserved clock input, in effect disconnecting the TM clock source. The TCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. TM Interrupts The Compact and Standard type TMs each have two internal interrupts, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. As the Enhanced type TM has three internal comparators and comparator A or comparator B or comparator P compare match functions, it consequently has three internal interrupts. When a TM interrupt is generated it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has one TM input pin, with the label TCKn. The TM input pin, is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in the TMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the TnCK2~TnCK0 bits. The TM input pin can be chosen to have either a rising or falling active edge. The TMs each have one or more output pins with the label TPn. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external TPn output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other function, the TM output function must first be setup using registers. A single bit in one of the registers determines if its associated pin is to be used as an external TM output pin or if it is to have another function. The number of output pins for each TM type and device is different, the details are provided in the accompanying table. All TM output pin names have a “_n” suffix. Pin names that include a “_1” or “_2” suffix indicate that they are from a TM with multiple output pins. This allows the TM to generate a complimentary output pair, selected using the I/O register data bits. Rev. 1.80 100 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Device CTM STM ETM Registers TMPC0 HT67F30 TP0_0, TP0_1 — TP1A, TP1B_0, TP1B_1 HT67F40 TP0_0, TP0_1 TP2_0, TP2_1 TP1A, TP1B_0, TP1B_1, TP1B_2 TMPC0, TMPC1 HT67F50 TP0_0, TP0_1 TP3_0, TP3_1 TP2_0, TP2_1 TP1A, TP1B_0, TP1B_1, TP1B_2 TMPC0, TMPC1 HT67F60 TP0_0, TP0_1 TP3_0, TP3_1 TP2_0, TP2_1 TP1A, TP1B_0, TP1B_1, TP1B_2 TMPC0, TMPC1 TM Output Pins TM Input/Output Pin Control Registers Selecting to have a TM input/output or whether to retain its other shared function, is implemented using one or two registers, with a single bit in each register corresponding to a TM input/output pin. Setting the bit high will setup the corresponding pin as a TM input/output, if reset to zero the pin will retain its original other function. Registers Device Bit 7 6 — 5 4 3 2 1 0 TMPC0 HT67F30 T1ACP0 T1BCP1 T1BCP0 — — T0CP1 T0CP0 TMPC0 HT67F40 HT67F50 T1ACP0 T1BCP2 T1BCP1 T1BCP0 HT67F60 — — T0CP1 T0CP0 TMPC1 HT67F40 — — — — — — T2CP1 T2CP0 TMPC1 HT67F50 HT67F60 — — T3CP1 T3CP0 — — T2CP1 T2CP0 TM Input/Output Pin Control Registers List Rev. 1.80 101 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM 0 P A 0 O u tp u t F u n c tio n P A 0 /T P 0 _ 0 1 0 1 T 0 C P 0 P A 0 0 P C 5 O u tp u t F u n c tio n O u tp u t 1 P C 5 /T P 0 _ 1 1 0 T 0 C P 1 P C 5 T C K In p u t P A 2 /T C K 0 0 P A 1 O u tp u t F u n c tio n P A 1 /T P 1 A 1 C C R A O u tp u t T 1 A C P 0 1 C C R A C a p tu re In p u t 0 T 1 A C P 0 P C 0 O u tp u t F u n c tio n 0 P C 0 /T P 1 B _ 0 1 0 1 T 1 B C P 0 P C 0 P C 1 O u tp u t F u n c tio n C C R B O u tp u t 0 1 0 1 P C 1 /T P 1 B _ 1 T 1 B C P 1 P C 1 1 C C R B C a p tu re In p u t 0 T 1 B C P 1 1 0 T 1 B C P 0 T C K In p u t P A 4 /T C K 1 HT67F30 TM Function Pin Control Block Diagram Note: (1) The I/O register data bits shown are used for TM output inversion control. (2) In the Capture Input Mode, the TM pin control register must never enable more than one TM input. Rev. 1.80 102 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM 0 P A 0 O u tp u t F u n c tio n P A 0 /T P 0 _ 0 1 0 1 T 0 C P 0 P A 0 0 P C 5 O u tp u t F u n c tio n O u tp u t 1 0 1 P C 5 /T P 0 _ 1 T 0 C P 1 P C 5 T C K In p u t P A 2 /T C K 0 P C 3 O u tp u t F u n c tio n 0 P C 3 /T P 2 _ 0 1 0 1 T 2 C P 0 P C 3 P C 4 O u tp u t F u n c tio n O u tp u t 0 1 0 1 P C 4 /T P 2 _ 1 T 2 C P 1 P C 4 1 C a p tu re In p u t 0 T 2 C P 1 1 0 T 2 C P 0 T C K In p u t P C 2 /T C K 2 HT67F40 TM0 & TM2 Function Pin Control Block Diagram Note: (1) The I/O register data bits shown are used for TM output inversion control. (2) In the Capture Input Mode, the TM pin control register must never enable more than one TM input. Rev. 1.80 103 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM 0 P A 1 O u tp u t F u n c tio n 1 C C R A O u tp u t P A 1 /T P 1 A T 1 A C P 0 1 C C R A C a p tu re In p u t 0 T 1 A C P 0 P C 0 O u tp u t F u n c tio n 0 P C 0 /T P 1 B _ 0 1 0 1 T 1 B C P 0 P C 0 P C 1 O u tp u t F u n c tio n 0 P C 1 /T P 1 B _ 1 1 0 1 T 1 B C P 1 P C 1 P C 5 O u tp u t F u n c tio n C C R B O u tp u t 0 1 0 1 P C 5 /T P 1 B _ 2 T 1 B C P 2 P C 5 1 C C R B C a p tu re In p u t 0 T 1 B C P 2 1 0 T 1 B C P 1 1 0 T 1 B C P 0 T C K In p u t P A 4 /T C K 1 HT67F40 TM1 Function Pin Control Block Diagram Note: (1) The I/O register data bits shown are used for TM output inversion control. (2) In the Capture Input Mode, the TM pin control register must never enable more than one TM input. Rev. 1.80 104 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM 0 P A 0 O u tp u t F u n c tio n P A 0 /T P 0 _ 0 1 0 1 T 0 C P 0 P A 0 0 P C 5 O u tp u t F u n c tio n P C 5 /T P 0 _ 1 1 O u tp u t 0 1 T 0 C P 1 P C 5 T C K In p u t P A 2 /T C K 0 P C 3 O u tp u t F u n c tio n 0 P C 3 /T P 2 _ 0 1 0 1 T 2 C P 0 P C 3 P C 4 O u tp u t F u n c tio n O u tp u t 0 P C 4 /T P 2 _ 1 1 0 1 T 2 C P 1 P C 4 1 C a p tu re In p u t 0 T 2 C P 1 1 0 T 2 C P 0 T C K In p u t P C 2 /T C K 2 0 P D 3 O u tp u t F u n c tio n P D 3 /T P 3 _ 0 1 0 1 T 3 C P 0 P D 3 0 P D 0 O u tp u t F u n c tio n O u tp u t 0 1 1 P D 0 /T P 3 _ 1 T 3 C P 1 P D 0 T C K In p u t P C 4 /T C K 3 HT67F50 and HT67F60 TM0, TM2, TM3 Function Pin Control Block Diagram Note: (1) The I/O register data bits shown are used for TM output inversion control. (2) In the Capture Input Mode, the TM pin control register must never enable more than one TM input. Rev. 1.80 105 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM 0 P A 1 O u tp u t F u n c tio n 1 C C R A O u tp u t P A 1 /T P 1 A T 1 A C P 0 1 C C R A C a p tu re In p u t 0 T 1 A C P 0 P C 0 O u tp u t F u n c tio n 0 P C 0 /T P 1 B _ 0 1 0 1 T 1 B C P 0 P C 0 P C 1 O u tp u t F u n c tio n 0 P C 1 /T P 1 B _ 1 1 0 1 T 1 B C P 1 P C 1 P C 5 O u tp u t F u n c tio n C C R B O u tp u t 0 1 0 1 P C 5 /T P 1 B _ 2 T 1 B C P 2 P C 5 1 C C R B C a p tu re In p u t 0 T 1 B C P 2 1 0 T 1 B C P 1 1 0 T 1 B C P 0 T C K In p u t P A 4 /T C K 1 HT67F50 and HT67F60 TM1 Function Pin Control Block Diagram Note: (1) The I/O register data bits shown are used for TM output inversion control. (2) In the Capture Input Mode, the TM pin control register must never enable more than one TM input. Rev. 1.80 106 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM TMPC0 Register ●● HT67F30 Bit 7 6 5 4 3 2 1 0 Name T1ACP0 — T1BCP1 T1BCP0 — — T0CP1 T0CP0 R/W R/W — R/W R/W — — R/W R/W POR 1 — 0 1 — — 0 1 Bit 7 T1ACP0: TP1A pin Control 0: disable 1: enable Bit 6 Unimplemented, read as "0" Bit 5 T1BCP1: TP1B_1 pin Control 0: disable 1: enable Bit 4 T1BCP0: TP1B_0 pin Control 0: disable 1: enable Bit 3~2 Unimplemented, read as "0" Bit 1 T0CP1: TP0_1 pin Control 0: disable 1: enable Bit 0 T0CP0: TP0_0 pin Control 0: disable 1: enable ●● HT67F40/HT67F50/HT67F60 Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name T1ACP0 T1BCP2 T1BCP1 T1BCP0 — — T0CP1 T0CP0 R/W R/W R/W R/W R/W — — R/W R/W POR 1 0 0 1 — — 0 1 Bit 7 T1ACP0: TP1A pin Control 0: disable 1: enable Bit 6 T1BCP2: TP1B_2 pin Control 0: disable 1: enable Bit 5 T1BCP1: TP1B_1 pin Control 0: disable 1: enable Bit 4 T1BCP0: TP1B_0 pin Control 0: disable 1: enable Bit 3~2 Unimplemented, read as "0" Bit 1 T0CP1: TP0_1 pin Control 0: disable 1: enable Bit 0 T0CP0: TP0_0 pin Control 0: disable 1: enable 107 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM TMPC1 Register ●● HT67F40 Bit 7 6 5 4 3 2 1 0 Name — — — — — — T2CP1 T2CP0 R/W — — — — — — R/W R/W POR — — — — — — 0 1 Bit 7~2 Unimplemented, read as "0" Bit 1 T2CP1: TP2_1 pin Control 0: disable 1: enable Bit 0 T2CP0: TP2_0 pin Control 0: disable 1: enable ●● HT67F50/HT67F60 Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name — — T3CP1 T3CP0 — — T2CP1 T2CP0 R/W — — R/W R/W — — R/W R/W POR — — 0 1 — — 0 1 Bit 7~6 Unimplemented, read as "0" Bit 5 T3CP1: TP3_1 pin Control 0: disable 1: enable Bit 4 T3CP0: TP3_0 pin Control 0: disable 1: enable Bit 3~2 Unimplemented, read as "0" Bit 1 T2CP1: TP2_1 pin Control 0: disable 1: enable Bit 0 T2CP0: TP2_0 pin Control 0: disable 1: enable 108 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRB registers, being either 10-bit or 16-bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. TM Co�nter Register (Read only) TMxDL TMxDH 8-bit B�ffer TMxAL TMxAH TM CCRA Register (Read/Write) TMxBL TMxBH TM CCRB Register (Read/Write) Data B�s The following steps show the read and write procedures: ●● Writing Data to CCRB or CCRA ♦♦ Step 1. Write data to Low Byte TMxAL or TMxBL ––note that here data is only written to the 8-bit buffer. ♦♦ Step 2. Write data to High Byte TMxAH or TMxBH ––here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. ●● Reading Data from the Counter Registers and CCRB or CCRA ♦♦ Step 1. Read data from the High Byte TMxDH, TMxAH or TMxBH ––here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte TMxDL, TMxAL or TMxBL ––this step reads data from the 8-bit buffer. As the CCRA and CCRB registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way described above, it is recommended to use the “MOV” instruction to access the CCRA and CCRB low byte registers, named TMxAL and TMxBL, using the following access procedures. Accessing the CCRA or CCRB low byte registers without following these access procedures will result in unpredictable values. Rev. 1.80 109 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Compact Type TM Although the simplest form of the three TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive one or two external output pins. These two external output pins can be the same signal or the inverse signal. TM Name TM No. TM Input Pin TM Output Pin HT67F30 10-bit CTM 0 TCK0 TP0_0, TP0_1 HT67F40 10-bit CTM 0 TCK0 TP0_0, TP0_1 HT67F50 10-bit CTM 0, 3 TCK0, TCK3 TP0_0, TP0_1; TP3_0, TP3_1 HT67F60 10-bit CTM 0, 3 TCK0, TCK3 TP0_0, TP0_1; TP3_0, TP3_1 Compact TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is three bits wide whose value is compared with the highest three bits in the counter while the CCRA is the ten bits and therefore compares with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Compact Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Compact Type TM Block Diagram Rev. 1.80 110 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Compact Type TM Register Description Overall operation of the Compact TM is controlled using six registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMnC0 TnPAU TnCK2 TnCK1 TnCK0 TnON TnRP2 TnRP1 TnRP0 TMnC1 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR TMnDL D7 D6 D5 D4 D3 D2 D1 D0 TMnDH — — — — — — D9 D8 TMnAL D7 D6 D5 D4 D3 D2 D1 D0 TMnAH — — — — — — D9 D8 Compact TM Register List (n=0 or 3) ●● TMnDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 TMnDL: TMn Counter Low Byte Register bit 7 ~ bit 0 TMn 10-bit Counter bit 7 ~ bit 0 ●● TMnDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 TMnDH: TMn Counter High Byte Register bit 1 ~ bit 0 TMn 10-bit Counter bit 9 ~ bit 8 ●● TMnAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 2 1 0 Bit 7~0 TMnAL: TMn CCRA Low Byte Register bit 7 ~ bit 0 TMn 10-bit CCRA bit 7 ~ bit 0 ●● TMnAH Register Bit Rev. 1.80 7 6 5 4 3 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 TMnAH: TMn CCRA High Byte Register bit 1 ~ bit 0 TMn 10-bit CCRA bit 9 ~ bit 8 111 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● TMnC0 Register Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name TnPAU TnCK2 TnCK1 TnCK0 TnON TnRP2 TnRP1 TnRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 TnPAU: TMn Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 TnCK2~TnCK0: Select TMn Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Undefined 110: TCKn rising edge clock 111: TCKn falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. Bit 3 TnON: TMn Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the TnOC bit, when the TnON bit changes from low to high. Bit 2~0 TnRP2~TnRP0: TMn CCRP 3-bit register, compared with the TMn Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TMn clocks 001: 128 TMn clocks 010: 256 TMn clocks 011: 384 TMn clocks 100: 512 TMn clocks 101: 640 TMn clocks 110: 768 TMn clocks 111: 896 TMn clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter's highest three bits. The result of this comparison can be selected to clear the internal counter if the TnCCLR bit is set to zero. Setting the TnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. 112 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● TMnC1 Register Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 TnM1~TnM0: Select TMn Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the TnM1 and TnM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4 TnIO1~TnIO0: Select TPn_0, TPn_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Undefined Timer/counter Mode unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the TnOC bit in the TMnC1 register. Note that the output level requested by the TnIO1 and TnIO0 bits must be different from the initial value setup using the TnOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the TnON bit from low to high. In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the TnIO1 and TnIO0 bits only after the TMn has been switched off. Unpredictable PWM outputs will occur if the TnIO1 and TnIO0 bits are changed when the TM is running. Bit 3 TnOC: TPn_0, TPn_1 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode. 113 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 TnPOL: TPn_0, TPn_1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TPn_0 or TPn_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1 TnDPX: TMn PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0 TnCCLR: Select TMn Counter clear condition 0: TMn Comparatror P match 1: TMn Comparatror A match This bit is used to select the method which clears the counter. Remember that the Compact TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the TnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The TnCCLR bit is not used in the PWM Mode. Compact Type TM Operating Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Match Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for the Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the TnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the TM output pin will change state. The TM output pin condition however only changes state when an TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the Rev. 1.80 114 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place. Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. Co�nter Val�e Co�nter overflow CCRP=0 0x�FF TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 Co�nter cleared by CCRP val�e CCRP > 0 CCRP CCRA Co�nter Restart Res�me Pa�se Stop Time TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin O�tp�t pin set to initial Level Low if TnOC=0 O�tp�t not affected by TnAF flag. Remains High �ntil reset by TnON bit O�tp�t Toggle with TnAF flag Note TnIO [1:0] = 10 Active High O�tp�t select Here TnIO [1:0] = 11 Toggle O�tp�t select O�tp�t Inverts when TnPOL is high O�tp�t Pin Reset to Initial val�e O�tp�t controlled by other pin-shared f�nction Compare Match Output Mode — TnCCLR = 0 Note: 1. With TnCCLR=0, a Comparator P match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge Rev. 1.80 115 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Co�nter Val�e TnCCLR = 1; TnM [1:0] = 00 CCRA = 0 Co�nter overflow CCRA > 0 Co�nter cleared by CCRA val�e 0x�FF CCRA=0 Res�me CCRA Pa�se Stop Co�nter Restart CCRP Time TnON TnPAU TnPOL No TnAF flag generated on CCRA overflow CCRA Int. Flag TnAF CCRP Int. Flag TnPF TnPF not generated O�tp�t does not change TM O/P Pin O�tp�t pin set to initial Level Low if TnOC=0 O�tp�t not affected by TnAF flag. Remains High �ntil reset by TnON bit O�tp�t Toggle with TnAF flag Here TnIO [1:0] = 11 Toggle O�tp�t select Note TnIO [1:0] = 10 Active High O�tp�t select O�tp�t Inverts when TnPOL is high O�tp�t Pin Reset to Initial val�e O�tp�t controlled by other pin-shared f�nction Compare Match Output Mode — TnCCLR = 1 Note: 1. With TnCCLR=1, a Comparator A match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge 4. The TnPF flag is not generated when TnCCLR=1 PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform. Rev. 1.80 116 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM CTM, PWM Mode, Edge-aligned Mode, T0DPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 100b and CCRA = 128, The CTM PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125 kHz, duty = 128/512 = 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. CTM, PWM Mode, Edge-aligned Mode, T0DPX=1 CCRP 001b 010b 011b 100b Period Duty 101b 110b 111b 000b 768 896 1024 CCRA 128 256 384 512 640 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value. Co�nter Val�e TnDPX = 0; TnM [1:0] = 10 Co�nter cleared by CCRP Co�nter Reset when TnON ret�rns high CCRP Pa�se Res�me CCRA Co�nter Stop if TnON bit low Time TnON TnPAU TnPOL CCRA Int. Flag TnAF CCRP Int. Flag TnPF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM D�ty Cycle set by CCRA PWM Period set by CCRP PWM res�mes operation O�tp�t controlled by O�tp�t Inverts other pin-shared f�nction when TnPOL = 1 PWM Mode — TnDPX = 0 Note: 1. Here TnDPX=0 – Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 1.80 117 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Co�nter Val�e TnDPX = 1; TnM [1:0] = 10 Co�nter cleared by CCRA Co�nter Reset when TnON ret�rns high CCRA Pa�se Res�me CCRP Co�nter Stop if TnON bit low Time TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM D�ty Cycle set by CCRP PWM Period set by CCRA PWM res�mes operation O�tp�t controlled by O�tp�t Inverts other pin-shared f�nction when TnPOL = 1 PWM Mode — TnDPX = 1 Note: 1. Here TnDPX = 1 – Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation Standard Type TM – STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with an external input pin and can drive one or two external output pins. CTM Name TM No. TM Input Pin HT67F30 — — — TM Output Pin — HT67F40 16-bit STM 2 TCK2 TP2_0, TP2_1 HT67F50 16-bit STM 2 TCK2 TP2_0, TP2_1 HT67F60 16-bit STM 2 TCK2 TP2_0, TP2_1 Standard TM Operation There are two sizes of Standard TMs, one is 10-bits wide and the other is 16-bits wide. At the core is a 10 or 16-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP comparator is 3 or 8-bits wide whose value is compared the with highest 3 or 8 bits in the counter while the CCRA is the ten or sixteen bits and therefore compares all counter bits. The only way of changing the value of the 10 or 16-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Standard Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Rev. 1.80 118 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Standard Type TM Register Description Overall operation of the Standard TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10 or 16-bit value, while a read/write register pair exists to store the internal 10 or 16-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three or eight CCRP bits. Standard Type TM Block Diagram Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TM2C0 T2PAU T2CK2 T2CK1 T2CK0 T2ON — — — TM2C1 T2M1 T2M0 T2IO1 T2IO0 T2OC T2POL T2DPX T2CCLR TM2DL D7 D6 D5 D4 D3 D2 D1 D0 TM2DH D15 D14 D13 D12 D11 D10 D9 D8 TM2AL D7 D6 D5 D4 D3 D2 D1 D0 TM2AH D15 D14 D13 D12 D11 D10 D9 D8 TM2RP D7 D6 D5 D4 D3 D2 D1 D0 16-bit Standard TM Register List (for HT67F40/HT67F50/HT67F60) Rev. 1.80 119 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM 16-bit Standard TM Register List - HT67F40/HT67F50/HT67F60 ●● TM2C0 Register - 16-bit STM Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name T2PAU T2CK2 T2CK1 T2CK0 T2ON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7 T2PAU: TM2 Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 T2CK2, T2CK1, T2CK0: Select TM2 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Undefined 110: TCK2 rising edge clock 111: TCK2 falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. Bit 3 T2ON: TM2 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T2OC bit, when the T2ON bit changes from low to high. Bit 2~0 Unimplemented, read as "0" 120 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● TM2C1 Register - 16-bit STM Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name T2M1 T2M0 T2IO1 T2IO0 T2OC T2POL T2DPX T2CCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 T2M1~T2M0: Select TM2 Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T2M1 and T2M0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4 T2IO1~T2IO0: Select TP2_0, TP2_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/ Single Pulse Output Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP2_0, TP2_1 01: Input capture at falling edge of TP2_0, TP2_1 10: Input capture at falling/rising edge of TP2_0, TP2_1 11: Input capture disabled Timer/counter Mode: Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the T2IO1 and T2IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T2OC bit in the TM2C1 register. Note that the output level requested by the T2IO1 and T2IO0 bits must be different from the initial value setup using the T2OC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T2ON bit from low to high. In the PWM Mode, the T1IO1 and T1IO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the T1IO1 and T1IO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the T1IO1 and T1IO0 bits are changed when the TM is running. 121 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Rev. 1.80 Bit 3 T2OC: TP2_0, TP2_1 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 T2POL: TP2_0, TP2_1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP2_0 or TP2_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1 T2DPX: TM2 PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0 T2CCLR: Select TM2 Counter clear condition 0: TM2 Comparator P match 1: TM2 Comparator A match This bit is used to select the method which clears the counter. Remember that the Standard TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the T2CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T1CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode. 122 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● TM2DL Register - 16-bit STM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 TM2DL: TM2 Counter Low Byte Register bit 7~bit 0 TM2 16-bit Counter bit 7~bit 0 ●● TM2DH Register - 16-bit STM Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 2 1 0 Bit 7~0 TM2DH: TM2 Counter High Byte Register bit 7~bit 0 TM2 16-bit Counter bit 15~bit 8 ●● TM2AL Register - 16-bit STM Bit 7 6 5 4 3 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 TM2AL: TM2 CCRA Low Byte Register bit 7~bit 0 TM2 16-bit CCRA bit 7~bit 0 ●● TM2AH Register - 16-bit STM Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 TM2AH: TM2 CCRA High Byte Register bit 7~bit 0 TM2 16-bit CCRA bit 15~bit 8 ●● TM2RP Register - 16-bit STM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.80 TM2RP: TM2 CCRP Register bit 7 ~ bit 0 TM2 CCRP 8-bit register, compared with the TM2 Counter bit 15 ~ bit 8. Comparator P Match Period 0: 65536 TM2 clocks 1~255: 256 x (1~255) TM2 clocks These eight bits are used to setup the value on the internal CCRP 8-bit register, which are then compared with the internal counter's highest eight bits. The result of this comparison can be selected to clear the internal counter if the T2CCLR bit is set to zero. Setting the T2CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. Clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value. 123 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Standard Type TM Operating Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to "0". As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when an TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place. 10-bit STM, PWM Mode, Edge-aligned Mode, T0DPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA If fSYS = 16MHz, TM clock source select fSYS/4, CCRP = 100b and CCRA = 128, The STM PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125kHz, duty = 128/512 = 25% If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. 10-bit STM, PWM Mode, Edge-aligned Mode, T0DPX=1 CCRP 001b 010b 011b 100b Period Duty 101b 110b 111b 000b 768 896 1024 CCRA 128 256 384 512 640 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value. Rev. 1.80 124 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM 16-bit STM, PWM Mode, Edge-aligned Mode, T0DPX=0 CCRP 1~255 000b Period CCRP x 256 65536 Duty CCRA If fSYS = 16MHz, TM clock source select fSYS/4, CCRP = 2 and CCRA = 128, The STM PWM output frequency = (fSYS/4) / (2 x 256) = fSYS/2048 = 7.8125kHz, duty = 128 / (2 x 256) = 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. 16-bit STM, PWM Mode, Edge-aligned Mode, T0DPX=1 CCRP 1~255 Period 000b CCRA Duty CCRP x 256 65536 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the (CCRP x 256) except when the CCRP value is equal to 000b. Co�nter overflow Co�nter Val�e CCRP=0 0x�FF TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 Co�nter cleared by CCRP val�e CCRP > 0 CCRP Pa�se CCRA Co�nter Restart Res�me Stop Time TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin O�tp�t pin set to initial Level Low if TnOC=0 O�tp�t not affected by TnAF flag. Remains High �ntil reset by TnON bit O�tp�t Toggle with TnAF flag Note TnIO [1:0] = 10 Active High O�tp�t select Here TnIO [1:0] = 11 Toggle O�tp�t select O�tp�t Inverts when TnPOL is high O�tp�t Pin Reset to Initial val�e O�tp�t controlled by other pin-shared f�nction Compare Match Output Mode — TnCCLR = 0 Note: 1. With TnCCLR=0 a Comparator P match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to itsinitial state by a TnON bit rising edge Rev. 1.80 125 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Co�nter Val�e TnCCLR = 1; TnM [1:0] = 00 CCRA = 0 Co�nter overflow CCRA > 0 Co�nter cleared by CCRA val�e 0x�FF CCRA=0 Res�me CCRA Pa�se Stop Co�nter Restart CCRP Time TnON TnPAU TnPOL No TnAF flag generated on CCRA overflow CCRA Int. Flag TnAF CCRP Int. Flag TnPF TnPF not generated O�tp�t does not change TM O/P Pin O�tp�t pin set to initial Level Low if TnOC=0 O�tp�t not affected by TnAF flag. Remains High �ntil reset by TnON bit O�tp�t Toggle with TnAF flag Here TnIO [1:0] = 11 Toggle O�tp�t select Note TnIO [1:0] = 10 Active High O�tp�t select O�tp�t Inverts when TnPOL is high O�tp�t Pin Reset to Initial val�e O�tp�t controlled by other pin-shared f�nction Compare Match Output Mode — TnCCLR = 1 Note: 1. With TnCCLR=1 a Comparator A match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge 4. A TnPF flag is not generated when TnCCLR=1 Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. Rev. 1.80 126 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform. Co�nter Val�e TnDPX = 0; TnM [1:0] = 10 Co�nter cleared by CCRP Co�nter Reset when TnON ret�rns high CCRP Pa�se Res�me CCRA Co�nter Stop if TnON bit low Time TnON TnPAU TnPOL CCRA Int. Flag TnAF CCRP Int. Flag TnPF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM D�ty Cycle set by CCRA PWM Period set by CCRP PWM res�mes operation O�tp�t controlled by O�tp�t Inverts other pin-shared f�nction when TnPOL = 1 PWM Mode — TnDPX = 0 Note: 1. Here TnDPX=0 – Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 1.80 127 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Co�nter Val�e TnDPX = 1; TnM [1:0] = 10 Co�nter cleared by CCRA Co�nter Reset when TnON ret�rns high CCRA Pa�se Res�me CCRP Co�nter Stop if TnON bit low Time TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM D�ty Cycle set by CCRP PWM res�mes operation O�tp�t controlled by O�tp�t Inverts other pin-shared f�nction when TnPOL = 1 PWM Period set by CCRA PWM Mode — TnDPX = 1 Note: 1. Here TnDPX=1 – Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation Single Pulse Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. Single Pulse Generation Rev. 1.80 128 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Co�nter Val�e TnM [1:0] = 10 ; TnIO [1:0] = 11 Co�nter stopped by CCRA Co�nter Reset when TnON ret�rns high CCRA Pa�se Co�nter Stops by software Res�me CCRP Time TnON Software Trigger A�to. set by TCKn pin Cleared by CCRA match TCKn pin Software Trigger Software Trigger Software Software Trigger Clear TCKn pin Trigger TnPAU TnPOL CCRP Int. Flag TnPF No CCRP Interr�pts generated CCRA Int. Flag TnAF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) O�tp�t Inverts when TnPOL = 1 P�lse Width set by CCRA Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse is triggered by the TCKn pin or by setting the TnON bit high 4. A TCKn pin active edge will automatically set the TnON bit hight 5. In the Single Pulse Mode, TnIO [1:0] must be set to “11” and can not be changed. However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR and TnDPX bits are not used in this Mode. Capture Input Mode To select this mode bits TnM1 and TnM0 in the TMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPn_0 or TPn_1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnIO1 and TnIO0 bits in the TMnC1 register. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TPn_0 or TPn_1 pin the present value in the counter will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what events occur on the TPn_0 or TPn_1 pin the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnIO1 and TnIO0 bits can select the active trigger edge on the TPn_0 or TPn_1 pin to be a rising edge, falling edge or both edge types. If the TnIO1 and TnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TPn_0 or TPn_1 pin, however it must be noted that the counter will continue to run. Rev. 1.80 129 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM As the TPn_0 or TPn_1 pin is pin shared with other functions, care must be taken if the TM is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The TnCCLR and TnDPX bits are not used in this Mode. Co�nter Val�e TnM [1:0] = 01 Co�nter cleared by CCRP Co�nter Co�nter Reset Stop CCRP YY Pa�se Res�me XX Time TnON TnPAU TM capt�re pin TPn_x Active edge Active edge Active edge CCRA Int. Flag TnAF CCRP Int. Flag TnPF CCRA Val�e TnIO [1:0] Val�e XX 00 – Rising edge YY 01 – Falling edge XX 10 – Both edges YY 11 – Disable Capt�re Capture Input Mode Note: 1. TnM [1:0] = 01 and active edge set by the TnIO [1:0] bits 2. A TM Capture input pin active edge transfers the counter value to CCRA 3. TnCCLR bit not used 4. No output function – TnOC and TnPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.80 130 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Enhanced Type TM – ETM The Enhanced Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Enhanced TM can also be controlled with an external input pin and can drive three or four external output pins. CTM Name TM No. TM Input Pin TM Output Pin HT67F30 10-bit ETM 1 TCK1 TP1A; TP1B_0, TP1B_1 HT67F40 10-bit ETM 1 TCK1 TP1A, TP1B_0, TP1B_1, TP1B_2 HT67F50 10-bit ETM 1 TCK1 TP1A, TP1B_0, TP1B_1, TP1B_2 HT67F60 10-bit ETM 1 TCK1 TP1A, TP1B_0, TP1B_1, TP1B_2 Enhanced TM Operation At its core is a 10-bit count-up/count-down counter which is driven by a user selectable internal or external clock source. There are three internal comparators with the names, Comparator A, Comparator B and Comparator P. These comparators will compare the value in the counter with the CCRA, CCRB and CCRP registers. The CCRP comparator is 3-bits wide whose value is compared with the highest 3-bits in the counter while CCRA and CCRB are 10-bits wide and therefore compared with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Enhanced Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control output pins. All operating setup conditions are selected using relevant internal registers. Enhanced Type TM Block Diagram Rev. 1.80 131 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Enhanced Type TM Register Description Overall operation of the Enhanced TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA and CCRB value. The remaining three registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TM1C0 T1PAU T1CK2 T1CK1 T1CK0 T1ON T1RP2 T1RP1 T1RP0 TM1C1 T1AM1 T1AM0 T1AIO1 T1AIO0 T1AOC T1APOL T1CDN T1CCLR TM1C2 T1BM1 T1BM0 T1BIO1 T1BIO0 T1BOC T1BPOL T1PWM1 T1PWM0 TM1DL D7 D6 D5 D4 D3 D2 D1 D0 TM1DH — — — — — — D9 D8 TM1AL D7 D6 D5 D4 D3 D2 D1 D0 TM1AH — — — — — — D9 D8 TM1BL D7 D6 D5 D4 D3 D2 D1 D0 TM1BH — — — — — — D9 D8 10-bit Enhanced TM Register List (if ETM is TM1) 10-bit Enhanced TM Register List - HT67F30/HT67F40/HT67F50/HT67F60 ●● TM1C0 Register - 10-bit ETM Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name T1PAU T1CK2 T1CK1 T1CK0 T1ON T1RP2 T1RP1 T1RP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 T1PAU: TM1 Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 T1CK2~T1CK0: Select TM1 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Undefined 110: TCK1 rising edge clock 111: TCK1 falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. 132 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Bit 3 T1ON: TM1 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T1OC bit, when the T1ON bit changes from low to high. Bit 2~0 T1RP2~T1RP0: TM1 CCRP 3-bit register, compared with the TM1 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TM1 clocks 001: 128 TM1 clocks 010: 256 TM1 clocks 011: 384 TM1 clocks 100: 512 TM1 clocks 101: 640 TM1 clocks 110: 768 TM1 clocks 111: 896 TM1 clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter┬ highest three bits. The result of this comparison can be selected to clear the internal counter if the T1CCLR bit is set to zero. Setting the T1CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. ●● TM1C1 Register - 10-bit ETM Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name T1AM1 T1AM0 T1AIO1 T1AIO0 T1AOC T1APOL T1CDN T1CCLR R/W R/W R/W R/W R/W R/W R/W R R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 T1AM1~T1AM0: Select TM1 CCRA Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T1AM1 and T1AM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4 T1AIO1~T1AIO0: Select TP1A output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/ Single Pulse Output Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Single pulse output 133 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Capture Input Mode 00: Input capture at rising edge of TP1A 01: Input capture at falling edge of TP1A 10: Input capture at falling/rising edge of TP1A 11: Input capture disabled Timer/counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the T1AIO1 and T1AIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T1AOC bit in the TM1C1 register. Note that the output level requested by the T1AIO1 and T1AIO0 bits must be different from the initial value setup using the T1AOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T1ON bit from low to high. In the PWM Mode, the T1AIO1 and T1AIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the T1AIO1 and T1AIO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the T1AIO1 and T1AIO0 bits are changed when the TM is running. Rev. 1.80 Bit 3 T1AOC: TP1A Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 T1APOL: TP1A Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP1A output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1 T1CDN: TM1 Counter count up or down flag 0: Count up 1: Count down Bit 0 T1CCLR: Select TM1 Counter clear condition 0: TM1 Comparator P match 1: TM1 Comparator A match This bit is used to select the method which clears the counter. Remember that the Enhanced TM contains three comparators, Comparator A, Comparator B and Comparator P, but only Comparator A or Comparator P can be selected to clear the internal counter. With the T1CCLR bit set high, the counter will be cleared when a 134 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T1CCLR bit is not used in the Single Pulse or Input Capture Mode. ●● TM1C2 Register - 10-bit ETM Bit 7 6 5 4 3 Name T1BM1 T1BM0 T1BIO1 T1BIO0 T1BOC R/W R/W R/W R/W R/W R/W R/W R R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Bit 5~4 Rev. 1.80 2 1 0 T1BPOL T1PWM1 T1PWM0 T1BM1~T1BM0: Select TM1 CCRB Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T1BM1 and T1BM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. T1BIO1~T1BIO0: Select TP1B_0, TP1B_1, TP1B_2 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP1B_0, TP1B_1, TP1B_2 01: Input capture at falling edge of TP1B_0, TP1B_1, TP1B_2 10: Input capture at falling/rising edge of TP1B_0, TP1B_1, TP1B_2 11: Input capture disabled Timer/counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the T1BIO1 and T1BIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T1BOC bit in the TM1C2 register. Note that the output level requested by the T1BIO1 and T1BIO0 bits must be different from the initial value setup using the T1BOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T1ON bit from low to high. In the PWM Mode, the T1BIO1 and T1BIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the value of the T1BIO1 and T1BIO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the T1BIO1 and T1BIO0 bits are changed when the TM is running. 135 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Bit 3 T1BOC: TP1B_0, TP1B_1, TP1B_2 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 T1BPOL: TP1B_0, TP1B_1, TB1B_2 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP1B_0, TP1B_1, TP1B_2 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1~0 T1PWM1~T1PWM0: Select PWM Mode 00: Edge aligned 01: Centre aligned, compare match on count up 10: Centre aligned, compare match on count down 11: Centre aligned, compare match on count up or down ●● TM1DL Register - 10-bit ETM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 2 1 0 Bit 7~0 TM1DL: TM1 Counter Low Byte Register bit 7~bit 0 TM1 10-bit Counter bit 7~bit 0 ●● TM1DH Register - 10-bit ETM Bit 7 6 5 4 3 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 TM1DH: TM1 Counter High Byte Register bit 1~bit 0 TM1 10-bit Counter bit 9~bit 8 ●● TM1AL Register - 10-bit ETM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.80 TM1AL: TM1 CCRA Low Byte Register bit 7~bit 0 TM1 10-bit CCRA bit 7~bit 0 136 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● TM1AH Register - 10-bit ETM Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 TM1AH: TM1 CCRA High Byte Register bit 1~bit 0 TM1 10-bit CCRA bit 9~bit 8 ●● TM1BL Register - 10-bit ETM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0 TM1BL: TM1 CCRB Low Byte Register bit 7~bit 0 TM1 10-bit CCRB bit 7~bit 0 ●● TM1BH Register - 10-bit ETM Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 TM1BH: TM1 CCRB High Byte Register bit 1~bit 0 TM1 10-bit CCRB bit 9 ~ bit 8 Enhanced Type TM Operating Modes The Enhanced Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnAM1 and TnAM0 bits in the TMnC1, and the TnBM1 and TnBM0 bits in the TMnC2 register. ETM Operating Mode Rev. 1.80 CCRA Compare CCRA Timer/ CCRB PWM Match Output Counter Mode Output Mode Mode CCRB Single CCRB Input Pulse Output Capture Mode Mode CCRB Compare Match Output Mode √ — — — — CCRB Timer/Counter Mode — √ — — — CCRB PWM Output Mode — — √ — — CCRB Single Pulse Output Mode — — — √ — CCRB Input Capture Mode — — — — √ “√”: permitted “—”: not permitted 137 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Compare Output Mode To select this mode, bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1/TMnC2 registers should be all cleared to zero. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both the TnAF and TnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when an TnAF or TnBF interrupt request flag is generated after a compare match occurs from Comparator A or Comparator B. The TnPF interrupt request flag, generated from a compare match from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state is determined by the condition of the TnAIO1 and TnAIO0 bits in the TMnC1 register for ETM CCRA, and the TnBIO1 and TnBIO0 bits in the TMnC2 register for ETM CCRB. The TM output pin can be selected using the TnAIO1, TnAIO0 bits (for the TPnA pin) and TnBIO1, TnBIO0 bits (for the TPnB_0, TPnB_1 or TPnB_2 pins) to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A or a compare match occurs from Comparator B. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnAOC or TnBOC bit for TPnA or TPnB_0, TPnB_1, TPnB_2 output pins. Note that if the TnAIO1,TnAIO0 and TnBIO1, TnBIO0 bits are zero then no pin change will take place. Co�nter Val�e Co�nter overflow CCRP=0 0x�FF TnCCLR = 0; TnAM [1:0] = 00 CCRP > 0 Co�nter cleared by CCRP val�e CCRP > 0 CCRP CCRA Co�nter Restart Res�me Pa�se Stop Time TnON TnPAU TnAPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TPnA O/P Pin O�tp�t pin set to initial Level Low if TnAOC=0 O�tp�t not affected by TnAF flag. Remains High �ntil reset by TnON bit O�tp�t Toggle with TnAF flag Note TnAIO [1:0] = 10 Active High O�tp�t select Here TnAIO [1:0] = 11 Toggle O�tp�t select O�tp�t Inverts when TnAPOL is high O�tp�t Pin Reset to Initial val�e O�tp�t controlled by other pin-shared f�nction ETM CCRA Compare Match Output Mode — TnCCLR = 0 Note: 1. With TnCCLR=0 a Comparator P match will clear the counter 2. The TPnA output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge Rev. 1.80 138 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Co�nter Val�e Co�nter overflow TnCCLR = 0; TnBM [1:0] = 00 CCRP > 0 Co�nter cleared by CCRP val�e CCRP=0 0x�FF CCRP > 0 Co�nter Restart Res�me CCRP Stop Pa�se CCRB Time TnON TnPAU TnBPOL CCRP Int. Flag TnPF CCRB Int. Flag TnBF TPnB O/P Pin O�tp�t pin set to initial Level Low if TnBOC=0 O�tp�t not affected by TnBF flag. Remains High �ntil reset by TnON bit O�tp�t Toggle with TnBF flag Note TnBIO [1:0] = 10 Active High O�tp�t select Here TnBIO [1:0] = 11 Toggle O�tp�t select O�tp�t Inverts when TnBPOL is high O�tp�t Pin Reset to Initial val�e O�tp�t controlled by other pin-shared f�nction ETM CCRB Compare Match Output Mode — TnCCLR = 0 Note: 1. With TnCCLR=0 a Comparator P match will clear the counter 2. The TPnB output pin is controlled only by the TnBF flag 3. The output pin is reset to its initial state by a TnON bit rising edge Co�nter Val�e TnCCLR = 1; TnAM [1:0] = 00 CCRA = 0 Co�nter overflow CCRA > 0 Co�nter cleared by CCRA val�e 0x�FF CCRA=0 Res�me CCRA Pa�se Stop Co�nter Restart CCRP Time TnON TnPAU TnAPOL No TnAF flag generated on CCRA overflow CCRA Int. Flag TnAF CCRP Int. Flag TnPF TnPF not generated O�tp�t does not change TPnA O/P Pin O�tp�t pin set to initial Level Low if TnAOC=0 O�tp�t not affected by TnAF flag. Remains High �ntil reset by TnON bit O�tp�t Toggle with TnAF flag Here TnAIO [1:0] = 11 Toggle O�tp�t select Note TnAIO [1:0] = 10 Active High O�tp�t select O�tp�t Inverts when TnAPOL is high O�tp�t Pin Reset to Initial val�e O�tp�t controlled by other pin-shared f�nction ETM CCRA Compare Match Output Mode — TnCCLR = 1 Note: 1. With TnCCLR=1 a Comparator A match will clear the counter 2. The TPnA output pin is controlled only by the TnAF flag 3. The TPnA output pin is reset to its initial state by a TnON bit rising edge 4. The TnPF flag is not generated when TnCCLR=1 Rev. 1.80 139 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Co�nter Val�e TnCCLR = 1; TnBM [1:0] = 00 CCRA = 0 Co�nter overflow CCRA > 0 Co�nter cleared by CCRA val�e 0x�FF Res�me CCRA Pa�se CCRA=0 Stop Co�nter Restart CCRB Time TnON TnPAU TnBPOL No TnAF flag generated on CCRA overflow CCRA Int. Flag TnAF CCRB Int. Flag TnBF TPnB O/P Pin O�tp�t pin set to initial Level Low if TnBOC=0 O�tp�t not affected by TnBF flag. Remains High �ntil reset by TnON bit O�tp�t Toggle with TnBF flag Here TnBIO [1:0] = 11 Toggle O�tp�t select Note TnBIO [1:0] = 10 Active High O�tp�t select O�tp�t Inverts when TnBPOL is high O�tp�t Pin Reset to Initial val�e O�tp�t controlled by other pin-shared f�nction ETM CCRB Compare Match Output Mode — TnCCLR = 1 Note: 1. With TnCCLR=1 a Comparator A match will clear the counter 2. The TPnB output pin is controlled only by the TnBF flag 3. The TPnB output pin is reset to its initial state by a TnON bit rising edge 4. The TnPF flag is not generated when TnCCLR=1 Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. Rev. 1.80 140 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform. ●● ETM, PWM Mode, Edge — aligned Mode, TnCCLR=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 A Duty CCRA B Duty CCRB If fSYS = 16MHz, TM clock source select fSYS/4, CCRP = 100b, CCRA = 128 and CCRB = 256, The TP1A PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125kHz, duty = 128/512 = 25%. The TP1B_n PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125kHz, duty = 256/512 = 50%. If the Duty value defined by CCRA or CCRB register is equal to or greater than the Period value, then the PWM output duty is 100%. ●● ETM, PWM Mode, Edge — aligned Mode, TnCCLR=1 CCRA 1 2 3 511 Period 1 2 3 511 B Duty 512 1021 1022 1023 512 1021 1022 1023 CCRB ●● ETM, PWM Mode, Center — aligned Mode, TnCCLR=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 256 512 768 1024 1280 1536 1792 2046 A Duty (CCRAx2)-1 B Duty (CCRBx2)-1 ●● ETM, PWM Mode, Center — aligned Mode, TnCCLR=1 CCRA 1 2 3 511 512 1021 1022 1023 Period 2 4 6 1022 1024 2042 2044 2046 B Duty Rev. 1.80 (CCRBx2)-1 141 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Co�nter Val�e TnCCLR = 0; TnAM [1:0] = 10� TnBM [1:0] = 10; TnPWM [1:0] = 00 Co�nter Cleared by CCRP CCRP CCRA Pa�se Res�me Co�nter Restart Stop CCRB Time TnON TnPAU TnAPOL CCRA Int. Flag TnAF CCRB Int. Flag TnBF CCRP Int. Flag TnPF TPnA Pin (TnAOC=1) D�ty Cycle set by CCRA TPnB Pin D�ty Cycle set by CCRA D�ty Cycle set by CCRA O�tp�t Inverts when TnAPOL is high (TnBOC=1) TPnB Pin (TnBOC=0) D�ty Cycle set by CCRB O�tp�t controlled by other pin-shared f�nction O�tp�t Pin Reset to Initial val�e PWM Period set by CCRP ETM PWM Mode — Edge Aligned Note: 1. Here TnCCLR=0 therefore CCRP clears counter and determines the PWM period 2. The internal PWM function continues running even when TnAIO [1:0] (or TnBIO [1:0]) = 00 or 01 3. CCRA controls the TPnA PWM duty and CCRB controls the TPnB PWM duty Co�nter Val�e Co�nter Cleared by CCRA TnCCLR = 1; TnBM [1:0] = 10; TnPWM [1:0] = 00 CCRA Pa�se Res�me Stop CCRB Co�nter Restart Time TnON TnPAU TnBPOL CCRP Int. Flag TnPF CCRB Int. Flag TnBF TPnB Pin (TnBOC=1) TPnB Pin (TnBOC=0) D�ty Cycle set by CCRB O�tp�t controlled by other pin-shared f�nction PWM Period set by CCRA O�tp�t Pin Reset to Initial val�e O�tp�t Inverts when TnBPOL is high ETM PWM Mode — Edge Aligned Note: 1. Here TnCCLR=1, therefore CCRA clears the counter and determines the PWM period 2. The internal PWM function continues running even when TnBIO [1:0] = 00 or 01 3. The CCRA controls the TPnB PWM period and CCRB controls the TPnB PWM duty 4. Here the TM pin control register should not enable the TPnA pin as a TM output pin. Rev. 1.80 142 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM TnCCLR = 0; TnAM [1:0] = 10� TnBM [1:0] = 10; TnPWM [1:0] = 11 Co�nter Val�e CCRP Stop Res�me CCRA Co�nter Restart Pa�se CCRB Time TnON TnPAU TnAPOL CCRA Int. Flag TnAF CCRB Int. Flag TnBF CCRP Int. Flag TnPF TPnA Pin (TnAOC=1) TPnB Pin D�ty Cycle set by CCRA O�tp�t Inverts when TnAPOL is high (TnBOC=1) TPnB Pin (TnBOC=0) D�ty Cycle set by CCRB O�tp�t controlled by Other pin-shared f�nction PWM Period set by CCRP O�tp�t Pin Reset to Initial val�e ETM PWM Mode — Centre Aligned Note: 1. Here TnCCLR=0 therefore CCRP clears the counter and determines the PWM period 2. TnPWM [1:0] =11 therefore the PWM is centre aligned 3. The internal PWM function continues running even when TnAIO [1:0] (or TnBIO [1:0]) = 00 or 01 4. CCRA controls the TPnA PWM duty and CCRB controls the TPnB PWM duty 5. CCRP will generate an interrupt request when the counter decrements to its zero value Co�nter Val�e TnCCLR = 1; TnBM [1:0] = 10; TnPWM [1:0] = 11 CCRA Stop Res�me Co�nter Restart Pa�se CCRB Time TnON TnPAU TnBPOL CCRA Int. Flag TnAF CCRB Int. Flag TnBF CCRP Int. Flag TnPF TPnB Pin (TnBOC=1) TPnB Pin (TnBOC=0) D�ty Cycle set by CCRB PWM Period set by CCRA O�tp�t controlled O�tp�t Inverts by other pin-shared when TnBPOL is high f�nction O�tp�t Pin Reset to Initial val�e ETM PWM Mode — Centre Aligned Note: 1. Here TnCCLR=1 therefore CCRA clears the counter and determines the PWM period 2. TnPWM [1:0] =11 therefore the PWM is centre aligned 3. The internal PWM function continues running even when TnBIO [1:0] = 00 or 01 4. CCRA controls the TPnB PWM period and CCRB controls the TPnB PWM duty 5. CCRP will generate an interrupt request when the counter decrements to its zero value Rev. 1.80 143 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Single Pulse Mode To select this mode, the required bit pairs, TnAM1, TnAM0 and TnBM1, TnBM0 should be set to 10 respectively and also the corresponding TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse TPnA output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. The trigger for the pulse TPnB output leading edge is a compare match from Comparator B, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output of TPnA. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge of TPnA will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge of TPnA and TPnB will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge of TPnA and TPnB. In this way the CCRA value can be used to control the pulse width of TPnA. The CCRA-CCRB value can be used to control the pulse width of TPnB. A compare match from Comparator A and Comparator B will also generate TM interrupts. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR bit is also not used. Co�nter Val�e CCRA CCRB Time 0 S/W Command SET“TnON” or TCKn Pin Transition CCRA Leading Edge CCRA Trailing Edge TnON bit 0 1 TnON bit 1 0 S/W Command CLR“TnON” or CCRA Compare Match TPnA O�tp�t Pin P�lse Width = CCRA Val�e TPnB O�tp�t Pin P�lse Width = (CCRA-CCRB) Val�e CCRB Compare Match TnON = 1 TnON bit 1 0 CCRB Leading Edge CCRB Trailing Edge S/W Command CLR“TnON” or CCRA Compare Match Single Pulse Generation Rev. 1.80 144 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse is triggered by the TCKn pin or by setting the TnON bit high 4. A TCKn pin active edge will automatically set the TnON bit high 5. In the Single Pulse Mode, TnAIO [1:0] and TnBIO [1:0] must be set to “11” and can not be changed. Rev. 1.80 145 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Capture Input Mode To select this mode bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1 and TMnC2 registers should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits in the TMnC1 and TMnC2 registers. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins the present value in the counter will be latched into the CCRA and CCRB registers and a TM interrupt generated. Irrespective of what events occur on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits can select the active trigger edge on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins to be a rising edge, falling edge or both edge types. If the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins, however it must be noted that the counter will continue to run. As the TPnA and TPnB_0, TPnB_1, TPnB_2 pins are pin shared with other functions, care must be taken if the TM is in the Capture Input Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The TnCCLR, TnAOC, TnBOC, TnAPOL and TnBPOL bits are not used in this mode. ETM CCRA Capture Input Mode Note: 1. TnAM [1:0] = 01 and active edge set by the TnAIO [1:0] bits 2. The TM Capture input pin active edge transfers the counter value to CCRA 3. TnCCLR bit not used 4. No output function – TnAOC and TnAPOL bits not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.80 146 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ETM CCRB Capture Input Mode Note: 1. TnBM [1:0] = 01 and active edge set by the TnBIO [1:0] bits 2. The TM Capture input pin active edge transfers the counter value to CCRB 3. TnCCLR bit not used 4. No output function – TnBOC and TnBPOL bits not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.80 147 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Overview The devices contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. Part No. Input Channels A/D Channel Select Bits Input Pins HT67F30 HT67F40 HT67F50 8 ACS4, ACS2~ACS0 AN0~AN7 HT67F60 12 ACS4, ACS3~ACS0 AN0~AN11 The accompanying block diagram shows the overall internal structure of the A/D converter, together with its associated registers. A/D Converter Register Description Overall operation of the A/D converter is controlled using six registers. A read only register pair exists to store the ADC data 12-bit value. The remaining three or four registers are control registers which setup the operating and control function of the A/D converter. Bit Register Name 7 6 5 4 3 2 1 0 ADRL(ADRFS=0) D3 D2 D1 D0 — — — — ADRL(ADRFS=1) D7 D6 D5 D4 D3 D2 D1 D0 ADRH(ADRFS=0) D11 D10 D9 D8 D7 D6 D5 D4 ADRH(ADRFS=1) — — — — D11 D10 D9 D8 ADCR0 START EOCB ADOFF ADRFS — ACS2 ACS1 ACS0 ADCR1 ACS4 V125EN — VREFS — ADCK2 ADCK1 ADCK0 ACE7 ACE6 ACE5 ACE4 ACE3 ACE2 ACE1 ACE0 ACERL HT67F30/HT67F40/HT67F50 A/D Converter Register List Register Name ADRL(ADRFS=0) Bit 7 6 5 4 3 2 1 0 D3 D2 D1 D0 — — — — ADRL(ADRFS=1) D7 D6 D5 D4 D3 D2 D1 D0 ADRH(ADRFS=0) D11 D10 D9 D8 D7 D6 D5 D4 ADRH(ADRFS=1) — — — — D11 D10 D9 D8 ADCR0 START EOCB ADOFF ADRFS ACS3 ACS2 ACS1 ACS0 ADCR1 ACS4 V125EN — VREFS — ADCK2 ADCK1 ADCK0 ACERL ACE7 ACE6 ACE5 ACE4 ACE3 ACE2 ACE1 ACE0 ACERH — — — — ACE11 ACE10 ACE9 ACE8 HT67F60 A/D Converter Register List Rev. 1.80 148 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM A/D Converter Structure A/D Converter Data Registers – ADRL, ADRH As the devices contain an internal 12-bit A/D converter, they require two data registers to store the converted value. These are a high byte register, known as ADRH, and a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the ADRFS bit in the ADCR0 register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any unused bits will be read as zero. ADRFS 0 1 ADRH 7 6 D11 D10 0 0 5 4 D9 D8 0 0 ADRL 3 2 D7 D6 D11 D10 1 0 7 6 5 4 3 2 1 0 D5 D4 D3 D2 D1 D0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A/D Data Registers A/D Converter Control Registers – ADCR0, ADCR1, ACERL, ACERH To control the function and operation of the A/D converter, three or four control registers known as ADCR0, ADCR1, ACERL and ACERH are provided. These 8-bit registers define functions such as the selection of which analog channel is connected to the internal A/D converter, the digitised data format, the A/D clock source as well as controlling the start function and monitoring the A/D converter end of conversion status. The ACS3~ACS0 bits in the ADCR0 register and ACS4 bit is the ADCR1 register define the ADC input channel number. As the device contains only one actual analog to digital converter hardware circuit, each of the individual 8 or 12 analog inputs must be routed to the converter. It is the function of the ACS4~ACS0 bits to determine which analog channel input pins or internal 1.25V is actually connected to the internal A/D converter. The ACERH and ACERL control registers contain the ACER11~ACER0 bits which determine which pins on Port A, PH0~PH3 are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D converter input. Setting the corresponding bit high will select the A/D input function, clearing the bit to zero will select either the I/O or other pin-shared function. When the pin is selected to be an A/D input, its original function whether it is an I/O or other pinshared function will be removed. In addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an A/D input. Rev. 1.80 149 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ADCR0 Register ●● HT67F30/HT67F40/HT67F50 Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name START EOCB ADOFF ADRFS — ACS2 ACS1 ACS0 R/W R/W R R/W R/W — R/W R/W R/W POR 0 1 1 0 — 0 0 0 Bit 7 START: Start the A/D conversion 0→1→0: start 0→1 : reset the A/D converter and set EOCB to "1" This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. When the bit is set high the A/D converter will be reset. Bit 6 EOCB: End of A/D conversion flag 0: A/D conversion ended 1: A/D conversion in progress This read only flag is used to indicate when an A/D conversion process has completed. When the conversion process is running the bit will be high. Bit 5 ADOFF : ADC module power on/off control bit 0: ADC module power on 1: ADC module power off This bit controls the power to the A/D internal function. This bit should be cleared to zero to enable the A/D converter. If the bit is set high then the A/D converter will be switched off reducing the device power consumption. As the A/D converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. Note: 1. It is recommended to set ADOFF=1 before entering IDLE/SLEEP Mode for saving power. 2. ADOFF=1 will power down the ADC module. Bit 4 ADRFS: ADC Data Format Control 0: ADC Data MSB is ADRH bit 7, LSB is ADRL bit 4 1: ADC Data MSB is ADRH bit 3, LSB is ADRL bit 0 This bit controls the format of the 12-bit converted A/D value in the two A/D data registers. Details are provided in the A/D data register section. Bit 3 unimplemented, read as "0" Bit 2~0 ACS2, ACS1, ACS0: Select A/D channel (when ACS4 is "0") 000: AN0 001: AN1 010: AN2 011: AN3 100: AN4 101: AN5 110: AN6 111: AN7 These are the A/D channel select control bits. As there is only one internal hardware A/D converter each of the eight A/D inputs must be routed to the internal converter using these bits. If bit ACS4 in the ADCR1 register is set high then the internal 1.25V will be routed to the A/D Converter. 150 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● HT67F60 Rev. 1.80 Bit Name R/W 7 START R/W 6 EOCB R 5 ADOFF R/W 4 ADRFS R/W 3 ACS3 R/W 2 ACS2 R/W 1 ACS1 R/W 0 ACS0 R/W POR 0 1 1 0 0 0 0 0 Bit 7 START: Start the A/D conversion 0→1→0: start 0→1: reset the A/D converter and set EOCB to "1" This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. When the bit is set high the A/D converter will be reset. Bit 6 EOCB: End of A/D conversion flag 0: A/D conversion ended 1: A/D conversion in progress This read only flag is used to indicate when an A/D conversion process has completed. When the conversion process is running the bit will be high. Bit 5 ADOFF : ADC module power on/off control bit 0: ADC module power on 1: ADC module power off This bit controls the power to the A/D internal function. This bit should be cleared to zero to enable the A/D converter. If the bit is set high then the A/D converter will be switched off reducing the device power consumption. As the A/D converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. Note: 1. It is recommended to set ADOFF=1 before entering IDLE/SLEEP Mode for saving power. 2. ADOFF=1 will power down the ADC module. Bit 4 ADRFS: ADC Data Format Control 0: ADC Data MSB is ADRH bit 7, LSB is ADRL bit 4 1: ADC Data MSB is ADRH bit 3, LSB is ADRL bit 0 This bit controls the format of the 12-bit converted A/D value in the two A/D data registers. Details are provided in the A/D data register section. Bit 3~0 ACS3, ACS2, ACS1, ACS0: Select A/D channel (when ACS4 is "0") 0000: AN0 0001: AN1 0010: AN2 0011: AN3 0100: AN4 0101: AN5 0110: AN6 0111: AN7 1000: AN8 1001: AN9 1010: AN10 1011: AN11 1100~1111: undefined, can't be used These are the A/D channel select control bits. As there is only one internal hardware A/D converter each of the eight A/D inputs must be routed to the internal converter using these bits. If bit ACS4 in the ADCR1 register is set high then the internal 1.25V will be routed to the A/DConverter. 151 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ADCR1 Register Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name ACS4 V125EN — VREFS — ADCK2 ADCK1 ADCK0 R/W R/W R/W — R/W — R/W R/W R/W POR 0 0 — 0 — 0 0 0 Bit 7 ACS4: Selecte Internal 1.25V as ADC input Control 0: Disable 1: Enable This bit enables 1.25V to be connected to the A/D converter. The V125EN bit must first have been set to enable the bandgap circuit 1.25V voltage to be used by the A/D converter. When the ACS4 bit is set high, the bandgap 1.25V voltage will be routed to the A/D converter and the other A/D input channels disconnected. Bit 6 V125EN: Internal 1.25V Control 0: Disable 1: Enable This bit controls the internal Bandgap circuit on/off function to the A/D converter. When the bit is set high the bandgap voltage 1.25V can be used by the A/D converter. If 1.25V is not used by the A/D converter and the LVR/LVD function is disabled then the bandgap reference circuit will be automatically switched off to conserve power. When 1.25V is switched on for use by the A/D converter, a time tBG should be allowed for the bandgap circuit to stabilise before implementing an A/D conversion. Bit 5 unimplemented, read as "0" Bit 4 VREFS: Selecte ADC reference voltage 0: Internal ADC power 1: VREF pin This bit is used to select the reference voltage for the A/D converter. If the bit is high, then the A/D converter reference voltage is supplied on the external VREF pin. If the pin is low, then the internal reference is used which is taken from the power supply pin VDD. Bit 3 unimplemented, read as "0" Bit 2~0 ADCK2, ADCK1, ADCK0: Select ADC clock source 000: fSYS 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: Undefined These three bits are used to select the clock source for the A/D converter. 152 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ACERL Register Bit 7 6 5 4 3 2 1 0 Name ACE7 ACE6 ACE5 ACE4 ACE3 ACE2 ACE1 ACE0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7 ACE7: Define PA7 is A/D input or not 0: Not A/D input 1: A/D input, AN7 Bit 6 ACE6: Define PA6 is A/D input or not 0: Not A/D input 1: A/D input, AN6 Bit 5 ACE5: Define PA5 is A/D input or not 0: Not A/D input 1: A/D input, AN5 Bit 4 ACE4: Define PA4 is A/D input or not 0: Not A/D input 1: A/D input, AN4 Bit 3 ACE3: Define PA3 is A/D input or not 0: Not A/D input 1: A/D input, AN3 Bit 2 ACE2: Define PA2 is A/D input or not 0: Not A/D input 1: A/D input, AN2 Bit 1 ACE1: Define PA1 is A/D input or not 0: Not A/D input 1: A/D input, AN1 Bit 0 ACE0: Define PA0 is A/D input or not 0: Not A/D input 1: A/D input, AN0 ACERH Register ●● HT67F60 Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name — — — — ACE11 ACE10 ACE9 ACE8 R/W — — — — R/W R/W R/W R/W POR — — — — 1 1 1 1 Bit 7~4 unimplemented, read as "0" Bit 3 ACE11: Define PH3 is A/D input or not 0: Not A/D input 1: A/D input, AN11 Bit 2 ACE10: Define PH2 is A/D input or not 0: Not A/D input 1: A/D input, AN10 Bit 1 ACE9: Define PH1 is A/D input or not 0: Not A/D input 1: A/D input, AN9 Bit 0 ACE8: Define PH0 is A/D input or not 0: Not A/D input 1: A/D input, AN8 153 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM A/D Operation The START bit in the ADCR0 register is used to start and reset the A/D converter. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. When the START bit is brought from low to high but not low again, the EOCB bit in the ADCR0 register will be set high and the analog to digital converter will be reset. It is the START bit that is used to control the overall start operation of the internal analog to digital converter. The EOCB bit in the ADCR0 register is used to indicate when the analog to digital conversion process is complete. This bit will be automatically set to "0" by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/ D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOCB bit in the ADCR0 register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen to be either fSYS or a subdivided version of fSYS The division ratio value is determined by the ADCK2~ADCK0 bits in the ADCR1 register. Although the A/D clock source is determined by the system clock f SYS , and by bits ADCK2~ADCK0, there are some limitations on the maximum A/D clock source speed that can be selected. As the minimum value of permissible A/D clock period, tADCK, is 0.5ms, care must be taken for system clock frequencies equal to or greater than 4MHz. For example, if the system clock operates at a frequency of 4MHz, the ADCK2~ADCK0 bits should not be set to "000". Doing so will give A/D clock periods that are less than the minimum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum A/D Clock Period. A/D Clock Period (tADCK) fSYS ADCK2, ADCK1, ADCK0 =000 (fSYS) ADCK2, ADCK1, ADCK0 =001 (fSYS/2) ADCK2, ADCK1, ADCK0 =010 (fSYS/4) ADCK2, ADCK1, ADCK0 =011 (fSYS/8) ADCK2, ADCK1, ADCK0 =100 (fSYS/16) ADCK2, ADCK1, ADCK0 =101 (fSYS/32) ADCK2, ADCK1, ADCK0 =110 (fSYS/64) ADCK2, ADCK1, ADCK0 =111 1MHz 1µs 2µs 4µs 8µs 16µs 32µs 64µs Undefined 2MHz 500ns 1µs 2µs 4µs 8µs 16µs 32µs Undefined 4MHz 250ns* 500ns 1µs 2µs 4µs 8µs 16µs Undefined 8MHz 125ns* 250ns* 500ns 1µs 2µs 4µs 8µs Undefined 12MHz 83ns* 167ns* 333ns* 667ns 1.33µs 2.67µs 5.33µs Undefined A/D Clock Period Examples Controlling the power on/off function of the A/D converter circuitry is implemented using the ADOFF bit in the ADCR0 register. This bit must be zero to power on the A/D converter. When the ADOFF bit is cleared to zero to power on the A/D converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no pins are selected for use as A/D inputs by clearing the ACE11~ACE0 bits in the ACERH and ACERL registers, if the ADOFF bit is zero then some power will still be consumed. In power conscious applications it is therefore recommended that the ADOFF is set high to reduce power consumption when the A/D converter function is not being used. Rev. 1.80 154 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM The reference voltage supply to the A/D Converter can be supplied from either the positive power supply pin, VDD, or from an external reference sources supplied on pin VREF. The desired selection is made using the VREFS bit. As the VREF pin is pin-shared with other functions, when the VREFS bit is set high, the VREF pin function will be selected and the other pin functions will be disabled automatically. A/D Input Pins All of the A/D analog input pins are pin-shared with the I/O pins on Port A, PH0~PH3 as well as other functions. The ACE11~ ACE0 bits in the ACERH and ACERL registers, determine whether the input pins are setup as A/D converter analog inputs or whether they have other functions. If the ACE11~ ACE0 bits for its corresponding pin is set high then the pin will be setup to be an A/D converter input and the original pin functions disabled. In this way, pins can be changed under program control to change their function between A/D inputs and other functions. All pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note that it is not necessary to first setup the A/D pin as an input in the PAC or PHC port control register to enable the A/D input as when the ACE11~ ACE0 bits enable an A/D input, the status of the port control register will be overridden. The A/D converter has its own reference voltage pin, VREF, however the reference voltage can also be supplied from the power supply pin, a choice which is made through the VREFS bit in the ADCR1 register. The analog input values must not be allowed to exceed the value of VREF. A/D Input Structure Rev. 1.80 155 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/ D conversion process. ●● Step 1 Select the required A/D conversion clock by correctly programming bits ADCK2~ADCK0 in the ADCR1 register. ●● Step 2 Enable the A/D by clearing the ADOFF bit in the ADCR0 register to zero. ●● Step 3 Select which channel is to be connected to the internal A/D converter by correctly programming the ACS4~ACS0 bits which are also contained in the ADCR1 and ADCR0 register. ●● Step 4 Select which pins are to be used as A/D inputs and configure them by correctly programming the ACE11~ACE0 bits in the ACERH and ACERL registers. ●● Step 5 If the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, and the A/D converter interrupt bit, EADI, must both be set high to do this. ●● Step 6 The analog to digital conversion process can now be initialised by setting the START bit in the ADCR register from low to high and then low again. Note that this bit should have been originally cleared to zero. ●● Step 7 To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR0 register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur. Note: When checking for the end of the conversion process, if the method of polling the EOCB bit in the ADCR0 register is used, the interrupt enable step above can be omitted. A/D Conversion Timing Rev. 1.80 156 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16tADCK where tADCK is equal to the A/D clock period. Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D internal circuitry can be switched off to reduce power consumption, by setting bit ADOFF high in the ADCR0 register. When this happens, the internal A/D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. A/D Transfer Function As the devices contain a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the VDD or VREF voltage, this gives a single bit analog input value of VDD or VREF divided by 4096. 1 LSB= (VDD or VREF) ÷ 4096 The A/D Converter input voltage value can be calculated using the following equation: A/D input voltage = A/D output digital value × (VDD or VREF) ÷ 4096 The diagram shows the ideal transfer function between the analog input value and the digitised output value for the A/D converter. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 LSB below the VDD or VREF level. A/D Programming Example The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR0 register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Ideal A/D Transfer Function Rev. 1.80 157 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Example: using an EOCB polling method to detect the end of conversion clrEADI ; mova,03H mov ADCR1,a ; clr ADOFF mov a,0Fh ; mov ACERL,a mova,00h mov ACERH,00h ; mova,00h mov ADCR0,a ; : start_conversion: clr START ; set START ; clr START ; polling_EOC: sz EOCB ; ; jmp polling_EOC ; mov a,ADRL ; mov ADRL_buffer,a ; mov a,ADRH ; mov ADRH_buffer,a ; : : jmp start_conversion disable ADC interrupt select fSYS/8 as A/D clock and switch off 1.25V setup ACERL and ACERH to configure pins AN0~AN3 ACERH is only for HT67F60 enable and connect AN0 channel to A/D converter high pulse on start bit to initiate conversion reset A/D start A/D poll the ADCR0 register EOCB bit to detect end of A/D conversion continue polling read low byte conversion result value save result to user defined register read high byte conversion result value save result to user defined register ; start next a/d conversion Example: using the interrupt method to detect the end of conversion clr EADI ; disable ADC interrupt mova,03H mov ADCR1,a ; select fSYS/8 as A/D clock and switch off 1.25V Clr ADOFF mov a,0Fh ; setup ACERL and ACERH to configure pins AN0~AN3 mov ACERL,a mova,00h mov ACERH,00h ; ACERH is only for HT67F60 mova,00h mov ADCR0,a ; enable and connect AN0 channel to A/D converter Start_conversion: clr START ; high pulse on START bit to initiate conversion set START ; reset A/D clr START ; start A/D clr ADF ; clear ADC interrupt request flag set EADI ; enable ADC interrupt set EMI ; enable global interrupt : : ; ADC interrupt service routine ADC_ISR: mov acc_stack,a ; save ACC to user defined memory mov a,STATUS mov status_stack,a ; save STATUS to user defined memory : : mov a,ADRL ; read low byte conversion result value mov adrl_buffer,a ; save result to user defined register mov a,ADRH ; read high byte conversion result value mov adrh_buffer,a ; save result to user defined register : : EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti Rev. 1.80 158 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Comparators Two independent analog comparators are contained within these devices. These functions offer flexibility via their register controlled features such as power-down, polarity select, hysteresis etc. In sharing their pins with normal I/O pins the comparators do not waste precious I/O pins if there functions are otherwise unused. Comparator Comparator Operation The device contains two comparator functions which are used to compare two analog voltages and provide an output based on their difference. Full control over the two internal comparators is provided via two control registers, CP0C and CP1C, one assigned to each comparator. The comparator output is recorded via a bit in their respective control register, but can also be transferred out onto a shared I/O pin. Additional comparator functions include, output polarity, hysteresis functions and power down control. Any pull-high resistors connected to the shared comparator input pins will be automatically disconnected when the comparator is enabled. As the comparator inputs approach their switching level, some spurious output signals may be generated on the comparator output due to the slow rising or falling nature of the input signals. This can be minimised by selecting the hysteresis function will apply a small amount of positive feedback to the comparator. Ideally the comparator should switch at the point where the positive and negative inputs signals are at the same voltage level, however, unavoidable input offsets introduce some uncertainties here. The hysteresis function, if enabled, also increases the switching offset value. Comparator Registers There are two registers for overall comparator operation, one for each comparator. As corresponding bits in the two registers have identical functions, they following register table applies to both registers. Bit Register Name 7 6 5 4 3 2 1 0 CP0C C0SEL C0EN C0POL C0OUT C0OS — — C0HYEN CP1C C1SEL C1EN C1POL C1OUT C1OS — — C1HYEN Comparator Registers List Comparator Interrupt Each also possesses its own interrupt function. When any one of the changes state, its relevant interrupt flag will be set, and if the corresponding interrupt enable bit is set, then a jump to its relevant interrupt vector will be executed. Note that it is the changing state of the C0OUT or C1OUT bit and not the output pin which generates an interrupt. If the microcontroller is in the SLEEP or IDLE Mode and the Comparator is enabled, then if the external input lines cause the Comparator output to change state, the resulting generated interrupt flag will also generate a wake-up. If it is required to disable a wake-up from occurring, then the interrupt flag should be first set high before entering the SLEEP or IDLE Mode. Rev. 1.80 159 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Programming Considerations If the comparator is enabled, it will remain active when the microcontroller enters the SLEEP or IDLE Mode, however as it will consume a certain amount of power, the user may wish to consider disabling it before the SLEEP or IDLE Mode is entered. As comparator pins are shared with normal I/O pins the I/O registers for these pins will be read as zero (port control register is "1") or read as port data register value (port control register is "0") if the comparator function is enabled. ●● CP0C Register Bit 7 6 5 4 3 2 1 0 Name C0SEL C0EN C0POL C0OUT C0OS — — C0HYEN R/W R/W R/W R/W R R/W — — R/W POR 1 0 0 0 0 — — 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2~1 Bit 0 Rev. 1.80 C0SEL: Select Comparator pins or I/O pins 0: I/O pin select 1: Comparator pin select This is the Comparator pin or I/O pin select bit. If the bit is high the comparator will be selected and the two comparator input pins will be enabled. As a result, these two pins will lose their I/O pin functions. Any pull-high configuration options associated with the comparator shared pins will also be automatically disconnected. C0EN: Comparator On/Off control 0: Off 1: On This is the Comparator on/off control bit. If the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. For power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the SLEEP or IDLE mode. C0POL: Comparator output polarity 0: output not inverted 1: output inverted This is the comparator polarity bit. If the bit is zero then the C0OUT bit will reflect the non-inverted output condition of the comparator. If the bit is high the comparator C0OUT bit will be inverted. C0OUT: Comparator output bit C0POL=0 0: C0+ < C01: C0+ > C0C0POL=1 0: C0+ > C01: C0+ < C0This bit stores the comparator output bit. The polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the C0POL bit. C0OS: Output path select 0: C0X pin 1: Internal use This is the comparator output path select control bit. If the bit is set to "0" and the C0SEL bit is "1" the comparator output is connected to an external C0X pin. If the bit is set to "1" or the C0SEL bit is "0" the comparator output signal is only used internally by the device allowing the shared comparator output pin to retain its normal I/O operation. unimplemented, read as "0" C0HYEN: Hysteresis Control 0: Off 1: On This is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specified in the Comparator Electrical Characteristics table. The positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. 160 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● CP1C Register Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name C1SEL C1EN C1POL C1OUT C1OS — — C1HYEN R/W R/W R/W R/W R R/W — — R/W POR 1 0 0 0 0 — — 1 Bit 7 C1SEL: Select Comparator pins or I/O pins 0: I/O pin select 1: Comparator pin select This is the Comparator pin or I/O pin select bit. If the bit is high the comparator will be selected and the two comparator input pins will be enabled. As a result, these two pins will lose their I/O pin functions. Any pull-high configuration options associated with the comparator shared pins will also be automatically disconnected. Bit 6 C1EN: Comparator On/Off control 0: Off 1: On This is the Comparator on/off control bit. If the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. For power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the SLEEP or IDLE mode. Bit 5 C1POL: Comparator output polarity 0: output not inverted 1: output inverted This is the comparator polarity bit. If the bit is zero then the C1OUT bit will reflect the non-inverted output condition of the comparator. If the bit is high the comparator C1OUT bit will be inverted. Bit 4 C1OUT: Comparator output bit C1POL=0 0: C1+ < C11: C1+ > C1- C1POL=1 0: C1+ > C11: C1+ < C1- This bit stores the comparator output bit. The polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the C1POL bit. Bit 3 C1OS: Output path select 0: C1X pin 1: Internal use This is the comparator output path select control bit. If the bit is set to "0" and the C1SEL bit is "1" the comparator output is connected to an external C1X pin. If the bit is set to "1" or the C1SEL bit is "0" the comparator output signal is only used internally by the device allowing the shared comparator output pin to retain its normal I/O operation. Bit 2~1 unimplemented, read as "0" Bit 0 C1HYEN: Hysteresis Control 0: Off 1: On This is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specified in the Comparator Electrical Characteristics table. The positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. 161 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Serial Interface Module – SIM These devices contain a Serial Interface Module, which includes both the four line SPI interface or the two line I2C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins therefore the SIM interface function must first be selected using a configuration option. As both interface types share the same pins and registers, the choice of whether the SPI or I2C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 register. These pull-high resistors of the SIM pin-shared I/O are selected using pull-high control registers, and also if the SIM function is enabled. SPI Interface This SPI interface function which is contained within the Serial Interface Module, should not be confused with the other independent SPI function, known as SPIA, which is described in another section of this datasheet. The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the device can be either master or slave. Although the SPI interface specification can control multiple slave devices from a single master, but this device provided only one SCS pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pin to select the slave devices. SPI Interface Operation ●● The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface must first be enabled by selecting the SIM enable configuration option and setting the correct bits in the SIMC0 and SIMC2 registers. After the SPI configuration option has been configured it can also be additionally disabled or enabled using the SIMEN bit in the SIMC0 register. Communication between devices connected to the SPI interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The Master also controls the clock signal. As the device only contains a single SCS pin only one slave device can be utilized. The SCS pin is controlled by software, set CSEN bit to "1" to enable SCS pin function, set CSEN bit to "0" the SCS pin will be floating state. SPI Master/Slave Connection Rev. 1.80 162 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM SPI Block Diagram The SPI function in this device offers the following features: ●● Full duplex synchronous data transfer ●● Both Master and Slave modes ●● LSB first or MSB first data transmission modes ●● Transmission complete flag ●● Rising or falling active clock edge ●● WCOL and CSEN bit enabled or disable select The status of the SPI interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN. There are several configuration options associated with the SPI interface. One of these is to enable the SIM function which selects the SIM pins rather than normal I/O pins. Note that if the configuration option does not select the SIM function then the SIMEN bit in the SIMC0 register will have no effect. Another two SPI configuration options determine if the CSEN and WCOL bits are to be used. Rev. 1.80 163 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM SPI Registers There are three internal registers which control the overall operation of the SPI interface. These are the SIMD data register and two registers SIMC0 and SIMC2. Note that the SIMC1 register is only used by the I2C interface. Bit Register Name 7 6 5 4 3 2 1 0 SIMC0 SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMC2 D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF SIM Registers List The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register. ●● SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknow There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2 register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used by the SPI function, only by the I2C function. Register SIMC0 is used to control the enable/disable function and to set the data transmission clock frequency. Although not connected with the SPI function, the SIMC0 register is also used to control the Peripheral Clock Prescaler. Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag etc. Rev. 1.80 164 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● SIMC0 Register Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — R/W R/W R/W R/W R/W R/W R/W R/W — POR 1 1 1 0 0 0 0 — Bit 7~5 SIM2, SIM1, SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fTBC 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Unused mode These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 PCKEN: PCK Output Pin Control 0: Disable 1: Enable Bit 3~2 PCKP1, PCKP0: Select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 Bit 1 SIMEN: SIM Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be in a floating condition and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 unimplemented, read as "0" 165 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● SIMC2 Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Undefined bit This bit can be read or written by user software program. Bit 5 CKPOLB: Determines the base condition of the clock line 0: the SCK line will be high when the clock is inactive 1: the SCK line will be low when the clock is inactive The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. Bit 4 CKEG: Determines SPI SCK active clock edge type CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit. Rev. 1.80 Bit 3 MLS: SPI Data shift order 0: LSB 1: MSB This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Bit 2 CSEN: SPI SCS pin Control 0: Disable 1: Enable The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the SCS pin will be disabled and placed into a floating condition. If the bit is high the SCS pin will be enabled and used as a select pin. Note that using the CSEN bit can be disabled or enabled via configuration option. Bit 1 WCOL: SPI Write Collision flag 0: No collision 1: Collision The WCOL flag is used to detect if a data collision has occurred. If this bit is high it means that data has been attempted to be written to the SIMD register during a data transfer operation. This writing operation will be ignored if data is being transferred. The bit can be cleared by the application program. Note that using the WCOL bit can be disabled or enabled via configuration option. Bit 0 TRF: SPI Transmit/Receive Complete flag 0: Data is being transferred 1: SPI data transmission is completed The TRF bit is the Transmit/Receive Complete flag and is set "1" automatically when an SPI data transmission is completed, but must set to "0" by the application program. It can be used to generate an interrupt. 166 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM SPI Communication After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output an SCS signal to enable the slave device before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI will continue to function even in the IDLE Mode. SPI Master Mode Timing SPI Slave Mode Timing – CKEG=0 Rev. 1.80 167 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM SPI Slave Mode Timing – CKEG=1 SPI Transfer Control Flowchart Rev. 1.80 168 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM I2C Interface The I 2C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. I2C Master Slave Bus Connection ●● I2C Interface Operation The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two devices communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For these devices, which only operates in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. There are several configuration options associated with the I2C interface. One of these is to enable the function which selects the SIM pins rather than normal I/O pins. Note that if the configuration option does not select the SIM function then the SIMEN bit in the SIMC0 register will have no effect. A configuration option exists to allow a clock other than the system clock to drive the I2C interface. Another configuration option determines the debounce time of the I2C interface. This uses the internal clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be chosen to be either 1 or 2 system clocks. Rev. 1.80 169 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM S T A R T s ig n a l fro m M a s te r S e n d s la v e a d d r e s s a n d R /W b it fr o m M a s te r A c k n o w le d g e fr o m s la v e S e n d d a ta b y te fro m M a s te r A c k n o w le d g e fr o m s la v e S T O P s ig n a l fro m M a s te r ●● I2C Registers There are three control registers associated with the I2C bus, SIMC0, SIMC1 and SIMA and one data register, SIMD. The SIMD register, which is shown in the above SPI section, is used to store the data being transmitted and received on the I2C bus. Before the microcontroller writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I 2C bus, the microcontroller can read it from the SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD register. Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface. Bit Register Name 7 6 5 4 3 2 1 0 SIMC0 SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — SIMC1 SIMD SIMA HCF D7 IICA6 HAAS D6 IICA5 HBB D5 IICA4 HTX D4 IICA3 TXAK D3 IICA2 SRW D2 IICA1 IAMWU D1 IICA0 RXAK D0 D0 I2C Registers List Rev. 1.80 170 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● SIMC0 Register Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — R/W R/W R/W R/W R/W R/W R/W R/W — POR 1 1 1 0 0 0 0 — Bit 7~5 SIM2, SIM1, SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fTBC 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Unused mode These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 PCKEN: PCK Output Pin Control 0: Disable 1: Enable Bit 3~2 PCKP1, PCKP0: Select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 Bit 1 SIMEN: SIM Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be in a floating condition and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective. If the SIM is configured to operate as an SPI interface via SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 Rev. 1.80 unimplemented, read as "0" 171 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● SIMC0 Register Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — R/W R/W R/W R/W R/W R/W R/W R/W — POR 1 1 1 0 0 0 0 — Bit 7~5 SIM2, SIM1, SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fTBC 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Unused mode These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 PCKEN: PCK Output Pin Control 0: Disable 1: Enable Bit 3~2 PCKP1, PCKP0: Select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 Bit 1 SIMEN: SIM Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be in a floating condition and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective. If the SIM is configured to operate as an SPI interface via SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 Rev. 1.80 unimplemented, read as "0" 172 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● SIMC1 Register Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R/W R R R R/W R/W R R/W R POR 1 0 0 0 0 0 0 1 Bit 7 HCF: I2C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Bit 6 HAAS: I2C Bus address match flag 0: Not address match 1: Address match The HASS flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. Bit 5 HBB: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The HBB flag is the I2C busy flag. This flag will be "1" when the I2C bus is busy which will occur when a START signal is detected. The flag will be set to "0" when the bus is free which will occur when a STOP signal is detected. Bit 4 HTX: Select I2C slave device is transmitter or receivera 0: Slave device is the receiver 1: Slave device is the transmitter Bit 3 TXAK: I2C Bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave do not send acknowledge flag The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always set TXAK bit to "0" before further data is received. Bit 2 SRW: I2C Slave Read/Write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SRW flag is the I2C Slave Read/Write flag. This flag determines whether the master device wishes to transmit or receive data from the I 2C bus. When the transmitted address and slave address is match, that is when the HAAS flag is set high, the slave device will check the SRW flag to determine whether it should be in transmit mode or receive mode. If the SRW flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SRW flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1 IAMWU: I2C Address Match Wake-up Control 0: Disable 1: Enable This bit should be set to "1" to enable I2C address match wake up from SLEEP or IDLE Mode. Bit 0 RXAK: I2C Bus Receive acknowledge flag 0: Slave receive acknowledge flag 1: Slave do not receive acknowledge flag 173 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM The RXAK flag is the receiver acknowledge flag. When the RXAK flag is "0", it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAK flag is "1". When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register. ●● SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "X" unknown ●● SIMA Register Bit 7 6 5 4 3 2 1 0 Name IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 — R/W R/W R/W R/W R/W R/W R/W R/W — POR x x x x x x x — "X" unknown Bit 7~1 IICA6~ IICA0: I2C slave address IICA6~ IICA0 is the I2C slave address bit 6~ bit 0. The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~ 1 of the SIMA register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the SIMA register, the slave device will be selected. Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface. Bit 0 Undefined bit This bit can be read or written by user software program. I C Block Diagram 2 Rev. 1.80 174 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM I2C Bus Communication Communication on the I2C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this: ●● Step 1 Set the SIM2~SIM0 and SIMEN bits in the SIMC0 register to "1" to enable the I2C bus. ●● Step 2 Write the slave address of the device to the I2C bus address register SIMA. ●● Step 3 Set the SIME and SIM Muti-Function interrupt enable bit of the interrupt control register to enable the SIM interrupt and Multi-function interrupt. I2C Bus Initialisation Flow Chart Rev. 1.80 175 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM I2C Bus Start Signal The START signal can only be generated by the master device connected to the I2C bus and not by the slave device. This START signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. Slave Address The transmission of a START signal by the master will be detected by all devices on the I2C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag HAAS when the addresses match. As an I 2C bus interrupt can come from two sources, when the program enters the interrupt subroutine, the HAAS bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I2C Bus Read/Write Signal The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW flag is "1" then this indicates that the master device wishes to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a transmitter. If the SRW flag is "0" then this indicates that the master wishes to send data to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver. I2C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address, any slave device on the I2C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAAS flag is high, the addresses have matched and the slave device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register should be set to "1". If the SRW flag is low, then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1 register should be set to "0". Rev. 1.80 176 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM I2C Bus Data and Acknowledge Signal The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the SIMD register. If setup as a transmitter, the slave device must first write the data to be transmitted into the SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD register. When the slave receiver receives the data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. I2C Communication Timing Diagram Note: *When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. Rev. 1.80 177 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM I2C Bus ISR Flow Chart Serial Interface – SPIA The devices contain an independent SPI function. It is important not to confuse this independent SPI function with the additional one contained within the combined SIM function, which is described in another section of this datasheet. This independent SPI function will carry the name SPIA to distinguish it from the other one in the SIM. The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the device can be either master or slave. Although the SPIA interface specification can control multiple slave devices from a single master, however this device is provided with only one SCSA pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pins to select the slave devices. Rev. 1.80 178 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM SPIA Interface Operation The SPIA interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDIA, SDOA, SCKA and SCSA. Pins SDIA and SDOA are the Serial Data Input and Serial Data Output lines, SCKA is the Serial Clock line and SCSA is the Slave Select line. As the SPIA interface pins are pin-shared with normal I/O pins, the SPIA interface must first be enabled by selecting the SPIA enable configuration option and setting the correct bits in the SPIAC0 and SPIAC1 registers. After the SPIA configuration option has been configured it can also be additionally disabled or enabled using the SPIAEN bit in the SPIAC0 register. Communication between devices connected to the SPIA interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The Master also controls the clock signal. As the device only contains a single SCSA pin only one slave device can be utilized. The SCSA pin is controlled by the application program, set the SACSEN bit to “1” to enable the SCSA pin function and clear the SACSEN bit to “0” to place the SCSA pin into a floating state. SPIA Master/Slave Connection SPIA Block Diagram The SPIA function in this device offers the following features: ●● Full duplex synchronous data transfer ●● Both Master and Slave modes ●● LSB first or MSB first data transmission modes ●● Transmission complete flag ●● Rising or falling active clock edge ●● SAWCOL and SACSEN bit enabled or disable select The status of the SPIA interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as SACSEN and SPIAEN. Rev. 1.80 179 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM There are several configuration options associated with the SPIA interface. One of these is to enable the SPIA function which selects the SPIA pins rather than normal I/O pins. Note that if the configuration option does not select the SPIA function then the SPIAEN bit in the SPIAC0 register will have no effect. Another two SPIA configuration options determine if the SACSEN and SAWCOL bits are to be used. SPIA Registers There are three internal registers which control the overall operation of the SPIA interface. These are the SPIAD data register and two registers SPIAC0 and SPIAC1. Bit Register Name 7 6 SPIAC0 SASPI2 SASPI1 SPIAC1 — — SPIAD D7 D6 5 4 SASPI0 — SACKPOL SACKEG D5 D4 3 — SAMLS D3 2 1 — SPIAEN 0 — SACSEN SAWCOL D2 D1 SATRF D0 SPIA Registers List The SPIAD register is used to store the data being transmitted and received. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SPIAD register. After the data is received from the SPI bus, the device can read it from the SPIAD register. Any transmission or reception of data from the SPI bus must be made via the SPIAD register. ●● SPIAD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x “x” unknown There are also two control registers for the SPIA interface, SPIAC0 and SPIAC1. Register SPIAC0 is used to control the enable/disable function and to set the data transmission clock frequency. Register SPIAC1 is used for other control functions such as LSB/MSB selection, write collision flag etc. ●● SPIAC0 Register Bit 7 6 5 4 3 2 1 0 Name SASPI2 SASPI1 SASPI0 — — — SPIAEN — R/W R/W R/W R/W — — — R/W — POR 1 1 1 0 0 0 0 0 Bit 7~5 Bit 4~2 Bit 1 Bit 0 Rev. 1.80 SASPI2~SASPI0: Master/Slave Clock Select 000 : SPIA master, fSYS/4 001 : SPIA master, fSYS/16 010 : SPIA master, fSYS/64 011 : SPIA master, fSUB 100 : SPIA master, TP0 CCRP match frequency/2 (PFD) 101 : SPIA slave Unimplemented, read as “0” SPIAEN: SPIA enable or disable 0: Disable 1: Enable Unimplemented, read as “0” 180 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● SPIAC1 Register Rev. 1.80 Bit 7 6 Name — — 5 4 R/W R R R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 SACKPOL SACKEG 3 SAMLS 2 1 SACSEN SAWCOL 0 SATRF Bit 7~6 Unimplemented, read as “0”. This bit can be read or written by user software program. Bit 5 SACKPOL: Determines the base condition of the clock line 0: SCKA line will be high when the clock is inactive 1: SCKA line will be low when the clock is inactive The SACKPOL bit determines the base condition of the clock line, if the bit is high, then the SCKA line will be low when the clock is inactive. When the SACKPOL bit is low, then the SCKA line will be high when the clock is inactive. Bit 4 SACKEG: Determines the SPIA SCKA active clock edge type SACKPOL = 0: 0: SCKA has high base level with data capture on SCKA rising edge 1: SCKA has high base level with data capture on SCKA falling edge SACKPOL = 1: 0: SCKA has low base level with data capture on SCKA falling edge 1: SCKA has low base level with data capture on SCKA rising edge The SACKEG and SACKPOL bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before a data transfer is executed otherwise an erroneous clock edge may be generated. The SACKPOL bit determines the base condition of the clock line, if the bit is high, then the SCKA line will be low when the clock is inactive. When the SACKPOL bit is low, then the SCKA line will be high when the clock is inactive. The SACKEG bit determines active clock edge type which depends upon the condition of the SACKPOL bit. Bit 3 SAMLS: MSB/LSB First Bit 0: LSB shift first 1: MSB shift first This is the data shift select bit and is used to select how the data is transferred, either MSB orLSB first. Setting the bit high will select MSB first and low for LSB first. Bit 2 SACSEN: Select Signal Enable/Disable Bit 0: SCSA floating 1: Enable The SACSEN bit is used as an enable/disable for the SCSA pin. If this bit is low, then the SCSA pin will be disabled and placed into a floating condition. If the bit is high the SCSA pin will be enabled and used as a select pin. Note that using the SACSEN bit can be disabled or enabled via configuration option. Bit 1 SAWCOL: Write Collision Bit 0: Collision free 1: Collision detected The SAWCOL flag is used to detect if a data collision has occurred. If this bit is high it means that data has been attempted to be written to the SPIAD register during a data transfer operation. This writing operation will be ignored if data is being transferred. The bit can be cleared by the application program. Note that using the SAWCOL bit can be disabled or enabled via configuration option. Bit 0 SATRF: Transmit /Receive Flag 0: Not complete 1: Transmission/reception complete The SATRF bit is the Transmit/Receive Complete flag and is set “1” automatically when an SPIA data transmission is completed, but must set to zero by the application program. It can be used to generate an interrupt. 181 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM SPIA Communication After the SPIA interface is enabled by setting the SPIAEN bit high, then in the Master Mode, when data is written to the SPIAD register, transmission/reception will begin simultaneously. When the data transfer is complete, the SATRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SPIAD register will be transmitted and any data on the SDIA pin will be shifted into the SPIAD register. The master should output an SCSA signal to enable the slave device before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCSA signal depending upon the configurations of the SACKPOL bit and SACKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the SACKPOL and SACKEG bits. The SPIA will continue to function even in the IDLE Mode. SPIA Master Mode Timing SPIA Slave Mode Timing – SACKEG=0 Rev. 1.80 182 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM SPIA Slave Mode Timing – SACKEG=1 SPIA Transfer Control Flowchart Rev. 1.80 183 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Peripheral Clock Output The Peripheral Clock Output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. Peripheral Clock Operation As the peripheral clock output pin, PCK, is shared with I/O line, the required pin function is chosen via PCKEN in the SIMC0 register. The Peripheral Clock function is controlled using the SIMC0 register. The clock source for the Peripheral Clock Output can originate from either the TM0 CCRP match frequency/2 or a divided ratio of the internal fSYS clock. The PCKEN bit in the SIMC0 register is the overall on/off control, setting PCKEN bit to "1" enables the Peripheral Clock, setting PCKEN bit to "0" disables it. The required division ratio of the system clock is selected using the PCKP1 and PCKP0 bits in the same register. If the device enters the SLEEP Mode this will disable the Peripheral Clock output. ●● SIMC0 Register Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — R/W R/W R/W R/W R/W R/W R/W R/W — POR 1 1 1 0 0 0 0 — Bit 7~5 SIM2, SIM1, SIM0: SIM operating mode control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fTBC 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Unused mode These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 PCKEN: PCK output pin control 0: Disable 1: Enable Bit 3~2 PCKP1, PCKP0: select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 Bit 1 SIMEN: SIM control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be in a floating condition and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective. Note that when the SIMEN bit changes from low to high the contents of the SPI control registers will be in an unknown condition and should therefore be first initialised by the application program. Bit 0 unimplemented, read as "0" 184 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains several external interrupt and internal interrupts functions. The external interrupts are generated by the action of the external INT0~INT3 and PINT pins, while the internal interrupts are generated by various internal functions such as the TMs, Comparators, Time Base, LVD, EEPROM, SIM, SPIA and the A/D converter. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The number of registers depends upon the device chosen but fall into three categories. The first is the INTC0~INTC3 registers which setup the primary interrupts, the second is the MFI0~MFI3 registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an “E” for enable/disable bit or “F” for request flag. Function Enable Bit Request Flag Global EMI — Notes — Comparator CPnE CPnF n = 0 or 1 INTn Pin INTnE INTnF n = 0~3 A/D Converter ADE ADF — Multi-function MFnE MFnF n = 0~5 Time Base TBnE TBnF n = 0 or 1 SIM SIME SIMF — SPIA SPIAE SPIAF — LVD LVE LVF — EEPROM DEE DEF — PINT Pin XPE XPF — TM TnPE TnPF n = 0~3 — TnAE TnAF — — TnBE TnBF — Interrupt Register Bit Naming Conventions Rev. 1.80 185 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Interrupt Register Contents ●● HT67F30 Name INTEG Bit 7 6 5 4 3 2 1 0 — — — — INT1S1 INT1S0 INT0S1 INT0S0 INTC0 — CP0F INT1F INT0F CP0E INT1E INT0E EMI INTC1 ADF MF1F MF0F CP1F ADE MF1E MF0E CP1E INTC2 MF3F TB1F TB0F MF2F MF3E TB1E TB0E MF2E MFI0 — — T0AF T0PF — — T0AE T0PE MFI1 — T1BF T1AF T1PF — T1BE T1AE T1PE MFI2 — — XPF SIMF — — XPE SIME MFI3 — SPIAF DEF LVF — SPIAE DEE LVE ●● HT67F40 Name Bit 7 6 5 4 3 2 1 0 — — — — INT1S1 INT1S0 INT0S1 INT0S0 CP0F INT1F INT0F CP0E INT1E INT0E EMI INTC1 ADF MF1F MF0F CP1F ADE MF1E MF0E CP1E INTC2 MF3F TB1F TB0F MF2F MF3E TB1E TB0E MF2E MFI0 T2AF T2PF T0AF T0PF T2AE T2PE T0AE T0PE MFI1 — T1BF T1AF T1PF — T1BE T1AE T1PE MFI2 — — XPF SIMF — XPE SIME MFI3 — SPIAF DEF LVF — DEE LVE 7 6 5 4 3 2 1 0 — — — — INT1S1 INT1S0 INT0S1 INT0S0 INTEG INTC0 SPIAE ●● HT67F50 Name INTEG Bit INTC0 — CP0F INT1F INT0F CP0E INT1E INT0E EMI INTC1 ADF MF1F MF0F CP1F ADE MF1E MF0E CP1E INTC2 MF3F TB1F TB0F MF2F MF3E TB1E TB0E MF2E MFI0 T2AF T2PF T0AF T0PF T2AE T2PE T0AE T0PE MFI1 — T1BF T1AF T1PF — T1BE T1AE T1PE MFI2 T3AF T3PF XPF SIMF T3AE T3PE XPE SIME MFI3 — SPIAF DEF LVF — SPIAE DEE LVE 7 6 5 4 3 2 1 0 INT3S1 INT3S0 INT2S1 INT2S0 INT1S1 INT1S0 INT0S1 INT0S0 ●● HT67F60 Name INTEG Rev. 1.80 Bit INTC0 — CP0F INT1F INT0F CP0E INT1E INT0E EMI INTC1 ADF MF1F MF0F CP1F ADE MF1E MF0E CP1E INTC2 MF3F TB1F TB0F MF2F MF3E TB1E TB0E MF2E INTC3 — — INT3F INT2F — — INT3E INT2E MFI0 T2AF T2PF T0AF T0PF T2AE T2PE T0AE T0PE MFI1 — T1BF T1AF T1PF — T1BE T1AE T1PE MFI2 T3AF T3PF XPF SIMF T3AE T3PE XPE SIME MFI3 — SPIAF DEF LVF — SPIAE DEE LVE 186 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM INTEG Register ●● HT67F30/HT67F40/HT67F50 Bit 7 6 5 4 3 2 1 0 Name — — — — INT1S1 INT1S0 INT0S1 INT0S0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 unimplemented, read as "0" Bit 3~2 INT1S1, INT1S0: interrupt edge control for INT1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges Bit 1~0 INT0S1, INT0S0: interrupt edge control for INT0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges ●● HT67F60 Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name INT3S1 INT3S0 INT2S1 INT2S0 INT1S1 INT1S0 INT0S1 INT0S0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 INT3S1, INT3S0: Interrupt edge control for INT3 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges Bit 5~4 INT2S1, INT2S0: interrupt edge control for INT2 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges Bit 3~2 INT1S1, INT1S0: interrupt edge control for INT1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges Bit 1~0 INT0S1, INT0S0: interrupt edge control for INT0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges 187 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM INTC0 Register ●● HT67F30/HT67F40/HT67F50/HT67F60 Bit 7 6 5 4 3 2 1 0 Name — CP0F INT1F INT0F CP0E INT1E INT0E EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 unimplemented, read as "0" CP0F: Comparator 0 interrupt request flag 0: no request 1: interrupt request INT1F: INT1 interrupt request flag 0: no request 1: interrupt request INT0F: INT0 interrupt request flag 0: no request 1: interrupt request CP0E: Comparator 0 interrupt control 0: disable 1: enable INT1E: INT1 interrupt control 0: disable 1: enable INT0E: INT0 interrupt control 0: disable 1: enable EMI: Global interrupt control 0: disable 1: enable INTC1 Register ●● HT67F30/HT67F40/HT67F50/HT67F60 Bit 7 6 5 4 3 2 1 0 Name ADF MF1F MF0F CP1F ADE MF1E MF0E CP1E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev. 1.80 ADF: A/D Converter Interrupt Request Flag 0: no request 1: interrupt request MF1F: Multi-function Interrupt 1 Request Flag 0: no request 1: interrupt request MF0F: Multi-function Interrupt 0 Request Flag 0: no request 1: interrupt request CP1F: Comparator 1 Interrupt Request Flag 0: no request 1: interrupt request ADE: A/D Converter Interrupt Control 0: disable 1: enable MF1E: Multi-function Interrupt 1 Control 0: disable 1: enable MF0E: Multi-function Interrupt 0 Control 0: disable 1: enable CP1E: Comparator 1 Interrupt Control 0: Disable 1: Enable 188 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM INTC2 Register ●● HT67F30/HT67F40/HT67F50/HT67F60 Bit 7 6 5 4 3 2 1 0 Name MF3F TB1F TB0F MF2F MF3E TB1E TB0E MF2E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 MF3F: Multi-function Interrupt 3 Request Flag 0: no request 1: interrupt request Bit 6 TB1F: Time Base 1 Interrupt Request Flag 0: no request 1: interrupt request Bit 5 TB0F: Time Base 0 IInterrupt Request Flag 0: no request 1: interrupt request Bit 4 MF2F: Multi-function Interrupt 2 Request Flag 0: no request 1: interrupt request Bit 3 MF3E: Multi-function Interrupt 3 Control 0: disable 1: enable Bit 2 TB1E: Time Base 1 Interrupt Control 0: disable 1: enable Bit 1 TB0E: Time Base 0 Interrupt Control 0: disable 1: enable Bit 0 MF2E: Multi-function Interrupt 2 Control 0: disable 1: enable INTC3 Register ●● HT67F60 Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name — — INT3F INT2F — — INT3E INT2E R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 unimplemented, read as "0" Bit 5 INT3F: INT3 interrupt request flag 0: no request 1: interrupt request Bit 4 INT2F: INT2 interrupt request flag 0: no request 1: interrupt request Bit 3~2 unimplemented, read as "0" Bit 1 INT3E: INT3 interrupt control 0: disable 1: enable Bit 0 INT2E: INT2 interrupt control 0: disable 1: enable 189 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM MFI0 Register ●● HT67F30 Bit 7 6 5 4 3 2 1 0 Name — — T0AF T0PF — — T0AE T0PE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 unimplemented, read as "0" Bit 5 T0AF: TM0 Comparator A match interrupt request flag 0: no request 1: interrupt request Bit 4 T0PF: TM0 Comparator P match interrupt request flag 0: no request 1: interrupt request Bit 3~2 unimplemented, read as "0" Bit 1 T0AE: TM0 Comparator A match interrupt control 0: disable 1: enable Bit 0 T0PE: TM0 Comparator P match interrupt control 0: disable 1: enable ●● HT67F40/HT67F50/HT67F60 Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name T2AF T2PF T0AF T0PF T2AE T2PE T0AE T0PE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 T2AF: TM2 Comparator A match interrupt request flag 0: no request 1: interrupt request Bit 6 T2PF: TM2 Comparator P match interrupt request flag 0: no request 1: interrupt request Bit 5 T0AF: TM0 Comparator A match interrupt request flag 0: no request 1: interrupt request Bit 4 T0PF: TM0 Comparator P match interrupt request flag 0: no request 1: interrupt request Bit 3 T2AE: TM2 Comparator A match interrupt control 0: disable 1: enable Bit 2 T2PE: TM2 Comparator P match interrupt control 0: disable 1: enable Bit 1 T0AE: TM0 Comparator A match interrupt control 0: disable 1: enable Bit 0 T0PE: TM0 Comparator P match interrupt control 0: disable 1: enable 190 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM MFI1 Register ●● HT67F30/HT67F40/HT67F50/HT67F60 Bit 7 6 5 4 3 2 1 0 Name — T1BF T1AF T1PF — T1BE T1AE T1PE R/W — R/W R/W R/W — R/W R/W R/W POR — 0 0 0 — 0 0 0 Bit 7 unimplemented, read as "0" Bit 6 T1BF: TM1 Comparator B match interrupt request flag 0: no request 1: interrupt request Bit 5 T1AF: TM1 Comparator A match interrupt request flag 0: no request 1: interrupt request Bit 4 T1PF: TM1 Comparator B match interrupt request flag 0: no request 1: interrupt request Bit 3 unimplemented, read as "0" Bit 2 T1BE: TM1 Comparator P match interrupt control 0: disable 1: enable Bit 1 T1AE: TM1 Comparator A match interrupt control 0: disable 1: enable Bit 0 T1PE: TM1 Comparator P match interrupt control 0: disable 1: enable MFI2 Register ●● HT67F30/HT67F40 Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name — — XPF SIMF — — XPE SIME R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 unimplemented, read as "0" Bit 5 XPF: External peripheral interrupt request flag 0: No request 1: Interrupt request Bit 4 SIMF: SIM interrupt request flag 0: No request 1: Interrupt request Bit 3~2 unimplemented, read as "0" Bit 1 XPE: External Peripheral Interrupt Control 0: Disable 1: Enable Bit 0 SIME: SIM Interrupt Control 0: Disable 1: Enable 191 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● HT67F50/HT67F60 Bit 7 6 5 4 3 2 1 0 Name T3AF T3PF XPF SIMF T3AE T3PE XPE SIME R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T3AF: TM3 Comparator A match interrupt request flag 0: no request 1: interrupt request T3PF: TM3 Comparator P match interrupt request flag 0: no request 1: interrupt request XPF: External peripheral interrupt request flag 0: No request 1: Interrupt request SIMF: SIM interrupt request flag 0: No request 1: Interrupt request T3AE: TM3 Comparator A match interrupt control 0: disable 1: enable T3PE: TM3 Comparator P match interrupt control 0: disable 1: enable XPE: External Peripheral Interrupt Control 0: Disable 1: Enable SIME: SIM Interrupt Control 0: Disable 1: Enable MFI3 Register ●● HT67F30/HT67F40/HT67F50/HT67F60 Bit 7 6 5 4 3 2 1 0 Name — SPIAF DEF LVF — SPIAE DEE LVE R/W — R/W R/W R/W — R/W R/W R/W POR — 0 0 0 — 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev. 1.80 unimplemented, read as "0" SPIAF: SPIA interrupt request flag 0: No request 1: Interrupt request DEF: Data EEPROM interrupt request flag 0: No request 1: Interrupt request LVF: LVD interrupt request flag 0: No request 1: Interrupt request unimplemented, read as "0" SPIAE: SPIA Interrupt Control 0: Disable 1: Enable DEE: Data EEPROM Interrupt Control 0: Disable 1: Enable LVE: LVD Interrupt Control 0: Disable 1: Enable 192 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P, Comparator A or Comparator B match or A/D conversion completion etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a “JMP” which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a "RETI" , which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. Rev. 1.80 193 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM EMI auto disabled in ISR Legend xxF Request Flag – no auto reset in ISR xxF Request Flag – auto reset in ISR xxE Enable Bit Interrupt Name Interrupt Request Name Flags Enable Bits Master Enable Vector INT0 Pin INT0F INT0E EMI 04H INT1 Pin INT1F INT1E EMI 08H Comp. 0 CP0F CP0E EMI 0CH Comp. 1 CP1F CP1E EMI 10H Request Flags Enable Bits TM0 P T0PF T0PE TM0 A T0AF T0AE M. Funct. 0 MF0F MF0E EMI 14H TM1 P T1PF T1PE M. Funct. 1 MF1F MF1E EMI 18H TM1 A T1AF T1AE ADF ADE EMI 1CH TM1 B T1BF T1BE SIM SIMF M. Funct. 2 MF2F MF2E EMI 20H Time Base 0 TB0F TB0E EMI 24H Time Base 1 TB1F TB1E EMI 28H M. Funct. 3 MF3F MF3E EMI 2CH PINT Pin LVD EEPROM SPIA XPF SIME XPE LVF LVE DEF DEE SPIAF ESPIA A/D Priority High Low Interrupts contained within Multi-Function Interrupts Interrupt Structure – HT67F30 Rev. 1.80 194 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM EMI auto disabled in ISR Legend xxF Request Flag – no auto reset in ISR Interrupt Name Request Flags Enable Bits Master Enable Vector xxF Request Flag – auto reset in ISR INT0 Pin INT0F INT0E EMI 04H INT1 Pin INT1F INT1E EMI 08H Comp. 0 CP0F CP0E EMI 0CH Comp. 1 CP1F CP1E EMI 10H M. Funct. 0 MF0F MF0E EMI 14H M. Funct. 1 MF1F MF1E EMI 18H ADF ADE EMI 1CH M. Funct. 2 MF2F MF2E EMI 20H Time Base 0 TB0F TB0E EMI 24H Time Base 1 TB1F TB1E EMI 28H MF3F MF3E EMI 2CH xxE Enable Bit Interrupt Name Request Flags Enable Bits TM0 P TP0AF T0PE TM0 A TP0AF T0AE TM2 P T2PF T2PE TM2 A T2AF T2AE TM1 P T1PF T1PE TM1 A T1AF T1AE TM1 B T1BF T1BE A/D TM3 P T3PF T3PE TM3 A T3AF T3AE SIM SIMF SIME PINT Pin XPF XPE LVF LVE DEF DEE LVD EEPROM M. Funct. 3 Priority High Low SPIA SPIAF ESPIA Interrupts contained within Multi-Function Interrupts HT67F50 only Interrupt Structure – HT67F40/HT67F50 Rev. 1.80 195 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM EMI auto disabled in ISR Legend xxF Request Flag – no auto reset in ISR xxF Request Flag – auto reset in ISR xxE Enable Bit Interrupt Name Request Flags Enable Bits TM0 P T0PF T0PE TM0 A T0AF T0AE TM2 P T2PF T2PE TM2 A T2AF T2AE TM1 P T1PF T1PE TM1 A T1AF T1AE TM1 B T1BF T1BE TM3 P T3PF T3PE TM3 A T3AF T3AE Interrupt Name Request Flags Enable Bits Master Enable INT0 Pin INT0F INT0E EMI 04H INT1 Pin INT1F INT1E EMI 08H Comp. 0 CP0F CP0E EMI 0CH Comp. 1 CP1F CP1E EMI 10H M. Funct. 0 MF0F MF0E EMI 14H M. Funct. 1 MF1F MF1E EMI 18H ADF ADE EMI 1CH M. Funct. 2 MF2F MF2E EMI 20H A/D Vector SIM SIMF SIME Time Base 0 TB0F TB0E EMI 24H PINT Pin XPF XPE Time Base 1 TB1F TB1E EMI 28H LVF LVE M. Funct. 3 MF3F MF3E EMI 2CH EEPROM DEF DEE INT2 Pin INT2F INT2E EMI 30H SPIA SPIAF ESPIA INT3 Pin INT3F INT3E EMI 34H LVD Interrupts contained within Multi-Function Interrupts Priority High Low Interrupt Structure – HT67F60 Rev. 1.80 196 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM External Interrupt The external interrupts are controlled by signal transitions on the pins INT0~INT3. An external interrupt request will take place when the external interrupt request flags, INT0F~INT3F, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E~INT3E, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flags, INT0F~INT3F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Comparator Interrupt The comparator interrupt is controlled by the two internal comparators. A comparator interrupt request will take place when the comparator interrupt request flags, CP0F or CP1F, are set, a situation that will occur when the comparator output changes state. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and comparator interrupt enable bits, CP0E and CP1E, must first be set. When the interrupt is enabled, the stack is not full and the comparator inputs generate a comparator output transition, a subroutine call to the comparator interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flags, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Multi-function Interrupt Within these devices there are up to four Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM Interrupts, SIM Interrupt, SPIA Interrupt, External Peripheral Interrupt, LVD interrupt and EEPROM Interrupt. A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags, MF0F~MF3F are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related Multi-Function request flag, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Rev. 1.80 197 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM However, it must be noted that, although the Multi-function Interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts, namely the TM Interrupts, SIM Interrupt, SPIA Interrupt, External Peripheral Interrupt, LVD interrupt and EEPROM Interrupt will not be automatically reset and must be manually reset by the application program. A/D Converter Interrupt The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs when the A/D conversion process finishes. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the A/D Converter Interrupt vector, will take place. When the interrupt is serviced, the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Time Base Interrupts The function of the Time Base Interrupts is to provide regular time signal in the form of an internal interrupt. They are controlled by the overflow signals from their respective timer functions. When these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to their respective vector locations will take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their clock sources originate from the internal clock source fTB. This fTB input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges. The clock source that generates fTB, which in turn controls the Time Base interrupt period, can originate from several different sources, as shown in the System Operating Mode section. Rev. 1.80 198 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● TBC Register Bit 7 6 5 4 3 2 1 0 Name TBON TBCK TB11 TB10 LXTLP TB02 TB01 TB00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 1 1 0 1 1 1 Bit 7 TBON: TB0 and TB1 Control 0: Disable 1: Enable Bit 6 TBCK: Select fTB Clock 0: fTBC 1: fSYS/4 Bit 5~4 TB11~TB10: Select Time Base 1 Time-out Period 00: 4096/fTB 01: 8192/fTB 10: 16384/fTB 11: 32768/fTB Bit 3 LXTLP: LXT Low Power Control 0: Disable 1: Enable Bit 2~0 TB02~TB00: Select Time Base 0 Time-out Period 000: 256/fTB 001: 512/fTB 010: 1024/fTB 011: 2048/fTB 100: 4096/fTB 101: 8192/fTB 110: 16384/fTB 111: 32768/fTB Time Base Interrupt Rev. 1.80 199 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Serial Interface Module Interrupt The Serial Interface Module Interrupt, also known as the SIM interrupt, is contained within the Multi-function Interrupt. A SIM Interrupt request will take place when the SIM Interrupt request flag, SIMF, is set, which occurs when a byte of data has been received or transmitted by the SIM interface. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface Interrupt enable bit, SIME, and Muti-function interrupt enable bits, must first be set. When the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the SIM interface, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the Serial Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the SIMF flag will not be automatically cleared, it has to be cleared by the application program. External Peripheral Interrupt The External Peripheral Interrupt operates in a similar way to the external interrupt and is contained within the Multi-function Interrupt. A Peripheral Interrupt request will take place when the External Peripheral Interrupt request flag, XPF, is set, which occurs when a negative edge transition appears on the PINT pin. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, external peripheral interrupt enable bit, XPE, and associated Multifunction interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a negative transition appears on the External Peripheral Interrupt pin, a subroutine call to the respective Multi-function Interrupt, will take place. When the External Peripheral Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the XPF flag will not be automatically cleared, it has to be cleared by the application program. The external peripheral interrupt pin is pin-shared with several other pins with different functions. It must therefore be properly configured to enable it to operate as an External Peripheral Interrupt pin. Serial Interface Interrupt The Serial Interface Interrupt, also known as the SPIA interrupt, is contained within the Multifunction Interrupt. A SPIA Interrupt request will take place when the SPIA Interrupt request flag, SPIAF, is set, which occurs when a byte of data has been received or transmitted by the SPIA interface. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface Interrupt enable bit, SPIAE, and Multi-function interrupt enable bits, must first be set. When the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the SPIA interface, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the Serial Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the SPIAF flag will not be automatically cleared, it has to be cleared by the application program. Rev. 1.80 200 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM EEPROM Interrupt The EEPROM Interrupt, is contained within the Multi-function Interrupt. An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, EEPROM Interrupt enable bit, DEE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the EEPROM Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the DEF flag will not be automatically cleared, it has to be cleared by the application program. LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the Multi-function Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically cleared, it has to be cleared by the application program. TM Interrupts The Compact and Standard Type TMs have two interrupts each, while the Enhanced Type TM has three interrupts. All of the TM interrupts are contained within the Multi-function Interrupts. For each of the Compact and Standard Type TMs there are two interrupt request flags TnPF and TnAF and two enable bits TnPE and TnAE. For the Enhanced Type TM there are three interrupt request flags TnPF, TnAF and TnBF and three enable bits TnPE, TnAE and TnBE. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P, A or B match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Rev. 1.80 201 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MF0F~MF3F, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the “CALL” instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Rev. 1.80 202 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Power Down Mode and Wake-up Entering the IDLE or SLEEP Mode There is only one way for the device to enter the SLEEP or IDLE Mode and that is to execute the "HALT" instruction in the application program. When this instruction is executed, the following will occur: ●● The system clock will be stopped and the application program will stop at the "HALT" instruction. ●● The Data Memory contents and registers will maintain their present condition. ●● The WDT will be cleared and resume counting if the WDT clock source is selected to come from the fSUB clock source and the WDT is enabled. The WDT will stop if its clock source originates from the system clock. ●● The I/O ports will maintain their present condition. ●● In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the configuration options have enabled the LIRC oscillator. Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: ●● An external reset ●● An external falling edge on Port A ●● A system interrupt ●● A WDT overflow If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the "HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the "HALT" instruction. Rev. 1.80 203 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HALT instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Low Voltage Detector – LVD Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be detemined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. ●● LVDC Register Rev. 1.80 Bit 7 6 5 4 3 2 1 0 Name — — LVDO LVDEN — VLVD2 VLVD1 VLVD0 R/W — — R R/W — R/W R/W R/W POR — — 0 0 — 0 0 0 Bit 7~6 unimplemented, read as "0" Bit 5 LVDO: LVD Output Flag 0: No Low Voltage Detect 1: Low Voltage Detect Bit LVDEN: Low Voltage Detector Control 0: Disable 1: Enable Bit 3 unimplemented, read as "0" Bit 2~0 VLVD2 ~ VLVD0: Select LVD Voltage 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.4V 204 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.4V. When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multifunction interrupts, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set high by a low voltage condition. When the device is powered down the Low Voltage Detector will remain active if the LVDEN bit is high. In this case, the LVF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is not required then the LVF flag should be first set high before the device enters the SLEEP or IDLE Mode. When LVD function is enabled, it is recommenced to clear LVD flag first, and then enables interrupt function to avoid mistake action. LCD Driver For large volume applications, which incorporate an LCD in their design, the use of a custom display rather than a more expensive character based display reduces costs significantly. However, the corresponding COM and SEG signals required, which vary in both amplitude and time, to drive such a custom display require many special considerations for proper LCD operation to occur. These devices all contain an LCD Driver function, which with their internal LCD signal generating circuitry and various options, will automatically generate these time and amplitude varying signals to provide a means of direct driving and easy interfacing to a range of custom LCDs. All devices include a wide range of options to enable LCD displays of various types to be driven. The table shows the range of options available across the device range. Rev. 1.80 205 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Part No. HT67F30 HT67F40 HT67F40 HT67F60 Duty Driver No. 1/2 21x2 1/3 21x3 1/4 20x4 1/2 33x2 1/3 33x3 1/4 32x4 1/2 41x2 1/3 41x3 1/4 40x4 1/2 57x2 1/3 57x3 1/4 56x4 Bias Bias Type Wave Type 1/2 or 1/3 C or R A or B 1/2 or 1/3 C or R A or B 1/2 or 1/3 C or R A or B 1/2 or 1/3 C or R A or B LCD Selections C Type Bias Voltage Levels V M A X V V L C D A (= V L C D ) V R L C D P o w e r S u p p ly V L C D V A (= V L C D ) R B (= V L C D 2 /3 ) V V M A X R V B (= V L C D 1 /2 ) C (= V L C D 1 /3 ) L C D P o w e r S u p p ly R R L C D O n /O ff L C D O n /O ff R Type Bias Voltage Levels Rev. 1.80 206 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM LCD Memory An area of Data Memory is especially reserved for use for the LCD display data. This data area is known as the LCD Memory. Any data written here will be automatically read by the internal display driver circuits, which will in turn automatically generate the necessary LCD driving signals. Therefore any data written into this Memory will be immediately reflected into the actual display connected to the microcontroller. As the LCD Memory addresses overlap those of the General Purpose Data Memory, it s stored in its own independent Bank 1 area. The Data Memory Bank to be used is chosen by using the Bank Pointer, which is a special function register in the Data Memory, with the name, BP. To access the LCD Memory therefore requires first that Bank 1 is selected by writing a value of 01H to the BP register. After this, the memory can then be accessed by using indirect addressing through the use of Memory Pointer MP1. With Bank 1 selected, then using MP1 to read or write to the memory area, starting with address 80H, will result in operations to the LCD Memory. Directly addressing the Display Memory is not applicable and will result in a data access to the Bank 0 General Purpose Data Memory. The accompanying LCD Memory Map diagrams shows how the internal LCD Memory is mapped to the Segments and Commons of the display for the devices. LCD Memory Maps for devices with smaller memory capacities can be extrapolated from these diagrams. HT67F30 LCD Memory Map Rev. 1.80 207 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM HT67F40 LCD Memory Map HT67F50 LCD Memory Map Rev. 1.80 208 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM HT67F60 LCD Memory Map LCD Registers Control Registers in the Data Memory, are used to control the various setup features of the LCD Driver. There is one control register for the LCD function, LCDCTRL. Various bits in this registers control functions such as duty type, bias type, bias resistor selection as well as overall LCD enable and disable. The LCDEN bit in the LCDCTRL register, which provides the overall LCD enable/disable function, will only be effective when the device is in the Normal, Slow or Idle Mode. If the device is in the Sleep Mode then the display will always be disabled. Bits RSEL0 and RSEL1 in the LCDCTRL register select the internal bias resistors to supply the LCD panel with the correct bias voltages. A choice to best match the LCD panel used in the application can be selected also to minimise bias current. The TYPE bit in the same register is used to select whether Type A or Type B LCD control signals are used. Three registers, LCDOUT0, LCDOUT1, LCDOUT2 and LCDOUT3 are used to determine if the output function of display pins SEG0~SEG31 are used as segment drivers or I/O functions. Rev. 1.80 209 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM LCD Reset Function The LCD has an internal reset function that is an OR function of the inverted LCDEN bit in the LCDCTRL register and the Sleep function. The LCD reset signal is active high. The LCDENB signal is the inverse of the LCDEN bit in the LCDCTRL register. Reset LCD = (Sleep Mode AND LCDEN) OR LCDENB. LCDEN Sleep Mode Reset LCD 0 Off √ 0 On √ 1 Off x 1 On √ LCD Reset Function Clock Source The LCD clock source is the internal clock signal, fSUB, divided by 8, using an internal divider circuit. The fSUB internal clock is supplied by either the LIRC or LXT oscillator, the choice of which is determined by a configuration option. For proper LCD operation, this arrangement is provided to generate an ideal LCD clock source frequency of 4kHz. fSUB Clock Source LCD Clock Frequency LIRC 4kHz LXT 4kHz LCD Clock Source LCD Driver Output The number of COM and SEG outputs supplied by the LCD driver, as well as its biasing and duty selections, are dependent upon how the LCD control bits are programmed. The Bias Type, whether C or R type is selected via a configuration option. The nature of Liquid Crystal Displays require that only AC voltages can be applied to their pixels as the application of DC voltages to LCD pixels may cause permanent damage. For this reason the relative contrast of an LCD display is controlled by the actual RMS voltage applied to each pixel, which is equal to the RMS value of the voltage on the COM pin minus the voltage applied to the SEG pin. This differential RMS voltage must be greater than the LCD saturation voltage for the pixel to be on and less than the threshold voltage for the pixel to be off. The requirement to limit the DC voltage to zero and to control as many pixels as possible with a minimum number of connections, requires that both a time and amplitude signal is generated and applied to the application LCD. These time and amplitude varying signals are automatically generated by the LCD driver circuits in the microcontroller. What is known as the duty determines the number of common lines used, which are also known as backplanes or COMs. The duty, which is chosen by a control bit to have a value of 1/2, 1/3, 1/4 etc and which equates to a COM number of 2, 3, 4 etc, therefore defines the number of time divisions within each LCD signal frame. Two types of signal generation are also provided, known as Type A and Type B, the required type is selected via the TYPE bit in the LCDCTRL register. Type B offers lower frequency signals, however lower frequencies may introduce flickering and influence display clarity. Rev. 1.80 210 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● LCDCTRL Register Bit 7 6 5 4 3 2 1 0 Name TYPE DTYC1 DTYC0 — BIAS RSEL1 RSEL0 LCDEN R/W R/W R/W R/W — R/W R/W R/W R/W POR 0 0 0 — 0 0 0 0 Bit 7 TYPE: LCD Type Control 0: Type A 1: Type B Bit 6~Bit 5 DTYC1, DTYC0: LCD Duty Control 00: 1/2 duty 01: 1/3 duty 10: 1/4 duty 11: undefined Bit 4 uniplemented, read as “0” Bit 3 BIAS: LCD Bias Control 0: 1/2 Bias 1: 1/3 Bias Bit 2~Bit 1 RSEL1, RSEL0: LCD Bias Resistor Select Bit 0 RSEL1 RSEL0 1/3 Bias 1/2 Bias 0 0 600kΩ 400kΩ 0 1 300kΩ 200kΩ 1 0 100kΩ 67kΩ 1 1 50kΩ 34kΩ LCDEN: LCD Enable Control 0: Disable 1: Enable In the Normal, Slow or Idle mode, the LCD on/off function can be controlled by this bit. In the Sleep mode, the LCD is always off. ●● LCDOUT0 Register Bit 7 6 5 4 3 2 1 0 Name LCDO7 LCDO6 LCDO5 LCDO4 LCDO3 LCDO2 LCDO1 LCDO0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~Bit0 LCDO7~LCDO0: SEG7~SEG0 Output or I/O 0: LCD Segment Output 1: I/O ●● LCDOUT1 Register Bit 7 6 5 4 3 2 1 0 Name LCDO15 LCDO14 LCDO13 LCDO12 LCDO11 LCDO10 LCDO9 LCDO8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~Bit0 Rev. 1.80 LCD15~LCDO8: SEG15~SEG8 Output or I/O 0: LCD Segment Output 1: I/O 211 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM ●● LCDOUT2 Register Bit 7 6 5 4 3 2 1 0 Name LCDO23 LCDO22 LCDO21 LCDO20 LCDO19 LCDO18 LCDO17 LCDO16 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~Bit0 LCD23~LCD16: SEG23~SEG16 Output or I/O 0: LCD Segment Output 1: I/O ●● LCDOUT3 Register Bit 7 6 5 4 3 2 1 0 Name LCDO31 LCDO30 LCDO29 LCDO28 LCDO27 LCDO26 LCDO25 LCDO24 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~Bit0 LCD31~LCD24: SEG31~SEG24 Output or I/O 0: LCD Segment Output 1: I/O LCD Voltage Source and Biasing The time and amplitude varying signals generated by the LCD Driver function require the generation of several voltage levels for their operation. The number of voltage levels used by the signal depends upon the value of the BIAS bit in the LCDCTRL register. The device can have either R type or C type biasing selected via a configuration option. Selecting the C type biasing will enable an internal charge pump whose multiplier ratio can be selected using an additional configuration option. For R type biasing an external LCD voltage source must be supplied on pin VLCD to generate the internal biasing voltages. This could be the microcontroller power supply or some other voltage source. For the R type 1/2 bias selection, three voltage levels VSS, VA and VB are utilised. The voltage VA is equal to the externally supplied voltage source applied to pin VLCD. VB is generated internally by the microcontroller and will have a value equal to VLCD/2. For the R type 1/3 bias selection, four voltage levels VSS, VA, VB and VC are utilised. The voltage VA is equal to VLCD, VB is equal to VLCDx 2/3 while VC is equal to VLCDx1/3. In addition to selecting 1/2 or 1/3 bias, several values of bias resistor can be chosen using bits in the LCDCTRL register. Different values of internal bias resistors can be selected using the RSEL0 and RESEL1 bits in the LCDCTRL register. This along with the voltage on pin VLCD will determine the bias current. The connection to the VMAX pin depends upon the voltage that is applied to VLCD. If the VDD voltage is greater than the voltage applied to the VLCD pin then the VMAX pin should be connected to VDD, otherwise the VMAX pin should be connected to pin VLCD. Note that no external capacitors or resistors are required to be connected if R type biasing is used. Condition VMAX connection VDD > VLCD1 Connect VMAX to VDD Otherwise Connect VMAX to VLCD R Type Bias Current VMAX Connection For C type biasing an external LCD voltage source must also be supplied on pin VLCD to generate the internal biasing voltages. The C type biasing scheme uses an internal charge pump circuit, which in the case of the 1/3 bias selection can generate voltages higher than what is supplied on VLCD. This feature is useful in applications where the microcontroller supply voltage is less than the supply voltage required by the LCD. An additional charge pump capacitor must also be connected between pins C1 and C2 to generate the necessary voltage levels. Rev. 1.80 212 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM For the C type 1/2 bias selection, three voltage levels VSS, VA and VB are utilised. The voltage VA is generated internally and has a value of VLCD. VB will have a value equal to VAx0.5. For the C type 1/2 bias configuration VC is not used. For the C type 1/3 bias selection, four voltage levels VSS, VA, VB and VC are utilised. The voltage VA is generated internally and has a value of VLCDx1.5. VB will have a value equal to VAx 2/3 and VC will have a value equal to VA x 1/3. The connection to the VMAX pin depends upon the bias and the voltage that is applied to VLCD, the details are shown in the table. It is extremely important to ensure that these charge pump generated internal voltages do not exceed the maximum VDD voltage of 5.5V. Biasing Type VMAX Connection 1/3 Bias VDD>VLCDx1.5 Connect VMAX to VDD Otherwise Connect VMAX to V1 1/2 Bias VDD>VLCD Connect VMAX to VDD Otherwise Connect VMAX to VLCD C Type Biasing VMAX Connection LCD Waveform Timing Diagrams The accompanying timing diagrams depict the display driver signals generated by the microcontroller for various values of duty and bias. The huge range of various permutations only permit a few types to be displayed here. LCD Driver Output – Type A - 1/2 Duty, 1/2 Bias Rev. 1.80 Note: For 1/2 Bias, VA=VLCD, VB=VLCDx1/2 for both R and C type. 213 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Rev. 1.80 LCD Driver Output – Type A- 1/3 Duty, 1/2 Bias Note: For 1/2 Bias, the VA=VLCD, VB=VLCDx1/2 for both R and C type. 214 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM LCD Driver Output – Type A - 1/4 Duty, 1/3 Bias Note: For 1/3 R type bias, the VA=VLCD, VB=VLCDx2/3 and VC=VLCDx1/3. For 1/3 C type bias, the VA=VLCDx1.5, VB=VLCD and VC=VLCDx1/2. Rev. 1.80 215 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM LCD Driver Output – Type A- 1/3 Duty, 1/3 Bias Note:For 1/3 R type bias, the VA=VLCD, VB=VLCD×2/3 and VC=VLCD×1/3. For 1/3 C type bias, VA=VLCD×1.5, VB=VLCD and VC=VLCD×1/2. Rev. 1.80 216 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM LCD Driver Output – Type B- 1/2 Duty, 1/2 Bias Note: For 1/2 bias, the VA=VLCD, VB=VLCDx1/2 for both R and C type. Rev. 1.80 217 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM During Reset or LCD Off COM0� COM1� COM� All segment o�tp�ts 1 Frame Normal Operation Mode VA VB VC VSS VA VB VC VSS VA VB VC VSS COM0 VA VB VC VSS VA VB VC VSS COM1 COM� All segments are OFF COM0 side segments are ON COM1 side segments are ON COM� side segments are ON COM0� 1 side segments are ON COM0� � side segments are ON VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS (other combinations are omitted) VA VB VC VSS All segments are ON LCD Driver Output – Type B- 1/3 Duty, 1/3 Bias Note: For 1/3 R type bias, the VA=VLCD, VB=VLCD×2/3 and VC=VLCD×1/3. For 1/3 C type bias, VA=VLCD×1.5, VB=VLCD and VC=VLCD×1/2. Rev. 1.80 218 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM During Reset or LCD Off COM0� COM1� COM�� COM� All segment o�tp�ts 1 Frame Normal Operation Mode VA VB VC VSS VA VB VC VSS VA VB VC VSS COM0 VA VB VC VSS VA VB VC VSS COM1 COM� VA VB VC VSS COM� All segments are OFF COM0 side segments are ON COM1 side segments are ON COM� side segments are ON COM� side segments are ON COM0� 1 side segments are ON COM0� � side segments are ON COM0� � side segments are ON VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS (other combinations are omitted) All segments are ON VA VB VC VSS LCD Driver Output – Type B- 1/4 Duty, 1/3 Bias Note:For 1/3 R type bias, the VA=VLCD, VB=VLCD×2/3 and VC=VLCD×1/3. For 1/3 C type bias, VA=VLCD×1.5, VB=VLCD and VC=VLCD×1/2. Rev. 1.80 219 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Programming Considerations Certain precautions must be taken when programming the LCD. One of these is to ensure that the LCD Memory is properly initialised after the microcontroller is powered on. Like the General Purpose Data Memory, the contents of the LCD Memory are in an unknown condition after poweron. As the contents of the LCD Memory will be mapped into the actual display, it is important to initialise this memory area into a known condition soon after applying power to obtain a proper display pattern. Consideration must also be given to the capacitive load of the actual LCD used in the application. As the load presented to the microcontroller by LCD pixels can be generally modeled as mainly capacitive in nature, it is important that this is not excessive, a point that is particularly true in the case of the COM lines which may be connected to many LCD pixels. The accompanying diagram depicts the equivalent circuit of the LCD. One additional consideration that must be taken into account is what happens when the microcontroller enters the Idle or Slow Mode. The LCDEN control bit in the LCDCTRL register permits the display to be powered off to reduce power consumption. If this bit is zero, the driving signals to the display will cease, producing a blank display pattern but reducing any power consumption associated with the LCD. After Power-on, note that as the LCDEN bit will be cleared to zero, the display function will be disabled. LCD Panel Equivalent Circuit Rev. 1.80 220 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Configuration Options Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. All options must be defined for proper system function, the details of which are shown in the table. No. Options Oscillator Options 1 High Speed System Oscillator Selection - fH: 1. HXT 2. ERC 3. HIRC 4. EC 2 Low Speed System Oscillator Selection - fL: 1. LXT 2. LIRC 3 HXT mode 1. 1MHz~12MHz 2. 455KHz 4 WDT Clock Selection - fS: 1. fSUB 2. fSYS/4 5 HIRC Frequency Selection: 1. 4MHz 2. 8MHz 3. 12MHz Note: The fSUB and the fTBC clock source are LXT or LIRC selection by the fL configuration option. Reset Pin Options 6 PB0/RES Pin Options: 1. RES pin 2. I/O pin 7 Watchdog Timer Function: 1. Enable 2. Disable 8 CLRWDT Instructions Selection: 1. 1 instructions 2. 2 instructions 9 LVR Function: 1. Enable 2. Disable 10 LVR Voltage Selection: 1. 2.10V 2. 2.55V 3. 3.15V 4. 4.20V 11 SIM Function: 1. Enable 2. Disable 12 SPI - WCOL bit: 1. Enable 2. Disable Watchdog Options LVR Options SIM Options Rev. 1.80 221 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM No. Options 13 SPI - CSEN bit: 1. Enable 2. Disable 14 I2C Debounce Time Selection: 1. No debounce 2. 1 system clock debounce 3. 2 system clock debounce 15 SPIA Function: 1. Enable 2. Disable 16 SPIA - SAWCOL bit: 1. Enable 2. Disable 17 SPIA - SACSEN bit: 1. Enable 2. Disable 18 TMR/INT pin input filter Function: 1. Enable 2. Disable 19 LCD R type or C type selection: 1. R Type 2. C Type 20 LCD voltage 1. VLCD is 3.0V or 4.5V 2. VLCD is 1.5V SPIA Options TMR/INT Options LCD Options Rev. 1.80 222 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Application Circuits Note: "*": It is recommended that this component is added for added ESD protection. "**": It is recommended that this component is added in environments where power line noise is significant. Rev. 1.80 223 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different Rev. 1.80 224 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m]. i" instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the "HALT" instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.80 225 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Arithmetic Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Rev. 1.80 226 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Mnemonic Description Cycles Flag Affected Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the "CLR WDT1" and "CLR WDT2" instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both "CLR WDT1" and "CLR WDT2" instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.80 227 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Instruction Definition ADC A,[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] + C Affected flag(s) OV, Z, AC, C ADCM A,[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. Operation [m] ← ACC + [m] + C Affected flag(s) OV, Z, AC, C ADD A,[m] Add Data Memory to ACC Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] Affected flag(s) OV, Z, AC, C ADD A,x Add immediate data to ACC Description The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. Operation AC ← ACC + x Affected flag(s) OV, Z, AC, C ADDM A,[m] Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. Operation [m] ← ACC + [m] Affected flag(s) OV, Z, AC, C AND A,[m] Logical AND Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical Operation ACC ← ACC "AND" [m] Affected flag(s) Z AND A,x Logical AND immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise AND operation. The result is stored in the Accumulator. logical AND operation. The result is stored in the Accumulator. Operation ACC ← ACC "AND"x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. Operation [m] ← ACC "AND" [m] Affected flag(s) Z Rev. 1.80 228 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Operation Stack ← Program Counter + 1 Program Counter ← addr Affected flag(s) None CLR [m] Clear Data Memory Description Each bit of the specified Data Memory is cleared to 0. Operation [m] ← 00H Affected flag(s) None CLR [m].i Clear bit of Data Memory Description Bit i of the specified Data Memory is cleared to 0. Operation [m].i ← 0 Affected flag(s) None CLR WDT Clear Watchdog Timer Description The TO, PDF flags and the WDT are all cleared. Operation WDT cleared TO ← 0 PDF ← 0 Affected flag(s) TO, PDF CLR WDT1 Pre-clear Watchdog Timer Description The TO, PDF flags and the WDTare all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. Operation WDT cleared TO ← 0 PDF ← 0 Affected flag(s) TO, PDF CLR WDT2 Pre-clear Watchdog Timer Description The TO, PDF flags and the WDTare all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing Operation WDT cleared TO ← 0 PDF ← 0 Affected flag(s) Rev. 1.80 TO, PDF 229 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM CPL [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1's complement). Bits which previously contained a 1 are changed to 0 and vice versa. Operation [m] ← [m] Affected flag(s) Z CPLA [m] Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented (1's complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC ← [m] Affected flag(s) Z DAA [m] Decimal-Adjust ACC for addition with result in Data Memory Description Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. Operation [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H Affected flag(s) C DEC [m] Decrement Data Memory Description Data in the specified Data Memory is decremented by 1. Operation [m] ← [m] − 1 Affected flag(s) Z DECA [m] Decrement Data Memory with result in ACC Description Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. Operation ACC ← [m] − 1 Affected flag(s) Z Rev. 1.80 230 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM HALT Enter power down mode Description This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO ← 0 PDF ← 0 Affected flag(s) TO, PDF INC [m] Increment Data Memory Description Data in the specified Data Memory is incremented by 1. Operation [m] ← [m]+1 Affected flag(s) Z INCA [m] Increment Data Memory with result in ACC Description Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. Operation ACC ← [m]+1 Affected flag(s) Z JMP addr Jump unconditionally Description The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Operation Program Counter ← addr Affected flag(s) None MOV A,[m] Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator. Operation ACC ← [m] Affected flag(s) None MOV A,x Move immediate data to ACC Description The immediate data specified is loaded into the Accumulator. Operation ACC ← x Affected flag(s) None MOV [m],A Move ACC to Data Memory Description The contents of the Accumulator are copied to the specified Data Memory. Operation [m] ← ACC Affected flag(s) None NOP No operation Description No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None Rev. 1.80 231 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. Operation ACC ← ACC "OR" [m] Affected flag(s) Z OR A,x Logical OR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. Operation ACC ← ACC "OR" x Affected flag(s) Z ORM A,[m] Logical OR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. Operation [m] ← ACC "OR" [m] Affected flag(s) Z RET Return from subroutine Description The Program Counter is restored from the stack. Program execution continues at the restored address. Operation Program Counter ← Stack Affected flag(s) None RET A,x Return from subroutine and load immediate data to ACC Description The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Operation Program Counter ← Stack ACC ← x Affected flag(s) None RETI Return from interrupt Description The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Operation Program Counter ← Stack EMI ← 1 Affected flag(s) None RL [m] Rotate Data Memory left Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. Operation [m].(i+1) ← [m].i; (i = 0~6) [m].0 ← [m].7 Affected flag(s) Rev. 1.80 None 232 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM RLA [m] Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.(i+1) ← [m].i; (i = 0~6) ACC.0 ← [m].7 Affected flag(s) None RLC [m] Rotate Data Memory left through Carry Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. Operation [m].(i+1) ← [m].i; (i = 0~6) [m].0 ← C C ← [m].7 Affected flag(s) C RLCA [m] Rotate Data Memory left through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.(i+1) ← [m].i; (i = 0~6) ACC.0 ← C C ← [m].7 Affected flag(s) C RR [m] Rotate Data Memory right Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. Operation [m].i ← [m].(i+1); (i = 0~6) [m].7 ← [m].0 Affected flag(s) None RRA [m] Rotate Data Memory right with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i = 0~6) ACC.7 ← [m].0 Affected flag(s) None RRC [m] Rotate Data Memory right through Carry Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. Operation [m].i ← [m].(i+1); (i = 0~6) [m].7 ← C C ← [m].0 Affected flag(s) Rev. 1.80 C 233 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM RRCA [m] Rotate Data Memory right through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i = 0~6) ACC.7 ← C C ← [m].0 Affected flag(s) C SBC A,[m] Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − [m] − C Affected flag(s) OV, Z, AC, C SBCM A,[m] Subtract Data Memory from ACC with Carry and result in Data Memory Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − [m] − C Affected flag(s) OV, Z, AC, C SDZ [m] Skip if decrement Data Memory is 0 Description The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] ← [m] − 1 Skip if [m] = 0 Affected flag(s) None SDZA [m] Skip if decrement Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following Operation instruction. ACC ← [m] − 1 Affected flag(s) Skip if ACC = 0 None Rev. 1.80 234 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM SET [m] Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] ← FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].1 ← 1 Affected flag(s) None SIZ [m] Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] ← [m] + 1 Skip if [m] = 0 Affected flag(s) None SIZA [m] Skip if increment Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation ACC ← [m] + 1 Skip if ACC = 0 Affected flag(s) None SNZ [m].i Skip if bit i of Data Memory is not 0 Description If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Operation Skip if [m].i ≠ 0 Affected flag(s) None SUB A,[m] Subtract Data Memory from ACC Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − [m] Affected flag(s) OV, Z, AC, C Rev. 1.80 235 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ← ACC − [m] Affected flag(s) OV, Z, AC, C SUB A,x Subtract immediate data from ACC Description The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − x Affected flag(s) OV, Z, AC, C SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. Operation [m].3~[m].0↔[m].7 ~ [m].4 Affected flag(s) None SWAPA [m] Swap nibbles of Data Memory with result in ACC Description The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 ← [m].7 ~ [m].4 Operation ACC.7 ~ ACC.4 ← [m].3 ~ [m].0 Affected flag(s) None SZ [m] Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation Skip if [m] = 0 Affected flag(s) None SZA [m] Skip if Data Memory is 0 with data movement to ACC Description The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation ACC ← [m] Skip if [m] = 0 Affected flag(s) Rev. 1.80 None 236 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM SZ [m].i Skip if bit i of Data Memory is 0 Description If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation Skip if [m].i = 0 Affected flag(s) None TABRDC [m] Read table (current page) to TBLH and Data Memory Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None TABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None XOR A,[m] Logical XOR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ← ACC "XOR" [m] Affected flag(s) Z XORM A,[m] Logical XOR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. Operation [m] ← ACC "XOR" [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ← ACC "XOR" x Affected flag(s) Z Rev. 1.80 237 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website (http://www.holtek.com.tw/english/ literature/package.pdf) for the latest version of the package information. 48-pin LQFP (7mmx7mm) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A 0.350 ― 0.358 B 0.272 ― 0.280 C 0.350 ― 0.358 D 0.272 ― 0.280 E ― 0.020 ― F ― 0.008 ― G 0.053 ― 0.057 H ― ― 0.063 I ― 0.004 ― J 0.018 ― 0.030 K 0.004 ― 0.008 α 0° ― 7° Symbol Rev. 1.80 Dimensions in mm Min. Nom. Max. A 8.90 ― 9.10 B 6.90 ― 7.10 C 8.90 ― 9.10 D 6.90 ― 7.10 E ― 0.50 ― F ― 0.20 ― G 1.35 ― 1.45 1.60 H ― ― I ― 0.10 ― J 0.45 ― 0.75 K 0.10 ― 0.20 α 0° ― 7° 238 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 Package Information TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM LQFP Outline Dimensions 64-pin64-pin LQFP (7mm7mm) Outline Dimensions LQFP (7mmx7mm) Outline Dimensions Symbol Symbol A Dimensions in inch Min. AB 0.350 Min. 0.272 0.350 Nom. in inch Dimensions Nom. ― Max. 0.358 Max. 0.280 0.358 BC 0.350 0.272 ― 0.358 0.280 CD 0.272 0.350 ― 0.280 0.358 DE 0.272 ― 0.016 0.280 EF FG ― 0.005 0.005 0.053 0.053 0.016 ― ― 0.009 0.009 0.057 0.057 0.063 GH HI ― ― I J J K K α ― 0.002 0.002 0.018 0.018 0.004 0.004 0 0° Symbol Symbol A A B B C C D D E E F F GG Min. Min. 8.90 8.90 6.90 6.90 8.90 8.90 6.90 6.90 ― 0.13 0.13 1.35 1.35 HH II ― 0.05 0.05 ― ― ― JJ 0.45 0.45 ― 0.75 0.75 KK 0.09 0.09 ― 0.20 0.20 α 0°0 ― 77° ― ― ― ― Dimensions in mm Dimensions in mm Nom. Nom. ― ― ― ― 0.40 0.40 ― 1 Rev. 1.80 239 0.063 0.006 0.006 0.030 0.030 0.008 0.008 7 7° Max. Max. 9.10 9.10 7.10 7.10 9.10 9.10 7.10 7.10 ― 0.23 0.23 1.45 1.45 1.60 1.60 0.15 0.15 February 8, 2010 August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 Package Information TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM LQFP Outline Dimensions 80-pin (10mmx10mm) Dimensions 80-pinLQFP LQFP (10mm10mm) Outline Outline Dimensions Dimensions in inch Symbol Symbol A B C D E F A B C D E F G Min. 0.469 0.390 0.469 0.390 ― 0.469 0.018 I K ― 0.004 0.018 B C D E F G H I 0.016 0.006 0.006 ―0.004 0 0.004 11.90 B 9.90 D E F G 11.90 9.90 11.90 9.90 10.10 12.10 10.10 ― 0.40 0.16 1.35 0.45 K ― ― α 0° 10.10 1.60 J 0.10 12.10 0.45 10.10 1.45 0.160.10 J Max. 12.10 0.40 K 7° 12.10 I ― 0.008 ― H ― 0.008 ― 1.35 0.057 Max. ― ― 0.063 Nom. ― ― 0.030 7 Nom. 9.90 0.057 ― ― Dimensions in mm 11.90 0.398 0.063 0.030 ― Min. 0.398 0.476 ― 0.004 Dimensions in mm A Min. 0.016 ― C 0.476 0.398 0.053 0.053 A ― Max. 0.476 ― I Symbol 0.398 J 0° ― H Symbol 0.476 ― 0.390 G α Max. Nom. 0.390 H K Nom. Dimensions in inch 0.469 ― J Rev. 1.80 Min. ― ― 1.45 0.75 0.10 ― ― 0 0.10 7― 1 ― 0.75 ― 0.20 April 1, 2010 ― 240 1.60 0.20 7° August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Package Information 100-pin LQFP (14mmx14mm) Outline Dimensions 100-pin LQFP (14mm14mm) Outline Dimensions Dimensions in inch Symbol Symbol A B C D A B C D E F E G F G Min. 0.626 0.547 0.626 0.547 ― H ― Nom. Max. 0.634 0.555 Dimensions in inch 0.626 Nom. 0.547 ― 0.626 0.634 0.555 0.020 ― ―0.008 ― 0.057 0.008 ― 0.063 J ― 0.018 ― I K ― 0.004 0.004 J 0.018 0 Symbol A B C D E F ―0.004 0.004 0° 15.90 B 13.90 D E F G H Min. 15.90 13.90 15.90 13.90 ― 0.008 Max. 16.10 14.10 16.10 14.10 0.50 0.20 1.45 ― ― ― ― 1.35 7° Nom. Nom. 13.90 ― 0.008 0.030 7 Dimensions in mm 15.90 0.063 0.030 ― ― Min. 0.057 ― Dimensions in mm A C 0.555 0.053 I Symbol 0.555 0.634 0.020 H α Max. 0.634 ― 0.547 0.053 K Rev. 1.80 Min. 0.50 Max. 16.10 14.10 16.10 14.10 ― 1.60 I ― 0.20 0.10 G J 1.35 0.45 ― 1.45 0.75 H K ― 0.10 ― 1.60 0.20 I ― 0 0.10 7― ― J 0.45 ― 0.75 K 0.10 ― 0.20 April 13, 2011 α 0° 1 ― 241 7° August 08, 2012 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor (China) Inc. (Dongguan Sales Office) Building No.10, Xinzhu Court, (No.1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808 Tel: 86-769-2626-1300 Fax: 86-769-2626-1311, 86-769-2626-1322 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright© 2012 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.80 242 August 08, 2012