Enhanced I/O Flash Type 8-Bit MCU with EEPROM HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Revision: V2.10 Date: ������������� July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Table of Contents Features............................................................................................................. 8 CPU Features.......................................................................................................................... 8 Peripheral Features.................................................................................................................. 9 General Description........................................................................................ 10 Selection Table.................................................................................................11 Block Diagram................................................................................................. 12 Pin Assignment............................................................................................... 13 Pin Description............................................................................................... 17 Absolute Maximum Ratings........................................................................... 22 D.C. Characteristics........................................................................................ 22 A.C. Characteristics........................................................................................ 24 Comparator Electrical Characteristics......................................................... 25 Power-on Reset Characteristics.................................................................... 25 System Architecture....................................................................................... 26 Clocking and Pipelining.......................................................................................................... 26 Program Counter.................................................................................................................... 27 Stack...................................................................................................................................... 28 Arithmetic and Logic Unit – ALU............................................................................................ 28 Flash Program Memory.................................................................................. 29 Structure................................................................................................................................. 29 Special Vectors...................................................................................................................... 30 Look-up Table......................................................................................................................... 30 Table Program Example......................................................................................................... 31 In Circuit Programming.......................................................................................................... 32 RAM Data Memory.......................................................................................... 33 Structure................................................................................................................................. 33 Special Function Register Description......................................................... 37 Indirect Addressing Registers – IAR0, IAR1.......................................................................... 37 Memory Pointers – MP0, MP1............................................................................................... 37 Bank Pointer – BP.................................................................................................................. 38 Accumulator – ACC................................................................................................................ 40 Program Counter Low Register – PCL................................................................................... 40 Look-up Table Registers – TBLP, TBHP, TBLH...................................................................... 40 Status Register – STATUS..................................................................................................... 41 Rev. 2.10 2 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM EEPROM Data Memory................................................................................... 43 EEPROM Data Memory Structure......................................................................................... 43 EEPROM Registers............................................................................................................... 43 Reading Data from the EEPROM.......................................................................................... 47 Writing Data to the EEPROM................................................................................................. 47 Write Protection...................................................................................................................... 47 EEPROM Interrupt................................................................................................................. 47 Programming Considerations................................................................................................. 48 Oscillator......................................................................................................... 49 Oscillator Overview................................................................................................................ 49 System Clock Configurations................................................................................................. 49 External Crystal/Ceramic Oscillator – HXT............................................................................ 51 External RC Oscillator – ERC................................................................................................ 52 Internal RC Oscillator – HIRC................................................................................................ 52 External 32.768kHz Crystal Oscillator – LXT......................................................................... 53 LXT Oscillator Low Power Function....................................................................................... 54 Internal 32kHz Oscillator – LIRC............................................................................................ 54 Supplementary Oscillators..................................................................................................... 54 Operating Modes and System Clocks.......................................................... 55 System Clocks....................................................................................................................... 55 System Operation Modes....................................................................................................... 57 Control Register..................................................................................................................... 58 Fast Wake-up......................................................................................................................... 60 Operating Mode Switching and Wake-up............................................................................... 61 NORMAL Mode to SLOW Mode Switching............................................................................ 62 SLOW Mode to NORMAL Mode Switching............................................................................ 63 Entering the SLEEP1 Mode................................................................................................... 64 Entering the IDLE0 Mode....................................................................................................... 64 Entering the IDLE1 Mode....................................................................................................... 65 Standby Current Considerations............................................................................................ 65 Wake-up................................................................................................................................. 66 Programming Considerations................................................................................................. 66 Watchdog Timer.............................................................................................. 67 Watchdog Timer Clock Source............................................................................................... 67 Watchdog Timer Control Register.......................................................................................... 67 Watchdog Timer Operation.................................................................................................... 68 Reset and Initialisation................................................................................... 69 Reset Functions..................................................................................................................... 69 Reset Initial Conditions.......................................................................................................... 72 Rev. 2.10 3 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Input/Output Ports.......................................................................................... 82 Pull-high Resistors................................................................................................................. 84 Port A Wake-up...................................................................................................................... 86 I/O Port Control Registers...................................................................................................... 86 Pin-remapping Functions....................................................................................................... 89 Pin-remapping Registers........................................................................................................ 89 I/O Pin Structures................................................................................................................... 96 Programming Considerations................................................................................................. 96 Timer Modules – TM....................................................................................... 97 Introduction............................................................................................................................ 97 TM Operation......................................................................................................................... 98 TM Clock Source.................................................................................................................... 98 TM Interrupts.......................................................................................................................... 98 TM External Pins.................................................................................................................... 98 TM Input/Output Pin Control Registers.................................................................................. 99 Programming Considerations............................................................................................... 109 Compact Type TM..........................................................................................110 Compact TM Operation.........................................................................................................110 Compact Type TM Register Description...............................................................................111 Compact Type TM Operating Modes....................................................................................115 Compare Match Output Mode...............................................................................................115 Timer/Counter Mode.............................................................................................................115 PWM Output Mode................................................................................................................118 Standard Type TM – STM............................................................................. 121 Standard TM Operation........................................................................................................ 121 Standard Type TM Register Description.............................................................................. 122 Standard Type TM Operating Modes................................................................................... 131 Compare Output Mode......................................................................................................... 131 Timer/Counter Mode............................................................................................................ 134 PWM Output Mode............................................................................................................... 134 Single Pulse Mode............................................................................................................... 138 Capture Input Mode............................................................................................................. 140 Enhanced Type TM – ETM............................................................................ 142 Enhanced TM Operation...................................................................................................... 143 Enhanced Type TM Register Description............................................................................. 143 Enhanced Type TM Operating Modes................................................................................. 150 Compare Output Mode......................................................................................................... 150 Timer/Counter Mode............................................................................................................ 155 PWM Output Mode............................................................................................................... 155 Single Pulse Output Mode................................................................................................... 161 Capture Input Mode............................................................................................................. 163 Rev. 2.10 4 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Comparators................................................................................................. 166 Comparator Operation......................................................................................................... 166 Comparator Registers.......................................................................................................... 166 Comparator Interrupt............................................................................................................ 169 Programming Considerations............................................................................................... 169 Serial Interface Module – SIM...................................................................... 169 SPI Interface........................................................................................................................ 170 SPI Registers....................................................................................................................... 171 SPI Communication............................................................................................................. 174 I2C Interface......................................................................................................................... 176 I2C Interface Operation......................................................................................................... 176 I2C Registers........................................................................................................................ 177 I2C Bus Communication....................................................................................................... 181 I2C Bus Start Signal.............................................................................................................. 182 Slave Address...................................................................................................................... 182 I2C Bus Read/Write Signal................................................................................................... 183 I2C Bus Data and Acknowledge Signal................................................................................ 183 Peripheral Clock Output............................................................................... 185 Peripheral Clock Operation.................................................................................................. 185 Interrupts....................................................................................................... 186 Interrupt Registers................................................................................................................ 186 Interrupt Operation............................................................................................................... 200 External Interrupt.................................................................................................................. 204 Comparator Interrupt............................................................................................................ 204 Multi-function Interrupt......................................................................................................... 205 Time Base Interrupts............................................................................................................ 205 Serial Interface Module Interrupt.......................................................................................... 207 External Peripheral Interrupt................................................................................................ 207 EEPROM Interrupt............................................................................................................... 207 LVD Interrupt........................................................................................................................ 208 TM Interrupts........................................................................................................................ 208 Interrupt Wake-up Function.................................................................................................. 208 Programming Considerations............................................................................................... 209 Power Down Mode and Wake-up................................................................. 210 Entering the IDLE or SLEEP Mode...................................................................................... 210 Standby Current Considerations.......................................................................................... 210 Wake-up................................................................................................................................211 Low Voltage Detector – LVD........................................................................ 212 LVD Register........................................................................................................................ 212 LVD Operation...................................................................................................................... 213 Rev. 2.10 5 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM SCOM Function for LCD............................................................................... 214 LCD Operation..................................................................................................................... 214 LCD Bias Control................................................................................................................. 215 Configuration Options.................................................................................. 217 Application Circuits...................................................................................... 218 UART Module Serial Interface..................................................................... 219 UART Module Features....................................................................................................... 219 UART Module Overview....................................................................................................... 219 UART Module Block Diagram.............................................................................................. 219 Pin Assignment.................................................................................................................... 220 UART Module Pin Description............................................................................................. 222 UART Module D.C. Characteristics...................................................................................... 223 UART Module A.C. Characteristics...................................................................................... 224 UART Module Functional Description.................................................................................. 224 UART Module Internal Signal............................................................................................... 225 UART Module SPI Interface................................................................................................. 225 UART Module External Pin Interfacing................................................................................ 226 UART Data Transfer Scheme.............................................................................................. 227 UART Commands................................................................................................................ 227 UART Status and Control Registers.................................................................................... 228 Baud Rate Generator........................................................................................................... 233 UART Module Setup and Control......................................................................................... 235 Managing Receiver Errors................................................................................................... 240 UART Module Interrupt Structure......................................................................................... 241 UART Module Power-down and Wake-up........................................................................... 242 Using the UART Function.................................................................................................... 243 Application Circuit with UART Module................................................................................. 244 Instruction Set............................................................................................... 245 Introduction.......................................................................................................................... 245 Instruction Timing................................................................................................................. 245 Moving and Transferring Data.............................................................................................. 245 Arithmetic Operations........................................................................................................... 245 Logical and Rotate Operation.............................................................................................. 246 Branches and Control Transfer............................................................................................ 246 Bit Operations...................................................................................................................... 246 Table Read Operations........................................................................................................ 246 Other Operations.................................................................................................................. 246 Instruction Set Summary............................................................................. 247 Table Conventions................................................................................................................ 247 Instruction Definition.................................................................................... 249 Rev. 2.10 6 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Package Information.................................................................................... 258 16-pin DIP (300mil) Outline Dimensions.............................................................................. 259 16-pin NSOP (150mil) Outline Dimensions.......................................................................... 261 16-pin SSOP (150mil) Outline Dimensions.......................................................................... 262 20-pin DIP (300mil) Outline Dimensions.............................................................................. 263 20-pin SOP (300mil) Outline Dimensions............................................................................ 265 20-pin SSOP (150mil) Outline Dimensions.......................................................................... 266 24-pin SKDIP (300mil) Outline Dimensions......................................................................... 267 24-pin SOP (300mil) Outline Dimensions............................................................................ 269 24-pin SSOP (150mil) Outline Dimensions.......................................................................... 270 28-pin SKDIP (300mil) Outline Dimensions......................................................................... 271 28-pin SOP (300mil) Outline Dimensions............................................................................ 272 28-pin SSOP (150mil) Outline Dimensions.......................................................................... 273 SAW Type 32-pin (5mm×5mm) QFN Outline Dimensions................................................... 274 SAW Type 40-pin (6mm×6mm for 0.75mm) QFN Outline Dimensions................................ 275 44-pin LQFP (10mm×10mm) (FP 2.0mm) Outline Dimensions........................................... 276 48-pin SSOP (300mil) Outline Dimensions.......................................................................... 277 SAW Type 48-pin (7mm×7mm) QFN Outline Dimensions................................................... 278 48-pin LQFP (7mm×7mm) Outline Dimensions................................................................... 279 Rev. 2.10 7 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Features CPU Features • Operating Voltage: ♦♦ fSYS=8MHz: 2.2V~5.5V ♦♦ fSYS=12MHz: 2.7V~5.5V ♦♦ fSYS=20MHz: 4.5V~5.5V • Up to 0.2μs instruction cycle with 20MHz system clock at VDD=5V • Power down and wake-up functions to reduce power consumption • Five oscillators: ♦♦ External Crystal -- HXT ♦♦ External 32.768kHz Crystal -- LXT ♦♦ External RC -- ERC ♦♦ Internal RC -- HIRC ♦♦ Internal 32kHz RC -- LIRC • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • Fully integrated internal 4MHz, 8MHz and 12MHz oscillator requires no external components • All instructions executed in one or two instruction cycles • Table read instructions • 63 powerful instructions • Up to 12-level subroutine nesting • Bit manipulation instruction Rev. 2.10 8 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Peripheral Features • Flash Program Memory: 1K×14~12K×16 • RAM Data Memory: 64×8~576×8 • EEPROM Memory: 32×8~256×8 • Watchdog Timer function • Up to 50 bidirectional I/O lines • Software controlled 4-SCOM lines LCD driver with 1/2 bias • Multiple pin-shared external interrupts • Multiple Timer Module for time measure, input capture, compare match output, PWM output or single pulse output function • Serial Interfaces Module – SIM for SPI or I2C • Dual Comparator functions • Dual Time-Base functions for generation of fixed time interrupt signals • Low voltage reset function • Low voltage detect function • Optional peripheral -- UART module for fully duplex asynchronous communication • Wide range of available package types • Flash program memory can be re-programmed up to 100,000 times • Flash program memory data retention > 10 years • EEPROM data memory can be re-programmed up to 1,000,000 times • EEPROM data memory data retention > 10 years Rev. 2.10 9 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM General Description The HT68FXX series of devices are Flash Memory I/O type 8-bit high performance RISC architecture microcontrollers. Offering users the convenience of Flash Memory multi-programming features, these devices also include a wide range of functions and features. Other memory includes an area of RAM Data Memory as well as an area of EEPROM memory for storage of non-volatile data such as serial numbers, calibration data etc. Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM generation functions. Analog features include dual comparator functions. Communication with the outside world is catered for by including fully integrated SPI or I2C interface functions, two popular interfaces which provide designers with a means of easy communication with external peripheral hardware. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of HXT, LXT, ERC, HIRC and LIRC oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. The UART module is contained in the HT68FUx0 series of devices. It can support the applications such as data communication networks between microcontrollers, low-cost data links between PCs and peripheral devices, portable and battery operated device communication, etc. The inclusion of flexible I/O programming features, Time-Base functions along with many other features ensure that the devices will find excellent use in applications such as electronic metering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. Rev. 2.10 10 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Selection Table Most features are common to all devices, the main feature distinguishing them are Memory capacity, I/O count, TM features, stack capacity and package types. The following table summarises the main features of each device. Part No. VDD HT68F20 2.2V~5.5V HT68F30 2.2V~5.5V Program Data Data I/O Memory Memory EEPROM 1K×14 64×8 32×8 2K×14 96×8 64×8 HT68FU30 2 10-bit CTM×1 10-bit STM×1 √ 2 10-bit CTM×1 10-bit ETM×1 √ 42 2.2V~5.5V 4K×15 192×8 128×8 HT68FU40 2 34 2.2V~5.5V 8K×16 384×8 256×8 HT68FU50 42 2 34 HT68F60 50 2.2V~5.5V 12K×16 HT68FU60 22 TM Module Interface UART Stack (SPI/I2C) 14 HT68F40 HT68F50 18 Ext. Int. 576×8 256×8 4 42 10-bit CTM×1 10-bit ETM×1 16-bit STM×1 √ 10-bit CTM×2 10-bit ETM×1 16-bit STM×1 √ 10-bit CTM×2 10-bit ETM×1 16-bit STM×1 — 4 Package 16DIP/NSOP/SSOP 20DIP/SOP/SSOP 4 16DIP/NSOP/SSOP 20DIP/SOP/SSOP 24SKDIP/SOP/SSOP √ 24SKDIP/SOP — 8 24/28SKDIP/SOP/SSOP 44LQFP, 32/40QFN 48SSOP/QFN — 40QFN, 44LQFP, 48SSOP/QFN √ — 8 28SKDIP/SOP/SSOP 44LQFP, 40QFN 48SSOP/QFN √ 44LQFP, 48QFN — 40QFN, 44LQFP 48SSOP/LQFP/QFN √ 12 √ 40QFN, 44LQFP 48LQFP/QFN Note: As devices exist in more than one package format, the table reflects the situation for the package with the most pins. There is an additional peripheral known as the UART module in HT68FU30, HT68FU40, HT68FU50 and HT68FU60 devices. All information related to the UART Module will be described in the following UART Module section. Rev. 2.10 11 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Block Diagram Rev. 2.10 12 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Pin Assignment Note: 1. Bracketed pin names indicate non-default pinout remapping locations. 2. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the "/" sign can be used for higher priority. Rev. 2.10 13 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Note: 1. Bracketed pin names indicate non-default pinout remapping locations. 2. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the "/" sign can be used for higher priority. Rev. 2.10 14 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Note: 1. Bracketed pin names indicate non-default pinout remapping locations. 2. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the "/" sign can be used for higher priority. Rev. 2.10 15 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Note: 1. Bracketed pin names indicate non-default pinout remapping locations. 2. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the "/" sign can be used for higher priority. Rev. 2.10 16 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Pin Description With the exception of the power pins, all pins on these devices can be referenced by their Port name, e.g. PA.0, PA.1 etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Serial Port pins etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. The following tables only include the pins which are directly related to the MCU. The pin descriptions of the additional peripheral functions are located at the end of the datasheet along with the relevant peripheral function functional description. HT68F20 Pin Name Function OP I/T O/T Pin-Shared Mapping PAWU PAPU ST CMOS — — PA0~PA7 Port A PB0~PB5 Port B PBPU ST CMOS PC0~PC3 Port C PCPU ST CMOS C0-, C1- Comparator 0, 1 input AN — PA3, PC3 C0+, C1+ Comparator 0, 1 input AN — PA2, PC2 C0X, C1X Comparator 0, 1 output — CMOS PA0, PA5 TCK0, TCK1 TM0, TM1 input — ST — PA2, PA4 TP0_0 TM0 I/O TMPC0 ST CMOS PA0 TP1_0, TP1_1 TM1 I/O TMPC0 ST CMOS PA1, PC0 INT0, INT1 Ext. Interrupt 0, 1 — ST — PA3, PA4 PINT Peripheral Interrupt — ST — PC3 PCK Peripheral Clock output — — CMOS PC2 SDI SPI Data input — ST — PA6 SDO SPI Data output — — CMOS PA5 SCS SPI Slave Select — ST CMOS PB5 SCK SPI Serial Clock — ST CMOS PA7 SCL I2C Clock — ST NMOS PA7 SDA I2C Data — ST NMOS PA6 SCOM0~SCOM3 SCOM0~SCOM3 SCOMC — SCOM PC0, PC1, PC2, PC3 OSC1 HXT/ERC pin CO HXT — PB1 OSC2 HXT pin CO — HXT PB2 XT1 LXT pin CO LXT — PB3 XT2 LXT pin CO — LXT PB4 RES Reset input CO ST — PB0 VDD Power supply — PWR — — VSS Ground — PWR — — CP0C CP1C — Note: I/T: Input type; O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option; ST: Schmitt Trigger input CMOS: CMOS output; NMOS: NMOS output SCOM: Software controlled LCD COM; AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator As the Pin Description Summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. Rev. 2.10 17 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM HT68F30 Pin Name Function OP I/T O/T Pin-Shared Mapping PAWU PAPU ST CMOS — — PA0~PA7 Port A PB0~PB5 Port B PBPU ST CMOS PC0~PC7 Port C PCPU ST CMOS C0-, C1- Comparator 0, 1 input AN — PA3, PC3 C0+, C1+ Comparator 0, 1 input AN — PA2, PC2 C0X, C1X Comparator 0, 1 output — CMOS PA0, PA5 TCK0, TCK1 TM0, TM1 input — ST — PA2, PA4 TP0_0, TP0_1 TM0 I/O TMPC0 ST CMOS PA0, PC5 TP1A TM1 I/O TMPC0 ST CMOS PA1 TP1B_0, TP1B_1 TM1 I/O TMPC0 ST CMOS PC0, PC1 INT0, INT1 Ext. Interrupt 0, 1 — ST — PA3, PA4 PINT Peripheral Interrupt PRM0 ST — PC3 or PC4 PCK Peripheral Clock output PRM0 — CMOS PC2 or PC5 SDI SPI Data input PRM0 ST — PA6 or PC0 SDO SPI Data output PRM0 — CMOS PA5 or PC1 SCS SPI Slave Select PRM0 ST CMOS PB5 or PC6 SCK SPI Serial Clock PRM0 ST CMOS PA7 or PC7 SCL I2C Clock PRM0 ST NMOS PA7 or PC7 SDA I2C Data PRM0 ST NMOS PA6 or PC0 SCOM0~SCOM3 SCOM0~SCOM3 SCOMC — SCOM PC0, PC1, PC6, PC7 OSC1 HXT/ERC pin CO HXT — PB1 OSC2 HXT pin CO — HXT PB2 XT1 LXT pin CO LXT — PB3 XT2 LXT pin CO — LXT PB4 RES Reset input CO ST — PB0 VDD Power supply — PWR — — VSS Ground — PWR — — CP0C CP1C — Note: I/T: Input type; O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option; ST: Schmitt Trigger input CMOS: CMOS output; NMOS: NMOS output SCOM: Software controlled LCD COM; AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator As the Pin Description Summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. Rev. 2.10 18 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM HT68F40 Pin Name Function OP I/T O/T Pin-Shared Mapping PAWU PAPU ST CMOS — PA0~PA7 Port A PB0~PB7 Port B PBPU ST CMOS — PC0~PC7 Port C PCPU ST CMOS — PD0~PD7 Port D PDPU ST CMOS — PE0~PE7 Port E PEPU ST CMOS — PF0~PF1 Port F PFPU ST CMOS — C0-, C1- Comparator 0, 1 input CP0C CP1C AN — PA3, PC3 C0+, C1+ Comparator 0, 1 input CP0C CP1C AN — PA2, PC2 C0X,C1X Comparator 0, 1 output CP0C CP1C PRM0 — CMOS TCK0~TCK2 TM0~TM2 input PA0, PA5 or PF0, PF1 PRM1 ST — PA2, PA4, PC2 or PD2, PD3, PD0 ST CMOS PA0, PC5 or PC6, PD5 TP0_0, TP0_1 TM0 I/O TMPC0 PRM2 TP1A TM1 I/O TMPC0 PRM2 ST CMOS PA1 or PC7 TP1B_0~TP1B_2 TM1 I/O TMPC0 PRM2 ST CMOS PC0, PC1, PC5 or -, -, PE4 TP2_0, TP2_1 TM2 I/O TMPC1 PRM2 ST CMOS PC3, PC4 or PD1, PD4 INT0, INT1 Ext. Interrupt 0, 1 PRM1 ST — PA3, PA4 or PC4, PC5 or PE6, PE7 PINT Peripheral Interrupt PRM0 ST — PC3 or PC4 PCK Peripheral Clock output PRM0 — CMOS PC2 or PC5 SDI SPI Data input PRM0 ST — PA6 or PD2 or PB7 SDO SPI Data output PRM0 — CMOS PA5 or PD3 or PB6 SCS SPI Slave Select PRM0 ST CMOS PB5 or PD0 or PD7 SCK SPI Serial Clock PRM0 ST CMOS PA7 or PD1 or PD6 SCL I2C Clock PRM0 ST NMOS PA7 or PD1 or PD6 SDA I C Data 2 SCOM0~SCOM3 SCOM0~SCOM3 PRM0 ST NMOS PA6 or PD2 or PB7 SCOMC — SCOM PC0, PC1, PC6, PC7 OSC1 HXT/ERC pin CO HXT — PB1 OSC2 HXT pin CO — HXT PB2 XT1 LXT pin CO LXT — PB3 XT2 LXT pin CO — LXT PB4 RES Reset input CO ST — PB0 VDD Power supply — PWR — — VSS Ground — PWR — — Note: I/T: Input type; O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option; ST: Schmitt Trigger input CMOS: CMOS output; NMOS: NMOS output SCOM: Software controlled LCD COM; AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator As the Pin Description Summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. Rev. 2.10 19 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM HT68F50 Pin Name Function OP I/T O/T Pin-Shared Mapping PAWU PAPU ST CMOS — PA0~PA7 Port A PB0~PB7 Port B PBPU ST CMOS — PC0~PC7 Port C PCPU ST CMOS — PD0~PD7 Port D PDPU ST CMOS — PE0~PE7 Port E PEPU ST CMOS — PF0~PF1 Port F PFPU ST CMOS — C0-, C1- Comparator 0, 1 input CP0C CP1C AN — PA3, PC3 C0+, C1+ Comparator 0, 1 input CP0C CP1C AN — PA2, PC2 C0X, C1X Comparator 0, 1 output CP0C CP1C PRM0 — TCK0~TCK3 TM0~TM3 input CMOS PA0, PA5 or PF0, PF1 PRM1 ST — PA2, PA4, PC2, PC4 or PD2, PD3, PD0, - ST CMOS PA0, PC5 or PC6, PD5 TP0_0, TP0_1 TM0 I/O TMPC0 PRM2 TP1A TM1 I/O TMPC0 PRM2 ST CMOS PA1 or PC7 TP1B_0~TP1B_2 TM1 I/O TMPC0 PRM2 ST CMOS PC0, PC1, PC5 or -, -, PE4 TP2_0, TP2_1 TM2 I/O TMPC1 PRM2 ST CMOS PC3, PC4 or PD1, PD4 TP3_0, TP3_1 TM3 I/O TMPC1 PRM2 ST CMOS PD3, PD0 or PE5, PE3 INT0, INT1 Ext. Interrupt 0, 1 PRM1 ST — PA3, PA4 or PC4, PC5 or PE6, PE7 PINT Peripheral Interrupt PRM0 ST — PC3 or PC4 PCK Peripheral Clock output PRM0 — SDI SPI Data input PRM0 ST SDO SPI Data output PRM0 — CMOS PA5 or PD3 or PB6 SCS SPI Slave Select PRM0 ST CMOS PB5 or PD0 or PD7 SCK SPI Serial Clock PRM0 ST CMOS PA7 or PD1 or PD6 SCL I2C Clock PRM0 ST NMOS PA7 or PD1 or PD6 SDA I2C Data PRM0 ST NMOS PA6 or PD2 or PB7 SCOMC — SCOM PC0, PC1, PC6, PC7 HXT — PB1 SCOM0~SCOM3 SCOM0~SCOM3 CMOS PC2 or PC5 — PA6 or PD2 or PB7 OSC1 HXT/ERC pin CO OSC2 HXT pin CO — HXT PB2 XT1 LXT pin CO LXT — PB3 XT2 LXT pin CO — LXT PB4 RES Reset input CO ST — PB0 VDD Power supply — PWR — — VSS Ground — PWR — — Note: I/T: Input type; O/T: Output type; ST: Schmitt Trigger input OP: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option; CMOS: CMOS output; NMOS: NMOS output SCOM: Software controlled LCD COM; AN: Analog input pin HXT: High frequency crystal oscillator; LXT: Low frequency crystal oscillator As the Pin Description Summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. Rev. 2.10 20 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM HT68F60 Pin Name Function OP I/T O/T Pin-Shared Mapping PAWU PAPU ST CMOS — PA0~PA7 Port A PB0~PB7 Port B PBPU ST CMOS — PC0~PC7 Port C PCPU ST CMOS — PD0~PD7 Port D PDPU ST CMOS — PE0~PE7 Port E PEPU ST CMOS — PF0~PF7 Port F PFPU ST CMOS — PG0~PG1 Port G PGPU ST CMOS — C0-, C1- Comparator 0, 1 input CP0C CP1C AN — PA3, PC3 C0+, C1+ Comparator 0, 1 input CP0C CP1C AN — PA2, PC2 C0X, C1X Comparator 0, 1 output CP0C CP1C PRM0 — TCK0~TCK3 TM0~TM3 input PRM1 ST TP0_0, TP0_1 TM0 I/O TMPC0 PRM2 ST CMOS PA0, PC5 or PC6, PD5 TP1A TM1 I/O TMPC0 PRM2 ST CMOS PA1 or PC7 TP1B_0~TP1B_2 TM1 I/O TMPC0 PRM2 ST CMOS PC0, PC1, PC5 or -, -, PE4 TP2_0, TP2_1 TM2 I/O TMPC1 PRM2 ST CMOS PC3, PC4 or PD1, PD4 TP3_0, TP3_1 TM3 I/O TMPC1 PRM2 ST CMOS PD3, PD0 or PE5, PE3 INT0~INT3 Ext. Interrupt 0~3 PRM1 ST PINT Peripheral Interrupt PRM0 ST PCK Peripheral Clock output PRM0 — SDI SPI Data input PRM0 ST SDO SPI Data output PRM0 — CMOS PA5 or PD3 or PB6 or PD1 SCS SPI Slave Select PRM0 ST CMOS PB5 or PD0 or PD7 SCK SPI Serial Clock PRM0 ST CMOS PA7 or PD1 or PD6 or PD3 SCL I C Clock PRM0 ST NMOS PA7 or PD1 or PD6 or PD3 SDA I2C Data PRM0 ST NMOS PA6 or PD2 or PB7 SCOMC — SCOM PC0, PC1, PC6, PC7 2 SCOM0~SCOM3 SCOM0~SCOM3 CMOS PA0, PA5 or PF0, PF1 or PG0, PG1 — PA2, PA4, PC2, PC4 or PD2, PD3, PD0, - — PA3, PA4, PC4, PC5 or PC4, PC5, PE2, or PE0, PE1, -, - or PE6, PE7, -, - — PC3 or PC4 CMOS PC2 or PC5 — PA6 or PD2 or PB7 OSC1 HXT/ERC pin CO HXT — PB1 OSC2 HXT pin CO — HXT PB2 XT1 LXT pin CO LXT — PB3 XT2 LXT pin CO — LXT PB4 RES Reset input CO ST — PB0 VDD Power supply — PWR — — VSS Ground — PWR — — Note: I/T: Input type; O/T: Output type; ST: Schmitt Trigger input OP: Optional by configuration option (CO) or register option; NMOS: NMOS output PWR: Power; CO: Configuration option; AN: Analog input pin CMOS: CMOS output; SCOM: Software controlled LCD COM HXT: High frequency crystal oscillator; LXT: Low frequency crystal oscillator As the Pin Description Summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. Rev. 2.10 21 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Absolute Maximum Ratings Supply Voltage ................................................................................................... VSS-0.3V~VSS+6.0V Input Voltage ......................................................................................................VSS-0.3V~VDD+0.3V Storage Temperature .................................................................................................... -50˚C~125˚C Operating Temperature . ................................................................................................. -40˚C~85˚C IOL Total ..................................................................................................................................... 80mA IOH Total ................................................................................................................................... -80mA Total Power Dissipation ........................................................................................................ 500mW Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Ta=25˚C Symbol VDD Parameter Operating Voltage (HXT, ERC, HIRC) Test Conditions — 3V 5V IDD1 Operating Current, Normal Mode, fSYS=fH (HXT, ERC, HIRC) Min. Typ. Max. Unit fSYS=8MHz 2.2 — 5.5 V fSYS=12MHz 2.7 — 5.5 V fSYS=20MHz 4.5 — 5.5 V No load, fSYS=fH=4MHz, WDT enable — 0.7 1.1 mA — 1.8 2.7 mA No load, fSYS=fH=8MHz, WDT enable — 1.6 2.4 mA — 3.3 5.0 mA No load, fSYS=fH=12MHz, WDT enable — 2.2 3.3 mA — 5.0 7.5 mA — 6.0 9.0 mA — 10 20 μA — 30 50 μA — 1.5 3.0 μA — 3.0 6.0 μA — 0.55 0.83 mA — 1.30 2.00 mA — — 1 μA — — 2 μA — 1.5 3.0 μA — 2.5 5.0 μA VDD 3V 5V 3V 5V Conditions IDD2 Operating Current, Normal Mode, fSYS=fH (HXT) IDD3 Operating Current, Slow Mode, fSYS=fL (LXT, LIRC) 3V IIDLE0 IDLE0 Mode Standby Current (LXT or LIRC on) 3V IIDLE1 IDLE1 Mode Standby Current (HXT, ERC, HIRC) 3V ISLEEP0 SLEEP0 Mode Standby Current (LXT or LIRC off) 3V ISLEEP1 SLEEP1 Mode Standby Current (LXT or LIRC on) 3V VIL1 Input Low Voltage for I/O Ports or Input Pins except RES pin — — 0 — 0.3VDD V VIH1 Input High Voltage for I/O Ports or Input Pins except RES pin — — 0.7VDD — VDD V VIL2 Input Low Voltage (RES) — — 0 — 0.4VDD V VIH2 Input High Voltage (RES) — — 0.9VDD — VDD V Rev. 2.10 5V 5V 5V 5V 5V 5V No load, fSYS=fH=20MHz, WDT enable No load, fSYS=fL, WDT enable No load, WDT enable No load, WDT enable fSYS=12MHz on No load, WDT disable No load, WDT enable 22 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Symbol VLVR VLVD ILV VOL VOH RPH ISCOM VSCOM Rev. 2.10 Parameter LVR Voltage Level LVD Voltage Level Additional Power Consumption if LVR and LVD is Used Output Low Voltage I/O Port Output High Voltage I/O Port Pull-high Resistance for I/O Ports SCOM Operating Current VDD/2 Voltage for LCD COM Test Conditions VDD — — — Conditions Min. Typ. Max. Unit LVR enable, 2.1V option -5% 2.1 +5% V LVR enable, 2.55V option -5% 2.55 +5% V LVR enable, 3.15V option -5% 3.15 +5% V LVR enable, 4.2V option -5% 4.20 +5% V LVDEN=1, VLVD=2.0V -5% 2.00 +5% V LVDEN=1, VLVD=2.2V -5% 2.20 +5% V LVDEN=1, VLVD=2.4V -5% 2.40 +5% V LVDEN=1, VLVD=2.7V -5% 2.70 +5% V LVDEN=1, VLVD=3.0V -5% 3.00 +5% V LVDEN=1, VLVD=3.3V -5% 3.30 +5% V LVDEN=1, VLVD=3.6V -5% 3.60 +5% V LVDEN=1, VLVD=4.4V -5% 4.4 +5% V LVR enable, LVDEN=0 — 60 90 μA LVR disable, LVDEN=1 — 75 115 μA LVR enable, LVDEN=1 — 90 135 μA 3V IOL=9mA — — 0.3 V 5V IOL=20mA — — 0.5 V 3V IOH=-3.2mA 2.7 — — V 5V IOH=-7.4mA 4.5 — — V 20 60 100 kΩ 10 30 50 kΩ SCOMC, ISEL[1:0]=00 17.5 25.0 32.5 μA SCOMC, ISEL[1:0]=01 35 50 65 μA SCOMC, ISEL[1:0]=10 70 100 130 μA SCOMC, ISEL[1:0]=11 140 200 260 μA 0.475 0.500 0.525 VDD 3V — 5V 5V 5V No load 23 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM A.C. Characteristics Symbol fCPU fSYS fHIRC fERC fLXT Parameter Operating Clock System Clock (HXT) System Clock (HIRC) System Clock (ERC) System Clock (LXT) Ta=25˚C Test Conditions Min. Typ. 2.2V~5.5V DC — 8 MHz 2.7V~5.5V DC — 12 MHz 4.5V~5.5V DC — 20 MHz 2.2V~5.5V 0.4 — 8 MHz 2.7V~5.5V 0.4 — 12 MHz 20 MHz VDD — — Conditions Max. Unit 4.5V~5.5V 0.4 — 3V/5V Ta=25˚C -2% 4 +2% MHz 3V/5V Ta=25˚C -2% 8 +2% MHz 5V Ta=25˚C -2% 12 +2% MHz 3V/5V Ta=0~70˚C -5% 4 +5% MHz 3V/5V Ta=0~70˚C -4% 8 +4% MHz 5V Ta=0~70˚C -5% 12 +3% MHz 2.2V~3.6V Ta=0~70˚C -7% 4 +7% MHz 3.0V~5.5V Ta=0~70˚C -5% 4 +9% MHz 2.2V~3.6V Ta=0~70˚C -6% 8 +4% MHz 3.0V~5.5V Ta=0~70˚C -4% 8 +9% MHz 3.0V~5.5V Ta=0~70˚C -6% 12 +7% MHz 2.2V~3.6V Ta=-40˚C~85˚C -12% 4 +8% MHz 3.0V~5.5V Ta=-40˚C~85˚C -10% 4 +9% MHz 2.2V~3.6V Ta=-40˚C~85˚C -15% 8 +4% MHz 3.0V~5.5V Ta=-40˚C~85˚C -8% 8 +9% MHz 3.0V~5.5V Ta=-40˚C~85˚C -12% 12 +7% MHz 5V Ta=25˚C, R=120kΩ* -2% 8 +2% MHz 5V Ta=0˚C~70˚C, R=120kΩ* -5% 8 +6% MHz 5V Ta=-40˚C~85˚C, R=120kΩ* -7% 8 +9% MHz 3.0V~5.5V Ta=-40˚C~85˚C, R=120kΩ* -9% 8 +10% MHz 2.2V~5.5V Ta=-40˚C~85˚C, R=120kΩ* -15% 8 +10% MHz — 5V — Ta=25˚C — 32.768 -10% 32 +10% kHz — kHz +60% kHz fLIRC System Clock (LIRC) -50% 32 fTIMER Timer Input Pin Frequency — — — — 1 tRES External Reset Low Pulse Width — — 1 — — μs tINT Interrupt Pulse Width — — 1 — — tSYS tLVR Low Voltage Width to Reset — — 120 240 480 μs 2.2V~5.5V Ta=-40˚C~85˚C fSYS tLVD Low Voltage Width to Interrupt — — 20 45 90 μs tLVDS LVDO stable time — — 15 — — μs tBGS VBG Turn on Stable Time — — 200 — — μs tEERD EEPROM Read Time — — — 45 90 μs tEEWR EEPROM Write Time — — ms tSST System Start-up Timer Period (Wake-up from HALT) — — 2 4 fSYS=HXT or LXT — 1024 — fSYS=ERC or HIRC — 15~16 — fSYS=LIRC — 1~2 — tSYS Note: 1. tSYS=1/fSYS 2. * For fERC, as the resistor tolerance will influence the frequency a precision resistor is recommended. 3. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor should be connected between VDD and VSS and located as close to the device as possible. Rev. 2.10 24 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Comparator Electrical Characteristics Ta=25˚C Test Conditions Symbol Parameter VCMP Comparator Operating Voltage VDD Conditions Min. Typ. Max. Unit — — 2.2 — 5.5 V 3V — — 37 56 μA ICMP Comparator Operating Current 5V — — 130 200 μA VCMPOS Comparator Input Offset Voltage — — -10 — 10 mV VHYS Hysteresis Width — — 20 40 60 mV VCM Comparator Common Mode Voltage Range — — VSS — VDD-1.4V V AOL Comparator Open Loop Gain — — 60 80 — dB tPD Comparator Response Time — With 100mV overdrive (Note) — 370 560 ns Note: Measured with comparator one input pin at VCM=(VDD-1.4)/2 while the other pin input transition from VSS to (VCM+100mV) or from VDD to (VCM-100mV). Power-on Reset Characteristics Ta=25˚C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV RRVDD VDD Raising Rate to Ensure Power-on Reset — — 0.035 — — V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms Rev. 2.10 25 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O control system with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a HXT, LXT, HIRC, LIRC or ERC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. System Clocking and Pipelining Rev. 2.10 26 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as "JMP" or "CALL" that demand a jump to a non-consecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Device Program Counter Program Counter High Byte HT68F20 PC9, PC8 HT68F30 PC10~PC8 HT68F40 PC11~PC8 HT68F50 PC12~PC8 HT68F60 PC13~PC8 PCL Register PCL7~PCL0 Program Counter The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Rev. 2.10 27 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has multiple levels depending upon the device and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P ro g ra m S ta c k L e v e l 1 T o p o f S ta c k S ta c k L e v e l 2 S ta c k P o in te r B o tto m C o u n te r P ro g ra m M e m o ry S ta c k L e v e l 3 o f S ta c k S ta c k L e v e l N Device Stack Levels HT68F20/HT68F30 4 HT68F40/HT68F50 8 HT68F60 12 Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA • Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC • Increment and Decrement INCA, INC, DECA, DEC • Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Rev. 2.10 28 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device series the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, these Flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 1K×14 bits to 12K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. Capacity Banks HT68F20 Device 1K×14 0 HT68F30 2K×14 0 HT68F40 4K×15 0 HT68F50 8K×16 0 HT68F60 12K×16 0, 1 The HT68F60 has its Program Memory divided into two Banks, Bank 0 and Bank 1. The required Bank is selected using Bit 5 of the BP Register. R e s e t R e s e t R e s e t R e s e t R e s e t 0 0 2 C H In te rru p t V e c to r In te rru p t V e c to r In te rru p t V e c to r In te rru p t V e c to r In te rru p t V e c to r 0 3 F F H 1 4 b its 0 0 0 0 H 0 0 0 4 H 0 0 3 C H 0 7 F F H B a n k 0 1 4 b its 1 5 b its 0 F F F H 1 F F F H 1 6 b its 1 F F F H 2 0 0 0 H 2 F F F H 1 6 b its B a n k 1 Program Memory Structure Rev. 2.10 29 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the "TABRD [m]" or "TABRDL [m]" instructions, respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as "0". The accompanying diagram illustrates the addressing data flow of the look-up table. A d d re s s L a s t p a g e o r T B H P R e g is te r T B L P R e g is te r Rev. 2.10 D a ta 1 4 ~ 1 6 b its R e g is te r T B L H U s e r S e le c te d R e g is te r H ig h B y te L o w B y te 30 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is "700H" which refers to the start address of the last page within the 2K Program Memory of the HT68F30. The table pointer is setup here to have an initial value of "06H". This will ensure that the first data read from the data table will be at the Program Memory address "706H" or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the "TABRD [m]" instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the "TABRD [m]" instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a mov a,07h ; initialise high table pointer tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address "706H" transferred to tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address "705H" transferred to tempreg2 and TBLH in this ; example the data "1AH" is transferred to tempreg1 and data "0FH" to ; register tempreg2 : : org 700h ; sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : Rev. 2.10 31 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM In Circuit Programming The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a 5-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. MCU Programming Pins Function PA0 Serial Data Input/Output PA2 Serial Clock RES Device Reset VDD Power Supply VSS Ground The Program Memory and EEPROM data memory can both be programmed serially in-circuit using this 5-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply and one line for the reset. The technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. During the programming process the RES pin will be held low by the programmer disabling the normal operation of the microcontroller and taking control of the PA0 and PA2 I/O pins for data and clock programming purposes. The user must there take care to ensure that no other outputs are connected to these two pins. W r ite r C o n n e c to r S ig n a ls M C U W r ite r _ V D D V D D R E S R E S D A T A P r o g r a m m in g P in s D A T A C L K C L K W r ite r _ V S S V S S * * * T o o th e r C ir c u it Note: * may be resistor or capacitor. The resistance of * must be greater than 1kΩ or the capacitance of * must be less than 1nF. Programmer Pin MCU Pins RES PB0 DATA PA0 CLK PA2 Programmer and MCU Pins Rev. 2.10 32 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM RAM Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into two sections, the first of these is an area of RAM, known as the Special Function Data Memory. Here are located registers which are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for general purpose use. All locations within this area are read and write accessible under program control. The overall Data Memory is subdivided into several banks, the structure of which depends upon the device chosen. The Special Purpose Data Memory registers are accessible in all banks, with the exception of the EEC register at address 40H, which is only accessible in Bank 1. Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value. The start address of the Data Memory for all devices is the address 00H. Device Capacity Bank HT68F20 64×8 0: 60H~7FH 1: 60H~7FH HT68F30 96×8 0: 60H~7FH 1: 60H~7FH 2: 60H~7FH HT68F40 192×8 0: 80H~FFH 1: 80H~BFH HT68F50 384×8 0: 80H~FFH 1: 80H~FFH 2: 80H~FFH 576×8 0: 80H~FFH 1: 80H~FFH 2: 80H~FFH 3: 80H~FFH 4: 80H~BFH HT68F60 Rev. 2.10 33 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM HT68F20 Special Purpose Data Memory Rev. 2.10 HT68F30 Special Purpose Data Memory 34 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM HT68F40 Special Purpose Data Memory Rev. 2.10 HT68F50 Special Purpose Data Memory 35 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM HT68F60 Special Purpose Data Memory Rev. 2.10 36 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section, however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of "00H" and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks according to BP register. Direct Addressing can only be used with Bank 0, all other Banks must be addressed indirectly using MP1 and IAR1. Note that for the HT68F20 and HT68F30 devices, bit 7 of the Memory Pointers is not required to address the full memory space. When bit 7 of the Memory Pointers for HT68F20 and HT68F30 devices is read, a value of "1" will be returned. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Rev. 2.10 37 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Indirect Addressing Program Example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp0,a ; setup memory pointer with first RAM address loop: clr IAR0 ; clear the data at address defined by MP0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above, no reference is made to specific RAM addresses. Bank Pointer – BP Depending upon which device is used, the Program and Data Memory are divided into several banks. Selecting the required Program and Data Memory area is achieved using the Bank Pointer. Bit 5 of the Bank Pointer is used to select Program Memory Bank 0 or 1, while bits 0~2 are used to select Data Memory Banks 0~4. The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within any bank. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from banks other than Bank 0 must be implemented using Indirect addressing. As both the Program Memory and Data Memory share the same Bank Pointer Register, care must be taken during programming. Device Bit 7 6 5 4 3 2 1 0 HT68F20 HT68F40 — — — — — — — DMBP0 HT68F30 HT68F50 — — — — — — DMBP1 DMBP0 HT68F60 — — PMBP0 — — DMBP2 DMBP1 DMBP0 BP Registers List Rev. 2.10 38 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM BP Register • HT68F20/HT68F40 Bit 7 6 5 4 3 2 1 0 Name — — — — — — — DMBP0 R/W — — — — — — — R/W POR — — — — — — — 0 Bit 7~1 Unimplemented, read as “0” Bit 0DMBP0: Select Data Memory Banks 0: Bank 0 1: Bank 1 • HT68F30/HT68F50 Bit 7 6 5 4 3 2 1 0 Name — — — — — — DMBP1 DMBP0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0 DMBP1, DMBP0: Select Data Memory Banks 00: Bank 0 01: Bank 1 10: Bank 2 11: Undefined • HT68F60 Bit 7 6 5 4 3 2 1 0 Name — — PMBP0 — — DMBP2 DMBP1 DMBP0 R/W — — R/W — — R/W R/W R/W POR — — 0 — — 0 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5PMBP0: Select Program Memory Banks 0: Bank 0, Program Memory Address is from 0000H~1FFFH 1: Bank 1, Program Memory Address is from 2000H~2FFFH Bit 4~3 Unimplemented, read as “0” Bit 2~0DMBP2~DMBP0: Select Data Memory Banks 000: Bank 0 001: Bank 1 010: Bank 2 011: Bank 3 100: Bank 4 101~111: Undefined Rev. 2.10 39 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the "INC" or "DEC" instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Rev. 2.10 40 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the "CLR WDT" instruction. PDF is set by executing the "HALT" instruction. • TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Rev. 2.10 41 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM STATUS Register Bit 7 6 5 4 3 2 1 0 Name — — TO PDF OV Z AC C R/W — — R R R/W R/W R/W R/W POR — — 0 0 × × × × “×” unknown Bit 7~6 Unimplemented, read as “0” Bit 5TO: Watchdog Time-Out flag 0: After power up or executing the "CLR WDT" or "HALT" instruction 1: A watchdog time-out occurred Bit 4PDF: Power down flag 0: After power up or executing the "CLR WDT" instruction 1: By executing the "HALT" instruction Bit 3OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa Bit 2Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1AC: Auxiliary flag 0: No auxiliary carry 1: An operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0C: Carry flag 0: No carry-out 1: An operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction. Rev. 2.10 42 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM EEPROM Data Memory The device contains an area of internal EEPROM Data Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of re-programmable memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. EEPROM Data Memory Structure The EEPROM Data Memory capacity varies from 32×8 to 256×8 bits, according to the device selected. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. Read and Write operations to the EEPROM are carried out in single byte operations using an address and data register in Bank 0 and a single control register in Bank 1. Device Capacity Address 32×8 00H~1FH HT68F30 64×8 00H~3FH HT68F40 128×8 00H~7FH HT68F50/HT68F60 256×8 00H~FFH HT68F20 EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory. These are the address register, EEA, the data register, EED and a single control register, EEC. As both the EEA and EED registers are located in Bank 0, they can be directly accessed in the same was as any other Special Function Register. The EEC register however, being located in Bank1, cannot be directly addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register, IAR1. Because the EEC control register is located at address 40H in Bank 1, the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer register, BP, set to the value, 01H, before any operations on the EEC register are executed. Rev. 2.10 43 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM EEPROM Register List • HT68F20 Name Bit 7 6 5 4 3 2 1 0 D0 EEA — — — D4 D3 D2 D1 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC — — — — WREN WR RDEN RD 7 6 5 4 3 2 1 0 D0 • HT68F30 Name Bit EEA — — D5 D4 D3 D2 D1 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC — — — — WREN WR RDEN RD 7 6 5 4 3 2 1 0 D0 • HT68F40 Name Bit EEA — D6 D5 D4 D3 D2 D1 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC — — — — WREN WR RDEN RD 7 6 5 4 3 2 1 0 D0 • HT68F50/HT68F60 Name Rev. 2.10 Bit EEA D7 D6 D5 D4 D3 D2 D1 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC — — — — WREN WR RDEN RD 44 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM EEA Register • HT68F20 Bit 7 6 5 4 3 2 1 0 Name — — — D4 D3 D2 D1 D0 R/W — — — R/W R/W R/W R/W R/W POR — — — × × × × × “×” unknown Bit 7~5 Unimplemented, read as “0” Bit 4~0 Data EEPROM address Data EEPROM address bit 4~bit 0 • HT68F30 Bit 7 6 5 4 3 2 1 0 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — × × × × × × “×” unknown Bit 7~6 Unimplemented, read as “0” Bit 5~0 Data EEPROM address Data EEPROM address bit 5~bit 0 • HT68F40 Bit 7 6 5 4 3 2 1 0 Name — D6 D5 D4 D3 D2 D1 D0 R/W — R/W R/W R/W R/W R/W R/W R/W POR — × × × × × × × “×” unknown Bit 7 Unimplemented, read as “0” Bit 6~0 Data EEPROM address Data EEPROM address bit 6~bit 0 • HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR × × × × × × × × “×” unknown Bit 7~0 Rev. 2.10 Data EEPROM address Data EEPROM address bit 7~bit 0 45 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM EEC Register Bit 7 6 5 4 3 2 1 0 Name — — — — WREN WR RDEN RD R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3WREN: Data EEPROM Write Enable 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2WR: EEPROM Write Control 0: Write cycle has finished 1: Activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high. Bit 1RDEN: Data EEPROM Read Enable 0: Disable 1: Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations. Bit 0RD: EEPROM Read Control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high. Note: The WREN, WR, RDEN and RD can not be set to "1" at the same time in one instruction. TheWRand RD can not be set to "1" at the same time. Rev. 2.10 46 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Writing Data to the EEPROM To write data to the EEPROM, the write enable bit, WREN, in the EEC register must first be set high to enable the write function. The EEPROM address of the data to be written must then be placed in the EEA register and the data placed in the EED register. If the WR bit in the EEC register is now set high, an internal write cycle will then be initiated. Setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered-on theWrite Enable bit in the control register will be cleared preventing any write operations. Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this adds a further measure of protection against spurious write operations. During normal program operation, ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write or read interrupt is generated when an EEPROM write or read cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. However as the EEPROM is contained within a Multi-function Interrupt, the associated Multi-function interrupt enable bit must also be set. When an EEPROM write cycle ends, the DEF request flag and its associated Multi-function interrupt request flag will both be set. If the global, EEPROM and Multi-function interrupts are enabled and the stack is not full, a jump to the associated Multi-function Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag will be automatically reset, the EEPROM interrupt flag must be manually reset by the application program. More details can be obtained in the Interrupt section. Rev. 2.10 47 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1 where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. Programming Examples Reading data from the EEPROM – polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A SET IAR1.1 SET IAR1.0 BACK: SZ IAR1.0 JMP BACK CLR IAR1 CLR BP MOV A, EEDATA MOV READ_DATA, A ; user defined address ; setup memory pointer MP1 ; MP1 points to EEC register ; setup Bank Pointer ; set RDEN bit, enable read operations ; start Read Cycle - set RD bit ; check for read cycle end ; disable EEPROM read/write ; move read data to register Writing Data to the EEPROM – polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, EEPROM_DATA MOV EED, A MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A CLR EMI SET IAR1.3 SET IAR1.2 SET EMI BACK: SZ IAR1.2 JMP BACK CLR IAR1 CLR BP Rev. 2.10 ; user defined address ; user defined data ; setup memory pointer MP1 ; MP1 points to EEC register ; setup Bank Pointer ; set WREN bit, enable write operations ; start Write Cycle - set WR bit ; check for write cycle end ; disable EEPROM read/write 48 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Oscillator Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for theWatchdog Timer and Time Base Interrupts. External oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. All oscillator options are selected through the configuration options. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/ power ratio, a feature especially important in power sensitive portable applications. Type External Crystal Name Freq. Pins HXT 400kHz~20MHz OSC1/OSC2 OSC1 External RC ERC 8MHz Internal High Speed RC HIRC 4, 8 or 12MHz — LXT 32.768kHz XT1/XT2 LIRC 32kHz — External Low Speed Crystal Internal Low Speed RC Oscillator Types System Clock Configurations There are five methods of generating the system clock, three high speed oscillators and two low speed oscillators. The high speed oscillators are the external crystal/ceramic oscillator, external RC network oscillator and the internal 4MHz, 8MHz or 12MHz RC oscillator. The two low speed oscillators are the internal 32kHz RC oscillator and the external 32.768kHz crystal oscillator. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK bit and CKS2~CKS0 bits in the SMOD register and as the system clock can be dynamically selected. The actual source clock used for each of the high speed and low speed oscillators is chosen via configuration options. The frequency of the slow speed or high speed system clock is also determined using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection for either the high or low speed oscillator. Rev. 2.10 49 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM System Clock Configurations Rev. 2.10 50 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM External Crystal/Ceramic Oscillator – HXT The External Crystal/Ceramic System Oscillator is one of the high frequency oscillator choices, which is selected via configuration option. For most crystal oscillator configurations, the simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. However, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer's specification. For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure thatthe crystal and any associated resistors andcapacitors along with interconnectinglines are all located as close to the MCUas possible. Crystal/Resonator Oscillator – HXT Crystal Oscillator C1 and C2 Values Crystal Frequency C1 C2 12MHz 0pF 0pF 8 MHz 0pF 0pF 4 MHz 0pF 0pF 1 MHz 100pF 100pF Note: C1 and C2 values are for guidance only. Crystal Recommended Capacitor Values Rev. 2.10 51 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM External RC Oscillator – ERC Using the ERC oscillator only requires that a resistor, with a value between 56kΩ and 2.4MΩ, is connected between OSC1 and VDD, and a capacitor is connected between OSC1 and ground, providing a low cost oscillator configuration. It is only the external resistor that determines the oscillation frequency; the external capacitor has no influence over the frequency and is connected for stability purposes only. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a resistance/frequency reference point, it can be noted that with an external 120kΩ resistor connected and with a 5V voltage power supply and temperature of 25˚C degrees, the oscillator will have a frequency of 8MHz within a tolerance of 2%. Here only the OSC1 pin is used, which is shared with I/O pin PB1, leaving pin PB2 free for use as a normal I/O pin. For oscillator stability and to minimise the effects of noise and crosstalk, it is important to locate the capacitor and resistoras close to the MCU as possible. External RC Oscillator – ERC Internal RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has three fixed frequencies of either 4MHz, 8MHz or 12MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of either 3V or 5V and at a temperature of 25˚C degrees, the fixed oscillation frequency of 4MHz, 8MHz or 12MHz will have a tolerance within 2%. Note that if this internal system clock option is selected, as it requires no external pins for its operation, I/O pins PB1 and PB2 are free for use as normal I/O pins. Rev. 2.10 52 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM External 32.768kHz Crystal Oscillator – LXT The External 32.768kHz Crystal System Oscillator is one of the low frequency oscillator choices, which is selected via configuration option. This clock source has a fixed frequency of 32.768kHz and requires a 32.768kHz crystal to be connected between pins XT1 and XT2. The external resistor and capacitor components connected to the 32.768kHz crystal are necessary to provide oscillation. For applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. During power-up there is a time delay associated with the LXT oscillator waiting for it to start-up. When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the SLEEP or IDLE Mode. To do this, another clock, independent of the system clock, must be provided. However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer's specification. The external parallel feedback resistor, RP, is required. Some configuration options determine if the XT1/XT2 pins are used for the LXT oscillator or as I/O pins. • If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/O pins. • If the LXT oscillator is used for any clock source, the 32.768kHz crystal should be connected to the XT1/XT2 pins. For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure thatthe crystal and any associated resistors andcapacitors along with interconnectinglines are all located as close to the MCUas possible. External LXT Oscillator LXT Oscillator C1 and C2 Values Crystal Frequency C1 C2 32.768kHz 10pF 10pF Note: 1. C1 and C2 values are for guidance only. 2. RP=5M~10MΩ is recommended. 32.768kHz Crystal Recommended Capacitor Values Rev. 2.10 53 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power Mode. The mode selection is executed using the LXTLP bit in the TBC register. LXTLP Bit LXT Mode 0 Quick Start 1 Low-power After power on the LXTLP bit will be automatically cleared to zero ensuring that the LXT oscillator is in the Quick Start operating mode. In the Quick Start Mode the LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has fully powered up it can be placed into the Low-power mode by setting the LXTLP bit high. The oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the LXT oscillator start-up. In power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the LXTLP bit high about 2 seconds after power-on. It should be noted that, no matter what condition the LXTLP bit is set to, the LXT oscillator will always function normally, the only difference is that it will take more time to start up if in the Low-power mode. Internal 32kHz Oscillator – LIRC The Internal 32kHz System Oscillator is one of the low frequency oscillator choices, which is selected via configuration option. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of 25˚C degrees, the fixed oscillation frequency of 32kHz will have a tolerance within 10%. Supplementary Oscillators The low speed oscillators, in addition to providing a system clock source are also used to provide a clock source to two other device functions. These are the Watchdog Timer and the Time Base Interrupts. Rev. 2.10 54 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The device has many different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock options using configuration options and register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency, fH, or low frequency, fL, source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from either an HXT, ERC or HIRC oscillator, selected via a configuration option. The low speed system clock source can be sourced from internal clock fL. If fL is selected then it can be sourced by either the LXT or LIRC oscillators, selected via a configuration option. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. There are two additional internal clocks for the peripheral circuits, the substitute clock, fSUB, and the Time Base clock, fTBC. Each of these internal clocks are sourced by either the LXT or LIRC oscillators, selected via configuration options. The fSUB clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. Together with fSYS/4 it is also used as one of the clock sources for the Watchdog timer. The fTBC clock is used as a source for the Time Base interrupt functions and for the TMs. Rev. 2.10 55 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM System Clock Configurations Note: When the system clock source fSYS is switched to fL from fH, the high speed oscillation will stop to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use. Rev. 2.10 56 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0, SLEEP1, IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power. Operation Mode Description CPU fSYS fSUB fS fTBC NORMAL Mode On fH~fH/64 On On On SLOW Mode On fL On On On IDLE0 Mode Off Off On On/Off On IDLE1 Mode Off On On On On SLEEP0 Mode Off Off Off Off Off SLEEP1 Mode Off Off On On Off • NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. This mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the HXT, ERC or HIRC oscillators. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. • SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from one of the low speed oscillators, either the LXT or the LIRC. Running the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW Mode, the fH is off. • SLEEP0 Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP0 mode the CPU will be stopped, and the fSUB and fS clocks will be stopped too, and the Watchdog Timer function is disabled. In this mode, the LVDEN is must set to "0". If the LVDEN is set to "1", it won't enter the SLEEP0 Mode. • SLEEP1 Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP1 mode the CPU will be stopped. However the fSUB and fS clocks will continue to operate if the LVDEN is "1" or the Watchdog Timer function is enabled and if its clock source is chosen via configuration option to come from the fSUB. Rev. 2.10 57 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • IDLE0 Mode The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the WDTC register is low. In the IDLE0 Mode the system oscillator will be inhibited from driving the CPU but some peripheral functions will remain operational such as the Watchdog Timer, TMs and SIM. In the IDLE0 Mode, the system oscillator will be stopped. In the IDLE0 Mode the Watchdog Timer clock, fS, will either be on or off depending upon the fS clock source. If the source is fSYS/4 then the fS clock will be off, and if the source comes from fSUB then fS will be on. • IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the WDTC register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational such as the Watchdog Timer, TMs and SIM. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. In the IDLE1 Mode the Watchdog Timer clock, fS, will be on. If the source is fSYS/4 then the fS clock will be on, and if the source comes from fSUB then fS will be on. Control Register A single register, SMOD, is used for overall control of the internal clocks within the device. SMOD Register Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 FSTEN LTO HTO IDLEN HLCLK R/W R/W R/W R/W R/W R R R/W R/W POR 0 0 0 0 0 0 1 1 Bit 7~5CKS2~CKS0: The system clock selection when HLCLK is "0" 000: fL (fLXT or fLIRC) 001: fL (fLXT or fLIRC) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which can be either the LXT or LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4 Rev. 2.10 FSTEN: Fast Wake-up Control (only for HXT) 0: Disable 1: Enable This is the Fast Wake-up Control bit which determines if the fSUB clock source is initially used after the device wakes up. When the bit is high, the fSUB clock source can be used as a temporary system clock to provide a faster wake up time as the fSUB clock is available. 58 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Bit 3LTO: Low speed system oscillator ready flag 0: Not ready 1: Ready This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. The flag will be low when in the SLEEP0 Mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if the LXT oscillator is used and 1~2 clock cycles if the LIRC oscillator is used. Bit 2HTO: High speed system oscillator ready flag 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to "0" by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as "1" by the application program after device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if the HXT oscillator is used and after 15~16 clock cycles if the ERC or HIRC oscillator is used. Bit 1IDLEN: IDLE Mode control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. Bit 0HLCLK: system clock selection 0: fH/2~fH/64 or fL 1: fH This bit is used to select if the fH clock or the fH/2~fH/64 or fL clock is used as the system clock. When the bit is high the f H clock will be selected and if low the fH/2~fH/64 or fL clock will be selected. When system clock switches from the fH clock to the fL clock and the fH clock will be automatically switched off to conserve power. Rev. 2.10 59 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Fast Wake-up To minimise power consumption the device can enter the SLEEP or IDLE0 Mode, where the system clock source to the device will be stopped. However when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. To ensure the device is up and running as fast as possible a Fast Wake-up function is provided, which allows fSUB, namely either the LXT or LIRC oscillator, to act as a temporary clock to first drive the system until the original system oscillator has stabilised. As the clock source for the Fast Wake-up function is fSUB, the Fast Wake-up function is only available in the SLEEP1 and IDLE0 modes. When the device is woken up from the SLEEP0 mode, the Fast Wake-up function has no effect because the fSUB clock is stopped. The Fast Wake-up enable/disable function is controlled using the FSTEN bit in the SMOD register. If the HXT oscillator is selected as the NORMAL Mode system clock, and if the Fast Wake-up function is enabled, then it will take one to two tSUB clock cycles of the LIRC or LXT oscillator for the system to wake-up. The system will then initially run under the fSUB clock source until 1024 HXT clock cycles have elapsed, at which point the HTO flag will switch high and the system will switch over to operating from the HXT oscillator. If the ERC or HIRC oscillators or LIRC oscillator is used as the system oscillator then it will take 15~16 clock cycles of the ERC or HIRC or 1~2 cycles of the LIRC to wake up the system from the SLEEP or IDLE0 Mode. The Fast Wake-up bit, FSTEN will have no effect in these cases. System FSTEN Oscillator Bit 0 HXT 1 Wake-up Time (SLEEP0 Mode) Wake-up Time (SLEEP1 Mode) Wake-up Time (IDLE0 Mode) Wake-up Time (IDLE1 Mode) 1024 HXT cycles 1024 HXT cycles 1~2 HXT cycles 1024 HXT cycles 1~2 fSUB cycles (System runs with fSUB first for 1024 HXT cycles and then switches over to run with the HXT clock) 1~2 HXT cycles ERC × 15~16 ERC cycles 15~16 ERC cycles 1~2 ERC cycles HIRC × 15~16 HIRC cycles 15~16 HIRC cycles 1~2 HIRC cycles LIRC × 1~2 LIRC cycles 1~2 LIRC cycles 1~2 LIRC cycles LXT × 1024 LTX cycles 1024 LXT cycles 1~2 LXT cycles Wake-Up Times Note that if the Watchdog Timer is disabled, which means that the LXT and LIRC are all both off, then there will be no Fast Wake-up function available when the device wakes-up from the SLEEP0 Mode. Rev. 2.10 60 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Operating Mode Switching and Wake-up The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the WDTC register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, fH, to the clock source, fH/2~fH/64 or fL. If the clock is from the fL, the high speed clock source will stop running to conserve power. When this happens it must be noted that the fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the TMs and the SIM. The accompanying flowchart shows what happens when the device moves between the various operating modes. Rev. 2.10 61 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the HLCLK bit to "0" and set the CKS2~CKS0 bits to "000" or "001" in the SMOD register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LXT or the LIRC oscillators and therefore requires these oscillators to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register. Rev. 2.10 62 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM SLOW Mode to NORMAL Mode Switching In SLOW Mode the system uses either the LXT or LIRC low speed system oscillator. To switch back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to "1" or HLCLK bit is "0", but CKS2~CKS0 is set to "010", "011", "100", "101", "110" or "111". As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. The amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. Rev. 2.10 63 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Entering the SLEEP0 Mode There is only one way for the device to enter the SLEEP0 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the WDT and LVD both off. When this instruction is executed under the conditions described above, the following will occur: • The system clock, WDT clock and Time Base clock will be stopped and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and stopped no matter if the WDT clock source originates from the fSUB clock or from the system clock. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the SLEEP1 Mode There is only one way for the device to enter the SLEEP1 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the WDT or LVD on. When this instruction is executed under the conditions described above, the following will occur: • The system clock and Time Base clock will be stopped and the application program will stop at the "HALT" instruction, but the WDT or LVD will remain with the clock source coming from the fSUB clock. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT clock source is selected to come from the fSUB clock as the WDT is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the FSYSON bit in WDTC register equal to "0". When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the "HALT" instruction, but the Time Base clock and fSUB clock will be on. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT clock source is selected to come from the fSUB clock and the WDT is enabled. The WDT will stop if its clock source originates from the system clock. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Rev. 2.10 64 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the FSYSON bit in WDTC register equal to "1". When this instruction is executed under the with conditions described above, the following will occur: • The system clock and Time Base clock and fSUB clock will be on and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled regardless of the WDT clock source which originates from the fSUB clock or from the system clock. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the configuration options have enabled the LXT or LIRC oscillator. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. Rev. 2.10 65 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external reset • An external falling edge on Port A • A system interrupt • A WDT overflow If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the "HALT" instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HALT" instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Programming Considerations The HXT and LXT oscillators both use the same SST counter. For example, if the system is woken up from the SLEEP0 Mode and both the HXT and LXT oscillators need to start-up from an off state. The LXT oscillator uses the SST counter after HXT oscillator has finished its SST period. • If the device is woken up from the SLEEP0 Mode to the NORMAL Mode, the high speed system oscillator needs an SST period. The device will execute first instruction after HTO is "1". At this time, the LXT oscillator may not be stability if fSUB is from LXT oscillator. The same situation occurs in the power-on state. The LXT oscillator is not ready yet when the first instruction is executed. • If the device is woken up from the SLEEP1 Mode to NORMAL Mode, and the system clock source is from HXT oscillator and FSTEN is "1", the system clock can be switched to the LXT or LIRC oscillator after wake up. • There are peripheral functions, such as WDT, TMs and SIM, for which the fSYS is used. If the system clock source is switched from fH to fL, the clock source to the peripheral functions mentioned above will change accordingly. • The on/off condition of fSUB and fS depends upon whether the WDT is enabled or disabled as the WDT clock source is selected from fSUB. Rev. 2.10 66 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal clock, fS, which is in turn supplied by one of two sources selected by configuration option: fSUB or fSYS/4. The fSUB clock can be sourced from either the LXT or LIRC oscillators, again chosen via a configuration option. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 215 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. The LXT oscillator is supplied by an external 32.768kHz crystal. The other Watchdog Timer clock source option is the fSYS/4 clock. The Watchdog Timer clock source can originate from its own internal LIRC oscillator, the LXT oscillator or fSYS/4. It is divided by a value of 28 to 215, using the WS2~WS0 bits in the WDTC register to obtain the required Watchdog Timer time-out period. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable operation. This register together with several configuration options control the overall operation of the Watchdog Timer. WDTC Register Bit 7 6 5 4 3 2 1 0 Name FSYSON WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 1 1 1 0 1 0 WDTEN3 WDTEN2 WDTEN1 WDTEN0 Bit 7FSYSON: fSYS Control in IDLE Mode 0: Disable 1: Enable Rev. 2.10 Bit 6~4 WS2, WS1, WS0: WDT time-out period selection 000: 256/fS 001: 512/fS 010: 1024/fS 011: 2048/fS 100: 4096/fS 101: 8192/fS 110: 16384/fS 111: 32768/fS These three bits determine the division ratio of the Watchdog Timer source clock, which in turn determines the timeout period. Bit 3~0 WDTEN3, WDTEN2, WDTEN1, WDTEN0: WDT Software Control 1010: Disable Other: Enable 67 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unkown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. Some of the Watchdog Timer options, such as enable/disable, clock source selection and clear instruction type are selected using configuration options. In addition to a configuration option to enable/disable the Watchdog Timer, there are also four bits, WDTEN3~WDTEN0, in the WDTC register to offer an additional enable/disable control of the Watchdog Timer. To disable the Watchdog Timer, as well as the configuration option being set to disable, the WDTEN3~WDTEN0 bits must also be set to a specific value of "1010". Any other values for these bits will keep theWatchdog Timer enabled, irrespective of the configuration enable/disable setting. After power on these bits will have the value of 1010. If theWatchdog Timer is used it is recommended that they are set to a value of 0101 for maximum noise immunity. Note that if the Watchdog Timer has been disabled, then any instruction relating to its operation will result in no operation. WDT Configuration Option WDTEN3~WDTEN0 Bits WDT WDT Enable ×××× Enable WDT Disable Except 1010 Enable WDT Disable 1010 Disable Watchdog Timer Enable/Disable Control Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is an external hardware reset, which means a low level on the RES pin, the second is using the Watchdog Timer software clear instructions and the third is via a HALT instruction. There are two methods of using software instructions to clear theWatchdog Timer, one of which must be chosen by configuration option. The first option is to use the single "CLR WDT" instruction while the second is to use the two commands "CLR WDT1" and "CLR WDT2". For the first option, a simple execution of "CLR WDT" will clear the WDT while for the second option, both "CLR WDT1" and "CLR WDT2" must both be executed alternately to successfully clear the Watchdog Timer. Note that for this second option, if "CLR WDT1" is used to clear the Watchdog Timer, successive executions of this instruction will have no effect, only the execution of a "CLR WDT2" instruction will clear the Watchdog Timer. Similarly after the "CLR WDT2" instruction has been executed, only a successive "CLR WDT1" instruction can clear the Watchdog Timer. The maximum time out period is when the 215 division ratio is selected. As an example, with a 32.768kHz LXT oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 215 division ratio, and a minimum timeout of 7.8ms for the 28 division ration. If the fSYS/4 clock is used as the Watchdog Timer clock source, it should be noted that when the system enters the SLEEP or IDLE0 Mode, then the instruction clock is stopped and the Watchdog Timer may lose its protecting purposes. For systems that operate in noisy environments, using the fSUB clock source is strongly recommended. Rev. 2.10 68 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Watchdog Timer Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both internally and externally: • Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Note: tRSTD is power-on delay, typical time=100ms Power-On Reset Timing Chart Rev. 2.10 69 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • RES Pin As the reset pin is shared with PB0, the reset function must be selected using a configuration option. Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer. For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference. For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended. Note: "*" It is recommended that this component is added for added ESD protection "**" It is recommended that this component is added in environments where power line noise is significant External RES Circuit More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website. Pulling the RES Pin low using external hardware will also execute a device reset. In this case, as in the case of other resets, the Program Counter will reset to zero and program execution initiated from this point. Note: tRSTD is power-on delay, typical time=100ms RES Reset Timing Chart Rev. 2.10 70 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM When the reset pin is driven low by external hardware, most of the microcontroller pins will be forced into a high impedance condition. However special attention must be made to the PA5/C1X/SDO and PB2/OSC2 pins as these two pins will be forced into a logical output low condition when the reset pin is held low. For this reason it is recommended that these two pins are not connected to low impedance sources in the application circuit to eliminate the possibility of two low impedance sources being connected together. This situation only occurs when the reset pin is pulled low by external hardware and not during a power on or other reset type. Pin Name Pin Status PA5/C1X/SDO Output Low PB2/OSC2 Output Low Other pins High Impedance Reset Pin Forced Low – Pin Status • Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a configuration option. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for greater than the value tLVR specified in the A.C. characteristics. If the low voltage state does not exceed tLVR, the LVR will ignore it and will not perform a reset function. One of a range of specified voltage values for VLVR can be selected using configuration options. Low Voltage Reset Timing Chart • Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to "1". Note: tRSTD is power-on delay, typical time=100ms WDT Time-out Reset during Normal Operation Timing Chart • Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for tSST details. Note: The tSST is 15~16 clock cycles if the system clock source is provided by ERC or HIRC. The tSST is 1024 clock for HXT or LXT. The tSST is 1~2 clock for LIRC. WDT Time-out Reset during SLEEP or IDLE Timing Chart Rev. 2.10 71 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: T0 PDF RESET Conditions 0 0 Power-on reset u u RES or LVR reset during NORMAL or SLOW Mode operation 1 u WDT time-out reset during NORMAL or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation Note: "u" stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Condition After RESET Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset, WDT begins counting Timer/Event Counter Timer Counter will be turned off Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation for the larger package type. HT68F20 Reset (Power-on) RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (IDLE) MP0 1xxx xxxx 1xxx xxxx 1xxx xxxx 1 uuu uuuu MP1 1xxx xxxx 1xxx xxxx 1xxx xxxx 1 uuu uuuu BP - - - - - - -0 - - - - - - -0 - - - - - - -0 - - - - - - -u ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH - - xx xxxx - - uu uuuu - - uu uuuu - - uu uuuu TBHP - - - - - -xx - - - - - - uu - - - - - - uu - - - - - - uu STATUS - -00 xxxx - - uu uuuu - - 1 u uuuu - - 11 uuuu SMOD 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 uuuu uuuu LVDC - - 00 - 000 - - 00 - 000 - - 00 - 000 - - uu - uuu INTEG - - - - 0000 - - - - 0000 - - - - 0000 - - - - uuuu WDTC 0 111 1 0 1 0 0 111 1 0 1 0 0 111 1 0 1 0 uuuu uuuu TBC 0 0 11 0 111 0 0 11 0 111 0 0 11 0 111 uuuu uuuu INTC0 - 000 0000 - 000 0000 - 000 0000 - uuu uuuu INTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI0 - -00 - -00 - -00 - -00 - -00 - -00 - - uu - - uu MFI1 - -00 - -00 - -00 - -00 - -00 - -00 - - uu - - uu Register Rev. 2.10 72 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Reset (Power-on) RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (IDLE) MFI2 0000 0000 0000 0000 0000 0000 uuuu uuuu PAWU 0000 0000 0000 0000 0000 0000 uuuu uuuu PAPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU - - 00 0000 - - 00 0000 - - 00 0000 - - uu uuuu PB - - 11 1111 - - 11 1111 - - 11 1111 - - uu uuuu PBC - - 11 1111 - - 11 1111 - - 11 1111 - - uu uuuu PCPU - - - - 0000 - - - - 0000 - - - - 0000 - - - - uuuu PC - - - - 1111 - - - - 1111 - - - - 1111 - - - - uuuu PCC - - - - 1111 - - - - 1111 - - - - 1111 - - - - uuuu CP0C 1000 0 - -1 1000 0 - -1 1000 0 - -1 uuuu u - - u CP1C 1000 0 - -1 1000 0 - -1 1000 0 - -1 uuuu u - - u SIMC0 111 0 0 0 0 - 111 0 0 0 0 - 111 0 0 0 0 - uuuu uuu - SIMC1 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMA/SIMC2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu TM0AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0AH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu EEA - - - x xxxx - - - x xxxx - - - x xxxx - - - 0 0000 EED xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu EEC - - - - 0000 - - - - 0000 - - - - 0000 - - - - uuuu TMPC0 - - 01 - - - 1 - - 01 - - - 1 - - 01 - - - 1 - - uu - - - u TM1C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu TM1AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1AH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu SCOMC 0000 0000 0000 0000 0000 0000 uuuu uuuu Register Note: "u" stands for unchanged "x" stands for unknown "–" stands for unimplemented Rev. 2.10 73 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM HT68F30 Reset (Power-on) RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (IDLE) MP0 1xxx xxxx 1xxx xxxx 1xxx xxxx 1 uuu uuuu MP1 1xxx xxxx 1xxx xxxx 1xxx xxxx 1 uuu uuuu BP - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH - - xx xxxx - - uu uuuu - - uu uuuu - - uu uuuu TBHP - - - - - xxx - - - - - uuu - - - - - uuu - - - - - uuu STATUS - -00 xxxx - - uu uuuu - - 1 u uuuu - - 11 uuuu SMOD 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 uuuu uuuu LVDC - - 00 - 000 - - 00 - 000 - - 00 - 000 - - uu - uuu INTEG - - - - 0000 - - - - 0000 - - - - 0000 - - - - uuuu WDTC 0 111 1 0 1 0 0 111 1 0 1 0 0 111 1 0 1 0 uuuu uuuu TBC 0 0 11 0 111 0 0 11 0 111 0 0 11 0 111 uuuu uuuu INTC0 - 000 0000 - 000 0000 - 000 0000 - uuu uuuu INTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI0 - -00 - -00 - -00 - -00 - -00 - -00 - - uu - - uu MFI1 - 000 - 000 - 000 - 000 - 000 -000 - uuu - uuu MFI2 0000 0000 0000 0000 0000 0000 uuuu uuuu PAWU 0000 0000 0000 0000 0000 0000 uuuu uuuu PAPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU - - 00 0000 - - 00 0000 - - 00 0000 - - uu uuuu PB - - 11 1111 - - 11 1111 - - 11 1111 - - uu uuuu PBC - - 11 1111 - - 11 1111 - - 11 1111 - - uu uuuu PCPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC 1111 1111 1111 1111 1111 1111 uuuu uuuu CP0C 1000 0 - -1 1000 0 - -1 1000 0 - -1 uuuu u - - u CP1C 1000 0 - -1 1000 0 - -1 1000 0 - -1 uuuu u - - u SIMC0 111 0 0 0 0 - 111 0 0 0 0 - 111 0 0 0 0 - uuuu uuu - SIMC1 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMA/SIMC2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu TM0AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0AH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu EEA - - xx xxxx - - xx xxxx - - xx xxxx - - uu uuuu EED xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu EEC - - - - 0000 - - - - 0000 - - - - 0000 - - - - uuuu Register Rev. 2.10 74 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Reset (Power-on) RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (IDLE) TMPC0 1 - 01 - - 01 1 - 01 - - 01 1 - 01 - - 01 u - uu - - uu PRM0 - - - - - 000 - - - - - 000 - - - - - 000 - - - - - uuu TM1C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu TM1AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1AH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu TM1BL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1BH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu SCOMC 0000 0000 0000 0000 0000 0000 uuuu uuuu Register Note: "u" stands for unchanged "x" stands for unknown "–" stands for unimplemented Rev. 2.10 75 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM HT68F40 Reset (Power-on) RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (IDLE) MP0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu MP1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu BP - - - - - - -0 - - - - - - -0 - - - - - - -0 - - - - - - -u ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH - xxx xxxx - uuu uuuu - uuu uuuu - uuu uuuu TBHP - - - - xxxx - - - - uuuu - - - - uuuu - - - - uuuu STATUS - -00 xxxx - - uu uuuu - - 1 u uuuu - - 11 uuuu SMOD 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 uuuu uuuu LVDC - - 00 - 000 - - 00 - 000 - - 00 - 000 - - uu - uuu INTEG - - - - 0000 - - - - 0000 - - - - 0000 - - - - uuuu WDTC 0 111 1 0 1 0 0 111 1 0 1 0 0 111 1 0 1 0 uuuu uuuu TBC 0 0 11 0 111 0 0 11 0 111 0 0 11 0 111 uuuu uuuu INTC0 - 000 0000 - 000 0000 - 000 0000 - uuu uuuu INTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI0 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI1 - 000 - 000 - 000 - 000 - 000 - 000 - uuu - uuu MFI2 0000 0000 0000 0000 0000 0000 uuuu uuuu PAWU 0000 0000 0000 0000 0000 0000 uuuu uuuu PAPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC 1111 1111 1111 1111 1111 1111 uuuu uuuu PDPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PD 1111 1111 1111 1111 1111 1111 uuuu uuuu PDC 1111 1111 1111 1111 1111 1111 uuuu uuuu PEPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PE 1111 1111 1111 1111 1111 1111 uuuu uuuu PEC 1111 1111 1111 1111 1111 1111 uuuu uuuu PFPU - - - - - -00 - - - - - -00 - - - - - -00 - - - - - - uu PF - - - - - - 11 - - - - - - 11 - - - - - - 11 - - - - - - uu PFC - - - - - - 11 - - - - - - 11 - - - - - - 11 - - - - - - uu CP0C 1000 0 - -1 1000 0 - -1 1000 0 - -1 uuuu u - - u CP1C 1000 0 - -1 1000 0 - -1 1000 0 - -1 uuuu u - - u SIMC0 111 0 0 0 0 - 111 0 0 0 0 - 111 0 0 0 0 - uuuu uuu - SIMC1 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMA/SIMC2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C0 0000 0000 0000 0000 0000 0000 uuuu uuuu Register Rev. 2.10 76 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Reset (Power-on) RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (IDLE) TM0C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu TM0AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0AH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu EEA - xxx xxxx - xxx xxxx - xxx xxxx - uuu uuuu EED xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu EEC - - - - 0000 - - - - 0000 - - - - 0000 - - - - uuuu TMPC0 1001 - - 01 1001 - - 01 1001 - - 01 uuuu - - uu TMPC1 - - - - - - 01 - - - - - - 01 - - - - - - 01 - - - - - - uu PRM0 - 0- 0 0000 - 0- 0 0000 - 0- 0 0000 - u - u uuuu PRM1 000 - 0000 000 - 0000 000 - 0000 uuu - uuuu PRM2 - -00 0000 - -00 0000 - -00 0000 - - uu uuuu TM1C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu TM1AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1AH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu TM1BL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1BH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu TM2C0 0000 0 - - - 0000 0 - - - 0000 0 - - - uuuu u - - - TM2C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2DH 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2AH 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2RP 0000 0000 0000 0000 0000 0000 uuuu uuuu SCOMC 0000 0000 0000 0000 0000 0000 uuuu uuuu Register Note: "u" stands for unchanged "x" stands for unknown "–" stands for unimplemented Rev. 2.10 77 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM HT68F50 Reset (Power-on) RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (IDLE) MP0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu MP1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu BP - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBHP - - -x xxxx - - - u uuuu - - - u uuuu - - - u uuuu STATUS - -00 xxxx - - uu uuuu - - 1 u uuuu - - 11 uuuu SMOD 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 uuuu uuuu LVDC - - 00 - 000 - - 00 - 000 - - 00 - 000 - - uu - uuu INTEG - - - - 0000 - - - - 0000 - - - - 0000 - - - - uuuu WDTC 0 111 1 0 1 0 0 111 1 0 1 0 0 111 1 0 1 0 uuuu uuuu TBC 0 0 11 0 111 0 0 11 0 111 0 0 11 0 111 uuuu uuuu INTC0 - 000 0000 - 000 0000 - 000 0000 - uuu uuuu INTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI0 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI1 - 000 - 000 - 000 - 000 - 000 - 000 - uuu - uuu MFI2 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI3 - -00 - -00 - -00 - -00 - -00 - -00 - - uu - - uu PAWU 0000 0000 0000 0000 0000 0000 uuuu uuuu PAPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC 1111 1111 1111 1111 1111 1111 uuuu uuuu PDPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PD 1111 1111 1111 1111 1111 1111 uuuu uuuu PDC 1111 1111 1111 1111 1111 1111 uuuu uuuu PEPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PE 1111 1111 1111 1111 1111 1111 uuuu uuuu PEC 1111 1111 1111 1111 1111 1111 uuuu uuuu PFPU - - - - - -00 - - - - - -00 - - - - - -00 - - - - - - uu PF - - - - - - 11 - - - - - - 11 - - - - - - 11 - - - - - - uu PFC - - - - - - 11 - - - - - - 11 - - - - - - 11 - - - - - - uu CP0C 1000 0 - -1 1000 0 - -1 1000 0 - -1 uuuu u - - u CP1C 1000 0 - -1 1000 0 - -1 1000 0 - -1 uuuu u - - u SIMC0 111 0 0 0 0 - 111 0 0 0 0 - 111 0 0 0 0 - uuuu uuu - SIMC1 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMA/SIMC2 0000 0000 0000 0000 0000 0000 uuuu uuuu Register Rev. 2.10 78 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Reset (Power-on) RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (IDLE) TM0C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu TM0AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0AH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu EEA xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu EED xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu EEC - - - - 0000 - - - - 0000 - - - - 0000 - - - - uuuu TMPC0 1001 - - 01 1001 - - 01 1001 - - 01 uuuu - - uu TMPC1 - - 01 - - 01 - - 01 - - 01 - - 01 - - 01 - - uu - - uu PRM0 - 0- 0 0000 - 0- 0 0000 - 0- 0 0000 - u - u uuuu PRM1 000 - 0000 000 - 0000 000 - 0000 uuu - uuuu PRM2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu TM1AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1AH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu TM1BL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1BH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu TM2C0 0000 0- - - 0000 0- - - 0000 0- - - uuuu u - - - TM2C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2DH 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2AH 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2RP 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3DH - - - - - -00 - - - - - -00 - - - - - -00 - - - - - - uu TM3AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3AH - - - - - -00 - - - - - -00 - - - - - -00 - - - - - - uu SCOMC 0000 0000 0000 0000 0000 0000 uuuu uuuu Register Note: "u" stands for unchanged "x" stands for unknown "–" stands for unimplemented Rev. 2.10 79 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM HT68F60 Reset (Power-on) RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (IDLE) MP0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu MP1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu BP - - 0- - 000 - - 0- - 000 - - 0- - 000 - - u - - uuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBHP - - xx xxxx - - uu uuuu - - uu uuuu - - uu uuuu STATUS - -00 xxxx - - uu uuuu - - 1 u uuuu - - 11 uuuu SMOD 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 uuuu uuuu LVDC - - 00 - 000 - - 00 - 000 - - 00 - 000 - - uu - uuu INTEG 0000 0000 0000 0000 0000 0000 uuuu uuuu WDTC 0 111 1 0 1 0 0 111 1 0 1 0 0 111 1 0 1 0 uuuu uuuu TBC 0 0 11 0 111 0 0 11 0 111 0 0 11 0 111 uuuu uuuu INTC0 - 000 0000 - 000 0000 - 000 0000 - uuu uuuu INTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC3 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI0 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI1 - 000 - 000 - 000 - 000 - 000 - 000 - uuu - uuu MFI2 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI3 - -00 - -00 - -00 - -00 - -00 - -00 - - uu - - uu PAWU 0000 0000 0000 0000 0000 0000 uuuu uuuu PAPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC 1111 1111 1111 1111 1111 1111 uuuu uuuu PDPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PD 1111 1111 1111 1111 1111 1111 uuuu uuuu PDC 1111 1111 1111 1111 1111 1111 uuuu uuuu PEPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PE 1111 1111 1111 1111 1111 1111 uuuu uuuu PEC 1111 1111 1111 1111 1111 1111 uuuu uuuu PFPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PF 1111 1111 1111 1111 1111 1111 uuuu uuuu PFC 1111 1111 1111 1111 1111 1111 uuuu uuuu PGPU - - - - - -00 - - - - - -00 - - - - - -00 - - - - - - uu PG - - - - - - 11 - - - - - - 11 - - - - - - 11 - - - - - - uu PGC - - - - - - 11 - - - - - - 11 - - - - - - 11 - - - - - - uu CP0C 1000 0 - -1 1000 0 - -1 1000 0 - -1 uuuu u - - u CP1C 1000 0 - -1 1000 0 - -1 1000 0 - -1 uuuu u - - u Register Rev. 2.10 80 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Reset (Power-on) RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (IDLE) SIMC0 111 0 0 0 0 - 111 0 0 0 0 - 111 0 0 0 0 - uuuu uuu - SIMC1 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMA/SIMC2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu TM0AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0AH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu EEA xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu EED xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu EEC - - - - 0000 - - - - 0000 - - - - 0000 - - - - uuuu TMPC0 1001 - - 01 1001 - - 01 1001 - - 01 uuuu - - uu TMPC1 - - 01 - - 01 - - 01 - - 01 - - 01 - - 01 - - uu - - uu PRM0 0000 0000 0000 0000 0000 0000 uuuu uuuu PRM1 0000 0000 0000 0000 0000 0000 uuuu uuuu PRM2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu TM1AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1AH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu TM1BL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1BH - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - uu TM2C0 0000 0- - - 0000 0- - - 0000 0- - - uuuu u - - - TM2C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2DH 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2AH 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2RP 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3DH - - - - - -00 - - - - - -00 - - - - - -00 - - - - - - uu TM3AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3AH - - - - - -00 - - - - - -00 - - - - - -00 - - - - - - uu SCOMC 0000 0000 0000 0000 0000 0000 uuuu uuuu Register Note: "u" stands for unchanged "x" stands for unknown "–" stands for unimplemented Rev. 2.10 81 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port names PA~PG. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction "MOV A, [m]", where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. I/O Register List • HT68F20 Bit Register Name 7 6 5 4 3 2 1 0 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PBPU — — D5 D4 D3 D2 D1 D0 PB — — D5 D4 D3 D2 D1 D0 PBC — — D5 D4 D3 D2 D1 D0 PCPU — — — — D3 D2 D1 D0 PC — — — — D3 D2 D1 D0 PCC — — — — D3 D2 D1 D0 Register Name 7 6 5 4 3 2 1 0 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PBPU — — D5 D4 D3 D2 D1 D0 PB — — D5 D4 D3 D2 D1 D0 • HT68F30 Rev. 2.10 Bit PBC — — D5 D4 D3 D2 D1 D0 PCPU D7 D6 D5 D4 D3 D2 D1 D0 PC D7 D6 D5 D4 D3 D2 D1 D0 PCC D7 D6 D5 D4 D3 D2 D1 D0 82 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • HT68F40/HT68F50 Bit Register Name 7 6 5 4 3 2 1 0 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PBPU D7 D6 D5 D4 D3 D2 D1 D0 PB D7 D6 D5 D4 D3 D2 D1 D0 PBC D7 D6 D5 D4 D3 D2 D1 D0 PCPU D7 D6 D5 D4 D3 D2 D1 D0 PC D7 D6 D5 D4 D3 D2 D1 D0 PCC D7 D6 D5 D4 D3 D2 D1 D0 PDPU D7 D6 D5 D4 D3 D2 D1 D0 PD D7 D6 D5 D4 D3 D2 D1 D0 PDC D7 D6 D5 D4 D3 D2 D1 D0 PEPU D7 D6 D5 D4 D3 D2 D1 D0 PE D7 D6 D5 D4 D3 D2 D1 D0 PEC D7 D6 D5 D4 D3 D2 D1 D0 PFPU — — — — — — D1 D0 PF — — — — — — D1 D0 PFC — — — — — — D1 D0 • HT68F60 Rev. 2.10 Bit Register Name 7 6 5 4 3 2 1 0 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PBPU D7 D6 D5 D4 D3 D2 D1 D0 PB D7 D6 D5 D4 D3 D2 D1 D0 PBC D7 D6 D5 D4 D3 D2 D1 D0 PCPU D7 D6 D5 D4 D3 D2 D1 D0 PC D7 D6 D5 D4 D3 D2 D1 D0 PCC D7 D6 D5 D4 D3 D2 D1 D0 PDPU D7 D6 D5 D4 D3 D2 D1 D0 PD D7 D6 D5 D4 D3 D2 D1 D0 PDC D7 D6 D5 D4 D3 D2 D1 D0 PEPU D7 D6 D5 D4 D3 D2 D1 D0 PE D7 D6 D5 D4 D3 D2 D1 D0 PEC D7 D6 D5 D4 D3 D2 D1 D0 PFPU D7 D6 D5 D4 D3 D2 D1 D0 PF D7 D6 D5 D4 D3 D2 D1 D0 PFC D7 D6 D5 D4 D3 D2 D1 D0 PGPU — — — — — — D1 D0 PG — — — — — — D1 D0 PGC — — — — — — D1 D0 83 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU~PGPU, and are implemented using weak PMOS transistors. PAPU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 PBPU Register • HT68F40/HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 PCPU Register • HT68F30/HT68F40/HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 5 4 3 2 1 0 PDPU Register • HT68F40/HT68F50/HT68F60 Bit 7 6 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 5 4 3 2 1 0 PEPU Register • HT68F40/HT68F50/HT68F60 Bit Rev. 2.10 7 6 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 84 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM PFPU Register • HT68F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 3 2 1 0 Bit 7~0 I/O Port bit 7~bit 0 Pull-High Control 0: Disable 1: Enable PBPU Register • HT68F20/HT68F30 Bit 7 6 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 3 2 1 0 Bit 7~6 5 4 Unimplemented, read as “0” Bit 5~0PBPU: Port B bit 5~bit 0 Pull-High Control 0: Disable 1: Enable PCPU Register • HT68F20 Bit 7 6 5 4 Name — — — — D3 D2 D1 D0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 1 0 Bit 7~4 Unimplemented, read as “0” Bit 3~0 PCPU: Port C bit 3~bit 0 Pull-High Control 0: Disable 1: Enable PFPU Register • HT68F40/HT68F50 Bit 7 6 5 4 3 2 Name — — — — — — D1 D0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0 PFPU: Port F bit 1~bit 0 Pull-High Control 0: Disable 1: Enable Rev. 2.10 85 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM PGPU Register • HT68F60 Bit 7 6 5 4 3 2 1 0 Name — — — — — — D1 D0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0PGPU: Port G bit 1~bit 0 Pull-High Control 0: Disable 1: Enable Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. PAWU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 PAWU: Port A bit 7~bit 0 Wake-up Control 0: Disable 1: Enable I/O Port Control Registers Each I/O port has its own control register known as PAC~PGC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a "1". This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a "0", the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. PAC Register Bit Rev. 2.10 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 86 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM PBC Register • HT68F40/HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 4 3 2 1 0 PCC Register • HT68F30/HT68F40/HT68F50/HT68F60 Bit 7 6 5 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 PDC Register • HT68F40/HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 5 4 3 2 1 0 PEC Register • HT68F40/HT68F50/HT68F60 Bit 7 6 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 PFC Register • HT68F60 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~0 Rev. 2.10 I/O Port bit 7~bit 0 Input/Output Control 0: Output 1: Input 87 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM PBC Register • HT68F20/HT68F30 Bit 7 6 5 4 3 2 1 0 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5~0PBC: Port B bit 5~bit 0 Input/Output Control 0: Output 1: Input PCC Register • HT68F20 Bit 7 6 5 4 3 2 1 0 Name — — — — D3 D2 D1 D0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3~0PCC: Port C bit 3~bit 0 Input/Output Control 0: Output 1: Input PFC Register • HT68F40/HT68F50 Bit 7 6 5 4 3 2 1 0 Name — — — — — — D1 D0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0PFC: Port F bit 1~bit 0 Input/Output Control 0: Output 1: Input PGC Register • HT68F60 Bit 7 6 5 4 3 2 1 0 Name — — — — — — D1 D0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0 PGC: Port G bit 1~bit 0 Input/Output Control 0: Output 1: Input Rev. 2.10 88 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Pin-remapping Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. The way in which the pin function of each pin is selected is different for each function and a priority order is established where more than one pin function is selected simultaneously. Additionally there are a series of PRM0, PRM1 and PRM2 registers to establish certain pin functions. Pin-remapping Registers The limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. However by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. Some devices include PRM0, PRM1 or PRM2 registers which can select the functions of certain pins. Pin-remapping Register List • HT68F30 Bit Register Name 7 6 5 4 3 2 1 0 PRM0 — — — — — PCPRM SIMPS0 PCKPS • HT68F40 Bit Register Name 7 6 5 4 3 2 1 0 PRM0 — C1XPS0 — C0XPS0 PDPRM SIMPS1 SIMPS0 PCKPS PRM1 TCK2PS TCK1PS TCK0PS — PRM2 — — TP21PS INT1PS1 INT1PS0 INT0PS1 INT0PS0 TP20PS TP1B2PS TP1APS TP01PS TP00PS • HT68F50 Bit Register Name 7 6 5 4 3 2 1 0 PRM0 — C1XPS0 — C0XPS0 PDPRM SIMPS1 SIMPS0 PCKPS PRM1 TCK2PS TCK1PS TCK0PS — PRM2 TP31PS TP30PS TP21PS INT1PS1 INT1PS0 INT0PS1 INT0PS0 TP20PS TP1B2PS TP1APS TP01PS TP00PS • HT68F60 Rev. 2.10 Bit Register Name 7 6 5 4 3 2 1 0 PRM0 C1XPS1 C1XPS0 C0XPS1 C0XPS0 PDPRM SIMPS1 SIMPS0 PCKPS PRM1 TCK2PS TCK1PS TCK0PS INT2PS1 INT1PS1 INT1PS0 INT0PS1 INT0PS0 PRM2 TP31PS TP30PS TP21PS TP20PS TP1B2PS TP1APS 89 TP01PS TP00PS July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM PRM0 Register • HT68F30 Bit 7 6 5 4 3 2 1 0 Name — — — — — PCPRM SIMPS0 PCKPS R/W — — — — — R/W R/W R/W POR — — — — — 0 0 0 Bit 7~3 Unimplemented, read as “0” Bit 2PCPRM: PC1~PC0 pin-shared function Pin Remapping Control 0: No change 1: TP1B_0 on PC0 change to PA6, TP1B_1 on PC1 change to PA7 if SIMPS0=1 Bit 1SIMPS0: SIM Pin Remapping Control 0: SDO on PA5; SDI/SDA on PA6; SCK/SCL on PA7; SCS on PB5 1: SDO on PC1; SDI/SDA on PC0; SCK/SCL on PC7; SCS on PC6 Bit 0PCKPS: PCK and PINT Pin Remapping Control 0: PCK on PC2; PINT on PC3 1: PCK on PC5; PINT on PC4 PRM0 Register • HT68F40/HT68F50 Bit 7 6 5 4 3 2 1 0 Name — C1XPS0 — C0XPS0 PDPRM SIMPS1 SIMPS0 PCKPS R/W — R/W — R/W R/W R/W R/W R/W POR — 0 — 0 0 0 0 0 Bit 7 Unimplemented, read as “0” Bit 6C1XPS0: C1X Pin Remapping Control 0: C1X on PA5 1: C1X on PF1 Bit 5 Unimplemented, read as “0” Bit 4C0XPS0: C0X Pin Remapping Control 0: C0X on PA0 1: C0X on PF0 Bit 3PDPRM: PD3~PD0 pin-shared function Pin Remapping Control 0: No change 1: TCK2 on PD0 change to PB6, TP2_0 on PD1 change to PB7, TCK0 on PD2 change to PD6, TCK1 on PD3 change to PD7 if SIMPS1, SIMPS0=01 Bit 2~1 SIMPS1, SIMPS0: SIM Pin Remapping Control 00: SDO on PA5; SDI/SDA on PA6; SCK/SCL on PA7; SCS on PB5 01: SDO on PD3; SDI/SDA on PD2; SCK/SCL on PD1; SCS on PD0 10: SDO on PB6; SDI/SDA on PB7; SCK/SCL on PD6; SCS on PD7 11: Undefined Bit 0PCKPS: PCK and PINT Pin Remapping Control 0: PCK on PC2; PINT on PC3 1: PCK on PC5; PINT on PC4 Rev. 2.10 90 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM PRM0 Register • HT68F60 Bit 7 6 5 4 3 2 1 0 Name C1XPS1 C1XPS0 C0XPS1 C0XPS0 PDPRM SIMPS1 SIMPS0 PCKPS R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 C1XPS1, C1XPS0: C1X Pin Remapping Control 00: C1X on PA5 01: C1X on PF1 10: C1X on PG1 11: Undefined Bit 5~4 C0XPS1, C0XPS0: C0X Pin Remapping Control 00: C0X on PA0 01: C0X on PF0 10: C0X on PG0 11: Undefined Bit 3PDPRM: PD3~PD0 pin-shared function Pin Remapping Control 0: No change 1: TCK2 on PD0 change to PB6, TP2_0 on PD1 change to PB7, TCK0 on PD2 change to PD6, TCK1 on PD3 change to PD7 if SIMPS1, SIMPS0=01 or 11 Bit 2~1 SIMPS1, SIMPS0: SIM Pin Remapping Control 00: SDO on PA5; SDI/SDA on PA6; SCK/SCL on PA7; SCS on PB5 01: SDO on PD3; SDI/SDA on PD2; SCK/SCL on PD1; SCS on PD0 10: SDO on PB6; SDI/SDA on PB7; SCK/SCL on PD6; SCS on PD7 11: SDO on PD1; SDI/SDA on PD2; SCK/SCL on PD3; SCS on PD0 Bit 0 PCKPS: PCK and PINT Pin Remapping Control 0: PCK on PC2; PINT on PC3 1: PCK on PC5; PINT on PC4 Rev. 2.10 91 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM PRM1 Register • HT68F40/HT68F50 Bit 7 6 5 4 Name TCK2PS TCK1PS TCK0PS — 3 2 1 0 R/W R/W R/W R/W — R/W R/W R/W R/W POR 0 0 0 — 0 0 0 0 INT1PS1 INT1PS0 INT0PS1 INT0PS0 Bit 7TCK2PS: TCK2 Pin Remapping Control 0: TCK2 on PC2 1: TCK2 on PD0 Bit 6TCK1PS: TCK1 Pin Remapping Control 0: TCK1 on PA4 1: TCK1 on PD3 Bit 5TCK0PS: TCK0 Pin Remapping Control 0: TCK0 on PA2 1: TCK0 on PD2 Rev. 2.10 Bit 4 Unimplemented, read as “0” Bit 3~2 INT1PS1, INT1PS0: INT1 Pin Remapping Control 00: INT1 on PA4 01: INT1 on PC5 10: Undefined 11: INT1 on PE7 Bit 1~0 INT0PS1, INT0PS0: INT0 Pin Remapping Control 00: INT0 on PA3 01: INT0 on PC4 10: Undefined 11: INT0 on PE6 92 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM PRM1 Register • HT68F60 Bit 7 6 5 4 Name TCK2PS TCK1PS TCK0PS INT2PS 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 INT1PS1 INT1PS0 INT0PS1 INT0PS0 Bit 7TCK2PS: TCK2 Pin Remapping Control 0: TCK2 on PC2 1: TCK2 on PD0 Bit 6TCK1PS: TCK1 Pin Remapping Control 0: TCK1 on PA4 1: TCK1 on PD3 Bit 5TCK0PS: TCK0 Pin Remapping Control 0: TCK0 on PA2 1: TCK0 on PD2 Bit 4INT2PS: INT2 Pin Remapping Control 0: INT2 on PC4 1: INT2 on PE2 Rev. 2.10 Bit 3~2 INT1PS1, INT1PS0: INT1 Pin Remapping Control 00: INT1 on PA4 01: INT1 on PC5 10: INT1 on PE1 11: INT1 on PE7 Bit 1~0 INT0PS1, INT0PS0: INT0 Pin Remapping Control 00: INT0 on PA3 01: INT0 on PC4 10: INT0 on PE0 11: INT0 on PE6 93 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM PRM2 Register • HT68F40 Bit 7 6 5 Name — — TP21PS R/W — — R/W R/W R/W POR — — 0 0 0 Bit 7~6 4 3 2 1 0 TP01PS TP00PS R/W R/W R/W 0 0 0 TP20PS TP1B2PS TP1APS Unimplemented, read as “0” Bit 5TP21PS: TP2_1 Pin Remapping Control 0: TP2_1 on PC4 1: TP2_1 on PD4 Bit 4TP20PS: TP2_0 Pin Remapping Control 0: TP2_0 on PC3 1: TP2_0 on PD1 Bit 3TP1B2PS: TP1B_2 Pin Remapping Control 0: TP1B_2 on PC5 1: TP1B_2 on PE4 Bit 2TP1APS: TP1A Pin Remapping Control 0: TP1A on PA1 1: TP1A on PC7 Bit 1TP01PS: TP0_1 Pin Remapping Control 0: TP0_1 on PC5 1: TP0_1 on PD5 Bit 0TP00PS: TP0_0 Pin Remapping Control 0: TP0_0 on PA0 1: TP0_0 on PC6 Rev. 2.10 94 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM PRM2 Register • HT68F50/HT68F60 Bit 7 6 5 Name TP31PS TP30PS TP21PS 4 3 R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 2 1 0 TP01PS TP00PS R/W R/W R/W 0 0 0 TP20PS TP1B2PS TP1APS Bit 7TP31PS: TP3_1 Pin Remapping Control 0: TP3_1 on PD0 1: TP3_1 on PE3 Bit 6TP30PS: TP3_0 Pin Remapping Control 0: TP3_0 on PD3 1: TP3_0 on PE5 Bit 5TP21PS: TP2_1 Pin Remapping Control 0: TP2_1 on PC4 1: TP2_1 on PD4 Bit 4TP20PS: TP2_0 Pin Remapping Control 0: TP2_0 on PC3 1: TP2_0 on PD1 Bit 3TP1B2PS: TP1B_2 Pin Remapping Control 0: TP1B_2 on PC5 1: TP1B_2 on PE4 Bit 2TP1APS: TP1A Pin Remapping Control 0: TP1A on PA1 1: TP1A on PC7 Bit 1TP01PS: TP0_1 Pin Remapping Control 0: TP0_1 on PC5 1: TP0_1 on PD5 Bit 0TP00PS: TP0_0 Pin Remapping Control 0: TP0_0 on PA0 1: TP0_0 on PC6 Rev. 2.10 95 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers, PAC~PGC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA~PG, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "SET [m].i" and "CLR [m].i" instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port Ahas the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Generic Input/Output Structure Rev. 2.10 96 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions each device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has either two or three individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Compact, Standard and Enhanced TM sections. Introduction The devices contain from two to four TMs depending upon which device is selected with each TM having a reference name of TM0, TM1, TM2 and TM3. Each individual TM can be categorised as a certain type, namely Compact Type TM, Standard Type TM or Enhanced Type TM. Although similar in nature, the different TM types vary in their feature complexity. The common features to all of the Compact, Standard and Enhanced TMs will be described in this section, the detailed operation regarding each of the TM types will be described in separate sections. The main features and differences between the three types of TMs are summarised in the accompanying table. CTM STM ETM Timer/Counter Function √ √ √ I/P Capture — √ √ Compare Match Output √ √ √ PWM Channels 1 1 2 Single Pulse Output PWM Alignment PWM Adjustment Period & Duty — 1 1 Edge Edge Edge & Centre Duty or Period Duty or Period Duty or Period TM Function Summary Each device in the series contains a specific number of either Compact Type, Standard Type and Enhanced Type TM units which are shown in the table together with their individual reference name, TM0~TM3. Device TM0 TM1 TM2 TM3 HT68F20 10-bit CTM 10-bit STM — — HT68F30 10-bit CTM 10-bit ETM — — HT68F40 10-bit CTM 10-bit ETM 16-bit STM — HT68F50 10-bit CTM 10-bit ETM 16-bit STM 10-bit CTM HT68F60 10-bit CTM 10-bit ETM 16-bit STM 10-bit CTM TM Name/Type Reference Rev. 2.10 97 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM TM Operation The three different types of TM offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the TnCK2~TnCK0 bits in the TM control registers. The clock source can be a ratio of either the system clock fSYS or the internal high clock fH, the fTBC clock source or the external TCKn pin. Note that setting these bits to the value 101 will select a reserved clock input, in effect disconnecting the TM clock source. The TCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. TM Interrupts The Compact and Standard type TMs each have two internal interrupts, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. As the Enhanced type TM has three internal comparators and comparator A or comparator B or comparator P compare match functions, it consequently has three internal interrupts. When a TM interrupt is generated it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has one TM input pin, with the label TCKn. The TM input pin, is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in the TMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the TnCK2~TnCK0 bits. The TM input pin can be chosen to have either a rising or falling active edge. The TMs each have one or more output pins with the label TPn. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external TPn output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other function, the TM output function must first be setup using registers. Asingle bit in one of the registers determines if its associated pin is to be used as an external TM output pin or if it is to have another function. The number of output pins for each TM type and device is different, the details are provided in the accompanying table. All TM output pin names have a "_n" suffix. Pin names that include a "_1" or "_2" suffix indicate that they are from a TM with multiple output pins. This allows the TM to generate a complimentary output pair, selected using the I/O register data bits. Rev. 2.10 98 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Device CTM STM ETM Registers HT68F20 TP0_0 TP1_0, TP1_1 — TMPC0 HT68F30 TP0_0, TP0_1 — HT68F40 TP0_0, TP0_1 TP2_0, TP2_1 TP1A, TP1B_0, TP1B_1, TP1B_2 TMPC0, TMPC1 HT68F50 TP0_0, TP0_1 TP3_0, TP3_1 TP2_0, TP2_1 TP1A, TP1B_0, TP1B_1, TP1B_2 TMPC0, TMPC1 HT68F60 TP0_0, TP0_1 TP3_0, TP3_1 TP2_0,TP2_1 TP1A, TP1B_0, TP1B_1, TP1B_2 TMPC0, TMPC1 TP1A, TP1B_0, TP1B_1 TMPC0 TM Output Pins TM Input/Output Pin Control Registers Selecting to have a TM input/output or whether to retain its other shared function, is implemented using one or two registers, with a single bit in each register corresponding to a TM input/output pin. Setting the bit high will setup the corresponding pin as a TM input/output, if reset to zero the pin will retain its original other function. Rev. 2.10 Registers Device TMPC0 Bit 7 6 5 4 3 2 1 0 HT68F20 — — T1CP1 T1CP0 — — — T0CP0 TMPC0 HT68F30 T1ACP0 — T1BCP1 T1BCP0 — — T0CP1 T0CP0 TMPC0 HT68F40 HT68F50 HT68F60 T1ACP0 T1BCP2 T1BCP1 T1BCP0 — — T0CP1 T0CP0 TMPC1 HT68F40 — — — — — — T2CP1 T2CP0 TMPC1 HT68F50 HT68F60 — — T3CP1 T3CP0 — — T2CP1 T2CP0 99 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM HT68F20 TM Function Pin Control Block Diagram Note: The I/O register data bits shown are used for TM output inversion control. In the Capture Input Mode, the TM pin control register must never enable more than one TM input. Rev. 2.10 100 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 0 P A 0 O u tp u t F u n c tio n P A 0 /T P 0 _ 0 1 0 1 T 0 C P 0 P A 0 0 P C 5 O u tp u t F u n c tio n O u tp u t 1 0 1 P C 5 /T P 0 _ 1 T 0 C P 1 P C 5 T C K In p u t P A 2 /T C K 0 0 P A 1 O u tp u t F u n c tio n 1 C C R A O u tp u t P A 1 /T P 1 A T 1 A C P 0 1 C C R A C a p tu re In p u t 0 T 1 A C P 0 P C 0 O u tp u t F u n c tio n 0 P C 0 /T P 1 B _ 0 1 0 1 T 1 B C P 0 P C 0 P C 1 O u tp u t F u n c tio n C C R B O u tp u t 0 1 0 1 P C 1 /T P 1 B _ 1 T 1 B C P 1 P C 1 1 C C R B C a p tu re In p u t 0 T 1 B C P 1 1 0 T 1 B C P 0 T C K In p u t P A 4 /T C K 1 HT68F30 TM Function Pin Control Block Diagram Note: The I/O register data bits shown are used for TM output inversion control. In the Capture Input Mode, the TM pin control register must never enable more than one TM input. Rev. 2.10 101 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 0 P A 0 O u tp u t F u n c tio n P A 0 /T P 0 _ 0 1 0 1 T 0 C P 0 P A 0 0 P C 5 O u tp u t F u n c tio n O u tp u t 1 0 1 P C 5 /T P 0 _ 1 T 0 C P 1 P C 5 T C K In p u t P A 2 /T C K 0 P C 3 O u tp u t F u n c tio n 0 P C 3 /T P 2 _ 0 1 0 1 T 2 C P 0 P C 3 P C 4 O u tp u t F u n c tio n O u tp u t 0 1 0 1 P C 4 /T P 2 _ 1 T 2 C P 1 P C 4 1 C a p tu re In p u t 0 T 2 C P 1 1 0 T 2 C P 0 T C K In p u t P C 2 /T C K 2 HT68F40 TM0 & TM2 Function Pin Control Block Diagram Note: The I/O register data bits shown are used for TM output inversion control. In the Capture Input Mode, the TM pin control register must never enable more than one TM input. Rev. 2.10 102 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 0 P A 1 O u tp u t F u n c tio n 1 C C R A O u tp u t P A 1 /T P 1 A T 1 A C P 0 1 C C R A C a p tu re In p u t 0 T 1 A C P 0 P C 0 O u tp u t F u n c tio n 0 P C 0 /T P 1 B _ 0 1 0 1 T 1 B C P 0 P C 0 P C 1 O u tp u t F u n c tio n 0 P C 1 /T P 1 B _ 1 1 0 1 T 1 B C P 1 P C 1 P C 5 O u tp u t F u n c tio n C C R B O u tp u t 0 1 0 1 P C 5 /T P 1 B _ 2 T 1 B C P 2 P C 5 1 C C R B C a p tu re In p u t 0 T 1 B C P 2 1 0 T 1 B C P 1 1 0 T 1 B C P 0 T C K In p u t P A 4 /T C K 1 HT68F40 TM1 Function Pin Control Block Diagram Note: The I/O register data bits shown are used for TM output inversion control. In the Capture Input Mode, the TM pin control register must never enable more than one TM input. Rev. 2.10 103 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 0 P A 0 O u tp u t F u n c tio n P A 0 /T P 0 _ 0 1 0 1 T 0 C P 0 P A 0 0 P C 5 O u tp u t F u n c tio n P C 5 /T P 0 _ 1 1 O u tp u t 0 1 T 0 C P 1 P C 5 T C K In p u t P A 2 /T C K 0 P C 3 O u tp u t F u n c tio n 0 P C 3 /T P 2 _ 0 1 0 1 T 2 C P 0 P C 3 P C 4 O u tp u t F u n c tio n O u tp u t 0 P C 4 /T P 2 _ 1 1 0 1 T 2 C P 1 P C 4 1 C a p tu re In p u t 0 T 2 C P 1 1 0 T 2 C P 0 T C K In p u t P C 2 /T C K 2 0 P D 3 O u tp u t F u n c tio n P D 3 /T P 3 _ 0 1 0 1 T 3 C P 0 P D 3 0 P D 0 O u tp u t F u n c tio n O u tp u t 0 1 1 P D 0 /T P 3 _ 1 T 3 C P 1 P D 0 T C K In p u t P C 4 /T C K 3 HT68F50 and HT68F60 TM0, TM2, TM3 Function Pin Control Block Diagram Note: The I/O register data bits shown are used for TM output inversion control. In the Capture Input Mode, the TM pin control register must never enable more than one TM input. Rev. 2.10 104 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 0 P A 1 O u tp u t F u n c tio n 1 C C R A O u tp u t P A 1 /T P 1 A T 1 A C P 0 1 C C R A C a p tu re In p u t 0 T 1 A C P 0 P C 0 O u tp u t F u n c tio n 0 P C 0 /T P 1 B _ 0 1 0 1 T 1 B C P 0 P C 0 P C 1 O u tp u t F u n c tio n 0 P C 1 /T P 1 B _ 1 1 0 1 T 1 B C P 1 P C 1 P C 5 O u tp u t F u n c tio n C C R B O u tp u t 0 1 0 1 P C 5 /T P 1 B _ 2 T 1 B C P 2 P C 5 1 C C R B C a p tu re In p u t 0 T 1 B C P 2 1 0 T 1 B C P 1 1 0 T 1 B C P 0 T C K In p u t P A 4 /T C K 1 HT68F50 and HT68F60 TM1 Function Pin Control Block Diagram Note: The I/O register data bits shown are used for TM output inversion control. In the Capture Input Mode, the TM pin control register must never enable more than one TM input. Rev. 2.10 105 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM TMPC0 Register • HT68F20 Bit 7 6 5 4 3 2 1 0 Name — — T1CP1 T1CP0 — — — T0CP0 R/W — — R/W R/W — — — R/W POR — — 0 1 — — — 1 Bit 7~6 Unimplemented, read as “0” Bit 5T1CP1: TP1_1 pin Control 0: Disable 1: Enable Bit 4T1CP0: TP1_0 pin Control 0: Disable 1: Enable Bit 3~1 Unimplemented, read as “0” Bit 0T0CP0: TP0_0 pin Control 0: Disable 1: Enable • HT68F30 Bit 7 6 5 4 3 2 1 0 Name T1ACP0 — T1BCP1 T1BCP0 — — T0CP1 T0CP0 R/W R/W — R/W R/W — — R/W R/W POR 1 — 0 1 — — 0 1 Bit 7T1ACP0: TP1A pin Control 0: Disable 1: Enable Bit 6 Unimplemented, read as “0” Bit 5T1BCP1: TP1B_1 pin Control 0: Disable 1: Enable Bit 4T1BCP0: TP1B_0 pin Control 0: Disable 1: Enable Bit 3~2 Unimplemented, read as “0” Bit 1T0CP1: TP0_1 pin Control 0: Disable 1: Enable Bit 0T0CP0: TP0_0 pin Control 0: Disable 1: Enable Rev. 2.10 106 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • HT68F40/HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name T1ACP0 T1BCP2 T1BCP1 T1BCP0 — — T0CP1 T0CP0 R/W R/W R/W R/W R/W — — R/W R/W POR 1 0 0 1 — — 0 1 Bit 7T1ACP0: TP1A pin Control 0: Disable 1: Enable Bit 6T1BCP2: TP1B_2 pin Control 0: Disable 1: Enable Bit 5T1BCP1: TP1B_1 pin Control 0: Disable 1: Enable Bit 4T1BCP0: TP1B_0 pin Control 0: Disable 1: Enable Bit 3~2 Unimplemented, read as “0” Bit 1T0CP1: TP0_1 pin Control 0: Disable 1: Enable Bit 0T0CP0: TP0_0 pin Control 0: Disable 1: Enable Rev. 2.10 107 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM TMPC1 Register • HT68F40 Bit 7 6 5 4 3 2 1 0 Name — — — — — — T2CP1 T2CP0 R/W — — — — — — R/W R/W POR — — — — — — 0 1 Bit 7~2 Unimplemented, read as “0” Bit 1T2CP1: TP2_1 pin Control 0: Disable 1: Enable Bit 0T2CP0: TP2_0 pin Control 0: Disable 1: Enable • HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name — — T3CP1 T3CP0 — — T2CP1 T2CP0 R/W — — R/W R/W — — R/W R/W POR — — 0 1 — — 0 1 Bit 7~6 Unimplemented, read as “0” Bit 5T3CP1: TP3_1 pin Control 0: Disable 1: Enable Bit 4T3CP0: TP3_0 pin Control 0: Disable 1: Enable Bit 3~2 Unimplemented, read as “0” Bit 1T2CP1: TP2_1 pin Control 0: Disable 1: Enable Bit 0T2CP0: TP2_0 pin Control 0: Disable 1: Enable Rev. 2.10 108 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Programming Considerations The TM Counter Registers and the Capture/Compare CCRAand CCRB registers, being either 10-bit or 16-bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. TM Counter Register (Read only) TMxDL TMxDH 8-bit Buffer TMxAL TMxAH TM CCRA Register (Read/Write) TMxBL TMxBH TM CCRB Register (Read/Write) Data Bus As the CCRA and CCRB registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way described above, it is recommended to use the "MOV" instruction to access the CCRA and CCRB low byte registers, named TMxAL and TMxBL, using the following access procedures. Accessing the CCRA or CCRB low byte registers without following these access procedures will result in unpredictable values. The following steps show the read and write procedures: • Writing Data to CCRB or CCRA ♦♦ Step 1. Write data to Low Byte TMxAL or TMxBL ––note that here data is only written to the 8-bit buffer. ♦♦ Step 2. Write data to High Byte TMxAH or TMxBH ––here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. • Reading Data from the Counter Registers and CCRB or CCRA Rev. 2.10 ♦♦ Step 1. Read data from the High Byte TMxDH, TMxAH or TMxBH ––here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte TMxDL, TMxAL or TMxBL ––this step reads data from the 8-bit buffer. 109 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Compact Type TM Although the simplest form of the three TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive one or two external output pins. These two external output pins can be the same signal or the inverse signal. CTM Name TM No. TM Input Pin TM Output Pin HT68F20 10-bit CTM 0 TCK0 TP0_0 HT68F30 10-bit CTM 0 TCK0 TP0_0, TP0_1 HT68F40 10-bit CTM 0 TCK0 TP0_0, TP0_1 HT68F50 10-bit CTM 0, 3 TCK0, TCK3 TP0_0, TP0_1; TP3_0, TP3_1 HT68F60 10-bit CTM 0, 3 TCK0, TCK3 TP0_0, TP0_1; TP3_0, TP3_1 Compact TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is three bits wide whose value is compared with the highest three bits in the counter while the CCRA is the ten bits and therefore compares with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Compact Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Compact Type TM Block Diagram Rev. 2.10 110 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Compact Type TM Register Description Overall operation of the Compact TM is controlled using six registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMnC0 TnPAU TnCK2 TnCK1 TnCK0 TnON TnRP2 TnRP1 TnRP0 TMnC1 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR TMnDL D7 D6 D5 D4 D3 D2 D1 D0 TMnDH — — — — — — D9 D8 TMnAL D7 D6 D5 D4 D3 D2 D1 D0 TMnAH — — — — — — D9 D8 Compact TM Register List (n=0 or 3) TMnDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0TMnDL: TMn Counter Low Byte Register bit 7~bit 0 TMn 10-bit Counter bit 7~bit 0 TMnDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0TMnDH: TMn Counter High Byte Register bit 1~bit 0 TMn 10-bit Counter bit 9~bit 8 TMnAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0TMnAL: TMn CCRA Low Byte Register bit 7~bit 0 TMn 10-bit CCRA bit 7~bit 0 TMnAH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0TMnAH: TMn CCRA High Byte Register bit 1~bit 0 TMn 10-bit CCRA bit 9~bit 8 Rev. 2.10 111 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM TMnC0 Register Bit 7 6 5 4 3 2 1 0 Name TnPAU TnCK2 TnCK1 TnCK0 TnON TnRP2 TnRP1 TnRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7TnPAU: TMn Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4TnCK2~TnCK0: Select TM0 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Underined 110: TCKn rising edge clock 111: TCKn falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. Bit 3TnON: TMn Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the TnOC bit, when the TnON bit changes from low to high. Bit 2~0TnRP2~TnRP0: TMn CCRP 3-bit register, compared with the TM0 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TMn clocks 001: 128 TMn clocks 010: 256 TMn clocks 011: 384 TMn clocks 100: 512 TMn clocks 101: 640 TMn clocks 110: 768 TMn clocks 111: 896 TMn clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter's highest three bits. The result of this comparison can be selected to clear the internal counter if the TnCCLR bit is set to zero. Setting the TnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. Rev. 2.10 112 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM TMnC1 Register Bit 7 6 5 4 3 2 1 0 Name TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6TnM1~TnM0: Select TMn Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the TnM1 and TnM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4TnIO1~TnIO0: Select TPn_0, TPn_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Undefined Timer/counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the TnOC bit in the TMnC1 register. Note that the output level requested by the TnIO1 and TnIO0 bits must be different from the initial value setup using the TnOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the TnON bit from low to high. In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the TnIO1 and TnIO0 bits only after the TMn has been switched off. Unpredictable PWM outputs will occur if the TnIO1 and TnIO0 bits are changed when the TM is running. Rev. 2.10 113 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Bit 3TnOC: TPn_0, TPn_1 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2TnPOL: TPn_0, TPn_1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TPn_0 or TPn_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1TnDPX: TMn PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0TnCCLR: Select TMn Counter clear condition 0: TMn Comparatror P match 1: TMn Comparatror A match This bit is used to select the method which clears the counter. Remember that the Compact TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the TnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The TnCCLR bit is not used in the PWM Mode. Rev. 2.10 114 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Compact Type TM Operating Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Match Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to "00" respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for the Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the TnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the TM output pin will change state. The TM output pin condition however only changes state when an TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place. Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. Rev. 2.10 115 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Co�nter Va��e Co�nter overf�ow CCRP=0 0x3FF TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 Co�nter c�eared b� CCRP va��e CCRP > 0 Co�nter Restart Res�me CCRP Pa�se CCRA Stop Time TnON TnPAU TnPOL CCRP Int. F�ag TnPF CCRA Int. F�ag TnAF TM O/P Pin O�tp�t pin set to initia� Leve� Low if TnOC=0 O�tp�t not affected b� TnAF f�ag. Remains High �nti� reset b� TnON bit O�tp�t Togg�e with TnAF f�ag Here TnIO [1:0] = 11 Togg�e O�tp�t se�ect Note TnIO [1:0] = 10 Active High O�tp�t se�ect O�tp�t Inverts when TnPOL is high O�tp�t Pin Reset to Initia� va��e O�tp�t contro��ed b� other pin-shared f�nction Compare Match Output Mode -- TnCCLR=0 Note: 1. With TnCCLR=0, a Comparator P match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge Rev. 2.10 116 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Co�nter Va��e TnCCLR = 1; TnM [1:0] = 00 CCRA = 0 Co�nter overf�ow CCRA > 0 Co�nter c�eared b� CCRA va��e 0x3FF CCRA=0 Res�me CCRA Pa�se Stop Co�nter Restart CCRP Time TnON TnPAU TnPOL No TnAF f�ag generated on CCRA overf�ow CCRA Int. F�ag TnAF CCRP Int. F�ag TnPF TnPF not generated O�tp�t does not change TM O/P Pin O�tp�t pin set to initia� Leve� Low if TnOC=0 O�tp�t not affected b� TnAF f�ag. Remains High �nti� reset b� TnON bit O�tp�t Togg�e with TnAF f�ag Here TnIO [1:0] = 11 Togg�e O�tp�t se�ect Note TnIO [1:0] = 10 Active High O�tp�t se�ect O�tp�t Inverts when TnPOL is high O�tp�t Pin Reset to Initia� va��e O�tp�t contro��ed b� other pin-shared f�nction Compare Match Output Mode -- TnCCLR=1 Note: 1. With TnCCLR=1, a Comparator A match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge 4. The TnPF flag is not generated when TnCCLR=1 Rev. 2.10 117 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform. CTM, PWM Mode, Edge-aligned Mode, TnDPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA If fSYS=16MHz, TM clock source is fSYS/4, CCRP=100b and CCRA=128, The CTM PWM output frequency=(fSYS/4)/512=fSYS/2048=7.8125kHz, duty=128/512=25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. CTM, PWM Mode, Edge-aligned Mode, TnDPX=1 CCRP 001b 010b 011b 100b 128 256 384 512 Period Duty 101b 110b 111b 000b 768 896 1024 CCRA 640 The PWM output period is determined by the CCRAregister value together with the TM clock while the PWM duty cycle is defined by the CCRP register value. Rev. 2.10 118 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Co�nter Va��e TnDPX = 0; TnM [1:0] = 10 Co�nter c�eared b� CCRP Co�nter Reset when TnON ret�rns high CCRP Pa�se Res�me CCRA Co�nter Stop if TnON bit �ow Time TnON TnPAU TnPOL CCRA Int. F�ag TnAF CCRP Int. F�ag TnPF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM D�t� C�c�e set b� CCRA PWM Period set b� CCRP PWM res�mes operation O�tp�t contro��ed b� O�tp�t Inverts other pin-shared f�nction when TnPOL = 1 PWM Mode -- TnDPX=0 Note: 1. Here TnDPX=0 -- Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when TnIO [1:0]=00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 2.10 119 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Co�nter Va��e TnDPX = 1; TnM [1:0] = 10 Co�nter c�eared b� CCRA Co�nter Reset when TnON ret�rns high CCRA Pa�se Res�me CCRP Co�nter Stop if TnON bit �ow Time TnON TnPAU TnPOL CCRP Int. F�ag TnPF CCRA Int. F�ag TnAF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM D�t� C�c�e set b� CCRP PWM Period set b� CCRA PWM res�mes operation O�tp�t contro��ed b� O�tp�t Inverts other pin-shared f�nction when TnPOL = 1 PWM Mode -- TnDPX=1 Note: 1. Here TnDPX=1 -- Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when TnIO [1:0]=00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 2.10 120 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Standard Type TM – STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with an external input pin and can drive two external output pins. STM Name TM No. TM Input Pin TM Output Pin HT68F20 10-bit STM 1 TCK1 TP1_0, TP1_1 HT68F30 — — — — HT68F40 16-bit STM 2 TCK2 TP2_0, TP2_1 HT68F50 16-bit STM 2 TCK2 TP2_0, TP2_1 HT68F60 16-bit STM 2 TCK2 TP2_0, TP2_1 Standard Type TM Block Diagram Standard TM Operation There are two sizes of Standard TMs, one is 10-bit wide and the other is 16-bit wide. At the core is a 10 or 16-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP comparator is 3 or 8 bits wide whose value is compared the with highest 3 or 8 bits in the counter while the CCRA is the ten or sixteen bits and therefore compares all counter bits. The only way of changing the value of the 10 or 16-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Standard Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Rev. 2.10 121 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Standard Type TM Register Description Overall operation of the Standard TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10 or 16-bit value, while a read/write register pair exists to store the internal 10 or 16-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three or eight CCRP bits. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TM1C0 T1PAU T1CK2 T1CK1 T1CK0 T1ON T1RP2 T1RP1 T1RP0 TM1C1 T1M1 T1M0 T1IO1 T1IO0 T1OC T1POL T1DPX T1CCLR TM1DL D7 D6 D5 D4 D3 D2 D1 D0 TM1DH — — — — — — D9 D8 TM1AL D7 D6 D5 D4 D3 D2 D1 D0 TM1AH — — — — — — D9 D8 Bit 1 Bit 0 10-bit Standard TM Register List (for HT68F20) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TM2C0 T2PAU T2CK2 T2CK1 T2CK0 T2ON — — — TM2C1 T2M1 T2M0 T2IO1 T2IO0 T2OC T2POL T2DPX T2CCLR TM2DL D7 D6 D5 D4 D3 D2 D1 D0 TM2DH D15 D14 D13 D12 D11 D10 D9 D8 TM2AL D7 D6 D5 D4 D3 D2 D1 D0 TM2AH D15 D14 D13 D12 D11 D10 D9 D8 TM2RP D7 D6 D5 D4 D3 D2 D1 D0 16-bit Standard TM Register List (for HT68F40/HT68F50/HT68F60) Rev. 2.10 122 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 10-bit Standard TM Register List – HT68F20 • TM1C0 Register – 10-bit STM Bit 7 6 5 4 3 2 1 0 Name T1PAU T1CK2 T1CK1 T1CK0 T1ON T1RP2 T1RP1 T1RP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7T1PAU: TM1 Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4T1CK2~T1CK0: Select TM1 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Undefined 110: TCK1 rising edge clock 111: TCK1 falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. Bit 3T1ON: TM1 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T1OC bit, when the T1ON bit changes from low to high. Bit 2~0T1RP2~T1RP0: TM1 CCRP 3-bit register, compared with the TM1 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TM1 clocks 001: 128 TM1 clocks 010: 256 TM1 clocks 011: 384 TM1 clocks 100: 512 TM1 clocks 101: 640 TM1 clocks 110: 768 TM1 clocks 111: 896 TM1 clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter's highest three bits. The result of this comparison can be selected to clear the internal counter if the T1CCLR bit is set to zero. Setting the T1CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. Rev. 2.10 123 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • TM1C1 Register – 10-bit STM Bit 7 6 5 4 3 2 1 0 Name T1M1 T1M0 T1IO1 T1IO0 T1OC T1POL T1DPX T1CCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6T1M1~T1M0: Select TM1 Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T1M1 and T1M0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4T1IO1~T1IO0: Select TP1_0, TP1_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP1_0, TP1_1 01: Input capture at falling edge of TP1_0, TP1_1 10: Input capture at falling/rising edge of TP1_0, TP1_1 11: Input capture disabled Timer/counter Mode: Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the T1IO1 and T1IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T1OC bit in the TM1C1 register. Note that the output level requested by the T1IO1 and T1IO0 bits must be different from the initial value setup using the T1OC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T1ON bit from low to high. In the PWM Mode, the T1IO1 and T1IO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the T1IO1 and T1IO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the T1IO1 and T1IO0 bits are changed when the TM is running. Rev. 2.10 124 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Bit 3T1OC: TP1_0, TP1_1 Output control bit Compare Match Output Mode 0: initial low 1: initial high PWM Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2T1POL: TP1_0, TP1_1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP1_0 or TP1_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1T1DPX: TM1 PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0T1CCLR: Select TM1 Counter clear condition 0: TM1 Comparatror P match 1: TM1 Comparatror A match This bit is used to select the method which clears the counter. Remember that the Standard TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the T1CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T1CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode. Rev. 2.10 125 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • TM1DL Register – 10-bit STM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0TM1DL: TM1 Counter Low Byte Register bit 7~bit 0 TM1 10-bit Counter bit 7~bit 0 • TM1DH Register – 10-bit STM Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0TM1DH: TM1 Counter High Byte Register bit 1~bit 0 TM1 10-bit Counter bit 9~bit 8 • TM1AL Register – 10-bit STM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0TM1AL: TM1 CCRA Low Byte Register bit 7~bit 0 TM1 10-bit CCRA bit 7~bit 0 • TM1AH Register – 10-bit STM Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0TM1AH: TM1 CCRA High Byte Register bit 1~bit 0 TM1 10-bit CCRA bit 9~bit 8 Rev. 2.10 126 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 16-bit Standard TM Register List – HT68F40/HT68F50/HT68F60 • TM2C0 Register – 16-bit STM Bit 7 6 5 4 3 2 1 0 Name T2PAU T2CK2 T2CK1 T2CK0 T2ON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7T2PAU: TM2 Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 T2CK2, T2CK1, T2CK0: Select TM2 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Undefined 110: TCK2 rising edge clock 111: TCK2 falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. Bit 3T2ON: TM2 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T2OC bit, when the T2ON bit changes from low to high. Bit 2~0 Rev. 2.10 Unimplemented, read as “0” 127 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • TM2C1 Register – 16-bit STM Bit 7 6 5 4 3 2 1 0 Name T2M1 T2M0 T2IO1 T2IO0 T2OC T2POL T2DPX T2CCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6T2M1~T2M0: Select TM2 Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T2M1 and T2M0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4T2IO1~T2IO0: Select TP2_0, TP2_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP2_0, TP2_1 01: Input capture at falling edge of TP2_0, TP2_1 10: Input capture at falling/rising edge of TP2_0, TP2_1 11: Input capture disabled Timer/counter Mode: Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the T2IO1 and T2IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T2OC bit in the TM2C1 register. Note that the output level requested by the T2IO1 and T2IO0 bits must be different from the initial value setup using the T2OC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T2ON bit from low to high. In the PWM Mode, the T2IO1 and T2IO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the T2IO1 and T2IO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the T2IO1 and T2IO0 bits are changed when the TM is running. Rev. 2.10 128 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Bit 3T2OC: TP2_0, TP2_1 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2T2POL: TP2_0, TP2_1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP2_0 or TP2_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1T2DPX: TM2 PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0T2CCLR: Select TM2 Counter clear condition 0: TM2 Comparator P match 1: TM2 Comparator A match This bit is used to select the method which clears the counter. Remember that the Standard TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the T2CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T1CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode. Rev. 2.10 129 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • TM2DL Register – 16-bit STM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0TM2DL: TM2 Counter Low Byte Register bit 7~bit 0 TM2 16-bit Counter bit 7~bit 0 • TM2DH Register – 16-bit STM Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0TM2DH: TM2 Counter High Byte Register bit 7~bit 0 TM2 16-bit Counter bit 15~bit 8 • TM2AL Register – 16-bit STM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0TM2AL: TM2 CCRA Low Byte Register bit 7~bit 0 TM2 16-bit CCRA bit 7~bit 0 • TM2AH Register – 16-bit STM Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0TM2AH: TM2 CCRA High Byte Register bit 7~bit 0 TM2 16-bit CCRA bit 15~bit 8 • TM2RP Register – 16-bit STM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0TM2RP: TM2 CCRP Register bit 7~bit 0 TM2 CCRP 8-bit register, compared with the TM2 Counter bit 15~bit 8. Comparator P Match Period 0: 65536 TM2 clocks 1~255: 256×(1~255) TM2 clocks These eight bits are used to setup the value on the internal CCRP 8-bit register, which are then compared with the internal counter's highest eight bits. The result of this comparison can be selected to clear the internal counter if the T2CCLR bit is set to zero. Setting the T2CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. Clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value. Rev. 2.10 130 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Standard Type TM Operating Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to "0". As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when an TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place. Rev. 2.10 131 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Counter Value CCRP = 0 TnCCLR = 0; TnM[1:0] = 00 Counter overflow 0x3FF/ 0xFFFF CCRP > 0 Counter cleared by CCRP value CCRP > 0 CCRP Pause Resume CCRA Stop Counter Reset Time TnON bit TnPAU bit TnPOL bit CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin Output Pin set to Initial Level Low if TnOC = 0 Output Toggle with TnAF flag Now TnIO1, TnIO0 = 10 Active High Output Select Output not affected by TnAF flag. Remains High until reset by TnON bit Here TnIO1, TnIO0 = 11 Toggle Output Select Output inverts when TnPOL is high Output Pin Reset to initial value Output controlled by other pin-shared function Compare Match Output Mode -- TnCCLR=0 Note: 1. With TnCCLR=0, a Comparator P match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge Rev. 2.10 132 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM TnCCLR = 1; TnM[1:0] = 00 Counter Value CCRA = 0 Counter overflows CCRA > 0 Counter cleared by CCRA value 0x3FF/ 0xFFFF CCRA = 0 CCRA Pause Resume Stop CCRP Counter Reset Time TnON bit TnPAU bit TnPOL bit No TnAF flag generated on CCRA overflow CCRA Int. Flag TnAF CCRP Int. Flag TnPF TM O/P Pin Output does not change TnPF not generated Output Pin set to Initial Level Low if TnOC = 0 Output not affected by TnAF flag remains High until reset by TnON bit Output Toggle with TnAF flag Now TnIO1, TnIO0 = 10 Active High Output Select Output controlled by other pin-shared function Output inverts when TnPOL is high Output Pin Reset to initial value Here TnIO1, TnIO0 = 11 Toggle Output Select Compare Match Output Mode -- TnCCLR=1 Note: 1. With TnCCLR=1, a Comparator A match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge 4. A TnPF flag is not generated when TnCCLR=1 Rev. 2.10 133 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect as the PWM period. Both of the CCRAand CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform. Rev. 2.10 134 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 10-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA If fSYS=16MHz, TM clock source is fSYS/4, CCRP=100b and CCRA=128, The STM PWM output frequency=(fSYS/4)/512=fSYS/2048=7.8125kHz, duty=128/512=25%. If the Duty value defined by the CCRAregister is equal to or greater than the Period value, then the PWM output duty is 100%. 10-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=1 CCRP 001b 010b 011b 100b 128 256 384 512 Period Duty 101b 110b 111b 000b 768 896 1024 CCRA 640 The PWM output period is determined by the CCRAregister value together with the TM clock while the PWM duty cycle is defined by the CCRP register value. 16-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=0 CCRP 1~255 0 Period CCRP×256 65536 Duty CCRA If fSYS=16MHz, TM clock source is fSYS/4, CCRP=2 and CCRA=128, The STM PWM output frequency=(fSYS/4)/(2×256)=fSYS/2048=7.8125kHz, duty=128/(2×256)=25%. If the Duty value defined by the CCRAregister is equal to or greater than the Period value, then the PWM output duty is 100%. 16-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=1 CCRP 1~255 Period 0 CCRA Duty CCRP×256 65536 The PWM output period is determined by the CCRAregister value together with the TM clock while the PWM duty cycle is defined by the (CCRP×256) except when the CCRP value is equal to 0. Rev. 2.10 135 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Co�nter Va��e TnDPX = 0; TnM [1:0] = 10 Co�nter c�eared b� CCRP Co�nter Reset when TnON ret�rns high CCRP Pa�se Res�me CCRA Co�nter Stop if TnON bit �ow Time TnON TnPAU TnPOL CCRA Int. F�ag TnAF CCRP Int. F�ag TnPF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM D�t� C�c�e set b� CCRA PWM Period set b� CCRP PWM res�mes operation O�tp�t contro��ed b� O�tp�t Inverts other pin-shared f�nction when TnPOL = 1 PWM Mode -- TnDPX=0 Note: 1. Here TnDPX=0 -- Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when TnIO [1:0]=00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 2.10 136 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Co�nter Va��e TnDPX = 1; TnM [1:0] = 10 Co�nter c�eared b� CCRA Co�nter Reset when TnON ret�rns high CCRA Pa�se Res�me CCRP Co�nter Stop if TnON bit �ow Time TnON TnPAU TnPOL CCRP Int. F�ag TnPF CCRA Int. F�ag TnAF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM D�t� C�c�e set b� CCRP PWM Period set b� CCRA PWM res�mes operation O�tp�t contro��ed b� O�tp�t Inverts other pin-shared f�nction when TnPOL = 1 PWM Mode -- TnDPX=1 Note: 1. Here TnDPX=1 -- Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when TnIO [1:0]=00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 2.10 137 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Single Pulse Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR and TnDPX bits are not used in this Mode. Single Pulse Generation Rev. 2.10 138 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Counter Value TnM [1:0] = 10 ; TnIO [1:0] = 11 Counter stopped by CCRA Counter Reset when TnON returns high CCRA Pause Counter Stops by software Resume CCRP Time TnON Software Trigger Auto. set by TCKn pin Cleared by CCRA match TCKn pin Software Trigger Software Clear Software Trigger Software Trigger TCKn pin Trigger TnPAU TnPOL CCRP Int. Flag TnPF No CCRP Interrupts generated CCRA Int. Flag TnAF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) Output Inverts when TnPOL = 1 Pulse Width set by CCRA Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse triggered by the TCKn pin or by setting the TnON bit high 4. A TCKn pin active edge will automatically set the TnON bit high. 5. In the Single Pulse Mode, TnIO [1:0] must be set to "11" and can not be changed. Rev. 2.10 139 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Capture Input Mode To select this mode bits TnM1 and TnM0 in the TMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPn_0 or TPn_1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnIO1 and TnIO0 bits in the TMnC1 register. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TPn_0 or TPn_1 pin the present value in the counter will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what events occur on the TPn_0 or TPn_1 pin the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnIO1 and TnIO0 bits can select the active trigger edge on the TPn_0 or TPn_1 pin to be a rising edge, falling edge or both edge types. If the TnIO1 and TnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TPn_0 or TPn_1 pin, however it must be noted that the counter will continue to run. As the TPn_0 or TPn_1 pin is pin shared with other functions, care must be taken if the TM is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The TnCCLR and TnDPX bits are not used in this Mode. Rev. 2.10 140 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Co�nter Va��e TnM [1:0] = 01 Co�nter c�eared b� CCRP Co�nter Co�nter Stop Reset CCRP YY Pa�se Res�me XX Time TnON TnPAU TM capt�re pin TPn_x Active edge Active edge Active edge CCRA Int. F�ag TnAF CCRP Int. F�ag TnPF CCRA Va��e TnIO [1:0] Va��e XX 00 – Rising edge YY 01 – Fa��ing edge XX 10 – Both edges YY 11 – Disab�e Capt�re Capture Input Mode Note: 1. TnM [1:0]=01 and active edge set by the TnIO [1:0] bits 2. A TM Capture input pin active edge transfers the counter value to CCRA 3. TnCCLR bit not used 4. No output function -- TnOC and TnPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero Rev. 2.10 141 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Enhanced Type TM – ETM The Enhanced Type TM contains five operating modes, which are Compare Match Output, Timer/Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Enhanced TM can also be controlled with an external input pin and can drive three or four external output pins. ETM Name TM No. TM Input Pin HT68F20 — — — TM Output Pin — HT68F30 10-bit ETM 1 TCK1 TP1A; TP1B_0, TP1B_1 HT68F40 10-bit ETM 1 TCK1 TP1A, TP1B_0, TP1B_1, TP1B_2 HT68F50 10-bit ETM 1 TCK1 TP1A, TP1B_0, TP1B_1, TP1B_2 HT68F60 10-bit ETM 1 TCK1 TP1A, TP1B_0, TP1B_1, TP1B_2 Enhanced Type TM Block Diagram Rev. 2.10 142 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Enhanced TM Operation At its core is a 10-bit count-up/count-down counter which is driven by a user selectable internal or external clock source. There are three internal comparators with the names, Comparator A, Comparator B and Comparator P. These comparators will compare the value in the counter with the CCRA, CCRB and CCRP registers. The CCRP comparator is 3-bit wide whose value is compared with the highest 3-bit in the counter while CCRA and CCRB are 10-bit wide and therefore compared with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Enhanced Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control output pins. All operating setup conditions are selected using relevant internal registers. Enhanced Type TM Register Description Overall operation of the Enhanced TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA and CCRB value. The remaining three registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TM1C0 T1PAU T1CK2 T1CK1 T1CK0 T1ON T1RP2 T1RP1 T1RP0 TM1C1 T1AM1 T1AM0 T1AIO1 T1AIO0 T1AOC T1APOL T1CDN T1CCLR TM1C2 T1BM1 T1BM0 T1BIO1 T1BIO0 T1BOC T1BPOL TM1DL D7 D6 D5 D4 D3 D2 D1 D0 TM1DH — — — — — — D9 D8 TM1AL D7 D6 D5 D4 D3 D2 D1 D0 TM1AH — — — — — — D9 D8 TM1BL D7 D6 D5 D4 D3 D2 D1 D0 TM1BH — — — — — — D9 D8 T1PWM1 T1PWM0 10-bit Enhanced TM Register List (if ETM is TM1) Rev. 2.10 143 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 10-bit Enhanced TM Register List – HT68F30/HT68F40/HT68F50/HT68F60 • TM1C0 Register – 10-bit ETM Bit 7 6 5 4 3 2 1 0 Name T1PAU T1CK2 T1CK1 T1CK0 T1ON T1RP2 T1RP1 T1RP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7T1PAU: TM1 Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4T1CK2~T1CK0: Select TM1 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Undefined 110: TCK1 rising edge clock 111: TCK1 falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. Bit 3T1ON: TM1 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T1OC bit, when the T1ON bit changes from low to high. Bit 2~0T1RP2~T1RP0: TM1 CCRP 3-bit register, compared with the TM1 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TM1 clocks 001: 128 TM1 clocks 010: 256 TM1 clocks 011: 384 TM1 clocks 100: 512 TM1 clocks 101: 640 TM1 clocks 110: 768 TM1 clocks 111: 896 TM1 clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter's highest three bits. The result of this comparison can be selected to clear the internal counter if the T1CCLR bit is set to zero. Setting the T1CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. Rev. 2.10 144 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • TM1C1 Register – 10-bit ETM Bit 7 6 5 4 3 2 1 0 Name T1AM1 T1AM0 T1AIO1 T1AIO0 T1AOC T1APOL T1CDN T1CCLR R/W R/W R/W R/W R/W R/W R/W R R/W POR 0 0 0 0 0 0 0 0 Bit 7~6T1AM1~T1AM0: Select TM1 CCRA Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T1AM1 and T1AM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4T1AIO1~T1AIO0: Select TP1A output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP1A 01: Input capture at falling edge of TP1A 10: Input capture at falling/rising edge of TP1A 11: Input capture disabled Timer/counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the T1AIO1 and T1AIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T1AOC bit in the TM1C1 register. Note that the output level requested by the T1AIO1 and T1AIO0 bits must be different from the initial value setup using the T1AOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T1ON bit from low to high. In the PWM Mode, the T1AIO1 and T1AIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the T1AIO1 and T1AIO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the T1AIO1 and T1AIO0 bits are changed when the TM is running. Rev. 2.10 145 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Bit 3T1AOC: TP1A Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2T1APOL: TP1A Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP1A output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1T1CDN: TM1 Counter count up or down flag 0: Count up 1: Count down Bit 0T1CCLR: Select TM1 Counter clear condition 0: TM1 Comparator P match 1: TM1 Comparator A match This bit is used to select the method which clears the counter. Remember that the Enhanced TM contains three comparators, Comparator A, Comparator B and Comparator P, but only Comparator A or Comparator Pan be selected to clear the internal counter. With the T1CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T1CCLR bit is not used in the Single Pulse or Input Capture Mode. Rev. 2.10 146 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • TM1C2 Register – 10-bit ETM Bit 7 6 5 4 3 2 Name T1BM1 T1BM0 T1BIO1 T1BIO0 T1BOC T1BPOL 1 0 R/W R/W R/W R/W R/W R/W R/W R R/W POR 0 0 0 0 0 0 0 0 T1PWM1 T1PWM0 Bit 7~6T1BM1~T1BM0: Select TM1 CCRB Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T1BM1 and T1BM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4T1BIO1~T1BIO0: Select TP1B_0, TP1B_1, TP1B_2 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP1B_0, TP1B_1, TP1B_2 01: Input capture at falling edge of TP1B_0, TP1B_1, TP1B_2 10: Input capture at falling/rising edge of TP1B_0, TP1B_1, TP1B_2 11: Input capture disabled Timer/counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the T1BIO1 and T1BIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator B. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator B. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T1BOC bit in the TM1C2 register. Note that the output level requested by the T1BIO1 and T1BIO0 bits must be different from the initial value setup using the T1BOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T1ON bit from low to high. In the PWM Mode, the T1BIO1 and T1BIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the T1BIO1 and T1BIO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the T1BIO1 and T1BIO0 bits are changed when the TM is running. Rev. 2.10 147 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Bit 3T1BOC: TP1B_0, TP1B_1, TP1B_2 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2T1BPOL: TP1B_0, TP1B_1, TB1B_2 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP1B_0, TP1B_1, TP1B_2 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1~0T1PWM1~T1PWM0: Select PWM Mode 00: Edge aligned 01: Centre aligned, compare match on count up 10: Centre aligned, compare match on count down 11: Centre aligned, compare match on count up or down • TM1DL Register – 10-bit ETM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0TM1DL: TM1 Counter Low Byte Register bit 7~bit 0 TM1 10-bit Counter bit 7~bit 0 • TM1DH Register – 10-bit ETM Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0TM1DH: TM1 Counter High Byte Register bit 1~bit 0 TM1 10-bit Counter bit 9~bit 8 Rev. 2.10 148 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • TM1AL Register – 10-bit ETM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 1 0 Bit 7~0TM1AL: TM1 CCRA Low Byte Register bit 7~bit 0 TM1 10-bit CCRA bit 7~bit 0 • TM1AH Register – 10-bit ETM Bit 7 6 5 4 3 2 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0TM1AH: TM1 CCRA High Byte Register bit 1~bit 0 TM1 10-bit CCRA bit 9~bit 8 • TM1BL Register – 10-bit ETM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0TM1BL: TM1 CCRB Low Byte Register bit 7~bit 0 TM1 10-bit CCRB bit 7~bit 0 • TM1BH Register – 10-bit ETM Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0TM1BH: TM1 CCRB High Byte Register bit 1~bit 0 TM1 10-bit CCRB bit 9~bit 8 Rev. 2.10 149 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Enhanced Type TM Operating Modes The Enhanced Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnAM1 and TnAM0 bits in the TMnC1, and the TnBM1 and TnBM0 bits in the TMnC2 register. CCRA Compare Match Output Mode CCRA Timer/ Counter Mode CCRB Compare Match Output Mode √ — — — — CCRB Timer/Counter Mode — √ — — — CCRB PWM Output Mode — — √ — — CCRB Single Pulse Output Mode — — — √ — CCRB Input Capture Mode — — — — √ ETM Operating Mode CCRA PWM CCRA Single Pulse CCRA Input Output Mode Output Mode Capture Mode "√": permitted; "—": not permitted Compare Output Mode To select this mode, bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1/TMnC2 registers should be all cleared to zero. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both the TnAF and TnPF interrupt request flags for Comparator Aand Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when an TnAF or TnBF interrupt request flag is generated after a compare match occurs from Comparator Aor Comparator B. The TnPF interrupt request flag, generated from a compare match from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state is determined by the condition of the TnAIO1 and TnAIO0 bits in the TMnC1 register for ETM CCRA, and the TnBIO1 and TnBIO0 bits in the TMnC2 register for ETM CCRB. The TM output pin can be selected using the TnAIO1, TnAIO0 bits (for the TPnA pin) and TnBIO1, TnBIO0 bits (for the TPnB_0, TPnB_1 or TPnB_2 pins) to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A or a compare match occurs from Comparator B. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnAOC or TnBOC bit for TPnA or TPnB_0, TPnB_1, TPnB_2 output pins. Note that if the TnAIO1,TnAIO0 and TnBIO1, TnBIO0 bits are zero then no pin change will take place. Rev. 2.10 150 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Co�nter Va��e Co�nter overf�ow CCRP=0 0x3FF TnCCLR = 0; TnAM [1:0] = 00 CCRP > 0 Co�nter c�eared b� CCRP va��e CCRP > 0 Co�nter Restart Res�me CCRP Pa�se CCRA Stop Time TnON TnPAU TnAPOL CCRP Int. F�ag TnPF CCRA Int. F�ag TnAF TPnA O/P Pin O�tp�t pin set to initia� Leve� Low if TnAOC=0 O�tp�t not affected b� TnAF f�ag. Remains High �nti� reset b� TnON bit O�tp�t Togg�e with TnAF f�ag Here TnAIO [1:0] = 11 Togg�e O�tp�t se�ect Note TnAIO [1:0] = 10 Active High O�tp�t se�ect O�tp�t Inverts when TnAPOL is high O�tp�t Pin Reset to Initia� va��e O�tp�t contro��ed b� other pin-shared f�nction ETM CCRA Compare Match Output Mode -- TnCCLR=0 Note: 1. With TnCCLR=0, a Comparator P match will clear the counter 2. The TPnA output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge Rev. 2.10 151 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Co�nter Va��e Co�nter overf�ow CCRP=0 0x3FF TnCCLR = 0; TnBM [1:0] = 00 CCRP > 0 Co�nter c�eared b� CCRP va��e CCRP > 0 Co�nter Restart Res�me CCRP Pa�se CCRB Stop Time TnON TnPAU TnBPOL CCRP Int. F�ag TnPF CCRB Int. F�ag TnBF TPnB O/P Pin O�tp�t pin set to initia� Leve� Low if TnBOC=0 O�tp�t not affected b� TnBF f�ag. Remains High �nti� reset b� TnON bit O�tp�t Togg�e with TnBF f�ag Here TnBIO [1:0] = 11 Togg�e O�tp�t se�ect Note TnBIO [1:0] = 10 Active High O�tp�t se�ect O�tp�t Inverts when TnBPOL is high O�tp�t Pin Reset to Initia� va��e O�tp�t contro��ed b� other pin-shared f�nction ETM CCRB Compare Match Output Mode -- TnCCLR=0 Note: 1. With TnCCLR=0, a Comparator P match will clear the counter 2. The TPnB output pin is controlled only by the TnBF flag 3. The output pin is reset to its initial state by a TnON bit rising edge Rev. 2.10 152 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Co�nter Va��e TnCCLR = 1; TnAM [1:0] = 00 CCRA = 0 Co�nter overf�ow CCRA > 0 Co�nter c�eared b� CCRA va��e 0x3FF CCRA=0 Res�me CCRA Pa�se Stop Co�nter Restart CCRP Time TnON TnPAU TnAPOL No TnAF f�ag generated on CCRA overf�ow CCRA Int. F�ag TnAF CCRP Int. F�ag TnPF TnPF not generated O�tp�t does not change TPnA O/P Pin O�tp�t pin set to initia� Leve� Low if TnAOC=0 O�tp�t not affected b� TnAF f�ag. Remains High �nti� reset b� TnON bit O�tp�t Togg�e with TnAF f�ag Here TnAIO [1:0] = 11 Togg�e O�tp�t se�ect Note TnAIO [1:0] = 10 Active High O�tp�t se�ect O�tp�t Inverts when TnAPOL is high O�tp�t Pin Reset to Initia� va��e O�tp�t contro��ed b� other pin-shared f�nction ETM CCRA Compare Match Output Mode -- TnCCLR=1 Note: 1. With TnCCLR=1, a Comparator A match will clear the counter 2. The TPnA output pin is controlled only by the TnAF flag 3. The TPnA output pin is reset to its initial state by a TnON bit rising edge 4. The TnPF flag is not generated when TnCCLR=1 Rev. 2.10 153 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Co�nter Va��e 0x3FF TnCCLR = 1; TnBM [1:0] = 00 CCRA = 0 Co�nter overf�ow CCRA > 0 Co�nter c�eared b� CCRA va��e Res�me CCRA Pa�se CCRA=0 Stop Co�nter Restart CCRB Time TnON TnPAU TnBPOL No TnAF f�ag generated on CCRA overf�ow CCRA Int. F�ag TnAF CCRB Int. F�ag TnBF TPnB O/P Pin O�tp�t pin set to initia� Leve� Low if TnBOC=0 O�tp�t Togg�e with TnBF f�ag Here TnBIO [1:0] = 11 Togg�e O�tp�t se�ect O�tp�t not affected b� TnBF f�ag. Remains High �nti� reset b� TnON bit Note TnBIO [1:0] = 10 Active High O�tp�t se�ect O�tp�t Inverts when TnBPOL is high O�tp�t Pin Reset to Initia� va��e O�tp�t contro��ed b� other pin-shared f�nction ETM CCRB Compare Match Output Mode -- TnCCLR=1 Note: 1. With TnCCLR=1, a Comparator A match will clear the counter 2. The TPnB output pin is controlled only by the TnBF flag 3. The TPnB output pin is reset to its initial state by a TnON bit rising edge 4. The TnPF flag is not generated when TnCCLR=1 Rev. 2.10 154 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Timer/Counter Mode To select this mode, bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1 and TMnC2 register should all be set high. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, the required bit pairs, TnAM1, TnAM0 and TnBM1, TnBM0 should be set to 10 respectively and also the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit is used to determine in which way the PWM period is controlled. With the TnCCLR bit set high, the PWM period can be finely controlled using the CCRA registers. In this case the CCRB registers are used to set the PWM duty value (for TPnB output pins). The CCRP bits are not used and TPnA output pin is not used. The PWM output can only be generated on the TPnB output pins. With the TnCCLR bit cleared to zero, the PWM period is set using one of the eight values of the three CCRP bits, in multiples of 128. Now both CCRA and CCRB registers can be used to setup different duty cycle values to provide dual PWM outputs on their relative TPnA and TPnB pins. The TnPWM1 and TnPWM0 bits determine the PWM alignment type, which can be either edge or centre type. In edge alignment, the leading edge of the PWM signals will all be generated concurrently when the counter is reset to zero. With all power currents switching on at the same time, this may give rise to problems in higher power applications. In centre alignment the centre of the PWM active signals will occur sequentially, thus reducing the level of simultaneous power switching currents. Interrupt flags, one for each of the CCRA, CCRB and CCRP, will be generated when a compare match occurs from either the Comparator A, Comparator B or Comparator P. The TnAOC and TnBOC bits in the TMnC1 and TMnC2 register are used to select the required polarity of the PWM waveform while the two TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits pairs are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnAPOL and TnBPOL bit are used to reverse the polarity of the PWM output waveform. Rev. 2.10 155 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM ETM, PWM Mode, Edge-aligned Mode, TnCCLR=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 A Duty CCRA B Duty CCRB If fSYS=16MHz, TM clock source select fSYS/4, CCRP=100b, CCRA=128 and CCRB=256, The TP1A PWM output frequency=(fSYS/4)/512=fSYS/2048=7.8125kHz, duty=128/512=25%. The TP1B_n PWM output frequency=(fSYS/4)/512=fSYS/2048=7.8125kHz, duty=256/512=50%. If the Duty value defined by CCRAor CCRB register is equal to or greater than the Period value, then the PWM output duty is 100%. ETM, PWM Mode, Edge-aligned Mode, TnCCLR=1 CCRA 1 2 3 …… 511 512 …… 1021 1022 1023 Period 1 2 3 …… 511 512 …… 1021 1022 1023 B Duty CCRB ETM, PWM Mode, Center-aligned Mode, TnCCLR=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 256 512 768 1024 1280 1536 1792 2046 A Duty (CCRA×2)-1 B Duty (CCRB×2)-1 ETM, PWM Mode, Center-aligned Mode, TnCCLR=1 CCRA 1 2 3 511 512 1021 1022 1023 Period 2 4 6 1022 1024 2042 2044 2046 B Duty Rev. 2.10 (CCRB×2)-1 156 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Co�nter Va��e TnCCLR = 0; TnAM [1:0] = 10� TnBM [1:0] = 10; TnPWM [1:0] = 00 Co�nter C�eared b� CCRP CCRP CCRA Pa�se Res�me Stop CCRB Co�nter Restart Time TnON TnPAU TnAPOL CCRA Int. F�ag TnAF CCRB Int. F�ag TnBF CCRP Int. F�ag TnPF TPnA Pin (TnAOC=1) TPnB Pin D�t� C�c�e set b� CCRA D�t� C�c�e set b� CCRA D�t� C�c�e set b� CCRA O�tp�t Inverts when TnAPOL is high (TnBOC=1) TPnB Pin (TnBOC=0) D�t� C�c�e set b� CCRB O�tp�t contro��ed b� other pin-shared f�nction O�tp�t Pin Reset to Initia� va��e PWM Period set b� CCRP PWM Mode -- Edge Aligned Note: 1. Here TnCCLR=0 therefore CCRP clears the counter and determines the PWM period 2. The internal PWM function continues running even when TnAIO [1:0] (or TnBIO [1:0])=00 or 01 3. CCRA controls the TPnA PWM duty and CCRB controls the TPnB PWM duty Rev. 2.10 157 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Co�nter Va��e Co�nter C�eared b� CCRA TnCCLR = 1; TnBM [1:0] = 10; TnPWM [1:0] = 00 CCRA Pa�se Res�me Co�nter Restart Stop CCRB Time TnON TnPAU TnBPOL CCRP Int. F�ag TnPF CCRB Int. F�ag TnBF TPnB Pin (TnBOC=1) TPnB Pin (TnBOC=0) D�t� C�c�e set b� CCRB O�tp�t contro��ed b� other pin-shared f�nction PWM Period set b� CCRA O�tp�t Pin Reset to Initia� va��e O�tp�t Inverts when TnBPOL is high ETM PWM Mode -- Edge Aligned Note: 1. Here TnCCLR=1 therefore CCRA clears the counter and determines the PWM period 2. The internal PWM function continues running even when TnBIO [1:0]=00 or 01 3. The CCRA controls the TPnB PWM period and CCRB controls the TPnB PWM duty 4. Here the TM pin control register should not enable the TPnA pin as a TM output pin Rev. 2.10 158 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Co�nter Va��e TnCCLR = 0; TnAM [1:0] = 10� TnBM [1:0] = 10; TnPWM [1:0] = 11 CCRP Res�me CCRA Stop Co�nter Restart Pa�se CCRB Time TnON TnPAU TnAPOL CCRA Int. F�ag TnAF CCRB Int. F�ag TnBF CCRP Int. F�ag TnPF TPnA Pin (TnAOC=1) TPnB Pin D�t� C�c�e set b� CCRA O�tp�t Inverts when TnAPOL is high (TnBOC=1) TPnB Pin (TnBOC=0) D�t� C�c�e set b� CCRB O�tp�t contro��ed b� Other pin-shared f�nction PWM Period set b� CCRP O�tp�t Pin Reset to Initia� va��e ETM PWM Mode -- Centre Aligned Note: 1. Here TnCCLR=0 therefore CCRP clears the counter and determines the PWM period 2. TnPWM [1:0]=11 therefore the PWM is centre aligned 3. The internal PWM function continues running even when TnAIO [1:0] (or TnBIO [1:0])=00 or 01 4. CCRA controls the TPnA PWM duty and CCRB controls the TPnB PWM duty 5. CCRP will generate an interrupt request when the counter decrements to its zero value Rev. 2.10 159 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Co�nter Va��e TnCCLR = 1; TnBM [1:0] = 10; TnPWM [1:0] = 11 CCRA Res�me Stop Co�nter Restart Pa�se CCRB Time TnON TnPAU TnBPOL CCRA Int. F�ag TnAF CCRB Int. F�ag TnBF CCRP Int. F�ag TnPF TPnB Pin (TnBOC=1) TPnB Pin (TnBOC=0) O�tp�t contro��ed O�tp�t Inverts b� other pin-shared when TnBPOL is high f�nction O�tp�t Pin Reset to Initia� va��e D�t� C�c�e set b� CCRB PWM Period set b� CCRA PWM Mode -- Centre Aligned Note: 1. Here TnCCLR=1 therefore CCRA clears the counter and determines the PWM period 2. TnPWM [1:0]=11 therefore the PWM is centre aligned 3. The internal PWM function continues running even when TnBIO [1:0]=00 or 01 4. CCRA controls the TPnB PWM period and CCRB controls the TPnB PWM duty 5. CCRP will generate an interrupt request when the counter decrements to its zero value Rev. 2.10 160 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Single Pulse Output Mode To select this mode, the required bit pairs, TnAM1, TnAM0 and TnBM1, TnBM0 should be set to 10 respectively and also the corresponding TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse TPnA output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. The trigger for the pulse TPnB output leading edge is a compare match from Comparator B, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output of TPnA. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge of TPnA will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge of TPnA and TPnB will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge of TPnA and TPnB. In this way the CCRA value can be used to control the pulse width of TPnA. The CCRA-CCRB value can be used to control the pulse width of TPnB. A compare match from Comparator A and Comparator B will also generate TM interrupts. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR bit is also not used. Counter Value CCRA CCRB 0 S/W Command SET“TnON” or TCKn Pin Transition Time CCRA Leading Edge CCRA Trailing Edge TnON bit 0®1 TnON bit 1®0 S/W Command CLR“TnON” or CCRA Compare Match TPnA Output Pin Pulse Width = CCRA Value TPnB Output Pin Pulse Width = (CCRA-CCRB) Value CCRB Compare Match TnON = 1 TnON bit 1®0 CCRB Leading Edge CCRB Trailing Edge S/W Command CLR“TnON” or CCRA Compare Match Single Pulse Generation Rev. 2.10 161 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Co�nter Va��e TnAM [1:0] = 10� TnBM [1:0] = 10; TnAIO [1:0] = 11� TnBIO [1:0] = 11 Co�nter stopped b� CCRA CCRA Pa�se Co�nter Stops b� software Res�me CCRB Co�nter Reset when TnON ret�rns high Time TnON Software Trigger C�eared b� CCRA match A�to. set b� TCKn pin TCKn pin Software Trigger Software Trigger Software C�ear Software Trigger TCKn pin Trigger TnPAU TnAPOL TnBPOL CCRB Int. F�ag TnBF CCRA Int. F�ag TnAF TPnA Pin (TnAOC=1) TPnA Pin P��se Width set b� CCRA (TnAOC=0) O�tp�t Inverts when TnAPOL=1 TPnB Pin (TnBOC=1) TPnB Pin (TnBOC=0) P��se Width set b� (CCRA-CCRB) O�tp�t Inverts when TnBPOL=1 ETM -- Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse triggered by the TCKn pin or by setting the TnON bit high 4. A TCKn pin active edge will automatically set the TnON bit high 5. In the Single Pulse Mode, TnAIO [1:0] and TnBIO [1:0] must be set to "11" and can not be changed Rev. 2.10 162 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Capture Input Mode To select this mode bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1 and TMnC2 registers should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits in the TMnC1 and TMnC2 registers. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins the present value in the counter will be latched into the CCRA and CCRB registers and a TM interrupt generated. Irrespective of what events occur on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits can select the active trigger edge on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins to be a rising edge, falling edge or both edge types. If the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins, however it must be noted that the counter will continue to run. As the TPnA and TPnB_0, TPnB_1, TPnB_2 pins are pin shared with other functions, care must be taken if the TM is in the Capture Input Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The TnCCLR, TnAOC, TnBOC, TnAPOL and TnBPOL bits are not used in this mode. Rev. 2.10 163 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Co�nter Va��e TnAM [1:0] = 01 Co�nter c�eared b� CCRP Co�nter Co�nter Reset Stop CCRP YY Pa�se Res�me XX Time TnON TnPAU TM capt�re pin TPnA Active edge Active edge Active edge CCRA Int. F�ag TnAF CCRP Int. F�ag TnPF CCRA Va��e TnAIO [1:0] Va��e XX 00 – Rising edge YY 01 – Fa��ing edge XX 10 – Both edges YY 11 – Disab�e Capt�re ETM CCRA Capture Input Mode Note: 1. TnAM [1:0]=01 and active edge set by the TnAIO [1:0] bits 2. The TM Capture input pin active edge transfers he counter value to CCRA 3. TnCCLR bit not used 4. No output function -- TnAOC and TnAPOL bits not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero Rev. 2.10 164 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM TnBM1� TnBM0 = 01 Co�nter Va��e Co�nter overf�ow CCRP Stop Co�nter Reset YY XX Pa�se Res�me Time TnON bit TnPAU bit TM Capt�re Pin Active edge Active edge Active edges CCRB Int. F�ag TnBF CCRP Int. F�ag TnPF CCRB Va��e TnBIO1� TnBIO0 Va��e XX 00 - Rising edge YY 01 - Fa��ing edge XX YY 10 - Both edges 11 - Disab�e Capt�re ETM CCRB Capture Input Mode Note: 1. TnBM [1:0]=01 and active edge set by the TnBIO [1:0] bits 2. The TM Capture input pin active edge transfers the counter value to CCRB 3. TnCCLR bit not used 4. No output function -- TnBOC and TnBPOL bits not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero Rev. 2.10 165 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Comparators Two independent analog comparators are contained within these devices. These functions offer flexibility via their register controlled features such as power-down, polarity select, hysteresis etc. In sharing their pins with normal I/O pins the comparators do not waste precious I/O pins if there functions are otherwise unused. Comparator Comparator Operation The device contains two comparator functions which are used to compare two analog voltages and provide an output based on their difference. Full control over the two internal comparators is provided via two control registers, CP0C and CP1C, one assigned to each comparator. The comparator output is recorded via a bit in their respective control register, but can also be transferred out onto a shared I/O pin. Additional comparator functions include, output polarity, hysteresis functions and power down control. Any pull-high resistors connected to the shared comparator input pins will be automatically disconnected when the comparator is enabled. As the comparator inputs approach their switching level, some spurious output signals may be generated on the comparator output due to the slow rising or falling nature of the input signals. This can be minimised by selecting the hysteresis function will apply a small amount of positive feedback to the comparator. Ideally the comparator should switch at the point where the positive and negative inputs signals are at the same voltage level, however, unavoidable input offsets introduce some uncertainties here. The hysteresis function, if enabled, also increases the switching offset value. Comparator Registers There are two registers for overall comparator operation, one for each comparator. As corresponding bits in the two registers have identical functions, they following register table applies to both registers. Bit Register Name 7 6 5 4 3 2 1 0 CP0C C0SEL C0EN C0POL C0OUT C0OS — — C0HYEN CP1C C1SEL C1EN C1POL C1OUT C1OS — — C1HYEN Comparator Registers List Rev. 2.10 166 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM CP0C Register Bit 7 6 5 4 3 2 1 0 Name C0SEL C0EN C0POL C0OUT C0OS — — C0HYEN R/W R/W R/W R/W R R/W — — R/W POR 1 0 0 0 0 — — 1 Bit 7C0SEL: Select Comparator pins or I/O pins 0: I/O pin select 1: Comparator pin select This is the Comparator pin or I/O pin select bit. If the bit is high the comparator will be selected and the two comparator input pins will be enabled. As a result, these two pins will lose their I/O pin functions. Any pull-high configuration options associated with the comparator shared pins will also be automatically disconnected. Bit 6C0EN: Comparator On/Off control 0: Off 1: On This is the Comparator on/off control bit. If the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. For power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the SLEEP or IDLE mode. Bit 5C0POL: Comparator output polarity 0: Output not inverted 1: Output inverted This is the comparator polarity bit. If the bit is zero then the C0OUT bit will reflect the non-inverted output condition of the comparator. If the bit is high the comparator C0OUT bit will be inverted. Bit 4C0OUT: Comparator output bit C0POL=0 0: C0+ < C01: C0+ > C0C0POL=1 0: C0+ > C01: C0+ < C0This bit stores the comparator output bit. The polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the C0POL bit. Bit 3C0OS: Output path select 0: C0X pin 1: Internal use This is the comparator output path select control bit. If the bit is set to "0" and the C0SEL bit is "1" the comparator output is connected to an external C0X pin. If the bit is set to "1" or the C0SEL bit is "0" the comparator output signal is only used internally by the device allowing the shared comparator output pin to retain its normal I/O operation. Bit 2~1 Unimplemented, read as“0” Bit 0C0HYEN: Hysteresis Control 0: Off 1: On This is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specified in the Comparator Electrical Characteristics table. The positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. Rev. 2.10 167 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM CP1C Register Bit 7 6 5 4 3 2 1 0 Name C1SEL C1EN C1POL C1OUT C1OS — — C1HYEN R/W R/W R/W R/W R R/W — — R/W POR 1 0 0 0 0 — — 1 Bit 7C1SEL: Select Comparator pins or I/O pins 0: I/O pin select 1: Comparator pin select This is the Comparator pin or I/O pin select bit. If the bit is high the comparator will be selected and the two comparator input pins will be enabled. As a result, these two pins will lose their I/O pin functions. Any pull-high configuration options associated with the comparator shared pins will also be automatically disconnected. Bit 6C1EN: Comparator On/Off control 0: Off 1: On This is the Comparator on/off control bit. If the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. For power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the SLEEP or IDLE mode. Bit 5C1POL: Comparator output polarity 0: Output not inverted 1: Output inverted This is the comparator polarity bit. If the bit is zero then the C1OUT bit will reflect the non-inverted output condition of the comparator. If the bit is high the comparator C1OUT bit will be inverted. Bit 4C1OUT: Comparator output bit C1POL=0 0: C1+ < C11: C1+ > C1C1POL=1 0: C1+ > C11: C1+ < C1This bit stores the comparator output bit. The polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the C1POL bit. Bit 3C1OS: Output path select 0: C1X pin 1: Internal use This is the comparator output path select control bit. If the bit is set to "0" and the C1SEL bit is "1" the comparator output is connected to an external C1X pin. If the bit is set to "1" or the C1SEL bit is "0" the comparator output signal is only used internally by the device allowing the shared comparator output pin to retain its normal I/O operation. Bit 2~1 Unimplemented, read as “0” Bit 0C1HYEN: Hysteresis Control 0: Off 1: On This is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specified in the Comparator Electrical Characteristics table. The positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. Rev. 2.10 168 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Comparator Interrupt Each also possesses its own interrupt function. When any one of the changes state, its relevant interrupt flag will be set, and if the corresponding interrupt enable bit is set, then a jump to its relevant interrupt vector will be executed. Note that it is the changing state of the C0OUT or C1OUT bit and not the output pin which generates an interrupt. If the microcontroller is in the SLEEP or IDLE Mode and the Comparator is enabled, then if the external input lines cause the Comparator output to change state, the resulting generated interrupt flag will also generate a wake-up. If it is required to disable a wake-up from occurring, then the interrupt flag should be first set high before entering the SLEEP or IDLE Mode. Programming Considerations If the comparator is enabled, it will remain active when the microcontroller enters the SLEEP or IDLE Mode, however as it will consume a certain amount of power, the user may wish to consider disabling it before the SLEEP or IDLE Mode is entered. As comparator pins are shared with normal I/O pins the I/O registers for these pins will be read as zero (port control register is "1") or read as port data register value (port control register is "0") if the comparator function is enabled. Serial Interface Module – SIM These devices contain a Serial Interface Module, which includes both the four line SPI interface or the two line I2C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins therefore the SIM interface function must first be selected using a configuration option. As both interface types share the same pins and registers, the choice of whether the SPI or I2C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 register. These pull-high resistors of the SIM pin-shared I/O are selected using pull-high control registers, and also if the SIM function is enabled. Rev. 2.10 169 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the device can be either master or slave. Although the SPI interface specification can control multiple slave devices from a single master, but this device provided only one SCS pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pin to select the slave devices. SPI Interface Operation The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface must first be enabled by selecting the SIM enable configuration option and setting the correct bits in the SIMC0 and SIMC2 registers. After the SPI configuration option has been configured it can also be additionally disabled or enabled using the SIMEN bit in the SIMC0 register. Communication between devices connected to the SPI interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The Master also controls the clock signal. As the device only contains a single SCS pin only one slave device can be utilized. The SCS pin is controlled by software, set CSEN bit to "1" to enable SCS pin function, set CSEN bit to "0" the SCS pin will be floating state. SPI Master/Slave Connection The SPI function in this device offers the following features: • Full duplex synchronous data transfer • Both Master and Slave modes • LSB first or MSB first data transmission modes • Transmission complete flag • Rising or falling active clock edge • WCOL and CSEN bit enabled or disable select The status of the SPI interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN. There are several configuration options associated with the SPI interface. One of these is to enable the SIM function which selects the SIM pins rather than normal I/O pins. Note that if the configuration option does not select the SIM function then the SIMEN bit in the SIMC0 register will have no effect. Another two SPI configuration options determine if the CSEN and WCOL bits are to be used. Rev. 2.10 170 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM SPI Registers There are three internal registers which control the overall operation of the SPI interface. These are the SIMD data register and two registers SIMC0 and SIMC2. Note that the SIMC1 register is only used by the I2C interface. Bit Register Name 7 6 5 4 3 2 1 0 SIMC0 SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMC2 D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF SIM Registers List The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register. SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR × × × × × × × × “×”: unknown There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2 register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used by the SPI function, only by the I2C function. Register SIMC0 is used to control the enable/disable function and to set the data transmission clock frequency. Although not connected with the SPI function, the SIMC0 register is also used to control the Peripheral Clock Prescaler. Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag etc. Rev. 2.10 171 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM SIMC0 Register Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — R/W R/W R/W R/W R/W R/W R/W R/W — POR 1 1 1 0 0 0 0 — Bit 7~5 SIM2, SIM1, SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fTBC 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Unused mode These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4PCKEN: PCK Output Pin Control 0: Disable 1: Enable Bit 3~2 PCKP1, PCKP0: Select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 Bit 1SIMEN: SIM Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be in a floating condition and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 Rev. 2.10 Unimplemented, read as “0” 172 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM SIMC2 Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Undefined bit This bit can be read or written by user software program. Bit 5CKPOLB: Determines the base condition of the clock line 0: The SCK line will be high when the clock is inactive 1: The SCK line will be low when the clock is inactive The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. Bit 4CKEG: Determines SPI SCK active clock edge type CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit. Bit 3MLS: SPI Data shift order 0: LSB 1: MSB This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Bit 2CSEN: SPI SCS pin Control 0: Disable 1: Enable The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the SCS pin will be disabled and placed into a floating condition. If the bit is high the SCS pin will be enabled and used as a select pin. Note that using the CSEN bit can be disabled or enabled via configuration option. Bit 1WCOL: SPI Write Collision flag 0: No collision 1: Collision The WCOL flag is used to detect if a data collision has occurred. If this bit is high it means that data has been attempted to be written to the SIMD register during a data transfer operation. This writing operation will be ignored if data is being transferred. The bit can be cleared by the application program. Note that using the WCOL bit can be disabled or enabled via configuration option. Bit 0TRF: SPI Transmit/Receive Complete flag 0: Data is being transferred 1: SPI data transmission is completed The TRF bit is the Transmit/Receive Complete flag and is set "1" automatically when an SPI data transmission is completed, but must set to "0" by the application program. It can be used to generate an interrupt. Rev. 2.10 173 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM SPI Communication After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output an SCS signal to enable the slave device before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI will continue to function even in the IDLE Mode. SPI Master Mode Timing SPI Slave Mode Timing – CKEG=0 Rev. 2.10 174 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM SPI Slave Mode Timing – CKEG=1 SPI Transfer Control Flowchart Rev. 2.10 175 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM I2C Interface The I 2C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. I2C Master Slave Bus Connection I2C Interface Operation The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two devices communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For these devices, which only operates in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. There are several configuration options associated with the I2C interface. One of these is to enable the function which selects the SIM pins rather than normal I/O pins. Note that if the configuration option does not select the SIM function then the SIMEN bit in the SIMC0 register will have no effect. A configuration option determines the debounce time of the I2C interface. This uses the system clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be chosen to be either 2 or 4 system clocks. To achieve the required I2C data transfer speed, there exists a relationship between the system clock, fSYS, and the I2C debounce time. For either the I2C Standard or Fast mode operation, users must take care of the selected system clock frequency and the configured debounce time to match the criterion shown in the following table. I2C Debounce Time Selection I2C Standard Mode (100kHz) I2C Fast Mode (400kHz) No debounce fSYS>2MHz fSYS>5MHz 2 system clock debounce fSYS>4MHz fSYS>10MHz fSYS>8MHz fSYS>20MHz 4 system clock debounce I C Minimum fSYS Frequency 2 Rev. 2.10 176 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM S T A R T s ig n a l fro m M a s te r S e n d s la v e a d d r e s s a n d R /W b it fr o m M a s te r A c k n o w le d g e fr o m s la v e S e n d d a ta b y te fro m M a s te r A c k n o w le d g e fr o m s la v e S T O P s ig n a l fro m M a s te r I2C Registers There are three control registers associated with the I2C bus, SIMC0, SIMC1 and SIMA and one data register, SIMD. The SIMD register, which is shown in the above SPI section, is used to store the data being transmitted and received on the I2C bus. Before the microcontroller writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the microcontroller can read it from the SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD register. Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface. Bit Register Name 7 6 5 4 3 2 1 0 SIMC0 SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — SIMC1 HCF HAAS HBB HTX TXAK SRW IAMWU RXAK SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMA IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 D0 I C Registers List 2 Rev. 2.10 177 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM SIMC0 Register Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — R/W R/W R/W R/W R/W R/W R/W R/W — POR 1 1 1 0 0 0 0 — Bit 7~5 SIM2, SIM1, SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fTBC 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Unused mode These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4PCKEN: PCK Output Pin Control 0: Disable 1: Enable Bit 3~2 PCKP1, PCKP0: Select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 Bit 1SIMEN: SIM Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be in a floating condition and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective. If the SIM is configured to operate as an SPI interface via SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 Unimplemented, read as “0” Rev. 2.10 178 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM SIMC1 Register Bit 7 6 5 4 3 2 1 0 Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R/W R R R R/W R/W R R/W R POR 1 0 0 0 0 0 0 1 Bit 7HCF: I2C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Bit 6HAAS: I2C Bus address match flag 0: Not address match 1: Address match The HAAS flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. Bit 5HBB: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The HBB flag is the I2C busy flag. This flag will be "1" when the I2C bus is busy which will occur when a START signal is detected. The flag will be set to "0" when the bus is free which will occur when a STOP signal is detected. Bit 4HTX: Select I2C slave device is transmitter or receiver 0: Slave device is the receiver 1: Slave device is the transmitter Bit 3TXAK: I2C Bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave do not send acknowledge flag The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bit of data, this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always set TXAK bit to "0" before further data is received. Bit 2SRW: I2C Slave Read/Write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SRW flag is the I 2C Slave Read/Write flag. This flag determines whether the master device wishes to transmit or receive data from the I2C bus. When the transmitted address and slave address is match, that is when the HAAS flag is set high, the slave device will check the SRW flag to determine whether it should be in transmit mode or receive mode. If the SRW flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SRW flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1IAMWU: I2C Address Match Wake-up Control 0: Disable 1: Enable – must be cleared by the application program after wake-up This bit should be set to "1" to enable the I2C address match wake up from the SLEEP or IDLE Mode. If the IAMWU bit has been set before entering either the SLEEP or IDLE mode to enable the I2C address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation. Rev. 2.10 179 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Bit 0RXAK: I2C Bus Receive acknowledge flag 0: Slave receive acknowledge flag 1: Slave do not receive acknowledge flag The RXAK flag is the receiver acknowledge flag. When the RXAK flag is "0", it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAK flag is "1". When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register. SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR × × × × × × × × SIMA Register Bit 7 6 5 4 3 2 1 0 Name IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 — R/W R/W R/W R/W R/W R/W R/W R/W — POR × × × × × × × — Bit 7~1IICA6~IICA0: I2C slave address IICA6~IICA0 is the I2C slave address bit 6~bit 0. The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the SIMA register, the slave device will be selected. Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface. Bit 0 Rev. 2.10 Undefined bit This bit can be read or written by user software program. 180 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM I2C Block Diagram I2C Bus Communication Communication on the I2C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this: • Step 1 Set the SIM2~SIM0 and SIMEN bits in the SIMC0 register to "1" to enable the I2C bus. • Step 2 Write the slave address of the device to the I2C bus address register SIMA. • Step 3 Set the SIME and SIM Muti-Function interrupt enable bit of the interrupt control register to enable the SIM interrupt and Multi-function interrupt. Rev. 2.10 181 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM I2C Bus Initialisation Flow Chart I2C Bus Start Signal The START signal can only be generated by the master device connected to the I2C bus and not by the slave device. This START signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. Slave Address The transmission of a START signal by the master will be detected by all devices on the I2C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag HAAS when the addresses match. As an I 2C bus interrupt can come from two sources, when the program enters the interrupt subroutine, the HAAS bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. Rev. 2.10 182 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM I2C Bus Read/Write Signal The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW flag is "1" then this indicates that the master device wishes to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a transmitter. If the SRW flag is "0" then this indicates that the master wishes to send data to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver. I2C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address, any slave device on the I2C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAAS flag is high, the addresses have matched and the slave device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register should be set to "1". If the SRW flag is low, then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1 register should be set to "0". I2C Bus Data and Acknowledge Signal The transmitted data is 8-bit wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8-bit of data, the receiver must transmit an acknowledge signal, level "0", before it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the SIMD register. If setup as a transmitter, the slave device must first write the data to be transmitted into the SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD register. When the slave receiver receives the data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte, if not then it will release the SDAline and await the receipt of a STOP signal from the master. Rev. 2.10 183 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Note: * When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I2C Communication Timing Diagram I2C Bus ISR Flow Chart Rev. 2.10 184 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Peripheral Clock Output The Peripheral Clock Output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. Peripheral Clock Operation As the peripheral clock output pin, PCK, is shared with I/O line, the required pin function is chosen via PCKEN in the SIMC0 register. The Peripheral Clock function is controlled using the SIMC0 register. The clock source for the Peripheral Clock Output can originate from either the TM0 CCRP match frequency/2 or a divided ratio of the internal fSYS clock. The PCKEN bit in the SIMC0 register is the overall on/off control, setting PCKEN bit to "1" enables the Peripheral Clock, setting PCKEN bit to "0" disables it. The required division ratio of the system clock is selected using the PCKP1 and PCKP0 bits in the same register. If the device enters the SLEEP Mode this will disable the Peripheral Clock output. SIMC0 Register Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — R/W R/W R/W R/W R/W R/W R/W R/W — POR 1 1 1 0 0 0 0 — SIM2, SIM1, SIM0: SIM operating mode control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fTBC 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Unused mode These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4PCKEN: PCK output pin control 0: Disable 1: Enable Bit 3~2 PCKP1, PCKP0: select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 Bit 1SIMEN: SIM control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be in a floating condition and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective. Note that when the SIMEN bit changes from low to high the contents of the SPI control registers will be in an unknown condition and should therefore be first initialised by the application program. Bit 0 Unimplemented, read as “0” Bit 7~5 Rev. 2.10 185 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains several external interrupt and internal interrupts functions. The external interrupts are generated by the action of the external INT0~INT3 and PINT pins, while the internal interrupts are generated by various internal functions such as the TMs, Comparators, Time Base, LVD, EEPROM and SIM. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The number of registers depends upon the device chosen but fall into three categories. The first is the INTC0~INTC3 registers which setup the primary interrupts, the second is the MFI0~MFI3 registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "E" for enable/disable bit or "F" for request flag. Function Enable Bit Request Flag EMI — Comparator CPnE CPnF n=0 or 1 INTn Pin INTnE INTnF n=0~3 Multi-function MFnE MFnF n=0~5 Time Base TBnE TBnF n=0 or 1 SIM SIME SIMF — LVD LVE LVF — EEPROM DEE DEF — PINT Pin XPE XPF — TnPE TnPF TnAE TnAF TnBE TnBF Global TM Notes — n=0~3 Interrupt Register Bit Naming Conventions Rev. 2.10 186 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Interrupt Register Contents • HT68F20 Name Bit 7 6 5 4 3 2 1 0 INT0S0 INTEG — — — — INT1S1 INT1S0 INT0S1 INTC0 — CP0F INT1F INT0F CP0E INT1E INT0E EMI INTC1 — MF1F MF0F CP1F — MF1E MF0E CP1E INTC2 MF3F TB1F TB0F MF2F MF3E TB1E TB0E MF2E MFI0 — — T0AF T0PF — — T0AE T0PE MFI1 — — T1AF T1PF — — T1AE T1PE MFI2 DEF LVF XPF SIMF DEE LVE XPE SIME 7 6 5 4 3 2 1 0 INT0S0 • HT68F30 Name Bit INTEG — — — — INT1S1 INT1S0 INT0S1 INTC0 — CP0F INT1F INT0F CP0E INT1E INT0E EMI INTC1 — MF1F MF0F CP1F — MF1E MF0E CP1E INTC2 MF3F TB1F TB0F MF2F MF3E TB1E TB0E MF2E MFI0 — — T0AF T0PF — — T0AE T0PE MFI1 — T1BF T1AF T1PF — T1BE T1AE T1PE MFI2 DEF LVF XPF SIMF DEE LVE XPE SIME • HT68F40 Name Rev. 2.10 Bit 7 6 5 4 3 2 1 0 INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0 INTC0 — CP0F INT1F INT0F CP0E INT1E INT0E EMI INTC1 — MF1F MF0F CP1F — MF1E MF0E CP1E INTC2 MF3F TB1F TB0F MF2F MF3E TB1E TB0E MF2E MFI0 T2AF T2PF T0AF T0PF T2AE T2PE T0AE T0PE MFI1 — T1BF T1AF T1PF — T1BE T1AE T1PE MFI2 DEF LVF XPF SIMF DEE LVE XPE SIME 187 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • HT68F50 Name Bit 7 6 5 4 3 2 1 0 INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0 INTC0 — CP0F INT1F INT0F CP0E INT1E INT0E EMI INTC1 — MF1F MF0F CP1F — MF1E MF0E CP1E INTC2 MF3F TB1F TB0F MF2F MF3E TB1E TB0E MF2E MFI0 T2AF T2PF T0AF T0PF T2AE T2PE T0AE T0PE MFI1 — T1BF T1AF T1PF — T1BE T1AE T1PE MFI2 DEF LVF XPF SIMF DEE LVE XPE SIME MFI3 — — T3AF T3PF — — T3AE T3PE 7 6 5 4 3 2 1 0 INTEG INT3S1 INT3S0 INT2S1 INT2S0 INT1S1 INT1S0 INT0S1 INT0S0 INTC0 — INT2F INT1F INT0F INT2E INT1E INT0E EMI INTC1 MF0F CP1F CP0F INT3F MF0E CP1E CP0E INT3E INTC2 — MF3F MF2F MF1F — MF3E MF2E MF1E INTC3 MF5F TB1F TB0F MF4F MF5E TB1E TB0E MF4E MFI0 T2AF T2PF T0AF T0PF T2AE T2PE T0AE T0PE MFI1 — T1BF T1AF T1PF — T1BE T1AE T1PE MFI2 DEF LVF XPF SIMF DEE LVE XPE SIME MFI3 — — T3AF T3PF — — T3AE T3PE • HT68F60 Name Rev. 2.10 Bit 188 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM INTEG Register • HT68F20/HT68F30/HT68F40/HT68F50 Bit 7 6 5 4 3 2 1 0 Name — — — — INT1S1 INT1S0 INT0S1 INT0S0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3~2 INT1S1, INT1S0: interrupt edge control for INT1 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges Bit 1~0 INT0S1, INT0S0: interrupt edge control for INT0 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges • HT68F60 Rev. 2.10 Bit 7 6 5 4 3 2 1 0 Name INT3S1 INT3S0 INT2S1 INT2S0 INT1S1 INT1S0 INT0S1 INT0S0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 INT3S1, INT3S0: Interrupt edge control for INT3 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges Bit5~4 INT2S1, INT2S0: interrupt edge control for INT2 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges Bit 3~2 INT1S1, INT1S0: interrupt edge control for INT1 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges Bit 1~0 INT0S1, INT0S0: interrupt edge control for INT0 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges 189 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM INTC0 Register • HT68F20/HT68F30/HT68F40/HT68F50 Bit 7 6 5 4 3 2 1 0 Name — CP0F INT1F INT0F CP0E INT1E INT0E EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as “0” Bit 6CP0F: Comparator 0 interrupt request flag 0: No request 1: Interrupt request Bit 5INT1F: INT1 interrupt request flag 0: No request 1: Interrupt request Bit 4INT0F: INT0 interrupt request flag 0: No request 1: Interrupt request Bit 3CP0E: Comparator 0 interrupt control 0: Disable 1: Enable Bit 2INT1E: INT1 interrupt control 0: Disable 1: Enable Bit 1INT0E: INT0 interrupt control 0: Disable 1: Enable Bit 0EMI: Global interrupt control 0: Disable 1: Enable Rev. 2.10 190 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • HT68F60 Bit 7 6 5 4 3 2 1 0 Name — INT2F INT1F INT0F INT2E INT1E INT0E EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as “0” Bit 6INT2F: INT2 interrupt request flag 0: No request 1: Interrupt request Bit 5INT1F: INT1 interrupt request flag 0: No request 1: Interrupt request Bit 4INT0F: INT0 interrupt request flag 0: No request 1: Interrupt request Bit 3INT2E: INT2 interrupt control 0: Disable 1: Enable Bit 2INT1E: INT1 interrupt control 0: Disable 1: Enable Bit 1INT0E: INT0 interrupt control 0: Disable 1: Enable Bit 0EMI: Global interrupt control 0: Disable 1: Enable Rev. 2.10 191 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM INTC1 Register • HT68F20/HT68F30/HT68F40/HT68F50 Bit 7 6 5 4 3 2 1 0 Name — MF1F MF0F CP1F — MF1E MF0E CP1E R/W — R/W R/W R/W — R/W R/W R/W POR — 0 0 0 — 0 0 0 Bit 7 Unimplemented, read as “0” Bit 6MF1F: Multi-function Interrupt 1 Request Flag 0: No request 1: Interrupt request Bit 5MF0F: Multi-function Interrupt 0 Request Flag 0: No request 1: Interrupt request Bit 4CP1F: Comparator 1 Interrupt Request Flag 0: No request 1: Interrupt request Bit 3 Unimplemented, read as “0” Bit 2MF1E: Multi-function Interrupt 1 Control 0: Disable 1: Enable Bit 1MF0E: Multi-function Interrupt 0 Control 0: Disable 1: Enable Bit 0CP1E: Comparator 1 Interrupt Control 0: Disable 1: Enable Rev. 2.10 192 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • HT68F60 Bit 7 6 5 4 3 2 1 0 Name MF0F CP1F CP0F INT3F MF0E CP1E CP0E INT3E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7MF0F: Multi-function Interrupt 0 Request Flag 0: No request 1: Interrupt request Bit 6CP1F: Comparator 1 Interrupt Request Flag 0: No request 1: Interrupt request Bit 5CP0F: Comparator 0 Interrupt Request Flag 0: No request 1: Interrupt request Bit 4INT3F: INT3 Interrupt Request Flag 0: No request 1: Interrupt request Bit 3MF0E: Multi-function Interrupt 0 Control 0: Disable 1: Enable Bit 2CP1E: Comparator 1 Interrupt Control 0: Disable 1: Enable Bit 1CP0E: Comparator 0 Interrupt Control 0: Disable 1: Enable Bit 0INT3E: INT3 Interrupt Control 0: Disable 1: Enable Rev. 2.10 193 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM INTC2 Register • HT68F20/HT68F30/HT68F40/HT68F50 Bit 7 6 5 4 3 2 1 0 Name MF3F TB1F TB0F MF2F MF3E TB1E TB0E MF2E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7MF3F: Multi-function Interrupt 3 Request Flag 0: No request 1: Interrupt request Bit 6TB1F: Time Base 1 Interrupt Request Flag 0: No request 1: Interrupt request Bit 5TB0F: Time Base 0 Interrupt Request Flag 0: No request 1: Interrupt request Bit 4MF2F: Multi-function Interrupt 2 Request Flag 0: No request 1: Interrupt request Bit 3MF3E: Multi-function Interrupt 3 Control 0: Disable 1: Enable Bit 2TB1E: Time Base 1 Interrupt Control 0: Disable 1: Enable Bit 1TB0E: Time Base 0 Interrupt Control 0: Disable 1: Enable Bit 0MF2E: Multi-function Interrupt 2 Control 0: Disable 1: Enable Rev. 2.10 194 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • HT68F60 Bit 7 6 5 4 3 2 1 0 Name — MF3F MF2F MF1F — MF3E MF2E MF1E R/W — R/W R/W R/W — R/W R/W R/W POR — 0 0 0 — 0 0 0 Bit 7 Unimplemented, read as “0” Bit 6MF3F: Multi-function Interrupt 3 Request Flag 0: No request 1: Interrupt request Bit 5MF2F: Multi-function Interrupt 2 Request Flag 0: No request 1: Interrupt request Bit 4MF1F: Multi-function Interrupt 1 Request Flag 0: No request 1: Interrupt request Bit 3 Unimplemented, read as “0” Bit 2MF3E: Multi-function Interrupt 3 Control 0: Disable 1: Enable Bit 1MF2E: Multi-function Interrupt 2 Control 0: Disable 1: Enable Bit 0MF1E: Multi-function Interrupt 1 Control 0: Disable 1: Enable Rev. 2.10 195 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM INTC3 Register • HT68F60 Bit 7 6 5 4 3 2 1 0 Name MF5F TB1F TB0F MF4F MF5E TB1E TB0E MF4E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7MF5F: Multi-function interrupt 5 request flag 0: No request 1: Interrupt request Bit 6TB1F: Time Base 1 interrupt request flag 0: No request 1: Interrupt request Bit 5TB0F: Time Base 0 interrupt request flag 0: No request 1: Interrupt request Bit 4MF4F: Multi-function interrupt 4 request flag 0: No request 1: Interrupt request Bit 3MF5E: Multi-function interrupt 5 control 0: Disable 1: Enable Bit 2TB1E: Time Base 1 interrupt control 0: Disable 1: Enable Bit 1TB0E: Time Base 0 interrupt control 0: Disable 1: Enable Bit 0MF4E: Multi-function interrupt 4 control 0: Disable 1: Enable MFI0 Register • HT68F20/HT68F30 Bit 7 6 5 4 3 2 1 0 Name — — T0AF T0PF — — T0AE T0PE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5T0AF: TM0 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4T0PF: TM0 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as “0” Bit 1T0AE: TM0 Comparator A match interrupt control 0: Disable 1: Enable Bit 0T0PE: TM0 Comparator P match interrupt control 0: Disable 1: Enable Rev. 2.10 196 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • HT68F40/HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name T2AF T2PF T0AF T0PF T2AE T2PE T0AE T0PE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7T2AF: TM2 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 6T2PF: TM2 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 5T0AF: TM0 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4T0PF: TM0 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3T2AE: TM2 Comparator A match interrupt control 0: Disable 1: Enable Bit 2T2PE: TM2 Comparator P match interrupt control 0: Disable 1: Enable Bit 1T0AE: TM0 Comparator A match interrupt control 0: Disable 1: Enable Bit 0T0PE: TM0 Comparator P match interrupt control 0: Disable 1: Enable Rev. 2.10 197 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM MFI1 Register • HT68F20 Bit 7 6 5 4 3 2 1 0 Name — — T1AF T1PF — — T1AE T1PE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5T1AF: TM1 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4T1PF: TM1 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as “0” Bit 1T1AE: TM1 Comparator A match interrupt control 0: Disable 1: Enable Bit 0T1PE: TM1 Comparator P match interrupt control 0: Disable 1: Enable • HT68F30/HT68F40/HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name — T1BF T1AF T1PF — T1BE T1AE T1PE R/W — R/W R/W R/W — R/W R/W R/W POR — 0 0 0 — 0 0 0 Bit 7 Unimplemented, read as “0” Bit 6T1BF: TM1 Comparator B match interrupt request flag 0: No request 1: Interrupt request Bit 5T1AF: TM1 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4T1PF: TM1 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3 Unimplemented, read as “0” Bit 2T1BE: TM1 Comparator B match interrupt control 0: Disable 1: Enable Bit 1T1AE: TM1 Comparator A match interrupt control 0: Disable 1: Enable Bit 0T1PE: TM1 Comparator P match interrupt control 0: Disable 1: Enable Rev. 2.10 198 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM MFI2 Register Bit 7 6 5 4 3 2 1 0 Name DEF LVF XPF SIMF DEE LVE XPE SIME R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7DEF: Data EEPROM interrupt request flag 0: No request 1: Interrupt request Bit 6LVF: LVD interrupt request flag 0: No request 1: Interrupt request Bit 5XPF: External peripheral interrupt request flag 0: No request 1: Interrupt request Bit 4SIMF: SIM interrupt request flag 0: No request 1: Interrupt request Bit 3DEE: Data EEPROM Interrupt Control 0: Disable 1: Enable Bit 2LVE: LVD Interrupt Control 0: Disable 1: Enable Bit 1XPE: External Peripheral Interrupt Control 0: Disable 1: Enable Bit 0SIME: SIM Interrupt Control 0: Disable 1: Enable MFI3 Register • HT68F50/HT68F60 Bit 7 6 5 4 3 2 1 0 Name — — T3AF T3PF — — T3AE T3PE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5T3AF: TM3 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4T3PF: TM3 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as “0” Bit 1T3AE: TM3 Comparator A match interrupt control 0: Disable 1: Enable Bit 0T3PE: TM3 Comparator P match interrupt control 0: Disable 1: Enable Rev. 2.10 199 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P, Comparator A or Comparator B match etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a "JMP" which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a "RETI", which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. Rev. 2.10 200 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM EMI a�to disab�ed in ISR Legend g xxF Req�est F�ag – no a�to reset in ISR xxF Req�est F�ag – a�to reset in ISR xxE Enab�e Bit Interr�pt Name Interr�pt Req�est Name F�ags Enab�e Bits Master Enab�e Vector INT0 Pin INT0F INT0E EMI 0�H INT1 Pin INT1F INT1E EMI 08H Comp. 0 CP0F CP0E EMI 0CH Comp. 1 CP1F CP1E EMI 10H Req�est F�ags Enab�e Bits TM0 P T0PF T0PE TM0 A T0AF T0AE M. F�nct. 0 MF0F MF0E EMI 1�H TM1 P T1PF T1PE M. F�nct. 1 MF1F MF1E EMI 18H TM1 A T1AF T1AE TM1 B T1BF T1BE SIM SIMF M. F�nct. 2 MF2F MF2E EMI 20H Time Base 0 TB0F TB0E EMI 2�H Time Base 1 TB1F TB1E EMI 28H M. F�nct. 3 MF3F MF3E EMI 2CH PINT Pin LVD EEPROM XPF SIME XPE LVF LVE DEF DEE Priorit� High Low Interr�pts contained within M��ti-F�nction Interr�pts HT66F30 on�� Interrupt Structure – HT68F20/HT68F30 Rev. 2.10 201 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM EMI a�to disab�ed in ISR Legend xxF Req�est F�ag – no a�to reset in ISR Interr�pt Name Req�est F�ags Enab�e Bits Master Enab�e Vector xxF Req�est F�ag – a�to reset in ISR INT0 Pin INT0F INT0E EMI 0�H xxE Enab�e Bit INT1 Pin INT1F INT1E EMI 08H Comp. 0 CP0F CP0E EMI 0CH Comp. 1 CP1F CP1E EMI 10H M. F�nct. 0 MF0F MF0E EMI 1�H M. F�nct. 1 MF1F MF1E EMI 18H M. F�nct. 2 MF2F MF2E EMI 20H Time Base 0 TB0F TB0E EMI 2�H Time Base 1 TB1F TB1E EMI 28H MF3F MF3E EMI 2CH Interr�pt Name Req�est F�ags Enab�e Bits TM0 P TP0AF T0PE TM0 A TP0AF T0AE TM2 P T2PF T2PE TM2 A T2AF T2AE TM1 P T1PF T1PE TM1 A T1AF T1AE TM1 B T1BF T1BE TM3 P T3PF T3PE TM3 A T3AF T3AE SIM PINT Pin LVD EEPROM SIMF XPF SIME XPE LVF LVE DEF DEE M. F�nct. 3 Priorit High Low Interr�pts contained within M��ti-F�nction Interr�pts HT66F50 on�� Interrupt Structure – HT68F40/HT68F50 Rev. 2.10 202 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM EMI a�to disab�ed in ISR Legend xxF Req�est F�ag – no a�to reset in ISR xxF Req�est F�ag – a�to reset in ISR xxE Enab�e Bit Interr�pt Name Req�est F�ags Enab�e Bits TM0 P T0PF T0PE TM0 A T0AF T0AE TM1 P T1PF T1PE TM1 A T1AF T1AE TM1 B T1BF T1BE TM2 P T2PF T2PE TM2 A T2AF T2AE TM3 P T3PF T3PE TM3 A T3AF T3AE SIM SIMF PINT Pin LVD EEPROM XPF SIME XPE LVF LVE DEF DEE Interr�pt Name Req�est F�ags Enab�e Bits Master Enab�e INT0 Pin INT0F INT0E EMI 0�H INT1 Pin INT1F INT1E EMI 08H INT2 Pin INT2F INT2E EMI 0CH INT3 Pin INT3F INT3E EMI 10H Comp. 0 CP0F CP0E EMI 1�H Comp. 1 CP1F CP1E EMI 18H M. F�nct. 0 MF0F MF0E EMI 1CH M. F�nct. 1 MF1F MF1E EMI 20H M. F�nct. 2 MF2F MF2E EMI 2�H M. F�nct. 3 MF3F MF3E EMI 28H MF�F MF�E EMI 30H Time Base 0 TB0F TB0E EMI 3�H Time Base 1 TB1F TB1E EMI 38H M. F�nct. 5 MF5F MF5E EMI 3CH M. F�nct. � Vector Priorit� High Low Interr�pts contained within M��ti-F�nction Interr�pts Interrupt Structure – HT68F60 Rev. 2.10 203 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM External Interrupt The external interrupts are controlled by signal transitions on the pins INT0~INT3. An external interrupt request will take place when the external interrupt request flags, INT0F~INT3F, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E~INT3E, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flags, INT0F~INT3F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Comparator Interrupt The comparator interrupt is controlled by the two internal comparators. A comparator interrupt request will take place when the comparator interrupt request flags, CP0F or CP1F, are set, a situation that will occur when the comparator output changes state. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and comparator interrupt enable bits, CP0E and CP1E, must first be set. When the interrupt is enabled, the stack is not full and the comparator inputs generate a comparator output transition, a subroutine call to the comparator interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flags, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Rev. 2.10 204 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Multi-function Interrupt Within these devices there are up to six Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM Interrupts, SIM Interrupt, External Peripheral Interrupt, LVD interrupt and EEPROM Interrupt. A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags, MF0F~MF5F are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related MultiFunction request flag, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts, namely the TM Interrupts, SIM Interrupt, External Peripheral Interrupt, LVD interrupt and EEPROM Interrupt will not be automatically reset and must be manually reset by the application program. Time Base Interrupts The function of the Time Base Interrupts is to provide regular time signal in the form of an internal interrupt. They are controlled by the overflow signals from their respective timer functions. When these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to their respective vector locations will take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their clock sources originate from the internal clock source fTB. This fTB input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges. The clock source that generates fTB, which in turn controls the Time Base interrupt period, can originate from several different sources, as shown in the System Operating Mode section. Rev. 2.10 205 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM TBC Register Bit 7 6 5 4 3 2 1 0 Name TBON TBCK TB11 TB10 LXTLP TB02 TB01 TB00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 1 1 0 1 1 1 Bit 7TBON: TB0 and TB1 Control 0: Disable 1: Enable Bit 6TBCK: Select fTB Clock 0: fTBC 1: fSYS/4 Bit 5~4TB11~TB10: Select Time Base 1 Time-out Period 00: 4096/fTB 01: 8192/fTB 10: 16384/fTB 11: 32768/fTB Bit 3LXTLP: LXT Low Power Control 0: Disable 1: Enable Bit 2~0TB02~TB00: Select Time Base 0 Time-out Period 000: 256/fTB 001: 512/fTB 010: 1024/fTB 011: 2048/fTB 100: 4096/fTB 101: 8192/fTB 110: 16384/fTB 111: 32768/fTB Time Base Interrupt Rev. 2.10 206 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Serial Interface Module Interrupt The Serial Interface Module Interrupt, also known as the SIM interrupt, is contained within the Multi-function Interrupt. A SIM Interrupt request will take place when the SIM Interrupt request flag, SIMF, is set, which occurs when a byte of data has been received or transmitted by the SIM interface. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface Interrupt enable bit, SIME, and Muti-function interrupt enable bits, must first be set. When the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the SIM interface, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the Serial Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the SIMF flag will not be automatically cleared, it has to be cleared by the application program. External Peripheral Interrupt The External Peripheral Interrupt operates in a similar way to the external interrupt and is contained within the Multi-function Interrupt. A Peripheral Interrupt request will take place when the External Peripheral Interrupt request flag, XPF, is set, which occurs when a negative edge transition appears on the PINT pin. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, external peripheral interrupt enable bit, XPE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a negative transition appears on the External Peripheral Interrupt pin, a subroutine call to the respective Multi-function Interrupt, will take place. When the External Peripheral Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the XPF flag will not be automatically cleared, it has to be cleared by the application program. The external peripheral interrupt pin is pin-shared with several other pins with different functions. It must therefore be properly configured to enable it to operate as an External Peripheral Interrupt pin. EEPROM Interrupt The EEPROM Interrupt, is contained within the Multi-function Interrupt. An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs when an EEPROM Write or Read cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, EEPROM Interrupt enable bit, DEE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write or Read cycle ends, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the EEPROM Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the DEF flag will not be automatically cleared, it has to be cleared by the application program. Rev. 2.10 207 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the Multi-function Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically cleared, it has to be cleared by the application program. TM Interrupts The Compact and Standard Type TMs have two interrupts each, while the Enhanced Type TM has three interrupts. All of the TM interrupts are contained within the Multi-function Interrupts. For each of the Compact and Standard Type TMs there are two interrupt request flags TnPF and TnAF and two enable bits TnPE and TnAE. For the Enhanced Type TM there are three interrupt request flags TnPF, TnAF and TnBF and three enable bits TnPE, TnAE and TnBE. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P, A or B match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Rev. 2.10 208 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MF0F~MF5F, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the "CALL" instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Rev. 2.10 209 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Power Down Mode and Wake-up Entering the IDLE or SLEEP Mode There is only one way for the device to enter the SLEEP or IDLE Mode and that is to execute the "HALT" instruction in the application program. When this instruction is executed, the following will occur: • The system clock will be stopped and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT clock source is selected to come from the fSUB clock source and the WDT is enabled. The WDT will stop if its clock source originates from the system clock. • The I/O ports will maintain their present condition. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the configuration options have enabled the LIRC oscillator. Rev. 2.10 210 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external reset • An external falling edge on Port A • A system interrupt • A WDT overflow If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the "HALT" instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HALT" instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Rev. 2.10 211 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Low Voltage Detector – LVD Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be detemined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Bit 7 6 5 4 3 2 1 0 Name — — LVDO LVDEN — VLVD2 VLVD1 VLVD0 R/W — — R R/W — R/W R/W R/W POR — — 0 0 — 0 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5LVDO: LVD Output Flag 0: No Low Voltage Detect 1: Low Voltage Detect Bit 4LVDEN: Low Voltage Detector Control 0: Disable 1: Enable Bit 3 Unimplemented, read as “0” Bit 2~0VLVD2~VLVD0: Select LVD Voltage 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.4V Rev. 2.10 212 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.4V. When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multi-function interrupts, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set high by a low voltage condition. When the device is powered down the Low Voltage Detector will remain active if the LVDEN bit is high. In this case, the LVF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is not required then the LVF flag should be first set high before the device enters the SLEEP or IDLE Mode. Rev. 2.10 213 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM SCOM Function for LCD The devices have the capability of driving external LCD panels. The common pins for LCD driving, SCOM0~SCOM3, are pin shared with certain pin on the PC0~PC3 or PC0~PC1, PC6~PC7 port. The LCD signals (COM and SEG) are generated using the application program. LCD Operation An external LCD panel can be driven using this device by configuring the PC0~PC3 or PC0~PC1, PC6~PC7 pins as common pins and using other output ports lines as segment pins. The LCD driver function is controlled using the SCOMC register which in addition to controlling the overall on/off function also controls the bias voltage setup function. This enables the LCD COM driver to generate the necessary VDD/2 voltage levels for LCD 1/2 bias operation. The SCOMEN bit in the SCOMC register is the overall master control for the LCD driver, however this bit is used in conjunction with the COMnEN bits to select which Port C pins are used for LCD driving. Note that the Port Control register does not need to first setup the pins as outputs to enable the LCD driver operation. LCD COM Bias SCOMEN COMnEN Pin Function O/P Level 0 × I/O 0 or 1 1 0 I/O 0 or 1 1 1 SCOMn VDD/2 Output Control Rev. 2.10 214 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM LCD Bias Control The LCD COM driver enables a range of selections to be provided to suit the requirement of the LCD panel which is being used. The bias resistor choice is implemented using the ISEL1 and ISEL0 bits in the SCOMC register. SCOMC Register • HT68F20 Bit 7 6 5 Name D7 ISEL1 ISEL0 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 SCOMEN COM3EN COM2EN COM1EN COM0EN Bit 7 Reserved Bit 0: Correct level – bit must be reset to zero for correct operation 1: Unpredictable operation – bit must not be set high Bit 6~5 ISEL1, ISEL0: Select SCOM typical bias current (VDD=5V) 00: 25μA 01: 50μA 10: 100μA 11: 200μA Bit 4SCOMEN: SCOM module Control 0: Disable 1: Enable Bit 3COM3EN: PC3 or SCOM3 selection 0: GPIO 1: SCOM3 Bit 2COM2EN: PC2 or SCOM2 selection 0: GPIO 1: SCOM2 Bit 1COM1EN: PC1 or SCOM1 selection 0: GPIO 1: SCOM1 Bit 0COM0EN: PC0 or SCOM0 selection 0: GPIO 1: SCOM0 Rev. 2.10 215 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • HT68F30/HT68F40/HT68F50/HT68F60 Bit 7 6 5 Name D7 ISEL1 ISEL0 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 SCOMEN COM3EN COM2EN COM1EN COM0EN Bit 7 Reserved Bit 0: Correct level – bit must be reset to zero for correct operation 1: Unpredictable operation – bit must not be set high Bit 6~5 ISEL1, ISEL0: Select SCOM typical bias current (VDD=5V) 00: 25μA 01: 50μA 10: 100μA 11: 200μA Bit 4SCOMEN: SCOM module control 0: Disable 1: Enable Bit 3COM3EN: PC7 or SCOM3 selection 0: GPIO 1: SCOM3 Bit 2COM2EN: PC6 or SCOM2 selection 0: GPIO 1: SCOM2 Bit 1COM1EN: PC1 or SCOM1 selection 0: GPIO 1: SCOM1 Bit 0COM0EN: PC0 or SCOM0 selection 0: GPIO 1: SCOM0 Rev. 2.10 216 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Configuration Options Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. All options must be defined for proper system function, the details of which are shown in the table. No. Options Oscillator Options 1 High speed system oscillator selection – fH: 1. HXT 2. ERC 3. HIRC 2 Low speed system oscillator selection – fL: 1. LXT 2. LIRC 3 WDT clock selection – fS: 1. fSUB 2. fSYS/4 4 HIRC frequency selection: 1. 4MHz 2. 8MHz 3. 12MHz Note: The fSUB and the fTBC clock source are LXT or LIRC selection by the fL configuration option. Reset Pin Options 5 PB0/RES pin options: 1. RES pin 2. I/O pin Watchdog Options 6 Watchdog Timer function: 1. Enable 2. Disable 7 CLR WDT instructions selection: 1. 1 instruction 2. 2 instructions LVR Options 8 LVR function: 1. Enable 2. Disable 9 LVR voltage selection: 1. 2.10V 2. 2.55V 3. 3.15V 4. 4.20V SIM Options Rev. 2.10 10 SIM function: 1. Enable 2. Disable 11 SPI – WCOL bit: 1. Enable 2. Disable 12 SPI - CSEN bit: 1. Enable 2. Disable 217 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM No. Options I2C debounce time selection: 1. No debounce 2. 2 system clock debounce 3. 4 system clock debounce 13 Application Circuits Note: "*" It is recommended that this component is added for added ESD protection. "**" It is recommended that this component is added in environments where power line noise is significant. Rev. 2.10 218 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM UART Module Serial Interface UART Module Features • Interconnected to Holtek MCU via SPI interface • Full-duplex, Universal Asynchronous Receiver and Transmitter (UART) communication ♦♦ 8 or 9 bits character length ♦♦ Even, odd or no parity options ♦♦ One or two stop bits ♦♦ Baud rate generator with 8-bit prescaler ♦♦ Parity, framing, noise and overrun error detection ♦♦ Support for interrupt on address detect ♦♦ Address Detect Interrupt - last character bit=1 ♦♦ Transmitter and receiver enabled independently ♦♦ 4-byte deep FIFO receiver data buffer ♦♦ Transmit and Receive Multiple Interrupt Generation Sources: ––Transmitter Empty ––Transmitter Idle ––Receiver Full ––Receiver Overrun ––Address Mode Detect ♦♦ TX pin is high impedance when the UART transmit module is disabled ♦♦ RX pin is high impedance when the UART receive module is disabled • CMOS clock input, CLKI, up to 20MHz at 5V operating voltage UART Module Overview The device contains a fully embedded full-duplex asynchronous serial communications UART interface that enables data transmission and data reception with external devices. Possible applications could include data communication networks between microcontrollers, low-cost data links between PCs and peripheral devices, portable and battery operated device communication, factory automation and process control to name but a few. UART Module Block Diagram Rev. 2.10 219 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Pin Assignment 220 Rev. 2.10 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Rev. 2.10 221 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM UART Module Pin Description Pin Name I/O Description RX I UART RX serial data input pin If UARTEN=1 and RXEN=1, then RX is the UART serial data input If UARTEN=0 or RXEN=0, then RX is high impedance TX O UART TX serial data output pin If UARTEN=1 and TXEN=1, then TX is the UART serial data output If UARTEN=0 or TXEN=0, then TX is high impedance SDI I Slave SPI Serial Data In Input Signal Internally connected to the MCU Master SPI SDO output signal SDO O Slave SPI Serial Data Out Output Signal Internally connected to the MCU Master SPI SDI input signal SCK I Slave SPI Serial Clock Input Signal Internally connected to the MCU Master SPI SCK output signal SCS I Slave SPI Device Select Input Signal Internally connected to the MCU Master SPI SCS output signal – connected to pull high resistor CLKI I Clock Input Signal Internally connected to the MCU Master PCK output signal PINT O UART Interrupt Output Signal Internally connected to the MCU Master PINT input signal A UART related interrupt will generate a low pulse signal on this line NC — Implies that the pin is Not Connected and can therefore not be used Note: The pin description for all pins with the exception of the UART TX and RX pins are described in the preceding MCU section. Rev. 2.10 222 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM UART Module D.C. Characteristics Ta=25°C Symbol Min. Typ. Max. Unit fCLKI=12MHz, SCK=fCLKI/4, Output no load — — 1.0 mA 5.0V fCLKI=16MHz, SCK=fCLKI/4, Output no load — — 2.0 mA 2.2V fCLKI=6MHz, SCK=fCLKI/4, Output no load — — 4.2 mA 5.0V fCLKI=12MHz, SCK=fCLKI/4, Output no load — — 4.8 mA ISTB fCLKI=16MHz, SCK=fCLKI/4, SCS=VDD, UARTEN=0, Standby Current * 5.0V TXEN=1, RXEN=1, (SPI disabled, UART disabled) SDI=H, RX=H, Output no load — — 0.6 μA VIL Input Low Voltage for RX Ports — — 0 — 0.3VDD V VIH Input High Voltage for RX Ports — — 0.7VDD — VDD V 2.5 5.0 — mA 10.0 25.0 — mA -1.5 -3.0 — mA -5.0 -8.0 — mA 20 60 100 kΩ 10 30 50 kΩ IDD1 IDD2 IOL Parameter Test Conditions Operating Current * (SPI Enabled, UART disabled) Operating Current * (SPI enabled, UART enabled) TX Port Sink Current VDD Conditions 3.0V 3.0V 5.0V 3.0V IOH RX Port Source Current RPH Pull-high Resistance for SCS 3.0V only 5.0V 5.0V VO=0.1VDD VO=0.9VDD — Note: "*" The operating current IDD1 listed here is the additional current consumed when the slave SPI interface in the UART module is enabled and the UART interface is disabled. Similarly, the operating current IDD2 here is the additional current consumed when both the slave SPI interface and UART interface are enabled. If the UART module is enabled, either IDD1 or IDD2 should be added to calculate the relevant operating current of the device for different conditions. To calculate the standby current for the whole device, the standby current shown above should be taken into account. Rev. 2.10 223 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM UART Module A.C. Characteristics Ta=25°C Symbol Parameter tCP SCK Period (tCH+tCL) tCH SCK High Time tCL SCK Low Time Test Conditions Min. Typ. Max. Unit — 62.5 — — ns — 50.0 — — ns 3.0V — 28 — — ns 5.0V — 22 — — ns 3.0V — 28 — — ns 5.0V — 22 — — ns 3.0V — 500 — — ns 5.0V — 400 — — ns VDD Parameter 3.0V 5.0V tCSW SCS High Pulse Width tCSS SCS to SCK Setup Time — — 100 — — ns tCSH SCS to SCK Hold Time — — 0 — — ns tSDS SDI to SCK Setup Time — — 100 — — ns tSDH SDI to SCK Hold Time — — 0 — — ns tR SPI Output Rise Time — — — 10 — ns tF SPI Output Fall Time — — — 10 — ns tW SPI Data Output Delay Time — — 0 — — ns UART Module Functional Description The embedded UART Module is full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. Interconnection between the MCU and the UART module is implemented by internally connecting the MCU Master SPI interface to the UART Slave SPI interface. All data transmissions and receptions between MCU and UART module including UART commands are conducted along this interconnected SPI interface. The UART function control is executed by the MCU using its SPI Master serial interface. The UART module contains its own independent interrupt which can be used to indicate when a data reception occurs or when a data transmission has terminated. Rev. 2.10 224 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM UART Module Internal Signal In addition to the TX and RX external pins described above there are other MCU to UART Module interconnecting lines that are described in the following table. Note that these lines are internal to the device and are not bonded to external pins. MCU to UART Internal Connection Note: PCK output frequency must be ≤ 12MHz. UART Module SPI Interface The MCU communicates with the UART Module via an internal SPI interface. The SPI interface on this device is comprised of four signals: SCS (SPI Chip Select), SCK (SPI Clock), SDI (Serial Data Input) and SDO (Serial Data Output). The SPI master, which is the MCU, asserts SCS by pulling it low to start the data transaction cycle. When the first 8 bits of data are transmitted, SCS should not return to a high level. Instead, SCS must remain at a low level until the whole 16-bit data transaction is completed. If SCS is de-asserted, that is returned to a high level before the 16-bit data transaction is completed, all data bits will be discarded by the UART Module SPI slave. SPI Timing Both read and write operations are conducted along the SPI common interface with the following format: • Write Type Format: 8-bit command input + 8-bit data input • Read Type Format: 8-bit command input + 8-bit data output SCS SCK SDI A7 A6 A5 A� A3 A2 A1 A0 D7 D6 D5 D� D3 D2 D1 D0 SDO Writing Type Format: 8-bit Command Input + 8-bit Data Input Rev. 2.10 225 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM SCS tw SCK SDI A7 A6 A5 A� A3 A2 A1 A0 SDO D7 D6 D5 D� D3 D2 D1 D0 Reading Type Format: 8-bit Command Input + 8-bit Data Output To initiate a data transaction, the MCU master SPI needs to pull SCS to a low level first and then also pull SCK low. The input data bit on SDI should be stable before the next SCK rising edge, as the device will latch the SDI status on the next SCK rising edge. Regarding the SDO line, the output data bit will be updated on the SCK falling edge. The master needs to obtain the line status before the next SCK falling edge. There are 16 bits of data transmitted and/or received by the SPI interface for each transaction. Each transaction consists of a command phase and a data phase. When SCS is high, the SPI interface is disabled and SDO will be set to a high impedance state. After a complete transaction has been implemented, which requires 16 SCK clock cycles, the master needs to set SCS to a high level in preparation for the next data transaction. For write operations, the device will begin to execute the command only after it receives a 16-bit serial data sequence and when the SCS has been set high again by the master. For read operations, the device will begin to execute the command only after it receives an 8-bit read command after which it will be ready to output data. If necessary, the master can de-assert the SCS pin to abort the transaction at any time which will cause any data transactions to be abandoned. UART Module External Pin Interfacing To communicate with an external serial interface, the internal UART has two external pins known as TX and RX. The TX pin is the UART transmitter serial data output pin if the corresponding control bits named UARTEN in UCR1 register and TXEN in UCR2 register are set to 1. If the control bit UARTEN or TXEN is equal to zero, the TX pin is in the state of high impedance. Similarly, the RX pin is the UART receiver serial data input pin if the corresponding control bits named UARTEN and RXEN in UCR1 and UCR2 registers are set to 1. If the control bit UARTEN or RXEN is equal to zero, the RX pin is in the state of high impedance. Rev. 2.10 226 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM UART Data Transfer Scheme The following block diagram shows the overall data transfer structure arrangement for the UART. The actual data to be transmitted from the MCU is first transferred to the TXR register by the application program. The data will then be transferred to the Transmitter Shift Register named TSR from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only the TXR register is accessible to the application program, the Transmitter Shift Register is not mapped into the Data Memory area and is inaccessible to the application program. Data to be received by the UART is accepted on the external RX pin, from where it is shifted in, LSB first, to the Receiver Shift Register named RSR at a rate controlled by the Baud Rate Generator. When the shift register is full, the data will then be transferred from the shift register to the internal RXR register, where it is buffered and can be manipulated by the application program. Only the RXR register is accessible to the application program, the Receiver Shift Register is not mapped into the Data Memory area and is inaccessible to the application program. It should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate TXR and RXR registers, only exists as a single shared register physically. This shared register known as the TXR/RXR register is used for both data transmission and data reception. Transmitter Shift Register (TSR) MSB ………………………… LSB TX Pin RX Pin Receiver Shift Register (RSR) MSB ………………………… LSB B�ffer 3 B�ffer 2 B�ffer 1 Ba�d Rate Generator TX Register (TXR) RX Register (RXR) Data to be transmitted Data received UART Data Transfer Scheme UART Data Transfer Scheme UART Commands There are both read and write commands for the UART Module. For reading and writing to registers both command and address information is contained within a single byte. The format for reading and writing is shown in the following table. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Read FIFO Command Type 0 0 0 0 0 × × Bit 0 × Read Register 0 0 0 1 0 A2 A1 A0 Write FIFO 0 0 0 0 1 × × × Write Register 0 0 0 1 1 A2 A1 A0 Note: "×" here stands for "don't care" Rev. 2.10 227 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM UART Status and Control Registers There are six registers associated with the UART function. The USR, UCR1, UCR2 and UCR3 registers control the overall function of the UART module, while the BRG register controls the Baud rate. The actual data to be transmitted and received on the serial interface is managed through the TXR/RXR data register. A[2:0] Name Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 00H USR 0000 1011 PERR NF FERR OERR RIDLE RXIF 01H UCR1 PREN PRT STOPS TXBRK RX8 TX8 02H UCR2 0000 0000 TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE 03H BRG xxxx xxxx BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 04H UCR3 0- - - - - - - URST — — — 0000 0x00 UARTEN BNO — — 05H~07H Unused - - - - - - - - Bit 1 Bit 0 TIDLE TXIF BRG1 BRG0 — — Reserved UART Register Summary USR Register The USR register is the status register for the UART, which can be read by the application program to determine the present status of the UART. All flags within the USR register are read only. Further explanation on each of the flags is given below: Bit 7 6 5 4 3 2 1 0 Name PERR NF FERR OERR RIDLE RXIF TIDLE TXIF R/W R R R R R R R R POR 0 0 0 0 1 0 1 1 Bit 7PERR: Parity error flag 0: No parity error is detected 1: Parity error is detected The PERR flag is the parity error flag. When this read only flag is 0, it indicates a parity error has not been detected. When the flag is 1, it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can also be cleared by a software sequence which involves a read to the status register USR followed by an access to the RXR data register. Bit 6NF: Noise flag 0: No noise is detected 1: Noise is detected The NR flag is the noise flag. When this read only flag is "0", it indicates no noise condition. When the flag is 1, it indicates that the UART has detected noise on the receiver input. The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of as overrun. The NF flag can be cleared by a software sequence which will involve a read to the status register USR followed by an access to the RXR data register. Bit 5FERR: Framing error flag 0: No framing error is detected 1: Framing error is detected The FERR flag is the framing error flag. When this read only flag is 0, it indicates that there is no framing error. When the flag is "1", it indicates that a framing error has been detected for the current character. The flag can also be cleared by a software sequence which will involve a read to the status register USR followed by an access to the RXR data register. Rev. 2.10 228 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Bit 4OERR: Overrun error flag 0: No overrun error is detected 1: Overrun error is detected The OERR flag is the overrun error flag which indicates when the receiver buffer has overflowed. When this read only flag is "0", it indicates that there is no overrun error. When the flag is "1", it indicates that an overrun error occurs which will inhibit further transfers to the RXR receive data register. The flag is cleared by a software sequence, which is a read to the status register USR followed by an access to the RXR data register. Bit 3RIDLE: Receiver status 0: Data reception is in progress (data being received) 1: No data reception is in progress (receiver is idle) The RIDLE flag is the receiver status flag. When this read only flag is "0", it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. When the flag is "1", it indicates that the receiver is idle. Between the completion of the stop bit and the detection of the next start bit, the RIDLE bit is "1" indicating that the UART receiver is idle and the RX pin stays in logic high condition. Bit 2RXIF: Receive RXR data register status 0: RXR data register is empty 1: RXR data register has available data The RXIF flag is the receive data register status flag. When this read only flag is "0", it indicates that the RXR read data register is empty. When the flag is 1, it indicates that the RXR read data register contains new data. When the contents of the shift register are transferred to the RXR register, an interrupt is generated if RIE=1 in the UCR2 register. If one or more errors are detected in the received word, the appropriate receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the RXR register, and if the RXR register has no data available. Bit 1TIDLE: Transmission idle 0: Data transmission is in progress (data being transmitted) 1: No data transmission is in progress (transmitter is idle) The TIDLE flag is known as the transmission complete flag. When this read only flag is 0, it indicates that a transmission is in progress. This flag will be set to "1" when the TXIF flag is 1 and when there is no transmit data or break character being transmitted. When TIDLE is equal to "1", the TX pin becomes idle with the pin state in logic high condition. The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR register. The flag is not generated when a data character or a break is queued and ready to be sent. Bit 0TXIF: Transmit TXR data register status 0: Character is not transferred to the transmit shift register 1: Character has transferred to the transmit shift register (TXR data register is empty) The TXIF flag is the transmit data register empty flag. When this read only flag is "0", it indicates that the character is not transferred to the transmitter shift register. When the flag is "1", it indicates that the transmitter shift register has received a character from the TXR data register. The TXIF flag is cleared by reading the UART status register (USR) with TXIF set and then writing to the TXR data register. Note that when the TXEN bit is set, the TXIF flag bit will also be set since the transmit data register is not yet full. Rev. 2.10 229 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM UCR1 register The UCR1 register together with the UCR2 register are the two UART control registers that are used to set the various options for the UART function such as overall on/off control, parity control, data transfer bit length, etc. Further explanation on each of the bits is given below: Bit 7 6 5 4 3 2 1 0 Name UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8 R/W R/W R/W R/W R/W R/W R/W R W POR 0 0 0 0 0 0 × 0 "x" unknown Bit 7UARTEN: UART function enable control 0: Disable UART. TX and RX pins are in the state of high impedance 1: Enable UART. TX and RX pins function as UART pins The UARTEN bit is the UART enable bit. When this bit is equal to "0", the UART will be disabled and the RX pin as well as the TX pin will be in the state of high impedance. When the bit is equal to "1", the UART will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN enable control bits. When the UART is disabled, it will empty the buffer so any character remaining in the buffer will be discarded. In addition, the value of the baud rate counter will be reset. If the UART is disabled, all error and status flags will be reset. Also the TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2 and BRG registers will remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. When the UART is re-enabled, it will restart in the same configuration. Bit 6BNO: Number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer This bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. When this bit is equal to 1, a 9-bit data length format will be selected. If the bit is equal to "0", then an 8-bit data length format will be selected. If 9-bit data length format is selected, then bits RX8 and TX8 will be used to store the 9th bit of the received and transmitted data respectively. Bit 5PREN: Parity function enable control 0: Parity function is disabled 1: Parity function is enabled This is the parity enable bit. When this bit is equal to "1", the parity function will be enabled. If the bit is equal to "0", then the parity function will be disabled. Bit 4PRT: Parity type selection bit 0: Even parity for parity generator 1: Odd parity for parity generator This bit is the parity type selection bit. When this bit is equal to "1", odd parity type will be selected. If the bit is equal to "0", then even parity type will be selected. Bit 3STOPS: Number of Stop bits selection 0: One stop bit format is used 1: Two stop bits format is used This bit determines if one or two stop bits are to be used. When this bit is equal to "1", two stop bits are used. If this bit is equal to "0", then only one stop bit is used. Rev. 2.10 230 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Bit 2TXBRK: Transmit break character 0: No break character is transmitted 1: Break characters transmit The TXBRK bit is the Transmit Break Character bit. When this bit is "0", there are no break characters and the TX pin operates normally. When the bit is "1", there are transmit break characters and the transmitter will send logic zeros. When this bit is equal to 1, after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset. Bit 1RX8: Receive data bit 8 for 9-bit data transfer format (read only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as RX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. Bit 0TX8: Transmit data bit 8 for 9-bit data transfer format (write only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data known as TX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. UCR2 register The UCR2 register is the second of the UART control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation if the UART Transmitter and Receiver as well as enabling the various UART interrupt sources. The register also serves to control the baud rate speed, receiver wake-up function enable and the address detect function enable. Further explanation on each of the bits is given below: Bit 7 6 5 4 3 2 1 0 Name TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE R/W R/W R/W R/W R/W R/W R/W R W POR 0 0 0 0 1 0 1 1 Bit 7TXEN: UART Transmitter enable control 0: UART transmitter is disabled 1: UART transmitter is enabled The bit named TXEN is the Transmitter Enable Bit. When this bit is equal to "0", the transmitter will be disabled with any pending data transmissions being aborted. In addition the buffers will be reset. In this situation the TX pin will be in the state of high impedance. If the TXEN bit is equal to "1" and the UARTEN bit is also equal to "1", the transmitter will be enabled and the TX pin will be controlled by the UART. Clearing the TXEN bit during a transmission will cause the data transmission to be aborted and will reset the transmitter. If this situation occurs, the TX pin will be in the state of high impedance. Bit 6RXEN: UART Receiver enable control 0: UART receiver is disabled 1: UART receiver is enabled The bit named RXEN is the Receiver Enable Bit. When this bit is equal to "0", the receiver will be disabled with any pending data receptions being aborted. In addition the receive buffers will be reset. In this situation the RX pin will be in the state of high impedance. If the RXEN bit is equal to "1" and the UARTEN bit is also equal to "1", the receiver will be enabled and the RX pin will be controlled by the UART. Clearing the RXEN bit during a reception will cause the data reception to be aborted and will reset the receiver. If this situation occurs, the RX pin will be in the state of high impedance. Rev. 2.10 231 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Bit 5BRGH: Baud Rate speed selection 0: Low speed baud rate 1: High speed baud rate The bit named BRGH selects the high or low speed mode of the Baud Rate Generator. This bit, together with the value placed in the baud rate register BRG, controls the Baud Rate of the UART. If this bit is equal to "1", the high speed mode is selected. If the bit is equal to "0", the low speed mode is selected. Bit 4ADDEN: Address detect function enable control 0: Address detect function is disabled 1: Address detect function is enabled The bit named ADDEN is the address detect function enable control bit. When this bit is equal to "1", the address detect function is enabled. When it occurs, if the 8th bit, which corresponds to RX7 if BNO=0 or the 9th bit, which corresponds to RX8 if BNO=1, has a value of "1", then the received word will be identified as an address, rather than data. If the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit depending on the value of BNO. If the address bit known as the 8th or 9th bit of the received word is "0" with the address detect function being enabled, an interrupt will not be generated and the received data will be discarded. Bit 3WAKE: RX pin falling edge wake-up function enable control 0: RX pin wake-up function is disabled 1: RX pin wake-up function is enabled This bit enables or disables the receiver wake-up function. If this bit is equal to "1" and the MCU is in IDLE or SLEEP mode, a falling edge on the RX input pin will wake-up the device. If this bit is equal to "0" and the MCU is in IDLE or SLEEP mode, any edge transitions on the RX pin will not wake-up the device. Bit 2RIE: Receiver interrupt enable control 0: Receiver related interrupt is disabled 1: Receiver related interrupt is enabled This bit enables or disables the receiver interrupt. If this bit is equal to "1" and when the receiver overrun flag OERR or receive data available flag RXIF is set, the UART interrupt request flag will be set. If this bit is equal to "0", the UART interrupt request flag will not be influenced by the condition of the OERR or RXIF flags. Bit 1TIIE: Transmitter Idle interrupt enable control 0: Transmitter idle interrupt is disabled 1: Transmitter idle interrupt is enabled This bit enables or disables the transmitter idle interrupt. If this bit is equal to "1" and when the transmitter idle flag TIDLE is set, due to a transmitter idle condition, the UART interrupt request flag will be set. If this bit is equal to "0", the UART interrupt request flag will not be influenced by the condition of the TIDLE flag. Bit 0TEIE: Transmitter Empty interrupt enable control 0: Transmitter empty interrupt is disabled 1: Transmitter empty interrupt is enabled This bit enables or disables the transmitter empty interrupt. If this bit is equal to "1" and when the transmitter empty flag TXIF is set, due to a transmitter empty condition, the UART interrupt request flag will be set. If this bit is equal to "0", the UART interrupt request flag will not be influenced by the condition of the TXIF flag. Rev. 2.10 232 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM UCR3 register The UCR3 register is the last of the UART control registers and controls the software reset operation of the UART module. The only one available bit named URST in the UART control register UCR3 is the UART software reset control bit. When this bit is equal to "0", the UART operates normally. If this bit is equal to "1", the whole UART module will be reset. When this situation occurs, the transmitter and receiver will be reset. The UART registers including the status register and control registers will keep the POR states shown in the above UART registers table after the reset condition occurs. Bit 7 6 5 4 3 2 1 0 Name URST — — — — — — — R/W R/W — — — — — — — POR 0 — — — — — — — Bit 7URST: UART software reset 0: No action 1: UART reset occurs Bit 6~0 Unimplemented, read as “0” Baud Rate Generator To setup the speed of the serial data communication, the UART function contains its own dedicated baud rate generator. The baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. The first of these is the value placed in the baud rate register BRG and the second is the value of the BRGH bit with the control register UCR2. The BRGH bit decides if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. The value N in the BRG register which is used in the following baud rate calculation formula determines the division factor. Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. UCR2 BRGH Bit 0 1 Baud Rate (BR) fCLKI [64 (N+1)] fCLKI [16 (N+1)] By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register, the required baud rate can be setup. Note that because the actual baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error associated between the actual and requested value. The following example shows how the BRG register value N and the error value can be calculated. Rev. 2.10 233 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • Calculating the baud rate and error values For a clock frequency of 4MHz, and with BRGH set to "0" determine the BRG register value N, the actual baud rate and the error value for a desired baud rate of 4800. fCLKI From the above table the desired baud rate BR= [64 (N+1)] Re-arranging this equation gives N= Giving a value for N= fCLKI −1 (BR×64) 4000000 −1 =12.0208 (4800×64) To obtain the closest value, a decimal value of 12 should be placed into the BRG register. This gives an actual or calculated baud rate value of BR= 4000000 =4808 [64 (12+1)] Therefore the error is equal to 4808−4800 =0.16% 4800 The following tables show the actual values of baud rate and error values for the two value of BRGH. Baud Rate K/BPS Baud Rates for BRGH=0 fCLKI=4MHz fCLKI=3.579545MHz fCLKI=7.159MHz BRG Kbaud Error(%) BRG Kbaud Error(%) BRG Kbaud Error(%) 0.3 207 0.300 0.16 185 0.300 0.00 — — — 1.2 51 1.202 0.16 46 1.190 -0.83 92 1.203 0.23 2.4 25 2.404 0.16 22 2.432 1.32 46 2.380 -0.83 4.8 12 4.808 0.16 11 4.661 -2.90 22 4.863 1.32 9.6 6 8.929 -6.99 5 9.321 -2.90 11 9.322 -2.90 19.2 2 20.833 8.51 2 18.643 -2.90 5 18.643 -2.90 38.4 — — — — — — 2 32.286 -2.90 57.6 0 62.500 8.51 0 55.930 -2.90 1 55.930 -2.90 115.2 — — — — — — 0 111.859 -2.90 Baud Rates and Error Values for BRGH=0 Baud Rate K/BPS Baud Rates for BRGH=1 fCLKI=4MHz BRG Kbaud fCLKI=3.579545MHz Error(%) BRG Kbaud fCLKI=7.159MHz Error(%) BRG Kbaud Error(%) — 0.3 — — — — — — — — 1.2 207 1.202 0.16 185 1.203 0.23 — — — 2.4 103 2.404 0.16 92 2.406 0.23 185 2.406 0.23 4.8 51 4.808 0.16 46 4.76 -0.83 92 4.811 0.23 9.6 25 9.615 0.16 22 9.727 1.32 46 9.520 -0.83 19.2 12 19.231 0.16 11 18.643 -2.90 22 19.454 1.32 38.4 6 35.714 -6.99 5 37.286 -2.90 11 37.286 -2.90 57.6 3 62.5 8.51 3 55.930 -2.90 7 55.930 -2.90 115.2 1 125 8.51 1 111.86 -2.90 3 111.86 -2.90 250 0 250 0 — — — — — — Baud Rates and Error Values for BRGH=1 Rev. 2.10 234 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM BRG Register Bit 7 6 5 4 3 2 1 0 Name BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR × × × × × × × × “×”: unknown Bit 7~0BRG7~BRG0: Baud Rate values By programming the BRGH bit in UCR2 Register which allows selection of the related formula described above and programming the required value in the BRG register, the required baud rate can be setup. UART Module Setup and Control For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ, format. This is composed of one start bit, eight or nine data bits and one or two stop bits. Parity is supported by the UART hardware and can be setup to be even, odd or no parity. For the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as the default setting, which is the setting at power-on. The number of data bits and stop bits, along with the parity, are setup by programming the corresponding BNO, PRT, PREN and STOPS bits in the UCR1 register. The baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received LSB first. Although the transmitter and receiver of the UART are functionally independent, they both use the same data format and baud rate. In all cases stop bits will be used for data transmission. • Enabling/Disabling the UART The basic on/off function of the internal UART function is controlled using the UARTEN bit in the UCR1 register. If the UARTEN, TXEN and RXEN bits are set, then these two UART pins will act as normal TX output pin and RX input pin respectively. If no data is being transmitted on the TX pin, then it will default to a logic high value. Clearing the UARTEN bit will disable the TX and RX pins and these two pins will be in the state of high impedance. When the UART function is disabled, the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. Disabling the UART will also reset the enable control, the error and status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF being cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaffected. If the UARTEN bit in the UCR1 register is cleared while the UART is active, then all pending transmissions and receptions will be immediately suspended and the UART will be reset to a condition as defined above. If the UART is then subsequently re-enabled, it will restart again in the same configuration. Rev. 2.10 235 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • Data, parity and stop bit selection The format of the data to be transferred is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. These factors are determined by the setup of various bits within the UCR1 register. The BNO bit controls the number of data bits which can be set to either 8 or 9. The PRT bit controls the choice if odd or even parity. The PREN bit controls the parity on/off function. The STOPS bit decides whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address detect mode control bit identifies the frame as an address character. The number of stop bits, which can be either one or two, is independent of the data length. Start Bit Data Bits Address Bits Parity Bits Stop Bit Example of 8-bit Data Formats 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 Example of 9-bit Data Formats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 Transmitter Receiver Data Format The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. • UART transmitter Data word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, needs to be stored in the TX8 bit in the UCR1 register. At the transmitter core lies the Transmitter Shift Register, more commonly known as the TSR, whose data is obtained from the transmit data register, which is known as the TXR register. The data to be transmitted is loaded into this TXR register by the application program. The TSR register is not written to with new data until the stop bit from the previous transmission has been sent out. As soon as this stop bit has been transmitted, the TSR can then be loaded with new data from the TXR register, if it is available. It should be noted that the TSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. An actual transmission of data will normally be enabled when the TXEN bit is set, but the data will not be transmitted until the TXR register has been loaded with data and the baud rate generator has defined a shift clock source. However, the transmission can also be initiated by first loading data into the TXR register, after which the TXEN bit can be set. When a transmission of data begins, the TSR is normally empty, in which case a transfer to the TXR register will result in an immediate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission will immediately cease and the transmitter will be reset. The TX output pin will then return to the high impedance state. Rev. 2.10 236 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • Transmitting data When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with the least significant bit LSB first. In the transmit mode, the TXR register forms a buffer between the internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a data transfer can be summarized as follows: ♦♦ Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. ♦♦ Setup the BRG register to select the desired baud rate. ♦♦ Set the TXEN bit to ensure that the UART transmitter is enabled and the TX pin is used as a UART transmitter pin. Access the USR register and write the data that is to be transmitted into the TXR register. Note that this step will clear the TXIF bit. This sequence of events can now be repeated to send additional data. It should be noted that when TXIF=0, data will be inhibited from being written to the TXR register. Clearing the TXIF flag is always achieved using the following software sequence: 1. A USR register access 2. A TXR register write execution The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is empty and that other data can now be written into the TXR register without overwriting the previous data. If the TEIE bit is set, then the TXIF flag will generate an interrupt. During a data transmission, a write instruction to the TXR register will place the data into the TXR register, which will be copied to the shift register at the end of the present transmission. When there is no data transmission in progress, a write instruction to the TXR register will place the data directly into the shift register, resulting in the commencement of data transmission, and the TXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the TIDLE bit will be set. To clear the TIDLE bit the following software sequence is used: 1. A USR register access 2. A TXR register write execution Note that both the TXIF and TIDLE bits are cleared by the same software sequence. ♦♦ • Transmitting break If the TXBRK bit is set, then the break characters will be sent on the next transmission. Break character transmission consists of a start bit, followed by 13×N "0" bits, where N=1, 2, etc. if a break character is to be transmitted, then the TXBRK bit must be first set by the application program and then cleared to generate the stop bits. Transmitting a break character will not generate a transmit interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually kept at a logic high level, then the transmitter circuitry will transmit continuous break characters. After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. The automatic logic high at the end of the last break character will ensure that the start bit of the next frame is recognized. Rev. 2.10 237 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • UART receiver The UART is capable of receiving word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, will be stored in the RX8 bit in the UCR1 register. At the receiver core lies the Receiver Shift Register more commonly known as the RSR. The data which is received on the RX external input pin is sent to the data recovery block. The data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the receive data register, if the register is empty. The data which is received on the external RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted that the RSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. • Receiving data When the UART receiver is receiving data, the data is serially shifted in on the external RX input pin to the shift register, with the least significant bit LSB first. The RXR register is a four byte deep FIFO data buffer, where four bytes can be held in the FIFO while the 5th byte can continue to be received. Note that the application program must ensure that the data is read from RXR before the 5th byte has been completely shifted in, otherwise the 5th byte will be discarded and an overrun error OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows: ♦♦ Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. ♦♦ Setup the BRG register to select the desired baud rate. Set the RXEN bit to ensure that the UART receiver is enabled and the RX pin is used as a UART receiver pin. At this point the receiver will be enabled which will begin to look for a start bit. When a character is received, the following sequence of events will occur: ♦♦ ♦♦ The RXIF bit in the USR register will be set then RXR register has data available, at least three more character can be read. ♦♦ When the contents of the shift register have been transferred to the RXR register and if the RIE bit is set, then an interrupt will be generated. If during reception, a frame error, noise error, parity error or an overrun error has been detected, then the error flags can be set. The RXIF bit can be cleared using the following software sequence: 1. A USR register access 2. A RXR register read execution ♦♦ Rev. 2.10 238 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • Receiving break Any break character received by the UART will be managed as a framing error. The receiver will count and expect a certain number of bit times as specified by the values programmed into the BNO and STOPS bits. If the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by BNO and STOPS. The RXIF bit is set, FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the RIDLE bit is set. If a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not make the assumption that the break condition on the line is the next start bit. A break is regarded as a character that contains only zeros with the FERR flag set. The break character will be loaded into the buffer and no further data will be received until stop bits are received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received. The reception of a break character on the UART registers will result in the following: ♦♦ The framing error flag, FERR, will be set. ♦♦ The receive data register, RXR, will be cleared. ♦♦ The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set. • Idle status When the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition. • Receiver interrupt The read only receive interrupt flag RXIF in the USR register is set by an edge generated by the receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift Register, RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if RIE=1. Rev. 2.10 239 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Managing Receiver Errors Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART. • Overrun Error – OERR flag The RXR register is composed of a four byte deep FIFO data buffer, where four bytes can be held in the FIFO register, while a 5th byte can continue to be received. Before the 5th byte has been entirely shifted in, the data should be read from the RXR register. If this is not done, the overrun error flag OERR will be consequently indicated. In the event of an overrun error occurring, the following will happen: ♦♦ The OERR flag in the USR register will be set. ♦♦ The RXR contents will not be lost. ♦♦ The shift register will be overwritten. An interrupt will be generated if the RIE bit is set. The OERR flag can be cleared by an access to the USR register followed by a read to the RXR register. ♦♦ • Noise Error – NF flag Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is detected within a frame, the following will occur: ♦♦ The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit. ♦♦ Data will be transferred from the shift register to the RXR register. No interrupt will be generated. However this bit rises at the same time as the RXIF bit which itself generates an interrupt. Note that the NF flag is reset by a USR register read operation followed by an RXR register read operation. ♦♦ • Framing Error – FERR flag The read only framing error flag, FERR, in the USR register, is set if a zero is detected instead of stop bits. If two stop bits are selected, both stop bits must be high. Otherwise the FERR flag will be set. The FERR flag is buffered along with the received data and is cleared in any reset. • Parity Error – PERR flag The read only parity error flag, PERR, in the USR register, is set if the parity of the received word is incorrect. This error flag is only applicable if the parity function is enabled, PREN=1, and if the parity type, odd or even, is selected. The read only PERR flag is buffered along with the received data bytes. It is cleared on any reset, it should be noted that the FERR and PERR flags are buffered along with the corresponding word and should be read before reading the data word. Rev. 2.10 240 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM UART Module Interrupt Structure Several individual UART conditions can generate a UART interrupt. When these conditions exist, a low pulse will be generated on the INT line to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. When any of these conditions are created, if its corresponding interrupt control is enabled and the stack is not full, the program will jump to its corresponding interrupt vector where it can be serviced before returning to the main program. Four of these conditions have the corresponding USR register flags which will generate a UART interrupt if its associated interrupt enable control bit in the UCR2 register is set. The two transmitter interrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. These enable bits can be used to mask out individual UART interrupt sources. The address detect condition, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt when an address detect condition occurs if its function is enabled by setting the ADDEN bit in the UCR2 register. An RX pin wake-up, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt if the microcontroller is woken up by a falling edge on the RX pin, if the WAKE and RIE bits in the UCR2 register are set. Note that in the event of an RX wake-up interrupt occurring, there will be a certain period of delay, commonly known as the System Start-up Time, for the oscillator to restart and stabilize before the system resumes normal operation. Note that the USR register flags are read only and cannot be cleared or set by the application program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the case for some of the other interrupts. The flags will be cleared automatically when certain actions are taken by the UART, the details of which are given in the UART register section. The overall UART interrupt can be disabled or enabled by the related interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the UART module is masked out or allowed. UART Interrupt Structure Rev. 2.10 241 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • Address detect mode Setting the Address Detect function enable control bit, ADDEN, in the UCR2 register, enables this special function. If this bit is set to "1", then an additional qualifier will be placed on the generation of a Receiver Data Available interrupt, which is requested by the RXIF flag. If the ADDEN bit is equal to "1", then when the data is available, an interrupt will only be generated, if the highest received bit has a high value. Note that the related interrupt enable control bit and the EMI bit of the microcontroller must also be enabled for correct interrupt generation. The highest address bit is the 9th bit if the bit BNO=1 or the 8th bit if the bit BNO=0. If the highest bit is high, then the received word will be defined as an address rather than data. A Data Available interrupt will be generated every time the last bit of the received word is set. If the ADDEN bit is equal to "0", then a Receive Data Available interrupt will be generated each time the RXIF flag is set, irrespective of the data last but status. The address detect and parity functions are mutually exclusive functions. Therefore if the address detect function is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity function enable bit PREN to zero. ADDEN 0 1 Bit 9(BNO=1) Bit 8(BNO=0) UART Interrupt Generated 0 √ 1 √ 0 × 1 √ ADDEN Bit Function UART Module Power-down and Wake-up The MCU and UART Module are powered down independently of each other. The method of powering down the MCU is covered in the previous MCU section of the datasheet. The UART Module must be powered down before the MCU is powered down. This is implemented by first clearing the UARTEN bit in the UCR1 register to disable the UART Module circuitry after which the SCS internal line can be set high to disable the SPI interface circuits. When the UART and SPI interfaces are powered down, the SCK and CLKI clock sources to the UART module will be disabled. The UART Module can be powered up by the MCU by first clearing the SCS line to zero and then setting the UARTEN bit. If the UART circuits is powered down while a transmission is still in progress, then the transmission will be terminated and the external TX transmit pin will be forced to a logic high level. In a similar way, if the UART circuits is powered down while receiving data, then the reception of data will likewise be terminated. When the UART circuits is powered down, note that the USR, UCR1, UCR2, UCR3, transmit and receive registers, as well as the BRG register will not be affected. The UART Module contains a receiver RX pin wake-up function, which is enabled or disabled by the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit named UARTEN, the receiver enable bit named RXEN and the receiver interrupt enable bit named RIE, are all set before the MCU and UART module are is powered down, then a falling edge on the RX pin will wake up the MCU from its power down condition. Note that as it takes a certain period of time known as the System Start-up Time for oscillator to restart and stabilize after a wake-up, any data received during this time on the RX pin will be ignored. For a UART wake-up interrupt to occur, in addition to the bits for the wake-up enable control and Receive interrupt enable control being set, the global interrupt enable control and the related interrupt enable control bits must also be set. If these two bits are not set, then only a wake-up event will occur and no interrupt will be serviced. Note also that as it takes a period of delay after a wake-up before normal microcontroller resumes, the relevant UART interrupt will not be serviced until this period of delay time has elapsed. Rev. 2.10 242 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Using the UART Function To use the UART function, several important steps must be implemented to ensure that the UART module operates normally: • The SPI pin-remapping function must be properly configured when the SPI functional pins of the microcontroller are used to control the UART module and for data transmission and data reception. To correctly connect the MCU Master SPI to the UART Module Slave SPI, the SIM pin-remapping settings for PCK and PINT in the MCU PRM0 register should be the same as the values listed in the following table. ♦♦ ♦♦ ♦♦ HT68FU30 ––PRM0 Register PCK and PINT pin-remap setup Bit 1 0 Name SIMPS0 PCKPS Setting value 1 1 HT68FU40/HT68FU50 ––PRM0 Register PCK and PINT pin-remap setup Bit 2 1 0 Name SIMPS1 SIMPS0 PCKPS Setting value 0 1 1 HT68FU60 ––PRM0 Register PCK and PINT pin-remap setup Bit 2 1 0 Name SIMPS1 SIMPS0 PCKPS Setting value 1 1 1 • The SIM operating mode control bits SIM2~SIM0, in the SIMC0 register have to be configured to enable the SIM to operate in the SPI master mode with a different SPI clock frequency. ♦♦ SIM operating mode control bits SIM2~SIM0 in the SIMC0 Register Bit 2 1 0 Name SIM2 SIM1 SIM0 Value 100,011,010,001,000 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fTBC 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101~111: Must not be used Rev. 2.10 243 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM • The PCK control bit is set to "1" to enable the PCK output as the clock source for the UART baud rate generator with various PCK output frequencies determined by the PCKP1 and PCKP0 bits in the SIMC0 Register. ♦♦ PCK output frequency selection bits PCKP1~PCKP0 in the SIMC0 Register Bit 3 Name PCKP1 Value 2 PCKP0 11,10,01,00 00: PCK output frequency is fSYS 01: PCK output frequency is fSYS/4 10: PCK output frequency is fSYS/8 11: PCK output frequency is TM0 CCRP match frequency/2 ♦♦ PCK output enable control bit PCKEN in the SIMC0 Register Bit 4 Name PCKEN Value 1 0: Disable PCK output 1: Enable PCK output After the above setup conditions have been implemented, the MCU can enable the SIM interface by setting the SIMEN bit high. The MCU can then begin communication with external UART connected devices using its SPI interface. The detailed MCU Master SPI functional description is provided within the Serial Interface Module section of the MCU datasheet. Application Circuit with UART Module Note: * It is recommended that this component is added for added ESD protection. ** It is recommended that this component is added in environments where power line noise is significant. Rev. 2.10 244 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 2.10 245 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction “RET” in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the “SET [m].i” or “CLR [m].i” instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the “HALT” instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 2.10 246 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 2.10 247 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Mnemonic Description Cycles Flag Affected Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Read table (specific page) to TBLH and Data Memory Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note 2Note None None None No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch Operation JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read Operation TABRD [m] TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the “CLR WDT1” and “CLR WDT2” instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both “CLR WDT1” and “CLR WDT2” instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 2.10 248 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Instruction Definition ADC A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C ADCM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC ADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C ADD A,x Description Operation Affected flag(s) Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C ADDM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C AND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z AND A,x Description Operation Affected flag(s) Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z ANDM A,[m] Description Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z Rev. 2.10 249 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM CALL addr Description Operation Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Affected flag(s) Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT1 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT2 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CPL [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z Rev. 2.10 250 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM CPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z DAA [m] Description Operation Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z HALT Description Operation Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Operation Affected flag(s) Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z Rev. 2.10 251 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM JMP addr Description Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Operation Affected flag(s) Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z OR A,x Description Operation Affected flag(s) Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z ORM A,[m] Description Operation Affected flag(s) Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z RET Description Operation Affected flag(s) Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None Rev. 2.10 252 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM RET A,x Description Operation Affected flag(s) Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None RETI Description Operation Affected flag(s) Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None RL [m] Description Operation Affected flag(s) Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None RLA [m] Description Operation Affected flag(s) Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None RLC [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C RLCA [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C RR [m] Description Operation Affected flag(s) Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None Rev. 2.10 253 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM RRA [m] Description Operation Affected flag(s) Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None RRC [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C RRCA [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C SBC A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C SBCM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C SDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None Rev. 2.10 254 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM SDZA [m] Description Operation Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Operation Affected flag(s) Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None SIZA [m] Description Operation Affected flag(s) Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None SNZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None SUB A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C Rev. 2.10 255 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C SUB A,x Description Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Operation Affected flag(s) Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SZ [m] Description Operation Affected flag(s) Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None SZA [m] Description Operation Affected flag(s) Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None SZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None Rev. 2.10 256 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM TABRD [m] Description Operation Affected flag(s) Read table (specific page) to TBLH and Data Memory The low byte of the program code (specific page) addressed by the table pointer pair (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDC [m] Description Operation Affected flag(s) Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDL [m] Description Operation Affected flag(s) Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None XOR A,[m] Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z XORM A,[m] Description Operation Affected flag(s) Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z XOR A,x Description Operation Affected flag(s) Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z Rev. 2.10 257 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the for the latest version of the package information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 2.10 258 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 16-pin DIP (300mil) Outline Dimensions Fig1. Full Lead Packages Fig2. 1/2 Lead Packages See Fig 1 Symbol Nom. Max. A 0.780 0.790 0.800 B 0.240 0.250 0.280 C 0.115 0.130 0.195 D 0.115 0.130 0.150 E 0.014 0.018 0.022 F 0.045 0.060 0.070 G — 0.1 BSC — H 0.300 0.310 0.325 I — — 0.430 Symbol Rev. 2.10 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. A 19.81 20.07 20.32 B 6.10 6.35 7.11 C 2.92 3.30 4.95 D 2.92 3.30 3.81 E 0.36 0.46 0.56 F 1.14 1.52 1.78 G — 2.54 BSC — H 7.62 7.87 8.26 I — — 10.92 259 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM See Fig 2 − Type 1 Symbol Dimensions in inch Min. Nom. Max. A 0.745 0.765 0.785 B 0.275 0.285 0.295 C 0.120 0.135 0.150 D 0.110 0.130 0.150 E 0.014 0.018 0.022 F 0.045 0.050 0.060 G — 0.1 BSC — H 0.300 0.310 0.325 I — — 0.430 Symbol Dimensions in mm Min. Nom. Max. A 18.92 19.43 19.94 B 6.99 7.24 7.49 C 3.05 3.43 3.81 D 2.79 3.30 3.81 E 0.36 0.46 0.56 F 1.14 1.27 1.52 G — 2.54 BSC — H 7.62 7.87 8.26 I — — 10.92 See Fig 2 − Type 2 Symbol Nom. Max. A 0.735 0.755 0.775 B 0.240 0.250 0.280 C 0.115 0.130 0.195 D 0.115 0.130 0.150 E 0.014 0.018 0.022 F 0.045 0.060 0.070 G — 0.1 BSC — H 0.300 0.310 0.325 I — — 0.430 Symbol Rev. 2.10 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. A 18.67 19.18 19.69 B 6.10 6.35 7.11 C 2.92 3.30 4.95 D 2.92 3.30 3.81 E 0.36 0.46 0.56 F 1.14 1.52 1.78 G — 2.54 BSC — H 7.62 7.87 8.26 I — — 10.92 260 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 16-pin NSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. — A — 0.236 BSC B — 0.154 BSC — C 0.012 — 0.020 C' — 0.390 BSC — D — — 0.069 E — 0.050 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° ― 8° Symbol Rev. 2.10 Dimensions in mm Min. Nom. Max. A — 6 BSC — B — 3.9 BSC — 0.51 C 0.31 — C' — 9.9 BSC — D — — 1.75 E — 1.27 BSC — F 0.10 — 0.25 G 0.40 — 1.27 H 0.10 — 0.25 α 0° ― 8° 261 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 16-pin SSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.236 BSC — B — 0.154 BSC — C 0.008 — 0.012 C’ — 0.193 BSC — D — — 0.069 E — 0.025 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° Symbol Rev. 2.10 Dimensions in mm Min. Nom. Max. A — 6.0 BSC — B — 3.9 BSC — C 0.20 — 0.30 C’ — 4.9 BSC — D — — 1.75 E — 0.635 BSC — F 0.10 — 0.25 G 0.41 — 1.27 H 0.10 — 0.25 α 0° — 8° 262 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 20-pin DIP (300mil) Outline Dimensions Fig1. Full Lead Packages Fig2. 1/2 Lead Packages See Fig 1 Symbol Nom. Max. A 0.980 1.030 1.060 B 0.240 0.250 0.280 C 0.115 0.130 0.195 D 0.115 0.130 0.150 E 0.014 0.018 0.022 F 0.045 0.060 0.070 G — 0.100 BSC — H 0.300 0.310 0.325 I — — 0.430 Symbol Rev. 2.10 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. A 24.89 26.16 26.92 B 6.10 6.35 7.11 C 2.92 3.30 4.95 D 2.92 3.30 3.81 E 0.36 0.46 0.56 F 1.14 1.52 1.78 G — 2.54 BSC — H 7.62 7.87 8.26 I — — 10.92 263 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM See Fig 2 Symbol Min. Nom. Max. A 0.945 0.965 0.985 B 0.275 0.285 0.295 C 0.120 0.135 0.150 D 0.110 0.130 0.150 E 0.014 0.018 0.022 F 0.045 0.050 0.060 G — 0.1 BSC — H 0.300 0.310 0.325 I — — 0.430 Symbol Rev. 2.10 Dimensions in inch Dimensions in mm Min. Nom. Max. A 24.00 24.51 25.02 B 6.99 7.24 7.49 C 3.05 3.43 3.81 D 2.79 3.30 3.81 E 0.36 0.46 0.56 F 1.14 1.27 1.52 G — 2.54 BSC — H 7.62 7.87 8.26 I — — 10.92 264 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 20-pin SOP (300mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.406 BSC — B — 0.295 BSC — C 0.012 — 0.020 C’ — 0.504 BSC — D — — 0.104 E — 0.050 BSC — F 0.004 — 0.012 G 0.016 — 0.050 H 0.008 — 0.013 α 0° — 8° Symbol Rev. 2.10 Dimensions in mm Min. Nom. Max. A — 10.30 BSC — B — 7.50 BSC — C 0.31 — 0.51 C’ — 12.80 BSC — D — — 2.65 E — 1.27 BSC — F 0.10 — 0.30 G 0.40 — 1.27 H 0.20 — 0.33 α 0° — 8° 265 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 20-pin SSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.236 BSC — B — 0.155 BSC — C 0.008 — 0.012 C’ — 0.341 BSC — D — — 0.069 E — 0.025 BSC — F 0.004 — 0.0098 G 0.016 — 0.05 H 0.004 — 0.01 α 0° — 8° Symbol Rev. 2.10 Dimensions in mm Min. Nom. Max. A — 6.0 BSC — B — 3.9 BSC — C 0.20 — 0.30 C’ — 8.66 BSC — D — — 1.75 E — 0.635 BSC — F 0.10 — 0.25 G 0.41 — 1.27 H 0.10 — 0.25 α 0° — 8° 266 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 24-pin SKDIP (300mil) Outline Dimensions Fig1. Full Lead Packages Fig2. 1/2 Lead Packages See Fig1 A Min. 1.230 Dimensions in inch Nom. 1.250 Max. 1.280 Symbol B 0.240 0.250 0.280 C 0.115 0.130 0.195 D 0.115 0.130 0.150 E 0.014 0.018 0.022 F 0.045 0.060 0.070 G — 0.1 BSC — H 0.300 0.310 0.325 I — — 0.430 A Min. 31.24 Dimensions in mm Nom. 31.75 Max. 32.51 Symbol Rev. 2.10 B 6.10 6.35 7.11 C 2.92 3.30 4.95 D 2.92 3.30 3.81 E 0.36 0.46 0.56 F 1.14 1.52 1.78 G — 2.54 BSC — H 7.62 7.87 8.26 I — — 10.92 267 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM See Fig2 − Type 1 A Min. 1.160 Dimensions in inch Nom. 1.185 Max. 1.195 Symbol B 0.240 0.250 0.280 C 0.115 0.130 0.195 D 0.115 0.130 0.150 E 0.014 0.018 0.022 F 0.045 0.060 0.070 G — 0.1 BSC — H 0.300 0.310 0.325 I — — 0.430 Symbol Dimensions in mm Min. Nom. Max. 30.35 A 29.46 30.10 B 6.10 6.35 7.11 C 2.92 3.30 4.95 D 2.92 3.30 3.81 E 0.36 0.46 0.56 F 1.14 1.52 1.78 G — 2.54 BSC — H 7.62 7.87 8.26 I — — 10.92 A Min. 1.145 Dimensions in inch Nom. 1.165 Max. 1.185 See Fig2 − Type 2 Symbol B 0.275 0.285 0.295 C 0.120 0.135 0.150 D 0.110 0.130 0.150 E 0.014 0.018 0.022 F 0.045 0.050 0.060 G — 0.1 BSC — H 0.300 0.310 0.325 I — — 0.430 A Min. 29.08 Dimensions in mm Nom. 29.59 Max. 30.10 Symbol Rev. 2.10 B 6.99 7.24 7.49 C 3.05 3.43 3.81 D 2.79 3.30 3.81 E 0.36 0.46 0.56 F 1.14 1.27 1.52 G — 2.54 BSC — H 7.62 7.87 8.26 I — — 10.92 268 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 24-pin SOP (300mil) Outline Dimensions Symbol A Dimensions in inch Min. Nom. Max. — 0.406 BSC — B — 0.295 BSC — C 0.012 — 0.020 C’ — 0.606 BSC — D — — 0.104 E — 0.050 BSC — F 0.004 — 0.012 G 0.016 — 0.050 H 0.008 — 0.013 α 0° — 8° Symbol Rev. 2.10 Dimensions in mm Min. Nom. Max. A — 10.30 BSC — B — 7.5 BSC — C 0.31 — 0.51 C’ — 15.4 BSC — D — — 2.65 E — 1.27 BSC — F 0.10 — 0.30 G 0.40 — 1.27 H 0.20 — 0.33 α 0° ― 8° 269 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 24-pin SSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. — A — 0.236 BSC B — 0.154 BSC — C 0.008 — 0.012 C’ — 0.341 BSC — D — — 0.069 E — 0.025 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° Symbol Rev. 2.10 Dimensions in mm Min. Nom. Max. — A — 6.0 BSC B — 3.9 BSC — C 0.20 — 0.30 C’ — 8.66 BSC — D — — 1.75 E — 0.635 BSC — F 0.10 — 0.25 G 0.41 — 1.27 H 0.10 — 0.25 α 0° — 8° 270 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 28-pin SKDIP (300mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A 1.380 — 1.420 B 0.280 — 0.310 C 0.060 — 0.130 D 0.125 — 0.200 E 0.015 — 0.022 F 0.045 — 0.065 G — 0.1 BSC — H 0.300 — 0.325 I — — 0.400 Symbol Rev. 2.10 Dimensions in mm Min. Nom. Max. A 35.05 — 36.07 B 7.11 — 7.87 C 1.52 — 3.30 D 3.18 — 5.08 E 0.38 — 0.56 F 1.14 — 1.65 G — 2.54 BSC — H 7.62 — 8.26 I — — 10.16 271 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 28-pin SOP (300mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.406 BSC — B — 0.295 BSC — 0.020 C 0.012 — C’ — 0.705 BSC — D — — 0.104 E — 0.050 BSC — F 0.004 — 0.012 G 0.016 — 0.050 H 0.008 — 0.013 α 0° ― 8° Symbol Rev. 2.10 Dimensions in mm Min. Nom. Max. — A — 10.30 BSC B — 7.5 BSC — C 0.31 — 0.51 C’ — 17.9 BSC — D — — 2.65 E — 1.27 BSC — F 0.10 — 0.30 G 0.40 — 1.27 H 0.20 — 0.33 α 0° ― 8° 272 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 28-pin SSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. — A — 0.236 BSC B — 0.154 BSC — C 0.008 — 0.012 C’ — 0.390 BSC — D — — 0.069 E — 0.025 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° Symbol Rev. 2.10 Dimensions in mm Min. Nom. Max. — A — 6.0 BSC B — 3.9 BSC — C 0.20 — 0.30 C’ — 9.9 BSC — D — — 1.75 E — 0.635 BSC — F 0.10 — 0.25 G 0.41 — 1.27 H 0.10 — 0.25 α 0° — 8° 273 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM SAW Type 32-pin (5mm×5mm) QFN Outline Dimensions Symbol Min. Nom. Max. A 0.028 0.030 0.031 A1 0.000 0.001 0.002 A3 — 0.008 REF — b 0.007 0.010 0.012 D 0.193 0.197 0.201 E 0.193 0.197 0.201 e — 0.020 BSC — D2 0.122 0.126 0.130 E2 0.122 0.126 0.130 L 0.014 0.016 0.018 K 0.008 — — Symbol Rev. 2.10 Dimensions in inch Dimensions in mm Min. Nom. Max. A 0.700 0.750 0.800 A1 0.000 0.020 0.050 A3 — 0.203 REF — b 0.180 0.250 0.300 D 4.900 5.000 5.100 E 4.900 5.000 5.100 e — 0.50 BSC — D2 3.10 3.20 3.30 E2 3.10 3.20 3.30 L 0.35 0.40 0.45 K 0.20 — — 274 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM SAW Type 40-pin (6mm×6mm for 0.75mm) QFN Outline Dimensions Symbol Min. Nom. Max. A 0.028 0.030 0.031 A1 0.000 0.001 0.002 A3 — 0.008 REF — b 0.007 0.010 0.012 D 0.232 0.236 0.240 E 0.232 0.236 0.240 e — 0.020 BSC — D2 0.173 0.177 0.181 E2 0.173 0.177 0.181 L 0.014 0.016 0.018 K 0.008 — — Symbol Rev. 2.10 Dimensions in inch Dimensions in mm Min. Nom. Max. A 0.700 0.750 0.800 A1 0.000 0.020 0.050 A3 — 0.203 REF — b 0.180 0.250 0.300 D 5.900 6.000 6.100 E 5.900 6.000 6.100 e — 0.50 BSC — D2 4.40 4.50 4.60 E2 4.40 4.50 4.60 L 0.35 0.40 0.45 K 0.20 — — 275 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 44-pin LQFP (10mm×10mm) (FP 2.0mm) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.472 BSC — B — 0.394 BSC — C — 0.472 BSC — D — 0.394 BSC — E — 0.0315 BSC — F 0.012 0.015 0.018 G 0.053 0.055 0.057 H — — 0.063 I 0.002 — 0.006 J 0.018 0.024 0.030 K 0.004 — 0.008 α 0° — 7° Symbol Rev. 2.10 Dimensions in mm Min. Nom. Max. A — 12.00 BSC — B — 10.00 BSC — C — 12.00 BSC — D — 10.00 BSC — E — 0.80 BSC — F 0.30 0.37 0.45 G 1.35 1.40 1.45 H — — 1.60 I 0.05 — 0.15 J 0.45 0.60 0.75 K 0.09 — 0.20 α 0° — 7° 276 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 48-pin SSOP (300mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. A 0.395 — 0.42 B 0.291 0.295 0.299 Max. C 0.008 — 0.014 C’ 0.620 0.625 0.630 D 0.095 0.102 0.11 E — 0.025 BSC — F 0.008 0.012 0.016 G 0.020 — 0.040 H 0.005 — 0.010 ɑ 0° — 8° Symbol Rev. 2.10 Dimensions in mm Min. Nom. Max. A 10.03 — 10.67 7.59 B 7.39 7.49 C 0.20 — 0.34 C’ 15.75 15.88 16.00 D 2.41 2.59 2.79 E — 0.64 BSC — F 0.20 0.30 0.41 G 0.51 — 1.02 H 0.13 — 0.25 ɑ 0° — 8° 277 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM SAW Type 48-pin (7mm×7mm) QFN Outline Dimensions Symbol Nom. Max. A 0.031 0.033 0.035 A1 0.000 0.001 0.002 A3 — 0.008 REF — b 0.008 0.010 0.012 D — 0.276 BSC — E — 0.276 BSC — e — 0.020 BSC — D2 0.219 0.222 0.226 E2 0.219 0.222 0.226 L 0.014 0.016 0.018 Symbol Rev. 2.10 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. A 0.800 0.850 0.900 A1 0.000 0.035 0.050 A3 — 0.203 REF — b 0.200 0.250 0.300 D — 7.000 BSC — E — 7.000 BSC — e — 0.50 BSC — D2 5.55 5.65 5.75 E2 5.55 5.65 5.75 L 0.35 0.40 0.45 278 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM 48-pin LQFP (7mm×7mm) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.354 BSC — B — 0.276 BSC — C — 0.354 BSC — D — 0.276 BSC — E — 0.020 BSC — F 0.007 0.009 0.011 G 0.053 0.055 0.057 H — — 0.063 I 0.002 — 0.006 J 0.018 0.024 0.030 K 0.004 — 0.008 α 0° ― 7° Symbol Rev. 2.10 Dimensions in mm Min. Nom. Max. A — 9.00 BSC — B — 7.00 BSC — C — 9.00 BSC — D — 7.00 BSC — E — 0.50 BSC — F 0.17 0.22 0.27 G 1.35 1.40 1.45 H — — 1.60 I 0.05 — 0.15 J 0.45 0.60 0.75 K 0.09 — 0.20 α 0° ― 7° 279 July 02, 2014 HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM Copyright© 2014 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 2.10 280 July 02, 2014