20-Bit Delta Sigma A/D + LCD Flash MCU HT67F5640 Revision: V1.10 Date: ���������������� October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Table of Contents Features............................................................................................................. 7 CPU Features.......................................................................................................................... 7 Peripheral Features.................................................................................................................. 7 General Description.......................................................................................... 8 Block Diagram................................................................................................... 8 Pin Assignment................................................................................................. 9 Pin Description............................................................................................... 10 Absolute Maximum Ratings........................................................................... 14 D.C. Characteristics........................................................................................ 14 A.C. Characteristics........................................................................................ 18 LDO+PGA+ADC+VCM Electrical Characteristics........................................ 19 Effective Number of Bits (ENOB)........................................................................................... 20 Comparator Electrical Characteristics......................................................... 21 LCD Electrical Characteristics...................................................................... 22 Power-on Reset Characteristics.................................................................... 22 System Architecture....................................................................................... 23 Clocking and Pipelining.......................................................................................................... 23 Program Counter.................................................................................................................... 24 Stack...................................................................................................................................... 25 Arithmetic and Logic Unit – ALU ........................................................................................... 25 Flash Program Memory ................................................................................. 26 Structure ................................................................................................................................ 26 Special Vectors...................................................................................................................... 26 Look-up Table ........................................................................................................................ 26 Table Program Example......................................................................................................... 27 In Circuit Programming – ICP................................................................................................ 28 On Chip Debug Support – OCDS.......................................................................................... 29 RAM Data Memory.......................................................................................... 30 Structure ................................................................................................................................ 30 Special Function Register Description......................................................... 32 Indirect Addressing Registers – IAR0, IAR1 ......................................................................... 32 Memory Pointers – MP0, MP1 .............................................................................................. 32 Bank Pointer – BP ................................................................................................................. 33 Accumulator – ACC ............................................................................................................... 33 Program Counter Low Register – PCL .................................................................................. 33 Look-up Table Registers – TBLP, TBHP, TBLH ..................................................................... 33 Status Register – STATUS .................................................................................................... 34 Rev. 1.10 2 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU EEPROM Data memory.................................................................................. 36 EEPROM Data Memory Structure......................................................................................... 36 EEPROM Registers............................................................................................................... 36 Reading Data from the EEPROM.......................................................................................... 38 Writing Data to the EEPROM................................................................................................. 38 Write Protection...................................................................................................................... 38 EEPROM Interrupt................................................................................................................. 38 Programming Considerations................................................................................................. 39 Oscillator......................................................................................................... 40 Oscillator Overview ............................................................................................................... 40 System Clock Configurations................................................................................................. 40 External Crystal/Ceramic Oscillator – HXT ........................................................................... 41 Internal RC Oscillator – HIRC................................................................................................ 42 Internal 32kHz Oscillator – LIRC ........................................................................................... 42 External 32.768kHz Crystal Oscillator – LXT ........................................................................ 42 LXT Oscillator Low Power Function ...................................................................................... 43 Supplementary Oscillators .................................................................................................... 44 Operating Modes and System Clocks.......................................................... 44 System Clocks....................................................................................................................... 44 System Operation Modes ...................................................................................................... 46 Control Register..................................................................................................................... 47 Fast Wake-up......................................................................................................................... 49 Operating Mode Switching .................................................................................................... 50 Standby Current Considerations ........................................................................................... 54 Wake-up ................................................................................................................................ 54 Programming Considerations ................................................................................................ 55 Watchdog Timer.............................................................................................. 55 Watchdog Timer Clock Source............................................................................................... 55 Watchdog Timer Control Register.......................................................................................... 55 Watchdog Timer Operation.................................................................................................... 57 Reset and Initialisation .................................................................................. 58 Reset Functions..................................................................................................................... 58 Reset Initial Conditions ......................................................................................................... 61 Input/Output Ports ......................................................................................... 65 I/O Register List..................................................................................................................... 65 Pull-high Resistors................................................................................................................. 66 Port A Wake-up...................................................................................................................... 67 I/O Port Control Registers...................................................................................................... 67 I/O Pin Structures................................................................................................................... 69 Programming Considerations ................................................................................................ 69 Rev. 1.10 3 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Timer Modules – TM....................................................................................... 70 Introduction............................................................................................................................ 70 TM Operation......................................................................................................................... 70 TM Clock Source.................................................................................................................... 71 TM Interrupts.......................................................................................................................... 71 TM External Pins ................................................................................................................... 71 TM Input/Output Pin Control Registers.................................................................................. 72 Programming Considerations................................................................................................. 73 Compact Type TM – CTM............................................................................... 74 Compact TM Operation ......................................................................................................... 74 Compact Type TM Register Description................................................................................ 75 Compact Type TM Operating Modes .................................................................................... 79 Periodic Type TM – PTM................................................................................. 85 Periodic TM Operation........................................................................................................... 85 Periodic Type TM Register Description.................................................................................. 86 Periodic Type TM Operating Modes....................................................................................... 90 Internal Power Supply ................................................................................... 98 Analog to Digital Converter – ADC.............................................................. 100 A/D Data Rate Definition...................................................................................................... 100 A/D Overview....................................................................................................................... 100 A/D Converter Register Description..................................................................................... 101 Programmable Gain Amplifier – PGA................................................................................... 102 A/D Converter Data Registers – ADRL, ADRM, ADRH........................................................ 104 A/D Converter Control Registers – ADCR0, ADCR1, ADCS................................................ 105 A/D Operation...................................................................................................................... 107 Summary of A/D Conversion Steps...................................................................................... 108 Programming Considerations............................................................................................... 109 A/D Transfer Function.......................................................................................................... 109 A/D Converted Data..............................................................................................................110 A/D Converted data to voltage..............................................................................................110 A/D Programming Example...................................................................................................111 Temperature sensor......................................................................................112 Comparators..................................................................................................112 Comparator Operation..........................................................................................................112 Comparator Register.............................................................................................................113 Comparator Interrupt.............................................................................................................115 Programming Considerations................................................................................................115 Serial Interface Module – SIM.......................................................................115 SPI Interface ........................................................................................................................115 SPI Interface Operation ........................................................................................................115 SPI Registers........................................................................................................................116 SPI Communication .............................................................................................................119 I2C Interface......................................................................................................................... 121 Rev. 1.10 4 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU I2C Interface Operation ........................................................................................................ 121 I2C Registers........................................................................................................................ 122 I2C Bus Communication....................................................................................................... 126 I2C Bus Start Signal ............................................................................................................. 127 Slave Address ..................................................................................................................... 127 I2C Bus Read/Write Signal .................................................................................................. 127 I2C Bus Slave Address Acknowledge Signal ....................................................................... 127 I2C Bus Data and Acknowledge Signal ............................................................................... 128 I2C Time Out function........................................................................................................... 129 I2C Time Out operation......................................................................................................... 129 UART Module Serial Interface with IR Carrier............................................ 131 UART Module features......................................................................................................... 131 UART Module Overview....................................................................................................... 131 UART external pin interfacing.............................................................................................. 131 UART data transfer scheme................................................................................................. 132 UART status and control registers....................................................................................... 132 Baud Rate Generator........................................................................................................... 138 UART Setup and Control..................................................................................................... 139 Managing receiver errors..................................................................................................... 143 UART Module Interrupt Structure......................................................................................... 144 Address detect mode........................................................................................................... 145 UART Module Power Down and Wake-up........................................................................... 146 IR Modulation Interface........................................................................................................ 146 Interrupts....................................................................................................... 147 Interrupt Registers................................................................................................................ 147 Interrupt Operation............................................................................................................... 152 External Interrupt.................................................................................................................. 153 Comparator Interrupt............................................................................................................ 154 A/D Converter Interrupt........................................................................................................ 154 Multi-function Interrupt......................................................................................................... 154 Serial Interface Module Interrupt.......................................................................................... 155 Time Base Interrupts............................................................................................................ 155 I2C Time Out Interrupt.......................................................................................................... 156 UART Interrupt..................................................................................................................... 157 EEPROM Interrupt............................................................................................................... 157 LVD Interrupt........................................................................................................................ 157 TM Interrupts........................................................................................................................ 158 Interrupt Wake-up Function.................................................................................................. 158 Programming Considerations............................................................................................... 158 Low Voltage Detector – LVD........................................................................ 159 LVD Register........................................................................................................................ 159 LVD Operation...................................................................................................................... 160 Rev. 1.10 5 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU LCD Driver..................................................................................................... 161 LCD Display Memory........................................................................................................... 161 Clock Source ....................................................................................................................... 162 LCD Registers...................................................................................................................... 162 LCD Driver Output................................................................................................................ 164 LCD Waveform Timing Diagrams ........................................................................................ 164 Programming Considerations............................................................................................... 165 Configuration Option.................................................................................... 166 Application Circuit........................................................................................ 167 Instruction Set............................................................................................... 168 Introduction.......................................................................................................................... 168 Instruction Timing................................................................................................................. 168 Moving and Transferring Data.............................................................................................. 168 Arithmetic Operations........................................................................................................... 168 Logical and Rotate Operation.............................................................................................. 169 Branches and Control Transfer............................................................................................ 169 Bit Operations...................................................................................................................... 169 Table Read Operations........................................................................................................ 169 Other Operations.................................................................................................................. 169 Instruction Set Summary............................................................................. 170 Table Conventions................................................................................................................ 170 Instruction Definition.................................................................................... 172 Package Information.................................................................................... 181 64-pin LQFP (7mm×7mm) Outline Dimensions................................................................... 182 Rev. 1.10 6 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Features CPU Features • Operating voltage: fSYS=8MHz: 2.2V~5.5V fSYS=12MHz: 2.7V~5.5V fSYS=20MHz: 4.5V~5.5V • Up to 0.2μs instruction cycle with 20MHz system clock at VDD=5V • Power down and wake-up functions to reduce power consumption • Four oscillators: External Crystal – HXT External 32.768kHz Crystal – LXT Internal RC – HIRC Internal 32kHz RC – LIRC • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • Fully integrated internal 4.9152MHz, 4.9152×2MHz and 4.9152×3MHz oscillator requires no external components • All instructions executed in one or two instruction cycles • Table read instructions • 63 powerful instructions • 8-level subroutine nesting • Bit manipulation instruction Peripheral Features • Flash Program Memory: 4K×16 • RAM Data Memory: 256×8 • EEPROM Memory: 64×8 • Watchdog Timer function • LCD COM driver with 1/3 bias • 41 bidirectional I/O lines • Dual pin-shared external interrupts • Multiple Timer Module for time measure, input capture, compare match output, PWM output or single pulse output function • Dual Time-Base functions for generation of fixed time interrupt signals • 2 differential and 4 single-end channels 20-bit resolution Delta-Sigma A/D converter • Low voltage reset function • Low voltage detect function • Internal LDO for PGA, ADC or external sensor power supply • Serial Interfaces Module – SIM for SPI or I2C • UART with IR carrier • Two comparators • Package type: 64-pin LQFP • Flash program memory can be re-programmed up 100,000times • Flash program memory data retention > 10 years • EEPROM data memory can be re-programmed up to 1,000,000 times • EEPROM data memory data retention > 10 years Rev. 1.10 7 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU General Description The device is a Flash Memory A/D type 8-bit high performance RISC architecture microcontroller with multi-channel 20-bit Delta-Sigma A/D (ΔΣA/D) converter, designed for applications that interface directly to analog signals and which require the low noise and high accuracy analog to digital converter. Offering users the convenience of Flash Memory multi-programming features, this device also includes a wide range of functions and features. Other memory includes an area of RAM Data Memory as well as an area of EEPROM memory for storage of non-volatile data such as serial numbers, calibration data etc. Analog features include a multi-channel with 20-bit ΔΣA/D converter and programmable gain amplifier (PGA) functions. An extremely flexible Timer Module provides timing, pulse generation and PWM generation functions. In addition, internal LDO function provides various power options to the internal and external devices. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of HXT, LXT, HIRC and LIRC oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. The inclusion of flexible I/O programming features, Time-Base functions along with many other features ensure that the device will find excellent use in applications such as weight scales, electronic metering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. Block Diagram Rev. 1.10 8 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Pin Assignment PE�/TCK1/SEG� PE3/TP1_1/SDI/SDA/SEG3 PE�/TP1_0/SD�/SEG� PE1/TCK0/SCS/SEG1 PE0/TP0_1/SCK/SCL/SEG0 PF0/C1N PB�/TP0_0/C1P PB7/INT1/C0N PB6/INT0/C0P PB0 PB�/�SC� PB1/�SC1 VSS PB3/XT1 PB�/XT� VDD/VIN AVDD/V�UT AVSS VCM NC NC VREFP VREFN AN0 AN1 AN� AN3 AN� AN� AN6 AN7 AVSS 1 � 3 � � 6 7 8 9 10 11 1� 13 1� 1� 16 6� 63 6� 61 60 �9 �8 �7 �6 �� �� �3 �� �� �3 �� �8 �7 �6 �� �� �3 �� HT67F5640 �1 64 LQFP-A �0 39 38 37 36 3� 3� 33 17 18 19 �0 �1 �� �3 �� �� �6 �7 �8 �9 30 31 3� PE�/TP�_0/SEG� PE6/TP�_1/SEG6 PE7/TCK�/SEG7 PA0/SEG8/ICPDA/�CDSDA PA�/SEG9/ICPCK/�CDSCK PA1/SEG10 PA3/SEG11 PA�/SEG1� PA�/SEG13 PA6/SEG1� PA7/SEG1� PD0/SEG16 PD1/SEG17 PD�/SEG18 PD3/SEG19 VSS PD�/SEG�0 PD�/SEG�1 PD6/SEG�� PD7/SEG�3 PC7/C1�UT/SEG�� PC6/C0�UT/SEG�� PC�/TX/SEG�6 PC�/RX/SEG�7 PC3/C�M3 PC�/C�M� PC1/C�M1 PC0/C�M0 V� V1 C� C1 Rev. 1.10 9 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Pin Description The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. Pin Name PA0/SEG8/ ICPDA/OCDSDA PA1/SEG10 PA2/SEG9/ ICPCK/OCDSCK PA3/SEG11 PA4/SEG12 PA5/SEG13 PA6/SEG14 PA7/SEG15 PB0 PB1/OSC1 PB2/OSC2 PB3/XT1 PB4/XT2 Rev. 1.10 Function OPT I/T O/T PA0 PAPU PAWU ST CMOS SEG8 LCD2 — CMOS LCD Segment output ICPDA — ST CMOS ICP address/data OCDSDA — ST CMOS OCDS address/data, for EV chip only. PA1 PAPU PAWU ST CMOS SEG10 LCD2 — CMOS LCD Segment output PA2 PAPU PAWU ST CMOS SEG9 LCD2 — CMOS LCD Segment output ICPCK — ST — ICP clock OCDSCK — ST — OCDS clock, for EV chip only. PA3 PAPU PAWU ST CMOS SEG11 LCD2 — CMOS LCD Segment output PA4 PAPU PAWU ST CMOS SEG12 LCD2 — CMOS LCD Segment output PA5 PAPU PAWU ST CMOS SEG13 LCD2 — CMOS LCD Segment output PA6 PAPU PAWU ST CMOS SEG14 LCD2 — CMOS LCD Segment output PA7 PAPU PAWU ST CMOS SEG15 LCD2 — CMOS LCD Segment output PB0 PBPU ST CMOS General purpose I/O. Register enabled pull-up. PB1 PBPU ST CMOS General purpose I/O. Register enabled pull-up. OSC1 CO HXT PB2 PBPU ST OSC2 CO — PB3 PBPU ST XT1 CO LXT PB4 PBPU ST XT2 CO — — Descriptions General purpose I/O. Register enabled pull-up and wake-up. General purpose I/O. Register enabled pull-up and wake-up. General purpose I/O. Register enabled pull-up and wake-up. General purpose I/O. Register enabled pull-up and wake-up. General purpose I/O. Register enabled pull-up and wake-up. General purpose I/O. Register enabled pull-up and wake-up. General purpose I/O. Register enabled pull-up and wake-up. General purpose I/O. Register enabled pull-up and wake-up. HXT Oscillator input CMOS General purpose I/O. Register enabled pull-up. HXT HXT Oscillator output CMOS General purpose I/O. Register enabled pull-up. — LXT Oscillator input CMOS General purpose I/O. Register enabled pull-up. LXT 10 LXT Oscillator output October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Pin Name PB5/TP0_0/C1P PB6/INT0/C0P PB7/INT1/C0N PC0/COM0 PC1/COM1 PC2/COM2 PC3/COM3 PC4/RX/SEG27 PC5/TX/SEG26 PC6/C0OUT/ SEG25 PC7/C1OUT/ SEG24 PD0/SEG16 PD1/SEG17 Rev. 1.10 Function OPT I/T O/T PB5 PBPU ST CMOS General purpose I/O. Register enabled pull-up. TP0_0 CTRL0 TM0C0 ST CMOS TM0 input/output C1P CP1C AN PB6 PBPU ST INT0 — ST — External Interrupt 0 input C0P CP0C AN — Comparator 0 postive input PB7 PBPU ST INT1 — ST — External Interrupt 1 input C0N CP0C AN — Comparator 0 negtive input PC0 PCPU ST CMOS General purpose I/O. Register enabled pull-up. COM0 LCD4 — CMOS LCD Common output PC1 PCPU ST CMOS General purpose I/O. Register enabled pull-up. COM1 LCD4 — CMOS LCD Common output PC2 PCPU ST CMOS General purpose I/O. Register enabled pull-up. COM2 LCD4 — CMOS LCD Common output PC3 PCPU ST CMOS General purpose I/O. Register enabled pull-up. COM3 LCD4 — CMOS LCD Common output PC4 PCPU ST CMOS General purpose I/O. Register enabled pull-up. RX — ST SEG27 LCD4 — CMOS LCD Segment output PC5 PCPU ST CMOS General purpose I/O. Register enabled pull-up. TX — — CMOS UART transceiver pin SEG26 LCD4 — CMOS LCD Segment output PC6 PCPU ST CMOS General purpose I/O. Register enabled pull-up. C0OUT CP0C — CMOS Comparator 0 output pin SEG25 LCD4 — CMOS LCD Segment output PC7 PCPU ST CMOS General purpose I/O. Register enabled pull-up. C1OUT CP1C — CMOS Comparator 1 output pin SEG24 LCD4 — CMOS LCD Segment output PD0 PDPU ST CMOS General purpose I/O. Register enabled pull-up. SEG16 LCD3 — CMOS LCD Segment output PD1 PDPU ST CMOS General purpose I/O. Register enabled pull-up. SEG17 LCD3 — CMOS LCD Segment output — Descriptions Comparator 1 postive input CMOS General purpose I/O. Register enabled pull-up. CMOS General purpose I/O. Register enabled pull-up. — 11 UART receiver pin October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Pin Name PD2/SEG18 PD3/SEG19 PD4/SEG20 PD5/SEG21 PD6/SEG22 PD7/SEG23 PE0/TP0_1/ SCK/SCL/SEG0 PE1/TCK0/ SCS/SEG1 PE2/TP1_0/ SDO/SEG2 PE3/TP1_1/ SDI/SDA/SEG3 PE4/TCK1/SEG4 Rev. 1.10 Function OPT I/T O/T PD2 PDPU ST CMOS General purpose I/O. Register enabled pull-up. SEG18 LCD3 — CMOS LCD Segment output PD3 PDPU ST CMOS General purpose I/O. Register enabled pull-up. SEG19 LCD3 — CMOS LCD Segment output PD4 PDPU ST CMOS General purpose I/O. Register enabled pull-up. SEG20 LCD3 — CMOS LCD Segment output PD5 PDPU ST CMOS General purpose I/O. Register enabled pull-up. SEG21 LCD3 — CMOS LCD Segment output PD6 PDPU ST CMOS General purpose I/O. Register enabled pull-up. SEG22 LCD3 — CMOS LCD Segment output PD7 PDPU ST CMOS General purpose I/O. Register enabled pull-up. SEG23 LCD3 — CMOS LCD Segment output PE0 PEPU ST CMOS General purpose I/O. Register enabled pull-up. TP0_1 CTRL0 TM0C0 ST CMOS TM0 input/output SCK SIMC2 ST CMOS SPI serial clock SCL SIMC0 ST CMOS I2C clock line SEG0 LCD1 — CMOS LCD Segment output PE1 PEPU ST CMOS General purpose I/O. Register enabled pull-up. TCK0 — ST SCS SIMC2 ST CMOS SPI slave select pin SEG1 LCD1 — CMOS LCD Segment output PE2 PEPU ST CMOS General purpose I/O. Register enabled pull-up. TP1_0 CTRL0 PTM1C0 ST CMOS TM1 input/output SDO SIMC2 — CMOS SPI serial data output SEG2 LCD1 — CMOS LCD Segment output PE3 PEPU ST CMOS General purpose I/O. Register enabled pull-up. TP1_1 CTRL0 PTM1C0 ST CMOS TM1 input/output SDI SIMC2 ST SDA SIMC0 ST CMOS I2C data line SEG3 LCD1 — CMOS LCD Segment output PE4 PEPU ST CMOS General purpose I/O. Register enabled pull-up. TCK1 — ST SEG4 LCD1 — — — — Descriptions TM0 clock input SPI serial data input TM1 clock input CMOS LCD Segment output 12 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Pin Name OPT I/T PE5 PEPU ST CMOS General purpose I/O. Register enabled pull-up. TP2_0 CTRL0 PTM2C0 ST CMOS TM2 input/output SEG5 LCD1 — CMOS LCD Segment output PE6 PEPU ST CMOS General purpose I/O. Register enabled pull-up. TP2_1 CTRL0 PTM2C0 ST CMOS TM2 input/output SEG6 LCD1 — CMOS LCD Segment output PE7 PEPU ST CMOS General purpose I/O. Register enabled pull-up. TCK2 — ST SEG7 LCD1 — CMOS LCD Segment output PF0 PFPU ST CMOS General purpose I/O. Register enabled pull-up. C1N CP1C AN — Comparator 1 negtive input ANn — AN — A/D input pin VERFP VERFP — PWR — ADC positive reference input VERFN VERFN — PWR — ADC negative reference input VCM — — PWR V1, V2 V1, V2 — — — LCD voltage pump. C1, C2 C1, C2 — — — LCD voltage pump. VDD — PWR — Digital Power supply VIN — PWR — LDO input pin AVDD — PWR — Analog power supply VOUT — — PWR LDO output pin AVSS AVSS — PWR — Analog Ground VSS VSS — PWR — Digital Ground PE5/TP2_0/SEG5 PE6/TP2_1/SEG6 PE7/TCK2/SEG7 PF0/C1N AN0~AN7 VCM VDD/VIN AVDD/VOUT Function O/T — Descriptions TM2 clock input ADC internal Common mode voltage output Note: I/T: Input type O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power CO: Configuration option ST: Schmitt Trigger input CMOS: CMOS output AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator Rev. 1.10 13 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Absolute Maximum Ratings Supply Voltage .................................................................................................VSS-0.3V to VSS+6.0V Input Voltage ...................................................................................................VSS-0.3V to VDD+0.3V Storage Temperature .................................................................................................. -50°C to 150°C Operating Temperature . ............................................................................................... -40°C to 85°C IOH Total...................................................................................................................................-100mA IOL Total . .................................................................................................................................. 150mA Total Power Dissipation ......................................................................................................... 500mW Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Ta=25°C Symbol VDD1 VDD2 Parameter Operating Voltage (HXT) Operating Voltage (HIRC) Test Conditions Min. Typ. Max. Unit fSYS=8MHz 2.2 — 5.5 V fSYS=12MHz 2.7 — 5.5 V fSYS=20MHz 4.5 — 5.5 V — fSYS=4.9152MHz 2.2 — 5.5 V 3V No load, fH=8MHz, LDO, LCD, ADC off, WDT enable — 1.0 1.5 mA — 2.5 4 mA No load, fH=10MHz, LDO, LCD, ADC off, WDT enable — 1.2 2.0 mA — 2.8 4.5 mA No load, fH=12MHz, LDO, LCD, ADC off, WDT enable — 1.5 2.5 mA — 3.5 5.5 mA No load, fH=16MHz, LDO, LCD, ADC off, WDT enable — 2.0 3.0 mA — 4.5 7.0 mA — 5.5 8.5 mA No load, fH=4.9152MHz, LDO, LCD, ADC off, WDT enable — 0.7 1.2 mA — 1.5 2.5 mA No load, fH=4.9152×2MHz, LDO, LCD, ADC off, WDT enable — 1.2 2.0 mA — 2.8 4.5 mA No load, fH=4.9152×3MHz, LDO, LCD, ADC off, WDT enable — 1.8 3.0 mA — 4.0 6.0 mA VDD — 5V 3V IDD1 Operating Current (HXT, fSYS=fH, fS=fSUB=fLXT or fLIRC) 5V 3V 5V 3V 5V 5V 3V 5V IDD2 Operating Current (HIRC, fSYS=fH, fS=fSUB=fLXT or fLIRC) 3V 5V 3V 5V Rev. 1.10 Conditions No load, fH=20MHz, LDO, LCD, ADC off, WDT enable 14 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Symbol Parameter Test Conditions 3V 5V 3V 5V 3V IDD3 Operating Current (HXT, fSYS=fSUB, fS=fSUB=fLXT or fLIRC) 5V 3V 5V 3V 5V 3V 5V 3V IDD4 Operating Current (LXT, fSYS=fSUB=fLXT, fS=fSUB=fLXT) 5V 3V 5V IDD5 Operating Current (LIRC, fSYS=fSUB=fLIRC, fS=fSUB=fLIRC) 3V Operating Current (LXT+LIRC, fSYS=fSUB=fLXT, fS=fSUB=fLIRC) 3V IDD6 ISTB1 Standby Current (Idle) (HXT, fSYS=fH, fS=fSUB=fLXT or fLIRC) 3V ISTB2 Standby Current (Idle) (HXT, fSYS=off, fS=T1) ISTB3 Standby Current (Idle) (HXT, fSYS=off, fS=fSUB=fLXT or fLIRC) ISTB4 Standby Current (Idle) (HIRC, fSYS=off, fS=fSUB=fLIRC) 3V ISTB5 Standby Current (Idle) (HXT, fSYS=fSUB, fS=fSUB=fLXT or fLIRC) 3V ISTB6 Standby Current (Idle) (HXT, fSYS=off, fS=fSUB=fLXT or fLIRC) Rev. 1.10 Min. Typ. Max. Unit No load, fH=12MHz, fL=fH/2, ADC off, WDT enable — 0.9 1.5 mA — 2.1 3.3 mA No load, fH=12MHz, fL=fH/4, LDO, LCD, ADC off, WDT enable — 0.6 1.0 mA — 1.6 2.5 mA No load, fH=12MHz, fL=fH/8, LDO, LCD, ADC off, WDT enable — 0.48 0.8 mA — 1.2 2.0 mA No load, fH=12MHz, fL=fH/16, LDO, ADC off, WDT enable — 0.42 0.7 mA — 1.1 1.7 mA No load, fH=12MHz, fL=fH/32, LDO, LCD, ADC off, WDT enable — 0.38 0.6 mA — 1.0 1.5 mA No load, fH=12MHz, fL=fH/64, LDO, LCD, ADC off, WDT enable — 0.36 0.55 mA — 1.0 1.5 mA No load, LDO, LCD, ADC off, WDT enable, LXTLP=0 — 10 20 μA — 30 50 μA No load, LDO, LCD, ADC off, WDT enable, LXTLP=1 — 10 20 μA — 30 50 μA No load, LDO, LCD, ADC off, WDT enable — 10 20 μA — 30 50 μA — 10 20 μA — 30 50 μA No load, system HALT, LDO, LCD, ADC off, WDT enable, fSYS=12MHz — 0.6 1.0 mA — 1.2 2.0 mA No load, system HALT, LDO, LCD, ADC off, WDT enable, fSYS=12MHz — 1.3 3.0 μA — 2.2 5.0 μA No load, system HALT, LDO, LCD, ADC off, WDT enable, fSYS=12MHz — 1.3 3.0 μA — 2.2 5.0 μA No load, system HALT, LDO, LCD, ADC off, WDT enable, fSYS=4.9152×3MHz — 1.3 3.0 μA — 2.2 5.0 μA No load, system HALT, LDO, LCD, ADC off, WDT enable, fSYS=12MHz/64 — 0.34 0.6 mA — 0.85 1.2 mA No load, system HALT, LDO, LCD, ADC off, WDT enable, fSYS=12MHz/64 — 1.3 3.0 μA — 2.2 5.0 μA VDD 5V 5V 5V 3V 5V 3V 5V 5V 5V 3V 5V Conditions No load, LDO, LCD, ADC off, WDT enable, LXTLP=0 15 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Symbol Parameter Test Conditions ISTB7 Standby Current (Idle) (LXT, fSYS=fSUB=fLXT, fS=fSUB=fLXT) ISTB8 Standby Current (Idle) (LXT, fSYS=off, fS=T1) ISTB9 Standby Current (Idle) (LXT, fSYS=off, fS=fSUB=fLXT) 3V ISTB10 Standby Current (Idle) (LIRC, fSYS=off, fS=fSUB=fLIRC) 3V ISTB11 Standby Current (Idle) (LXT, fSYS=off, fS=fSUB=fLIRC) 3V ISTB12 Standby Current (Sleep) (HXT, fSYS=off, fS=fSUB=fLXT or fLIRC) ISTB13 Standby Current (Sleep) (HXT, fSYS=off, fS=fSUB=fLXT) 3V ISTB14 Standby Current (Sleep) (HXT, fSYS=off, fS=fSUB=fLIRC) 3V ISTB15 Standby Current (Sleep) (LXT, fSYS=off, fS=fSUB=fLXT or fLIRC) ISTB16 Standby Current (Sleep) (LXT, fSYS=off, fS=fSUB=fLXT) ISTB17 Standby Current (Sleep) (HXT, fSYS=off, fS=fSUB=fLXT or fLIRC) VIL Input Low Voltage for I/O Ports, TCKn, TPn_0, TPn_1 and INTn VIH Input High Voltage for I/O Ports, TCKn, TPn_0, TPn_1 and INTn 3V 5V 3V 5V 5V 5V 5V 3V 5V 5V 5V 3V 5V 3V 5V — VLVR3 Rev. 1.10 Max. Unit No load, system HALT, LDO, LCD, ADC off, WDT enable, fSYS=32768Hz — 1.9 4.0 μA — 3.3 7.0 μA No load, system HALT, LDO, LCD, ADC off, WDT enable, fSYS=32768Hz — 1.3 3.0 μA — 2.2 5.0 μA No load, system HALT, LDO, LCD, ADC off, WDT enable, fSYS=32768Hz — 1.3 3.0 μA — 2.2 5.0 μA No load, system HALT, LDO, LCD, ADC off, WDT enable, fSYS=32kHz — 1.3 3.0 μA — 2.2 5.0 μA No load, system HALT, LDO, LCD, ADC off, WDT enable, fSYS=32768Hz — 1.3 3.0 μA — 2.2 5.0 μA No load, system HALT, LDO, LCD, ADC off, WDT disable, fSYS=12MHz — 0.1 1 μA — 0.3 2 μA No load, system HALT, LDO, LCD, ADC off, WDT enable, fSYS=12MHz — 1.3 5 μA — 2.2 10 μA No load, system HALT, LDO, ADC off, WDT enable, fSYS=12MHz — 1.3 5 μA — 2.2 10 μA No load, system HALT, LDO, LCD, ADC off, WDT disable, fSYS=32768Hz — 0.1 1 μA — 0.3 2 μA No load, system HALT, LDO, ADC off, WDT enable, fSYS=32768Hz — 1.3 3.0 μA — 2.2 5.0 μA — 90 120 μA No load, system HALT, LDO, LCD, ADC off, WDT disable, fSYS=12MHz, LVR enable and LVDEN=1 — 0 — 0.2VDD V 5V — 0 — 1.5 V — — 0.8VDD — VDD V 5V — 3.5 — 5 V LVR enable, 2.1V option Low Voltage Reset Voltage — VLVR4 ILVR Typ. Conditions — VLVR1 VLVR2 Min. VDD LVR enable, 2.55V option LVR enable, 3.15V option 2.1 -5% LVR enable, 3.8V option Low Voltage Reset Current — LVR enable, LVDEN=0 16 2.55 3.15 V +5% 3.8 — 60 V V V 90 μA October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit VLVD1 LVDEN=1, VLVD=2.0V 2.0 V VLVD2 LVDEN=1, VLVD=2.2V 2.2 V VLVD3 LVDEN=1, VLVD=2.4V 2.4 V VLVD4 VLVD5 Low Voltage Detector Voltage — LVDEN=1, VLVD=2.7V LVDEN=1, VLVD=3.0V -5% 2.7 3.0 +5% V V VLVD6 LVDEN=1, VLVD=3.3V 3.3 V VLVD7 LVDEN=1, VLVD=3.6V 3.6 V VLVD8 LVDEN=1, VLVD=4.0V 4.0 V ILVD1 LVR disable, LVDEN=1 — 75 120 μA LVR enable, LVDEN=1 — 90 150 μA — VDD=3V, VOL=0.1VDD 4 8 — mA — VDD=5V, VOL=0.1VDD 10 20 — mA — VDD=3V, VOH=0.9VDD -2 -4 — mA — VDD=5V, VOH=0.9VDD -5 -10 — mA LCD Sink Current (PA, PC, PD, PE) — VLCD=3V, VOL=0.1VLCD 210 420 — μA — VLCD=5V, VOL=0.1VLCD 350 700 — μA IOH2 LCD Source Current (PA, PC, PD, PE) — VLCD=3V, VOH=0.9VLCD -80 -160 — μA — VLCD=5V, VOH=0.9VLCD -180 -360 — μA RPH Pull-high Resistance of I/O Ports 3V — 20 60 100 kΩ 5V — 10 30 50 kΩ Low Voltage Detector Current — IOL1 I/O Port Sink Current (PA~PF) IOH1 I/O Port Source Current (PA~PF) IOL2 ILVD2 Rev. 1.10 17 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU A.C. Characteristics Ta=25°C Symbol Parameter Test Conditions Min. Typ. Max. Unit 0.4 ─ 8 MHz 0.4 ─ 10 MHz 0.4 ─ 12 MHz 0.4 ─ 16 MHz -2% 4.9152×2 +2% MHz ─ 32768 ─ Hz -10% 32 +10% kHz -50% 32 +60% kHz fSYS=HXT or LXT ─ 1024 ─ fSYS=HIRC ─ 16 ─ fSYS=LIRC ─ 1~2 ─ VDD Conditions 2.2V~5.5V fSYS1 System Clock (HXT) 2.7V~5.5V ─ 2.7V~5.5V 4.5V~5.5V fSYS2 System Clock (HIRC) 5V fSYS3 System Clock (LXT) ─ fLIRC System Clock (LIRC) tSST System Start-up Timer Period (Wake-up from HALT) ─ System Reset Delay Time (Power On Reset) ─ ─ 25 50 100 ms System Reset Delay Time (Any Reset except Power On Reset) ─ ─ 8.3 16.7 33.3 ms tINT Interrupt Pulse Width ─ ─ 10 ─ ─ μs tLVR Low Voltage Width to Reset ─ ─ 120 240 480 μs tLVD Low Voltage Width to Interrupt ─ ─ 60 120 240 μs tRSTD tLVDS 5V Ta=25°C ─ Ta=25°C 2.2V~5.5V Ta=-40°C~85°C tSYS ─ For LVR enable, LVD off→on ─ ─ 15 μs ─ For LVR disable, LVD off→on ─ ─ 150 μs LVDO Stable Time tEERD EEPROM Read Time ─ ─ ─ ─ 4 tSYS tEEWR EEPROM Write Timet ─ ─ 1 2 4 ms tTIMER TCKn and Timer Capture Input Pulse Width ─ ─ 0.3 ─ ─ μs Note: tSYS = 1/fSYS Rev. 1.10 18 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU LDO+PGA+ADC+VCM Electrical Characteristics Ta=25°C Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit VIN LDO Supply Voltage — — 2.7 — 5.5 V IVOREG LDO Operating Current — No load, LDOVS[1:0]=00 — 135 150 μA — LDOVS[1:0]=00 — LDOVS[1:0]=01 — LDOVS[1:0]=10 +5% V — LDOVS[1:0]=11 — LDOVS[1:0]=00 — — 100 — LDOVS[1:0]=01 — — 130 — LDOVS[1:0]=10 — — 180 — LDOVS[1:0]=11 — — 200 — Ta=-40°C~85°C — — 30 Ppm/°C — VDD=2.7V~5.5V -0.3 — +0.3 %/V — 25 50 mV LDO Output Voltage (IL=0.1mA, VIN>VOREG+0.2V) VOREG Dropout Voltage (IL=10mA) Temperature Drift LDOVS[1:0]=00b V Voltage Drift IL=100μA OREG ΔVLOAD Load Regulation Load =0mA~10mA, MCU HALT, LDO=2.5V, 2.7V LDO enable, Other function disable 2.5 -5% 2.6 2.9 3.3 mV — No load -5% 1.2 +5% V — IL=200μA 0.98 — 1.02 V Temperature Drift — IL=10μA, Ta=-40°C~85°C — — 100 Ppm/°C VDDA Voltage Drift — No load, VDDA=2.5V~3.3V — 100 — μV/V tVCM VCM Turn on Stable Time — 10 — — ms ICMSRC VCM Source Current — VCM drop 2% of VCM 1 — — mA ICMSNK VCM Sink Current — VCM raise 2% of VCM 1 — — mA — 2.5 — 3.3 V VCM enable, VRBUFP=1, VRBUFN=1 — — 750 VCM enable, VRBUFP=0, VRBUFN=0 — 450 675 VCM disable, VRBUFP=0, VRBUFN=0 — 378 450 System HALT, No load — — 1 μA — — 20 Bit VCM Output Voltage VCM — ADC & ADC internal reference Voltage (Delta Sigma ADC) AVDD ICM+IPGA +IADC Supply Voltage for VCM, ADC, PGA Operating Current for VCM, PGA and ADC — — μA IADSTB Standby Current — RSAD ADC Resolution — NNFC Noise Free Code — PGA Gain=128 Data Rate=12.5Hz — 14.9 — Bit ENOB Effective Number of Bits — PGA Gain=128 Data Rate=12.5Hz — 17.6 — Bit Rev. 1.10 — 19 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Symbol fAD Test Conditions Parameter VDD A/D Clock Frequency (fMCLK) fADO — ADC Output Data Rate — VREF+ VREF- Conditions Reference Input Voltage VREF — Min. Typ. Max. Unit MHz — 4.9152 — fMCLK= 4.9152MHz FLMS[2:0]=000, ADC CLK=MCLK/30 5 — 640 fMCLK= 4.9152MHz FLMS[2:0]=010, ADC CLK=MCLK/12 12.5 — 1600 Hz — VREFS=1, VRBUFP=0, VRBUFN=0 0.96 1.2 2.2 0 0 1.0 — VREF=(VREF+)-(VREF-) 0.96 1.2 1.44 0.4 — AVDD1.3 V ΔVR/Gain — ΔVR+ /Gain V V PGA VDI+, VDI- Absolute/common Input Voltage — ΔDI± Differentail Input Voltage Range — TCPGA Gain Temperature Drift — — — 5 — Ppm/°C — ΔVR=1.2V, VGS[1:0]=00 (Gain=1), VRBUFP=0, VRBUFN=0 — 175 — μV/°C — Gain = PGS×AGS Temperature sensor Sensor Temperature Drift TCS Effective Number of Bits (ENOB) AVDD=3.3V, VREF=1.2V, MCLK=4.9152MHz, FLMS[2:0]=000 PGA Gain DATA RATE (SPS) 1 2 4 8 16 32 64 128 5 19.7 19.8 19.6 19.7 19.7 19.6 19.2 18.6 10 19.4 19.3 19.3 19.3 19.3 19.1 18.7 18.1 20 19.0 18.8 18.7 18.9 18.8 18.6 18.2 17.5 40 18.4 18.3 18.3 18.3 18.3 18.1 17.7 17.0 80 18.1 17.9 18.0 17.9 17.9 17.6 17.2 16.5 160 17.6 17.4 17.4 17.4 17.3 17.1 16.6 15.9 320 15.8 15.8 15.9 15.8 15.9 15.9 15.8 15.3 640 14.1 14.0 14.0 14.1 14.1 14.0 14.1 14.4 Rev. 1.10 20 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU AVDD=3.3V, VREF=1.2V, MCLK=4.9152MHz, FLMS[2:0]=010 PGA Gain DATA RATE (SPS) 1 2 4 8 16 32 64 128 12.5 19.4 18.8 18.7 18.8 18.8 18.7 18.9 18.1 25 19.0 18.3 18.3 18.3 18.3 18.2 17.9 17.3 50 18.5 17.8 17.8 17.8 17.9 17.7 17.4 16.8 100 18.2 18.2 18.1 18.2 18.1 17.8 17.2 16.4 200 17.9 17.8 17.8 17.8 17.6 17.3 16.7 15.9 400 17.4 17.2 17.2 17.2 17.1 16.8 16.2 15.4 800 16.2 16.1 16.1 16.1 16.1 15.9 15.5 14.8 1600 14.5 14.5 14.5 14.4 14.5 14.5 14.3 14.0 Comparator Electrical Characteristics Ta=25°C Symbol Parameter Test Conditions Min. Typ. Max. Unit — 2.2 — 5.5 V — — 37 56 — 130 200 VDD Conditions — 3V VCMP Comparator Operating Voltage ICMP Comparator Operating Current VCMPOS Comparator Input Offset Voltage — — -10 — 10 mV VHYS Hysteresis Width — — 20 40 80 mV VCM Comparator Common Mode Voltage Range — — VSS — VDD1.4V V AOL Comparator Open Loop Gain — — 60 80 — dB tPD Comparator Response Time — — 200 450 ns 5V With 100mV overdrive (Note) μA Note: Measured with comparator one input pin at VCM = (VDD-1.4)/2 while the other pin input transition from VSS to (VCM + 100mV) or from VDD to (VCM – 100mV). Rev. 1.10 21 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU LCD Electrical Characteristics Ta=25°C Symbol ILCD1 ILCD2 Test Conditions Parameter VDD Only LCD on Current, LCD Clock = 4kHz 5V Standby Current (Idle) (fSYS, fWDT off, fS=fSUB=fLXT or fLIRC) 5V Min. Typ. Max. LCDIS[1:0]=00b — 25 37.5 LCDIS[1:0]=01b — 50 75.0 LCDIS[1:0]=10b — 100 150 LCDIS[1:0]=11b — 200 300 — 3 6 Conditions VLCD=5V (R type) No load, 1/3 Bias VLCD=5V (C type) No load, system HALT, LCD on, WDT off, C type, 1/3 Bias Unit μA μA Note: User has to take care that VMAX must be greater than or equal to VLCD, VDD=VMAX=VLCD=2.7V ~ 5.5V. Power-on Reset Characteristics Ta=25°C Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV RRVDD VDD Raising Rate to Ensure Power-on Reset — — 0.035 — — V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms Rev. 1.10 22 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of the device take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a HXT, LXT, HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. System Clocking and Pipelining For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. Rev. 1.10 23 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is ex ecuted except for instructions, such as "JMP" or "CALL" that demands a jump to a non-consecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Program Counter Program Counter High Byte PCL Register PC11~PC8 PCL7~PCL0 Program Counter The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Rev. 1.10 24 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is organized into 8 levels and neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P ro g ra m T o p o f S ta c k S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k P o in te r B o tto m C o u n te r S ta c k L e v e l 3 o f S ta c k P ro g ra m M e m o ry S ta c k L e v e l 8 Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA • Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC • Increment and Decrement INCA, INC, DECA, DEC • Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Rev. 1.10 25 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, this Flash device offers users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 4K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. Program Memory Structure Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the "TABRD [m]" or "TABRDL [m]" instructions, respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as 0. The accompanying diagram illustrates the addressing data flow of the look-up table. A d d re s s L a s t p a g e o r T B H P R e g is te r T B L P R e g is te r Rev. 1.10 D a ta 1 6 b its R e g is te r T B L H U s e r S e le c te d R e g is te r H ig h B y te L o w B y te 26 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is "F00H" which refers to the start address of the last page within the 4K Program Memory of the microcontroller. The table pointer is setup here to have an initial value of "06H". This will ensure that the first data read from the data table will be at the Program Memory address "F06H" or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address specified by TBLP and TBHP if the "TABRD [m]" instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the "TABRD [m]" instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a ; to the last page or present page mov a,0Fh ; initialise high table pointer mov tbhp,a : : tabrdl tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address "F06H" transferred to tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address "F05H" transferred to ; tempreg2 and TBLH in this example the data "1AH" is ; transferred to tempreg1 and data "0FH" to register tempreg2 : : org F00h; sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : Rev. 1.10 27 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. The Holtek Flash MCU to Writer Programming Pin correspondence table is as follows: Holtek Writer Pins MCU Programming Pins Pin Description ICPDA PA0 Programming Serial Data/Address ICPCK PA2 Programming Clock VDD VDD Power Supply VSS VSS Ground The Program Memory can be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply. The technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. During the programming process, taking control of the PA0 and PA2 pins for data and clock programming purposes. The user must there take care to ensure that no other outputs are connected to these two pins. W r ite r C o n n e c to r S ig n a ls M C U W r ite r _ V D D V D D IC P D A P A 0 IC P C K P A 2 W r ite r _ V S S V S S * P r o g r a m m in g P in s * T o o th e r C ir c u it Note: * may be resistor or capacitor. The resistance of * must be greater than 1k or the capacitance of * must be less than 1nF. Rev. 1.10 28 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU On Chip Debug Support – OCDS There is an EV chip which is used to emulate the device. The EV chip device also provides an "OnChip Debug" function to debug the device during the development process. The EV chip and the actual MCU device are almost functionally compatible except for "On-Chip Debug" function. Users can use the EV chip device to emulate the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/ Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip for debugging, other functions which are shared with the OCDSDA and OCDSCK pins in the actual MCU device will have no effect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For more detailed OCDS information, refer to the corresponding document named "Holtek e-Link for 8-bit MCU OCDS User’s Guide". Rev. 1.10 Holtek e-Link Pins EV Chip Pins OCDSDA OCDSDA On-Chip Debug Support Data/Address input/output OCDSCK OCDSCK On-Chip Debug Support Clock input VDD VDD Power Supply VSS VSS Ground 29 Pin Description October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU RAM Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into three sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. The third area is reserved for the LCD Memory. This special area of Data Memory is mapped directly to the LCD display so data written into this memory area will directly affect the displayed data. The addresses of the LCD Memory area overlap those in the General Purpose Data Memory area. Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value. The overall Data Memory is subdivided into several banks. The Special Purpose Data Memory registers are accessible in all banks, with the exception of the EEC register at address 40H, which is only accessible in Bank 1. Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value. The start address of the Data Memory for all devices is the address 00H. Data Memory Structure Rev. 1.10 30 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Special Purpose Data Memory Rev. 1.10 31 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section; however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of "00H" and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks according to BP register. Direct Addressing can only be used with Bank 0, all other Banks must be addressed indirectly using MP1 and IAR1. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Indirect Addressing Program Example data.section ‘data’ adres1 db? adres2 db? adres3 db? adres4 db? block db? code.section at 0 code org 00h start: mov a, 04h; setup size of block mov block, a mov a, offset adres1 ; Accumulator loaded with first RAM address mov mp0, a ; setup memory pointer with first RAM address loop: clr IAR0 ; clear the data at address defined by MP0 inc mp0; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Rev. 1.10 32 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Bank Pointer – BP The Data Memory are divided into several banks. Selecting the required Data Memory area is achieved using the Bank Pointer. Bits 0~1 of the Bank Pointer is used to select Data Memory Banks 0~2. The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within any bank. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from banks other than Bank 0 must be implemented using Indirect addressing. BP Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — DMBP1 DMBP0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0DMBP1~DMBP0: Select Data Memory Banks 00: Bank 0 01: Bank 1 10: Bank 2 11: Undefined Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the "INC" or "DEC" instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Rev. 1.10 33 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the "CLR WDT" instruction. PDF is set by executing the "HALT" instruction. • TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Rev. 1.10 34 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU STATUS Register Bit 7 6 5 4 3 2 1 0 Name — — TO PDF OV Z AC C R/W — — R R R/W R/W R/W R/W POR — — 0 0 x x x x "x" unknown Bit 7~6 Unimplemented, read as "0" Bit 5TO: Watchdog Time-Out flag 0: After power up or executing the "CLR WDT" or "HALT" instruction 1: A watchdog time-out occurred. Bit 4PDF: Power down flag 0: After power up or executing the "CLR WDT" instruction 1: By executing the "HALT" instruction Bit 3OV: Overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1AC: Auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0C: Carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction. Rev. 1.10 35 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU EEPROM Data memory This device contains an area of internal EEPROM Data Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of re-programmable memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. EEPROM Data Memory Structure The EEPROM Data Memory capacity is 64×8 bits for the device. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. Read and Write operations to the EEPROM are carried out in single byte operations using an address and data register in Bank 0 and a single control register in Bank 1. Device Capacity Address HT67F5640 64×8 00H~3FH EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory. These are the address register, EEA, the data register, EED and a single control register, EEC. As both the EEA and EED registers are located in Bank 0, they can be directly accessed in the same was as any other Special Function Register. The EEC register however, being located in Bank1, cannot be directly addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register, IAR1. Because the EEC control register is located at address 40H in Bank 1, the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer register, BP, set to the value, 01H, before any operations on the EEC register are executed. EEPROM Register List Name Bit 7 6 5 4 3 2 1 0 EEA — — D5 D4 D3 D2 D1 D0 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC — — — — WREN WR RDEN RD 7 6 5 4 3 2 1 0 EEA Register Bit Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — x x x x x x "x" unknown Bit 7~6 Unimplemented, read as "0" Bit 5~0D5~D0: Data EEPROM address Data EEPROM address bit 5 ~ bit 0 Rev. 1.10 36 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU EED Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown Bit 7~0D7~D0: Data EEPROM data Data EEPROM data bit 7 ~ bit 0 EEC Register Bit 7 6 5 4 3 2 1 0 Name — — — — WREN WR RDEN RD R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3WREN: Data EEPROM Write Enable 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2WR: EEPROM Write Control 0: Write cycle has finished 1: Activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high. Bit 1RDEN: Data EEPROM Read Enable 0: Disable 1: Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations. Bit 0RD: EEPROM Read Control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high. Note: The WREN, WR, RDEN and RD can not be set high at the same time in one instruction. The WR and RD can not be set high at the same time. Rev. 1.10 37 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Writing Data to the EEPROM To write data to the EEPROM, the write enable bit, WREN, in the EEC register must first be set high to enable the write function. The EEPROM address of the data to be written must then be placed in the EEA register and the data placed in the EED register. If the WR bit in the EEC register is now set high, an internal write cycle will then be initiated. Setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered-on the Write Enable bit in the control register will be cleared preventing any write operations. Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this adds a further measure of protection against spurious write operations. During normal program operation, ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. However as the EEPROM is contained within a Multi-function Interrupt, the associated multi-function interrupt enable bit must also be set. When an EEPROM write cycle ends, the DEF request flag and its associated multi-function interrupt request flag will both be set. If the global, EEPROM and Multifunction interrupts are enabled and the stack is not full, a jump to the associated Multi-function Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag will be automatically reset, the EEPROM interrupt flag must be manually reset by the application program. More details can be obtained in the Interrupt section. Rev. 1.10 38 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1 where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete. Otherwise, the EEPROM read or write operation will fail. Programming Examples • Reading data from the EEPROM – polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A SET IAR1.1 SET IAR1.0 BACK: SZ IAR1.0 JMP BACK CLR IAR1 CLR BP MOV A, EED MOV READ_DATA, A ; user defined address ; setup memory pointer MP1 ; MP1 points to EEC register ; setup Bank Pointer ; set RDEN bit, enable read operations ; start Read Cycle - set RD bit ; check for read cycle end ; disable EEPROM read/write ; move read data to register • Writing Data to the EEPROM – polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, EEPROM_DATA MOV EED, A MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A CLR EMI SET IAR1.3 SET IAR1.2 SET EMI BACK: SZ IAR1.2 JMP BACK CLR IAR1 CLR BP Rev. 1.10 ; user defined address ; user defined data ; setup memory pointer MP1 ; MP1 points to EEC register ; setup Bank Pointer ; set WREN bit, enable write operations ; start Write Cycle - set WR bit ; check for write cycle end ; disable EEPROM read/write 39 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Oscillator Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. External oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. All oscillator options are selected through the configuration options. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/ power ratio, a feature especially important in power sensitive portable applications. Type Name Freq. Pins External Crystal HXT 400kHz~20MHz OSC1/OSC2 Internal High Speed RC HIRC 4.9152, 4.9152×2 or 4.9152×3MHz — External Low Speed Crystal LXT 32.768kHz XT1/XT2 Internal Low Speed RC LIRC 32kHz — Oscillator Types System Clock Configurations There are four methods of generating the system clock, two high speed oscillators and two low speed oscillators. The high speed oscillators are the external crystal oscillator and the internal 4.9152MHz, 4.9152×2MHz or 4.9152×3MHz RC oscillator. The two low speed oscillators are the internal 32kHz RC oscillator and the external 32.768kHz crystal oscillator. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK bit and CKS2~CKS0 bits in the SMOD register and as the system clock can be dynamically selected. The actual source clock used for each of the high speed and low speed oscillators is chosen via configuration options. The frequency of the slow speed or high speed system clock is also determined using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection for either the high or low speed oscillator. Rev. 1.10 40 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU High Speed �s�illato� HXT fH 6-stage P�es�ale� HIRC fH/� fH/� High Speed �s�illation Configu�ation �ption Low Speed �s�illato� LIRC fH/8 fH/16 fH/3� fH/6� fSYS fSUB LXT HLCLK� CKS�~CKS0 �its Low Speed �s�illation Configu�ation �ption fSUB Fast Wake-up f�om SLEEP Mode o� IDLE Mode Cont�ol (fo� HXT only) System Clock Configurations External Crystal/Ceramic Oscillator – HXT The External Crystal/Ceramic System Oscillator is one of the high frequency oscillator choices, which is selected via configuration option. For most crystal oscillator configurations, the simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. However, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer’s specification. For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure thatthe crystal and any associated resistors andcapacitors along with interconnectinglines are all located as close to the MCUas possible. Crystal/Resonator Oscillator – HXT Rev. 1.10 41 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Crystal Oscillator C1 and C2 Values Crystal Frequency C1 C2 12MHz 0pF 0pF 8MHz 0pF 0pF 4MHz 0pF 0pF 1MHz 100pF 100pF Note: C1 and C2 values are for guidance only. Crystal Recommended Capacitor Values Internal RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has three fixed frequencies of either 4.9152MHz, 4.9152×2MHz or 4.9152×3MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of 25°C degrees, the fixed oscillation frequency of 4.9152×2MHz will have a tolerance within 2%. Note that if this internal system clock option is selected, as it requires no external pins for its operation, I/O pins PB1 and PB2 are free for use as normal I/O pins. Internal 32kHz Oscillator – LIRC The Internal 32kHz System Oscillator is one of the low frequency oscillator choices, which is selected via configuration option. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of 25°C degrees, the fixed oscillation frequency of 32kHz will have a tolerance within 10%. External 32.768kHz Crystal Oscillator – LXT The External 32.768kHz Crystal System Oscillator is one of the low frequency oscillator choices, which is selected via configuration option. This clock source has a fixed frequency of 32.768kHz and requires a 32.768kHz crystal to be connected between pins XT1 and XT2. The external resistor and capacitor components connected to the 32.768kHz crystal are necessary to provide oscillation. For applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. During power-up there is a time delay associated with the LXT oscillator waiting for it to start-up. When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the SLEEP or IDLE Mode. To do this, another clock, independent of the system clock, must be provided. However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer specification. The external parallel feedback resistor, RP, is required. Rev. 1.10 42 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Some configuration options determine if the XT1/XT2 pins are used for the LXT oscillator or as I/O pins. • If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/ O pins. • If the LXT oscillator is used for any clock source, the 32.768kHz crystal should be connected to the XT1/XT2 pins. For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure thatthe crystal and any associated resistors andcapacitors along with interconnectinglines are all located as close to the MCUas possible. External LXT Oscillator LXT Oscillator C1 and C2 Values Crystal Frequency C1 C2 32.768kHz 10pF 10pF Note: 1. C1 and C2 values are for guidance only. 2. RP=5M~10MΩ is recommended. 32.768kHz Crystal Recommended Capacitor Values LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power Mode. The mode selection is executed using the LXTLP bit in the TBC register. LXTLP Bit LXT Mode 0 Quick Start 1 Low-power After power on, the LXTLP bit will be automatically cleared to zero ensuring that the LXT oscillator is in the Quick Start operating mode. In the Quick Start Mode the LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has fully powered up it can be placed into the Low-power mode by setting the LXTLP bit high. The oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the LXT oscillator start-up. In power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the LXTLP bit high about 2 seconds after power-on. It should be noted that, no matter what condition the LXTLP bit is set to, the LXT oscillator will always be function normally, the only difference is that it will take more time to start up if in the Low-power mode. Rev. 1.10 43 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Supplementary Oscillators The low speed oscillators, in addition to providing a system clock source are also used to provide a clock source to four other device functions. These are the Watchdog Timer, the Time Base Interrupts function, the LCD driver, and the SIM. Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The device has many different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock options using configuration options and register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency fH or low frequency fSUB source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from either an HXT or HIRC oscillator, selected via a configuration option. The low speed system clock source can be sourced from internal clock fSUB. If fSUB is selected then it can be sourced by either the LXT or LIRC oscillator, selected via a configuration option. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. The fSUB clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. The fSUB is used as a clock source for the Watchdog timer, the Time Base interrupt, the TMs, the LCD and the SIM functions. Rev. 1.10 44 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU High Speed �s�illato� HXT fH 6-stage P�es�ale� HIRC fH/� fH/� High Speed �s�illation Configu�ation �ption Low Speed �s�illato� LIRC fH/8 fH/16 fH/3� fH/6� fSYS fSUB LXT HLCLK� CKS�~CKS0 �its Low Speed �s�illation Configu�ation �ption fSUB Fast Wake-up f�om SLEEP Mode o� IDLE Mode Cont�ol (fo� HXT only) fSUB fTB Time Base fSYS/� TBCK fSUB fS WDT fSYS/� Configu�ation �ption fSUB fSUB fSYS ÷8 �KHz Clo�k Sou��e Sele�tion LCD D�ive� SIM System Clock Configurations Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillation will stop to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use. Rev. 1.10 45 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0, SLEEP1, IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power. Operating Mode Description CPU fSYS fSUB fS NORMAL Mode on fH~fH/64 on on SLOW Mode on fSUB on on IDLE0 Mode off off on on/off IDLE1 Mode off on on on SLEEP0 Mode off off off off SLEEP1 Mode off off on on NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. This mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the HXT or HIRC oscillators. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from one of the low speed oscillators, either the LXT or the LIRC. Running the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW Mode, the fH is off. SLEEP0 Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP0 mode the CPU will be stopped, and the fSUB and fS clocks will be stopped too, and the Watchdog Timer function is disabled. In this mode, the LVDEN is must cleared to zero. If the LVDEN is set high, it won’t enter the SLEEP0 Mode. SLEEP1 Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP1 mode the CPU will be stopped. However the fSUB and fS clocks will continue to operate if the LVDEN is "1" or the Watchdog Timer function is enabled and if its clock source is chosen via configuration option to come from the fSUB. Rev. 1.10 46 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU IDLE0 Mode The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is low. In the IDLE0 Mode the system oscillator will be inhibited from driving the CPU but some peripheral functions will remain operational such as the Watchdog Timer, TMs, LCD driver and SIM. In the IDLE0 Mode, the system oscillator will be stopped. In the IDLE0 Mode the Watchdog Timer clock, fS, will either be on or off depending upon the fS clock source. If the source is fSYS/4 then the fS clock will be off, and if the source comes from fSUB then fS will be on. IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational such as the Watchdog Timer, TMs, LCD driver and SIM. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. In the IDLE1 Mode the Watchdog Timer clock, fS, will be on. If the source is fSYS/4 then the fS clock will be on, and if the source comes from fSUB then fS will be on. Control Register The registers, SMOD and CTRL, are used for overall control of the internal clocks within the device. SMOD Register Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 FSTEN LTO HTO IDLEN HLCLK R/W R/W R/W R/W R/W R R R/W R/W POR 0 0 0 0 0 0 1 1 Bit 7~5CKS2~CKS0: The system clock selection when HLCLK is "0" 000: fSUB (fLXT or fLIRC) 001: fSUB (fLXT or fLIRC) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which can be either the LXT or LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4FSTEN: Fast Wake-up Control (only for HXT) 0: Disable 1: Enable This is the Fast Wake-up Control bit which determines if the fSUB clock source is initially used after the device wakes up. When the bit is high, the fSUB clock source can be used as a temporary system clock to provide a faster wake up time as the fSUB clock is available. Rev. 1.10 47 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Bit 3LTO: Low speed system oscillator ready flag 0: Not ready 1: Ready This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. The flag will be low when in the SLEEP0 Mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if the LXT oscillator is used and 1~2 clock cycles if the LIRC oscillator is used. Bit 2HTO: High speed system oscillator ready flag 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to zero by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as "1" by the application program after device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a wakeup has occurred, the flag will change to a high level after 1024 clock cycles if the HXT oscillator is used and after 15~16 clock cycles if the HIRC oscillator is used. Bit 1IDLEN: IDLE Mode control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. Bit 0HLCLK: system clock selection 0: fH/2 ~ fH/64 or fSUB 1: fH This bit is used to select if the fH clock or the fH/2~fH/64 or fSUB clock is used as the system clock. When the bit is high the fH clock will be selected and if low the fH/2~fH/64 or fSUB clock will be selected. When system clock switches from the fH clock to the fSUB clock and the fH clock will be automatically switched off to conserve power. CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — — R/W R/W — — — — LVRF LRF WRF R/W R/W R/W POR 0 — — — — x 0 0 "x" unknown Bit 7FSYSON: fSYS Control in IDLE Mode 0: Disable 1: Enable Bit 6~3 Unimplemented, read as "0" Bit 2LVRF: LVR function reset flag Described elsewhere. Bit 1LRF: LVR Control register software reset flag Described elsewhere. Bit 0WRF: WDT Control register software reset flag Described elsewhere. Rev. 1.10 48 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Fast Wake-up To minimise power consumption the device can enter the SLEEP or IDLE0 Mode, where the system clock source to the device will be stopped. However when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. To ensure the device is up and running as fast as possible a Fast Wake-up function is provided, which allows fSUB, namely either the LXT or LIRC oscillator, to act as a temporary clock to first drive the system until the original system oscillator has stabilised. As the clock source for the Fast Wake-up function is fSUB, the Fast Wake-up function is only available in the SLEEP1 and IDLE0 modes. When the device is woken up from the SLEEP0 mode, the Fast Wake-up function has no effect because the fSUB clock is stopped. The Fast Wake-up enable/disable function is controlled using the FSTEN bit in the SMOD register. If the HXT oscillator is selected as the NORMAL Mode system clock, and if the Fast Wake-up function is enabled, then it will take one to two tSUB clock cycles of the LIRC or LXT oscillator for the system to wake-up. The system will then initially run under the fSUB clock source until 1024 HXT clock cycles have elapsed, at which point the HTO flag will switch high and the system will switch over to operating from the HXT oscillator. If the HIRC oscillator or LIRC oscillator is used as the system oscillator then it will take 15~16 clock cycles of the HIRC or 1~2 cycles of the LIRC to wake up the system from the SLEEP or IDLE0 Mode. The Fast Wake-up bit, FSTEN will have no effect in these cases. System FSTEN Oscillator Bit Wake-up Time (SLEEP0 Mode) Wake-up Time (SLEEP1 Mode) 1024 HXT cycles 1024 HXT cycles 1~2 HXT cycles 1 1024 HXT cycles 1~2 fSUB cycles (System runs with fSUB first for 1024 HXT cycles and then switches over to run with the HXT clock) 1~2 HXT cycles HIRC × 15~16 HIRC cycles 15~16 HIRC cycles 1~2 HIRC cycles LIRC × 1~2 LIRC cycles 1~2 LIRC cycles 1~2 LIRC cycles LXT × 1024 LXT cycles 1024 LXT cycles 1~2 LXT cycles 0 HXT Wake-Up Times Wake-up Time (IDLE0 Mode) Wake-up Time (IDLE1 Mode) "×": don’t care Note that if the Watchdog Timer is disabled, which means that the LXT and LIRC are all both off, then there will be no Fast Wake-up function available when the device wake-up from the SLEEP0 Mode. Rev. 1.10 49 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Operating Mode Switching The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the CTRL register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, fH, to the clock source, fH/2~fH/64 or fSUB. If the clock is from the fSUB, the high speed clock source will stop running to conserve power. When this happens it must be noted that the fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the TMs and the SIM. The accompanying flowchart shows what happens when the device moves between the various operating modes. Rev. 1.10 50 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the HLCLK bit to "0" and set the CKS2~CKS0 bits to "000" or "001" in the SMOD register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LXT or the LIRC oscillators and therefore requires these oscillators to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register. Rev. 1.10 51 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU SLOW Mode to NORMAL Mode Switching In SLOW Mode the system uses either the LXT or LIRC low speed system oscillator. To switch back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set high or HLCLK bit is "0", but CKS2~CKS0 is set to "010", "011", "100", "101", "110" or "111". As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. The amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. Entering the SLEEP0 Mode There is only one way for the device to enter the SLEEP0 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the WDT and LVD both off. When this instruction is executed under the conditions described above, the following will occur: • The system clock and the fSUB clock will be stopped and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and stopped no matter if the WDT clock source originates from the fSUB clock or from the system clock. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Rev. 1.10 52 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Entering the SLEEP1 Mode There is only one way for the device to enter the SLEEP1 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the WDT or LVD on. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the "HALT" instruction, but the WDT or LVD will remain with the clock source coming from the fSUB clock. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT clock source is selected to come from the fSUB clock as the WDT is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the FSYSON bit in CTRL register equal to "0". When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the "HALT" instruction, but the fSUB clock will be on. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT clock source is selected to come from the fSUB clock and the WDT is enabled. The WDT will stop if its clock source originates from the system clock. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the FSYSON bit in CTRL register equal to "1". When this instruction is executed under the conditions described above, the following will occur: • The system clock and the fSUB clock will be on and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled regardless of the WDT clock source which originates from the fSUB clock or from the system clock. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Rev. 1.10 53 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to the device which has different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the configuration options have enabled the LXT or LIRC oscillator. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred microamps. Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external falling edge on Port A • A system interrupt • A WDT overflow If the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the "HALT" instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HALT" instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Rev. 1.10 54 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Programming Considerations The HXT and LXT oscillators both use the same SST counter. For example, if the system is woken up from the SLEEP0 Mode and both the HXT and LXT oscillators need to start-up from an off state. The LXT oscillator uses the SST counter after HXT oscillator has finished its SST period. • If the device is woken up from the SLEEP0 Mode to the NORMAL Mode, the high speed system oscillator needs an SST period. The device will execute first instruction after HTO is "1". At this time, the LXT oscillator may not be stability if fSUB is from LXT oscillator. The same situation occurs in the power-on state. The LXT oscillator is not ready yet when the first instruction is executed. • If the device is woken up from the SLEEP1 Mode to NORMAL Mode, and the system clock source is from HXT oscillator and FSTEN is "1", the system clock can be switched to the LXT or LIRC oscillator after wake up. • There are peripheral functions, such as WDT, TMs, LCD driver and SIM, for which the fSYS is used. If the system clock source is switched from fH to fSUB, the clock source to the peripheral functions mentioned above will change accordingly. Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal clock, fS, which is in turn supplied by one of two sources selected by configuration option: fSUB or fSYS/4. The fSUB clock can be sourced from either the LXT or LIRC oscillators, again chosen via a configuration option. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. The LXT oscillator is supplied by an external 32.768kHz crystal. The other Watchdog Timer clock source option is the fSYS/4 clock. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable operation. This register together with several configuration options control the overall operation of the Watchdog Timer. Rev. 1.10 55 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~3WE4~WE0: WDT function software control If the WDT configuration option is "always enable": 10101 or 01010: enable Others: reset MCU If the WDT configuration option is "controlled by the WDT control register": 10101: disable 01010: enable Others: reset MCU When these bits are changed by the environmental noise or software setting to reset the microcontroller, the reset operation will be activated after 2~3 LIRC clock cycles and the WRF bit in the CTRL register will be set high. Bit 2~0WS2~WS0: WDT time-out period selection 000: 28/fS 001: 210/fS 010: 212/fS 011: 214/fS 100: 215/fS 101: 216/fS 110: 217/fS 111: 218/fS CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — — LVRF LRF WRF R/W R/W — — — — R/W R/W R/W POR 0 — — — — x 0 0 "x" unknown Bit 7FSYSON: fSYS Control in IDLE Mode Described elsewhere. Bit 6~3 Unimplemented, read as "0" Bit 2LVRF: LVR function reset flag Described elsewhere. Bit 1LRF: LVR Control register software reset flag Described elsewhere. Bit 0WRF: WDT Control register software reset flag 0: not occur 1: occurred This bit is set high by the WDT Control register software reset and cleared by the application program. Note that this bit can only be cleared to zero by the application program. Rev. 1.10 56 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. Some of the Watchdog Timer options, such as always on select and clear instruction type are selected using configuration options. With regard to the Watchdog Timer enable/disable function, there are also five bits, WE4~WE0, in the WDTC register to offer additional enable/disable and reset control of the Watchdog Timer. If the WDT configuration option is determined that the WDT function is always enabled, the WE4~WE0 bits still have effects on the WDT function. When the WE4~WE0 bits value is equal to 01010B or 10101B, the WDT function is enabled. However, if the WE4~WE0 bits are changed to any other values except 01010B and 10101B, which is caused by the environmental noise or software setting, it will reset the microcontroller after 2~3 LIRC clock cycles. If the WDT configuration option is determined that the WDT function is controlled by the WDT control register, the WE4~WE0 values can determine which mode the WDT operates in. The WDT function will be disabled when the WE4~WE0 bits are set to a value of 10101B. The WDT function will be enabled if the WE4~WE0 bits value is equal to 01010B. If the WE4~WE0 bits are set to any other values by the environmental noise or software setting, except 01010B and 10101B, it will reset the device after 2~3 LIRC clock cycles. After power on these bits will have the value of 01010B. WDT Configuration Option Always Enable WE4 ~ WE0 Bits WDT Function 01010B or 10101B Enable Any other values Reset MCU 10101B Disable 01010B Enable Any other values Reset MCU Controlled by WDT Control Register Watchdog Timer Enable/Disable Control Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is a WDT reset, which means a certain value except 01010B and 10101B written into the WE4~WE0 bit filed, the second is using the Watchdog Timer software clear instructions and the third is via a HALT instruction. There is only one method of using software instruction to clear the Watchdog Timer. That is to use the single "CLR WDT" instruction to clear the WDT. The maximum time out period is when the 218 division ratio is selected. As an example, with a 32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration. Rev. 1.10 57 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Watchdog Timer Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. Another type of reset is when the Watchdog Timer overflows and resets. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are four ways in which a reset can occur, through events occurring both internally and externally: Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all I/O ports will be first set to inputs. Note: tRSTD is power-on delay, typical time=50ms Power-On Reset Timing Chart Rev. 1.10 58 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is always enabled with a specific LVR voltage VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally and the LVRF bit in the CTRL register will also be set high. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR value can be selected by the LVS bits in the LVRC register. If the LVS7~LVS0 bits are changed to some certain values by the environmental noise or software setting, the LVR will reset the device after 2~3 LIRC clock cycles. When this happens, the LRF bit in the CTRL register will be set high. After power on the register will have the value of 01010101B. Note that the LVR function will be automatically disabled when the device enters the power down mode. Note: tRSTD is power-on delay, typical time= 16.7ms Low Voltage Reset Timing Chart • LVRC Register Bit 7 6 5 4 3 2 1 0 Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7~0LVS7~LVS0: LVR voltage select 01010101: 2.1V 00110011: 2.55V 10011001: 3.15V 10101010: 3.8V Other values: MCU reset (register is reset to POR value). When an actual low voltage condition occurs, as specified by one of the four defined LVR voltage values above, an MCU reset will be generated. The reset operation will be activated after 2~3 LIRC clock cycles. In this situation the register contents will remain the same after such a reset occurs. Any register value, other than the four defined LVR values above, will also result in the generation of an MCU reset. The reset operation will be activated after 2~3 LIRC clock cycles. However in this situation the register contents will be reset to the POR value. CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — — LVRF LRF WRF R/W R/W — — — — R/W R/W R/W POR 0 — — — — x 0 0 "x" unknown Bit 7FSYSON: fSYS Control in IDLE Mode Described elsewhere. Bit 6~3 Rev. 1.10 Unimplemented, read as "0" 59 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Bit 2LVRF: LVR function reset flag 0: not occur 1: occurred This bit is set high when a specific Low Voltage Reset situation condition occurs. This bit can only be cleared to zero by the application program. Bit 1LRF: LVR Control register software reset flag 0: not occur 1: occurred This bit is set high if the LVRC register contains any non defined LVR voltage register values. This in effect acts like a software reset function. This bit can only be cleared to zero by the application program. Bit 0WRF: WDT Control register software reset flag Described elsewhere. Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as LVR reset except that the Watchdog time-out flag TO will be set high. Note: tRSTD is power-on delay, typical time=16.7ms WDT Time-out Reset during Normal Operation Timing Chart Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to zero and the TO flag will be set high. Refer to the A.C. Characteristics for tSST details. Note: The tSST is 15~16 clock cycles if the system clock source is provided by HIRC. The tSST is 1024 clock for HXT or LXT. The tSST is 1~2 clock for LIRC. WDT Time-out Reset during Sleep Timing Chart Rev. 1.10 60 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 0 Power-on reset Reset Conditions u u LVR reset during Normal or SLOW Mode operation 1 u WDT time-out reset during Normal or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation Note: "u" stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Condition after Reset Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset, WDT begins counting Timer/Event Counter Timer Counter will be turned off Input/Output Ports I/O ports will be setup as inputs, and AN0~AN7 as A/D input pin. Stack Pointer Stack Pointer will point to the top of the stack The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Power On Reset LVR Reset WDT Time-out (Normal Operation) WDT Time-out (HALT) MP0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu MP1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBHP ---- xxxx ---- uuuu ---- uuuu ---- uuuu STATUS --00 xxxx --uu uuuu --1u uuuu - - 11 u u u u BP ---- --00 ---- --00 ---- --00 ---- --uu SMOD 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 uuuu uuuu INTEG ---- 0000 ---- 0000 ---- 0000 ---- uuuu LVDC --00 -000 --00 -000 --00 -000 --uu –uuu INTC0 -000 0000 -000 0000 -000 0000 -uuu uuuu INTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu Register Rev. 1.10 61 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Power On Reset LVR Reset WDT Time-out (Normal Operation) WDT Time-out (HALT) INTC2 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI0 --00 –00 --00 –00 --00 –00 --uu –uu MFI1 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI2 0-00 0-00 0-00 0-00 0-00 0-00 u-uu u-uu MFI3 --00 –00 --00 –00 --00 –00 --uu –uu PAWU 0000 0000 0000 0000 0000 0000 uuuu uuuu PAPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC 1111 1111 1111 1111 1111 1111 uuuu uuuu PDPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PD 1111 1111 1111 1111 1111 1111 uuuu uuuu PDC 1111 1111 1111 1111 1111 1111 uuuu uuuu PEPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PE 1111 1111 1111 1111 1111 1111 uuuu uuuu PEC 1111 1111 1111 1111 1111 1111 uuuu uuuu PFPU ---- ---0 ---- ---0 ---- ---0 ---- ---u PF ---- ---1 ---- ---1 ---- ---1 ---- ---u PFC ---- ---1 ---- ---1 ---- ---1 ---- ---u WDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 uuuu uuuu TBC 0 0 11 0 111 0 0 11 0 111 0 0 11 0 111 uuuu uuuu TM0C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DH ---- --00 ---- --00 ---- --00 ---- --uu TM0AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0AH ---- --00 ---- --00 ---- --00 ---- --uu PTM1C0 0000 0--- 0000 0--- 0000 0--- uuuu u--- PTM1C1 0000 0000 0000 0000 0000 0000 uuuu uuuu Register Rev. 1.10 62 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Power On Reset LVR Reset WDT Time-out (Normal Operation) WDT Time-out (HALT) PTM1DL 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM1DH ---- --00 ---- --00 ---- --00 ---- --uu PTM1AL 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM1AH ---- --00 ---- --00 ---- --00 ---- --uu PTM2C0 0000 0--- 0000 0--- 0000 0--- uuuu u--- PTM2C1 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM2DL 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM2DH ---- --00 ---- --00 ---- --00 ---- --uu PTM2AL 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM2AH ---- --00 ---- --00 ---- --00 ---- --uu PTM1RPL 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM1RPH ---- --00 ---- --00 ---- --00 ---- --uu PTM2RPL 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM2RPH ---- --00 ---- --00 ---- --00 ---- --uu CTRL0 ---- -000 ---- -000 ---- -000 ---- -uuu LCDC 00-- --00 00-- --00 00-- --00 uu-- --uu LCD1 0000 0000 0000 0000 0000 0000 uuuu uuuu LCD2 0000 0000 0000 0000 0000 0000 uuuu uuuu LCD3 0000 0000 0000 0000 0000 0000 uuuu uuuu LCD4 0000 0000 0000 0000 0000 0000 uuuu uuuu CP1C 1000 0--1 1000 0--1 1000 0--1 uuuu u--u CP0C 1000 0--1 1000 0--1 1000 0--1 uuuu u--u PWRC 00-- --00 00-- --00 00-- --00 uu-- --uu PGAC0 -000 0000 -000 0000 -000 0000 -uuu uuuu PGAC1 10-- 000- 10-- 000- 10-- 000- uu-- uuu- PGACS --00 0000 --00 0000 --00 0000 --uu uuuu USR 0 0 0 0 1 0 11 0 0 0 0 1 0 11 0 0 0 0 1 0 11 uuuu uuuu UCR1 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu UCR2 0000 0000 0000 0000 0000 0000 uuuu uuuu BRG xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TXR/RXR xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu IRCTRL0 0000 0000 0000 0000 0000 0000 uuuu uuuu IRCTRL1 ---- ---0 ---- ---0 ---- ---0 ---- ---u ADCR0 0010 00-0 0010 00-0 0010 00-0 uuuu uu-u Register Rev. 1.10 63 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Power On Reset LVR Reset WDT Time-out (Normal Operation) WDT Time-out (HALT) ADCR1 0000 000- 0000 000- 0000 000- uuuu uuu- ADRL xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRM xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRH ---- xxxx ---- xxxx ---- xxxx ---- uuuu ADCS ---0 0000 ---0 0000 ---0 0000 ---u uuuu LVRC 0101 0101 0101 0101 0101 0101 uuuu uuuu CTRL 0--- -x00 0--- -x00 0--- -x00 u--- -uuu SIMC0 111 - 0 0 0 0 111 - 0 0 0 0 111 - 0 0 0 0 uuu- uuuu SIMC1 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMA/SIMC2 0000 0000 0000 0000 0000 0000 uuuu uuuu SIMD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMTOC 0000 0000 0000 0000 0000 0000 uuuu uuuu EEA --xx xxxx --xx xxxx --xx xxxx --uu uuuu EED xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu EEC ---- 0000 ---- 0000 ---- 0000 ---- uuuu Register Note: "u" stands for unchanged "x" stands for unknown "-" stands for unimplemented Rev. 1.10 64 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port names PA~PF. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction "MOV A, [m]", where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. I/O Register List Rev. 1.10 Bit Register Name 7 6 5 4 3 2 1 0 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PBPU D7 D6 D5 D4 D3 D2 D1 D0 PB D7 D6 D5 D4 D3 D2 D1 D0 PBC D7 D6 D5 D4 D3 D2 D1 D0 PCPU D7 D6 D5 D4 D3 D2 D1 D0 PC D7 D6 D5 D4 D3 D2 D1 D0 PCC D7 D6 D5 D4 D3 D2 D1 D0 PDPU D7 D6 D5 D4 D3 D2 D1 D0 PD D7 D6 D5 D4 D3 D2 D1 D0 PDC D7 D6 D5 D4 D3 D2 D1 D0 PEPU D7 D6 D5 D4 D3 D2 D1 D0 PE D7 D6 D5 D4 D3 D2 D1 D0 PEC D7 D6 D5 D4 D3 D2 D1 D0 PFPU — — — — — — — D0 PF — — — — — — — D0 PFC — — — — — — — D0 65 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU~PFPU, and are implemented using weak PMOS transistors. PAPU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 3 2 1 0 Bit 7~0 Port A bit 7 ~ bit 0 Pull-high Control 0: Disable 1: Enable PBPU Register Bit 7 6 5 4 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 3 2 1 0 Bit 7~0 Port B bit 7 ~ bit 0 Pull-high Control 0: Disable 1: Enable PCPU Register Bit 7 6 5 4 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 3 2 1 0 Bit 7~0 Port C bit 7 ~ bit 0 Pull-high Control 0: Disable 1: Enable PDPU Register Bit 6 5 4 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.10 7 Port D bit 7 ~ bit 0 Pull-high Control 0: Disable 1: Enable 66 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU PEPU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Port E bit 7 ~ bit 0 Pull-high Control 0: Disable 1: Enable PFPU Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — — D0 R/W — — — — — — — R/W POR — — — — — — — 0 Bit 7~1 Unimplemented, read as "0" Bit 0 Port F bit 0 Pull-high Control 0: Disable 1: Enable Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. PAWU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Port A bit 7~bit 0 Wake-up Control 0: Disable 1: Enable I/O Port Control Registers Each I/O port has its own control register known as PAC~PFC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a "1". This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a "0", the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. Rev. 1.10 67 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU PAC Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~0 Port A bit 7 ~ bit 0 Input/Output Control 0: Output 1: Input PBC Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~0 Port B bit 7 ~ bit 0 Input/Output Control 0: Output 1: Input PCC Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~0 Port C bit 7 ~ bit 0 Input/Output Control 0: Output 1: Input PDC Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 3 2 1 0 Bit 7~0 Port D bit 7 ~ bit 0 Input/Output Control 0: Output 1: Input PEC Register Bit 6 5 4 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~0 Rev. 1.10 7 Port E bit 7 ~ bit 0 Input/Output Control 0: Output 1: Input 68 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU PFC Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — — D0 R/W — — — — — — — R/W POR — — — — — — — 1 Bit 7~1 Unimplemented, read as "0" Bit 0 Port F bit 0 Input/Output Control 0: Output 1: Input I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. Generic Input/Output Structure Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers, PAC~PFC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA~PF, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "SET [m].i" and "CLR [m].i" instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Rev. 1.10 69 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions each device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Compact and Periodic TM sections. Introduction The device contains three TMs having a reference name of TM0, TM1 and TM2. Each individual TM can be categorised as a certain type, namely Compact Type TM or Periodic Type TM. Although similar in nature, the different TM types vary in their feature complexity. The common features to all of the Compact and Periodic TMs will be described in this section, the detailed operation regarding each of the TM types will be described in separate sections. The main features and differences between the two types of TMs are summarised in the accompanying table. CTM PTM Timer/Counter Function √ √ I/P Capture — √ Compare Match Output √ √ PWM Channels 1 1 Single Pulse Output — 1 PWM Alignment PWM Adjustment Period & Duty Edge Edge Duty or Period Duty or Period TM Function Summary Device TM0 TM1 TM2 HT67F5640 10-bit CTM 10-bit PTM 10-bit PTM TM Name/Type Reference TM Operation The two different types of TM offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. Rev. 1.10 70 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the TnCK2~TnCK0 bits in the TM control registers. The clock source can be a ratio of either the system clock fSYS or the internal high clock fH, the fSUB clock source or the external TCKn pin. The TCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. TM Interrupts The Compact Type and Periodic Type TMs each have two internal interrupts, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has one TM input pin, with the label TCKn. The TM input pin is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in the TMnC0/PTMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the TnCK2~TnCK0 bits. The TM input pin can be chosen to have either a rising or falling active edge. The TMs each have two output pins with the label TPn. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external TPn output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other function, the TM output function must first be setup using the CTRL0 register. A single bit in one of the registers determines if its associated pin is to be used as an external TM output pin or if it is to have another function. The number of output pins for each TM type is different, the details are provided in the accompanying table. All TM output pin names have a "_n" suffix. Pin names that include a "_0" or "_1" suffix indicate that they are from a TM with multiple output pins. This allows the TM to generate a complimentary output pair, selected using the I/O register data bits. TM0 TM1 TM2 Register TP0_0, TP0_1 TP1_0, TP1_1 TP2_0, TP2_1 CTRL0 TM Output Pins Rev. 1.10 71 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU TM Input/Output Pin Control Registers Selecting to have a TM input/output or whether to retain its other shared functions is implemented using one register with a single bit in each register corresponding to a TM input/output pin. When the TMn is enabled, if the corresponding pin is setup as a TM input/output, and the complimentary output will be as a normal I/O pin. CTRL0 Register Bit 7 6 5 4 3 2 1 0 Name — — — — — TP2CPS TP1CPS TP0CPS R/W — — — — — R/W R/W R/W POR — — — — — 0 0 0 Bit 7~3 Unimplemented, read as "0" Bit 2TP2CPS: TP2_0, TP2_1 pin selection 0: TP2_0 1: TP2_1 When TM2 is enabled, the output function of TP2_0 is timer, then the TP2_1 is I/O, and vice versa. Bit 1TP1CPS: TP1_0, TP1_1 pin selection 0: TP1_0 1: TP1_1 When TM1 is enabled, the output function of TP1_0 is timer, then the TP1_1 is I/O, and vice versa. Bit 0TP0CPS: TP0_0, TP0_1 pin selection 0: TP0_0 1: TP0_1 When TM0 is enabled, the output function of TP0_0 is timer, then the TP0_1 is I/O, and vice versa. Rev. 1.10 72 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, being 10-bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA and CCRP registers are implemented in the way shown in the following diagram and accessing the register is carried out in a specific way described above, it is recommended to use the "MOV" instruction to access the CCRA and CCRP low byte registers, named TMxAL/PTMxAL and PTMxRPL, using the following access procedures. Accessing the CCRA or CCRP low byte register without following these access procedures will result in unpredictable values. TM Counte� Registe� (Read only) TMxDL/ PTMxDL TMxDH/ PTMxDH 8-�it Buffe� TMxAL/ PTMxAL TMxAH/ PTMxAH TM CCRA Registe� (Read/W�ite) PTMxRPL PTMxRPH TM CCRP Registe� (Read/W�ite) Data Bus The following steps show the read and write procedures: • Writing Data to CCRA or CCRP ♦♦ Step 1. Write data to Low Byte TMxAL/PTMxAL or PTMxRPL – Note that here data is only written to the 8-bit buffer. ♦♦ Step 2. Write data to High Byte TMxAH/PTMxAH or PTMxRPH – Here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. • Reading Data from the Counter Registers and CCRA or CCRP Rev. 1.10 ♦♦ Step 1. Read data from the High Byte TMxDH/PTMxDH, TMxAH/PTMxAH or PTMxRPH – Here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte TMxDL/PTMxDL, TMxAL/PTMxAL or PTMxRPL – This step reads data from the 8-bit buffer. 73 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Compact Type TM – CTM Although the simplest form of the two TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can be controlled with an external input pin and can drive two external output pins. These two external output pins can be the same signal or the inverse signal. Name TM No. TM Input Pin TM Output Pin 10-bit CTM 0 TCK0 TP0_0, TP0_1 Compact TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is three bits wide whose value is compared with the highest three bits in the counter while the CCRA is the ten bits and therefore compares with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Compact Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Compact Type TM Block Digram (n=0) Rev. 1.10 74 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Compact Type TM Register Description Overall operation of the Compact TM is controlled using six registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMnC0 TnPAU TnCK2 TnCK1 TnCK0 TnON TnRP2 TnRP1 TnRP0 TMnC1 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR TMnDL D7 D6 D5 D4 D3 D2 D1 D0 TMnDH — — — — — — D9 D8 TMnAL D7 D6 D5 D4 D3 D2 D1 D0 TMnAH — — — — — — D9 D8 Compact TM Register List (n=0) TMnC0 Register (n=0) Bit 7 6 5 4 3 2 1 0 Name TnPAU TnCK2 TnCK1 TnCK0 TnON TnRP2 TnRP1 TnRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7TnPAU: TMn Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4TnCK2~TnCK0: Select TMn Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: Reserved 110: TCKn rising edge clock 111: TCKn falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. Bit 3TnON: TMn Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the TnOC bit, when the TnON bit changes from low to high. Rev. 1.10 75 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Bit 2~0TnRP2~TnRP0: TMn CCRP 3-bit register, compared with the TMn Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TMn clocks 001: 128 TMn clocks 010: 256 TMn clocks 011: 384 TMn clocks 100: 512 TMn clocks 101: 640 TMn clocks 110: 768 TMn clocks 111: 896 TMn clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the TnCCLR bit is set to zero. Setting the TnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. TMnC1 Register (n=0) Bit 7 6 5 4 3 2 1 0 Name TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6TnM1~TnM0: Select TMn Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the TnM1 and TnM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4TnIO1~TnIO0: Select TPn_0, TPn_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Undefined Timer/Counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the TnOC bit in the TMnC1 register. Note that the output Rev. 1.10 76 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU level requested by the TnIO1 and TnIO0 bits must be different from the initial value setup using the TnOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state, it can be reset to its initial level by changing the level of the TnON bit from low to high. In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the TnIO1 and TnIO0 bits only after the TMn has been switched off. Unpredictable PWM outputs will occur if the TnIO1 and TnIO0 bits are changed when the TM is running. Bit 3TnOC: TPn_0, TPn_1 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2TnPOL: TPn_0, TPn_1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TPn_0 or TPn_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1TnDPX: TMn PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0TnCCLR: Select TMn Counter clear condition 0: TMn Comparatror P match 1: TMn Comparatror A match This bit is used to select the method which clears the counter. Remember that the Compact TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the TnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The TnCCLR bit is not used in the PWM Mode. Rev. 1.10 77 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU TMnDL Register (n=0) Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0D7~D0: TMn Counter Low Byte Register bit 7 ~ bit 0 TMn 10-bit Counter bit 7 ~ bit 0 TMnDH Register (n=0) Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0D9~D8: TMn Counter High Byte Register bit 1 ~ bit 0 TMn 10-bit Counter bit 9 ~ bit 8 TMnAL Register (n=0) Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 1 0 Bit 7~0D7~D0: TMn CCRA Low Byte Register bit 7 ~ bit 0 TMn 10-bit CCRA bit 7 ~ bit 0 TMnAH Register (n=0) Bit 7 6 5 4 3 2 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0D9~D8: TMn CCRA High Byte Register bit 1 ~ bit 0 TMn 10-bit CCRA bit 9 ~ bit 8 Rev. 1.10 78 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Compact Type TM Operating Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Match Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for the Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the TnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the TM output pin will change state. The TM output pin condition however only changes state when an TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place. Rev. 1.10 79 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Counte� Value Counte� ove�flow CCRP=0 0x3FF TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 Counte� �lea�ed �y CCRP value CCRP > 0 Counte� Resta�t Resume CCRP Pause CCRA Stop Time Tn�N TnPAU TnP�L CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM �/P Pin �utput pin set to initial Level Low if Tn�C=0 �utput not affe�ted �y TnAF flag. Remains High until �eset �y Tn�N �it �utput Toggle with TnAF flag He�e TnI� [1:0] = 11 Toggle �utput sele�t Note TnI� [1:0] = 10 A�tive High �utput sele�t �utput Inve�ts when TnP�L is high �utput Pin Reset to Initial value �utput �ont�olled �y othe� pin-sha�ed fun�tion Compare Match Output Mode – TnCCLR = 0 (n=0) Note: 1. With TnCCLR=0, a Comparator P match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge Rev. 1.10 80 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Counte� Value TnCCLR = 1; TnM [1:0] = 00 CCRA = 0 Counte� ove�flow CCRA > 0 Counte� �lea�ed �y CCRA value 0x3FF CCRA=0 Resume CCRA Pause Stop Counte� Resta�t CCRP Time Tn�N TnPAU TnP�L No TnAF flag gene�ated on CCRA ove�flow CCRA Int. Flag TnAF CCRP Int. Flag TnPF TnPF not gene�ated �utput does not �hange TM �/P Pin �utput pin set to initial Level Low if Tn�C=0 �utput not affe�ted �y TnAF flag. Remains High until �eset �y Tn�N �it �utput Toggle with TnAF flag He�e TnI� [1:0] = 11 Toggle �utput sele�t Note TnI� [1:0] = 10 A�tive High �utput sele�t �utput Inve�ts when TnP�L is high �utput Pin Reset to Initial value �utput �ont�olled �y othe� pin-sha�ed fun�tion Compare Match Output Mode - TnCCLR = 1 (n=0) Note: 1. With TnCCLR=1, a Comparator A match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge 4. The TnPF flag is not generated when TnCCLR=1 Rev. 1.10 81 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform. • CTM, PWM Mode, Edge-aligned Mode, TnDPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 100b and CCRA = 128, The CTM PWM output frequency = (fSYS/4)/512 = fSYS/2048 = 7.8125 kHz, duty = 128/512 = 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. • CTM, PWM Mode, Edge-aligned Mode, TnDPX=1 CCRP 001b 010b 011b 100b Period Duty 101b 110b 111b 000b 768 896 1024 CCRA 128 256 384 512 640 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value. Rev. 1.10 82 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Counte� Value TnDPX = 0; TnM [1:0] = 10 Counte� �lea�ed �y CCRP Counte� Reset when Tn�N �etu�ns high CCRP Pause Resume CCRA Counte� Stop if Tn�N �it low Time Tn�N TnPAU TnP�L CCRA Int. Flag TnAF CCRP Int. Flag TnPF TM �/P Pin (Tn�C=1) TM �/P Pin (Tn�C=0) PWM Duty Cy�le set �y CCRA PWM Pe�iod set �y CCRP PWM �esumes ope�ation �utput �ont�olled �y �utput Inve�ts othe� pin-sha�ed fun�tion when TnP�L = 1 PWM Mode – TnDPX = 0 (n=0) Note: 1. Here TnDPX=0 – Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 1.10 83 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Counte� Value TnDPX = 1; TnM [1:0] = 10 Counte� �lea�ed �y CCRA Counte� Reset when Tn�N �etu�ns high CCRA Pause Resume CCRP Counte� Stop if Tn�N �it low Time Tn�N TnPAU TnP�L CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM �/P Pin (Tn�C=1) TM �/P Pin (Tn�C=0) PWM Duty Cy�le set �y CCRP PWM Pe�iod set �y CCRA PWM �esumes ope�ation �utput �ont�olled �y �utput Inve�ts othe� pin-sha�ed fun�tion when TnP�L = 1 PWM Mode – TnDPX = 1 (n=0) Note: 1. Here TnDPX = 1 – Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 1.10 84 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Periodic Type TM – PTM The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can be controlled with an external input pin and can drive two external output pin. Name TM No. TM Input Pin TM Output Pin 10-bit PTM 1, 2 TCK1, TCK2 TP1_0, TP1_1 TP2_0, TP2_1 Periodic TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with the CCRA and CCRP registers. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Periodic Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control the output pin. All operating setup conditions are selected using relevant internal registers. Periodic Type TM Block Diagram (n=1 or 2) Rev. 1.10 85 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Periodic Type TM Register Description Overall operation of the Periodic TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA and CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Bit Register Name 7 6 5 4 3 2 1 0 PTMnC0 TnPAU TnCK2 TnCK1 TnCK0 TnON — — — PTMnC1 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL PTMnDL D7 D6 D5 D4 D3 D2 D1 D0 PTMnDH — — — — — — D9 D8 PTMnAL D7 D6 D5 D4 D3 D2 D1 D0 PTMnAH — — — — — — D9 D8 PTMnRPL D7 D6 D5 D4 D3 D2 D1 D0 PTMnRPH — — — — — — D9 D8 TnCAPTS TnCCLR 10-bit Periodic TM Register List (n=1 or 2) PTMnC0 Register (n=1 or 2) Bit 7 6 5 4 3 2 1 0 Name TnPAU TnCK2 TnCK1 TnCK0 TnON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7TnPAU: TMn Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4TnCK2~TnCK0: Select TMn Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: Reserved 110: TCKn rising edge clock 111: TCKn falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. Rev. 1.10 86 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Bit 3TnON: TMn Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the TM Output control bit, when the bit changes from low to high. Bit 2~0 Unimplemented, read as "0" PTMnC1 Register (n=1 or 2) Bit 7 6 5 4 3 2 1 0 Name TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnCAPTS TnCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6TnM1~TnM0: Select TMn Operation Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the TnM1 and TnM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4TnIO1~TnIO0: Select TPn_0, TPn_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TPn_0, TPn_1, TCKn 01: Input capture at falling edge of TPn_0, TPn_1, TCKn 10: Input capture at falling/rising edge of TPn_0, TPn_1, TCKn 11: Input capture disabled Timer/counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. Rev. 1.10 87 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU In the Compare Match Output Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When these bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the TnOC bit. Note that the output level requested by the TnIO1 and TnIO0 bits must be different from the initial value setup using the TnOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state, it can be reset to its initial level by changing the level of the TnON bit from low to high. In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the TnIO1 and TnIO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the TnIO1 and TnIO0 bits are changed when the TM is running. Bit 3TnOC: TPn_0, TPn_1 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2TnPOL: TPn_0, TPn_1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TPn_0, TPn_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1TnCAPTS: TMn capture trigger source select 0: From TPn_0, TPn_1 pin 1: From TCKn pin Bit 0TnCCLR: Select TMn Counter clear condition 0: TMn Comparatror P match 1: TMn Comparatror A match This bit is used to select the method which clears the counter. Remember that the Periodic TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the TnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The TnCCLR bit is not used in the PWM, Single Pulse or Input Capture Mode. Rev. 1.10 88 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU PTMnDL Register (n=1 or 2) Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0PTMnDL: TMn Counter Low Byte Register bit 7 ~ bit 0 TMn 10-bit Counter bit 7 ~ bit 0 PTMnDH Register (n=1 or 2) Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0PTMnDH: TMn Counter High Byte Register bit 1 ~ bit 0 TMn 10-bit Counter bit 9 ~ bit 8 PTMnAL Register (n=1 or 2) Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0PTMnAL: TMn CCRA Low Byte Register bit 7 ~ bit 0 TMn 10-bit CCRA bit 7 ~ bit 0 PTMnAH Register (n=1 or 2) Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0PTMnAH: TMn CCRA High Byte Register bit 1 ~ bit 0 TMn 10-bit CCRA bit 9 ~ bit 8 PTMnRPL Register (n=1 or 2) Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0PTMnRPL: TMn CCRP Low Byte Register bit 7 ~ bit 0 TMn 10-bit CCRP bit 7 ~ bit 0 Rev. 1.10 89 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU PTMnRPH Register (n=1 or 2) Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0PTMnRPH: TMn CCRP High Byte Register bit 1 ~ bit 0 TMn 10-bit CCRP bit 9 ~ bit 8 Periodic Type TM Operating Modes The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the PTMnC1 register. Compare Match Output Mode To select this mode, bits TnM1 and TnM0 in the PTMnC1 register, should be all cleared to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both the TnAF and TnPF interrupt request flags for Comparator Aand Comparator P respectively, will both be generated. If the TnCCLR bit in the PTMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be cleared to zero. As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when a TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the PTMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1, TnIO0 bits are zero then no pin change will take place. Rev. 1.10 90 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Counter Value Counter overflow CCRP=0 0x3FF TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value CCRP > 0 Counter Restart Resume CCRP Pause CCRA Stop Time TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin Output pin set to initial Level Low if TnOC=0 Output not affected by TnAF flag. Remains High until reset by TnON bit Output Toggle with TnAF flag Here TnIO [1:0] = 11 Toggle Output select Note TnIO [1:0] = 10 Active High Output select Output Inverts when TnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – TnCCLR = 0 (n=1 or 2) Note: 1. With TnCCLR = 0 – a Comparator P match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to initial state by a TnON bit rising edge Rev. 1.10 91 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Counter Value TnCCLR = 1; TnM [1:0] = 00 CCRA = 0 Counter overflow CCRA > 0 Counter cleared by CCRA value 0x3FF CCRA=0 Resume CCRA Pause Stop Counter Restart CCRP Time TnON TnPAU TnPOL No TnAF flag generated on CCRA overflow CCRA Int. Flag TnAF CCRP Int. Flag TnPF TnPF not generated Output does not change TM O/P Pin Output pin set to initial Level Low if TnOC=0 Output not affected by TnAF flag. Remains High until reset by TnON bit Output Toggle with TnAF flag Here TnIO [1:0] = 11 Toggle Output select Note TnIO [1:0] = 10 Active High Output select Output Inverts when TnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – TnCCLR = 1 (n=1 or 2) Note: 1. With TnCCLR = 1 – a Comparator A match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to initial state by a TnON rising edge 4. The TnPF flag is not generated when TnCCLR = 1 Rev. 1.10 92 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the PTMnC1 register should all be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits TnM1 and TnM0 in the PTMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect as the PWM period. Both of the CCRP and CCRA registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the PTMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform. • 10-bit PTM, PWM Mode CCRP 0 Period 1024 Duty 1~1023 1~1023 CCRA If fSYS = 16MHz, TM clock source select fSYS/4, CCRP = 100b and CCRA = 128, The PTM PWM output frequency = (fSYS/4) / 512 = fSYS/2048 =7.8125kHz, duty = 128/512 = 25%, If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. Rev. 1.10 93 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Counter Value TnM [1:0] = 10 Counter cleared by CCRP Counter Reset when TnON returns high CCRP Pause Resume CCRA Counter Stop if TnON bit low Time TnON TnPAU TnPOL CCRA Int. Flag TnAF CCRP Int. Flag TnPF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM Duty Cycle set by CCRA PWM Period set by CCRP PWM resumes operation Output controlled by Output Inverts other pin-shared function when TnPOL = 1 PWM Mode (n=1 or 2) Note: 1. Here Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when TnIO[1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 1.10 94 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Single Pulse Output Mode To select this mode, the required bit pairs, TnM1 and TnM0 should be set to 10 respectively and also the corresponding TnIO1 and TnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate TM interrupts. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR bit is also not used. Single Pulse Generation (n=1 or 2) Capture Input Mode To select this mode bits TnM1 and TnM0 in the PTMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPn_0, TPn_1 or TCKn pin, selected by the TnCAPTS bit in the PTMnC0 register. The input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnIO1 and TnIO0 bits in the PTMnC1 register. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TPn_0, TPn_1 or TCKn pin the present value in the counter will be latched into the CCRA register and a TM interrupt generated. Irrespective of what events occur on the TPn_0, TPn_1 or TCKn pin the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnIO1 and TnIO0 bits can select the active trigger edge on the TPn_0, TPn_1 or TCKn pin to be a rising edge, falling edge or both edge types. If the TnIO1 and TnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TPn_0, TPn_1 or TCKn pin, however it must be noted that the counter will continue to run. Rev. 1.10 95 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU As the TPn_0, TPn_1 or TCKn pin is pin shared with other functions, care must be taken if the TMn is in the Capture Input Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The TnCCLR, TnOC and TnPOL bits are not used in this Mode. Counter Value TnM [1:0] = 10 ; TnIO [1:0] = 11 Counter stopped by CCRA Counter Reset when TnON returns high CCRA Pause Counter Stops by software Resume CCRP Time TnON Software Trigger Auto. set by TCKn pin Cleared by CCRA match TCKn pin Software Trigger Software Clear Software Trigger Software Trigger TCKn pin Trigger TnPAU TnPOL CCRP Int. Flag TnPF No CCRP Interrupts generated CCRA Int. Flag TnAF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) Output Inverts when TnPOL = 1 Pulse Width set by CCRA Single Pulse Mode (n=1 or 2) Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse is triggered by the TCKn pin or by setting the TnON bit high 4. A TCKn pin active edge will automatically set the TnON bit high 5. In the Single Pulse Mode, TnIO [1:0] must be set to "11" and can not be changed. Rev. 1.10 96 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Counter Value TnM [1:0] = 01 Counter cleared by CCRP Counter Counter Reset Stop CCRP YY Pause Resume XX Time TnON TnPAU TM capture pin TPn_x or TCKn Active edge Active edge Active edge CCRA Int. Flag TnAF CCRP Int. Flag TnPF CCRA Value TnIO [1:0] Value XX 00 – Rising edge YY 01 – Falling edge XX 10 – Both edges YY 11 – Disable Capture Capture Input Mode (n=1 or 2) Note: 1. TnM[1:0] = 01 and active edge set by the TnIO[1:0] bits 2. A TM Capture input pin active edge transfers counter value to CCRA 3. The TnCCLR bit is not used 4. No output function – TnOC and TnPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero Rev. 1.10 97 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Internal Power Supply This device contains the LDO and VCM for the regulated power supply. The accompanying block diagram illustrates the basic functional operation. The internal LDO can provide the fixed voltage for PGA, ADC or the external components; as well the VCM can be used as the reference voltage for ADC module. There are four LDO voltage levels, 2.5V, 2.6V, 2.9V or 3.3V, decided by LDOVS1~LDOVS0 bits in the PWRC register, as well the VCM has two output voltage levels, 1.0V or 1.2V, selected by the VCMS bit in the PGAC1 register. The LDO and VCM functions can be controlled by the ENLDO and ENVCM bits respectively and can be powered off to reduce the power consumption. Registers Output Voltage ADOFF ENLDO ENVCM VOREG/AVDD VCM 1 0 × Disable Disable 1 1 × Enable Disable 0 0 0 Disable Disable 0 1 0 Enable Disable 0 0 1 Disable Disable 0 1 1 Enable Enable "x" means don’t care Power Control Table Rev. 1.10 98 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU PWRC Register Bit 7 6 5 4 3 2 1 0 Name ENLDO ENVCM — — — — LDOVS1 LDOVS0 R/W R/W R/W — — — — R/W R/W POR 0 0 — — — — 0 0 Bit 7ENLDO: LDO function control bit 0: Disable 1: Enable If the LDO is disabled, there will be no power consumption and LDO output pin is floating. Bit 6ENVCM: VCM function control bit 0: Disable 1: Enable If the VCM is disabled, there will be no power consumption and VCM output pin is floating. Bit 5~2 Unimplemented, read as "0" Bit 1~0LDOVS1~LDOVS0: LDO output voltage selection 00: 2.5V 01: 2.6V 10: 2.9V 11: 3.3V PGAC1 Register Bit 7 6 5 4 3 2 1 0 Name VCMS INIS — — DCSET2 DCSET1 DCSET0 — R/W R/W R/W — — R/W R/W R/W — POR 1 0 — — 0 0 0 — Bit 7VCMS: Analog Common mode voltage selection 0: 1.0V 1: 1.2V Bit 6INIS: The selected input ends, IN1 and IN2, connection control bit Described elsewhere. Bit 5~4 unimplemented, read as "0" Bit 3~1DCSET2~DCSET0: The DI+/DI- differential input offset voltage adjustment control Described elsewhere. Bit 0 Rev. 1.10 Unimplemented, read as "0" 99 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Analog to Digital Converter – ADC The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Data Rate Definition The delta-sigma ADC data rate can be calculated by the equation list below: Data Rate = (ADC clock) / (FLMS[2:0] × ADOR[2:0]) Where ADC clock comes from FMCLK, and FLMS[2:0] define a constant number which can only be 30 or 12, finally ADOR[2:0] define chopper average function and Over-Sampling Rating (OSR). For example, if a data rate of 10Hz is desired. You can have a 4.9152MHz ADC clock, then set FLMS[2:0] = 000b (ADC clock divided by 30); finally set ADOR[2:0] = 001b to define chopper = 2 and OSR = 8192. Thus Data Rate = 4.9152MHz / (30 × 2 × 8192) = 10Hz A/D Overview This device contains a high accuracy multi-channel 20-bit delta-sigma analog-to-digital (ΔΣA/D) converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 20-bit digital value. In addition, the PGA gain control, ADC gain control and ADC reference gain control determine the amplification gain for ADC input signal. The designer can select the best gain combination for the desired amplification applied to the input signal. The following block diagram illustrates the ADC basic operational function. The ADC input channel can be arranged as four single-ended A/D input channels and two differential input channels. The input signal can be amplified by PGA before entering the 20-bit delta-sigma ADC. The ΔΣADC modulator will output one bit converted data to SINC filter which can transform the converted one-bit data to 20 bits and store them into the specific data registers. Additionally, this device also provides a temperature sensor to compensate the A/D converter deviation caused by the temperature. With high accuracy and performance, this device is very suitable for the Weight Scale related products. Rev. 1.10 100 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU AN0 AN� AN� MUX AN� AN6 AD�R[�:0] IN1 VCM ADRST DCSET[�:0] AN7 VCM VTS�+ �0-�it ADC DI+ CHSP[�:0] INIS PGS=x1�x��x�� x8�x16�x3�� x6��x1�8 DI- SINC Filte� AGS = x1� x�� x�� x8 VGS = x1� x1/�� x1/� AN1 REFP AN3 VTS�- MUX VDD/� VCM IN� VRBUFP REFN VRBUFN �uffe� �uffe� VRN VRP 0 1 0 1 VREFS CHSN[�:0] VCM VREFP AVSS VREFN A/D Converter Structure A/D Converter Register Description Overall operation of the A/D converter is controlled by using 9 registers. A read only register pair exists to store the ADC data 20-bit value. The remaining 6 registers are control registers which set up the gain selections and control functions of the A/D converter. Bit Register Name 7 6 5 4 3 2 1 0 PGAC0 — VGS1 VGS0 AGS1 AGS0 PGS2 PGS1 PGS0 PGAC1 VCMS INIS — — DCSET2 DCSET1 DCSET0 — PGACS — — CHSN2 CHSN1 CHSN0 CHSP2 CHSP1 CHSP0 ADRL D7 D6 D5 D4 D3 D2 D1 D0 ADRM D15 D14 D13 D12 D11 D10 D9 D8 ADRH — — — — D19 D18 D17 D16 ADCR0 ADRST ADSLP ADOFF ADOR2 ADOR1 ADOR0 — VREFS ADCR1 FLMS2 FLMS1 FLMS0 ADCS — — — VRBUFN VRBUFP ADCK4 ADCK3 ADCDL EOC — ADCK2 ADCK1 ADCK0 A/D Converter Register List Rev. 1.10 101 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Programmable Gain Amplifier – PGA There are three registers related to the programmable gain control, PGAC0, PGAC1 and PGACS. The PGAC0 resister is used to select the PGA gain, ADC gain and the ADC reference gain. As well, the PGAC1 register is used to define the input connection, differential input offset voltage adjustment control and the VCM voltage selection. In addition, The PGACS register is used to select the input ends for the PGA. Therefore, the input channels have to be determined by the CHSP2~0 and CHSN2~0 bits to determine which analog channel input pins, temperature detector inputs or internal power supply are actually connected to the internal differential A/D converter. PGAC0 Register Bit 7 6 5 4 3 2 1 0 Name — VGS1 VGS0 AGS1 AGS0 PGS2 PGS1 PGS0 R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6~5VGS1~VGS0: VREF gain selection 00: 1 01: 1/2 10: 1/4 11: Reserved Bit 4~3AGS1~AGS0: ADC gain selection 00: 1 01: 2 10: 4 11: 8 Bit 2~0PGS2~PGS0: PGA gain selection 000: 1 001: 2 010: 4 011: 8 100: 16 101: 32 110: 64 111: 128 Rev. 1.10 102 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU PGAC1 Register Bit 7 6 5 4 3 2 1 0 Name VCMS INIS — — DCSET2 DCSET1 DCSET0 — R/W R/W R/W — — R/W R/W R/W — POR 1 0 — — 0 0 0 — Bit 7VCMS: Analog Common mode voltage selection 0: 1.0V 1: 1.2V Bit 6INIS: The selected input ends, IN1 and IN2, connection control bit 0: Not shorted 1: Shorted Bit 5~4 Unimplemented, read as "0" Bit 3~1DCSET2~DCSET0: The DI+/DI- differential input offset voltage adjustment control 000: +0V 001: +0.25VR 010: +0.5VR 011: +0.75VR 100: +0V 101: -0.25VR 110: -0.5VR 111: -0.75VR Bit 0 Unimplemented, read as "0" PGACS Register Bit 7 6 5 4 3 2 1 0 Name — — CHSN2 CHSN1 CHSN0 CHSP2 CHSP1 CHSP0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5~3CHSN2~CHSN0: PGA negative input ends selection 000: AN1 001: AN3 010: reserved 011: reserved 100: reserved 101: VDD/5 110: VCM 111: Temperature sensor VTSOBit 2~0CHSP2~CHSP0: PGA positive input ends selection 000: AN0 001: AN2 010: AN4 011: AN5 100: AN6 101: AN7 110: VCM 111: Temperature sensor VTSO+ Note: If the PGA is assigned the single end input to DI+, then the DI- input must be selected the VCM. Rev. 1.10 103 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU A/D Converter Data Registers – ADRL, ADRM, ADRH This device contains an internal 20-bit ΔΣA/D converter, it requires three data registers to store the converted value. These are a high byte register, known as ADRH, ADRM and a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. D0~D19 are the A/D conversion result data bits. ADRH Register Bit 7 6 5 4 3 2 1 0 Name — — — — D19 D18 D17 D16 R/W — — — — R R R R POR — — — — × × × × "x" unknown Bit 7~4 Unimplemented, read as "0" Bit 3~0 A/D conversion data Register bit 19~bit 16 ADRM Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R R R R R R R R POR × × × × × × × × "x" unknown Bit 7~0 A/D conversion data Register bit 15~bit 8 ADRL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR × × × × × × × × "x" unknown Bit 7~0 Rev. 1.10 A/D conversion data Register bit 7~bit 0 104 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU A/D Converter Control Registers – ADCR0, ADCR1, ADCS To control the function and operation of the A/D converter, three control registers known as ADCR0, ADCR1 and ADCS are provided. These 8-bit registers define functions such as the selection of which reference source is used to the internal ADC, the ADC clock source , the ADC output data rate as well as controlling the power-up function and monitoring the ADC end of conversion status. ADCR0 Register Bit 7 6 5 4 3 2 1 0 Name ADRST ADSLP ADOFF ADOR2 ADOR1 ADOR0 — VREFS R/W R/W R/W R/W R/W R/W R/W — R/W POR 0 0 1 0 0 0 — 0 Bit 7 ADRST: ADC software reset control bit. 0: Disable 1: Enable This bit is used to reset the ADC internal digital SINC filter. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process data. Bit 6ADSLP: ADC sleep mode control bit 0: Normal mode 1: Sleep mode This bit is used for ADC sleep mode control bit. To set this bit high will force the ADC enter sleep mode which can reduce the power consumption and prevent the ADC startup time. Bit 5ADOFF: ADC module power on/off control bit 0: ADC module power on 1: ADC module power off This bit controls the power of the ADC module. This bit should be cleared to zero to enable the A/D converter. If the bit is set high then the ADC will be switched off reducing the device power consumption. As the ADC will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. Note: 1. It is recommended to set ADOFF=1 before entering IDLE/SLEEP Mode for saving power. 2. ADOFF=1 will power down the ADC module, no matter the settings of ADSLP and ADRST bits. 3. The relationship about these bits, ADOFF, ADSLP, ADRST will be further described else where. Bit 4 ~ 2ADOR2~ADOR0: Output data rate selection 000: CHOP = 2, OSR=16384 001: CHOP = 2, OSR=8192 010: CHOP = 2, OSR=4096 011: CHOP = 2, OSR=2048 100: CHOP = 2, OSR=1024 101: CHOP = 2, OSR=512 110: CHOP = 2, OSR=256 111: CHOP = 2, OSR=128 Bit 1 Unimplemented, read as „0" Bit 0VREFS: ADC reference source selection 0: Internal reference (VCM, AVSS) 1: External reference (VREFP,VREFN) Rev. 1.10 105 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU ADCR1 Register Bit 7 6 5 Name FLMS2 FLMS1 FLMS0 4 R/W R/W R/W R/W R/W POR 0 0 0 0 3 2 1 0 ADCDL EOC — R/W R/W R/W — 0 0 0 — VRBUFN VRBUFP Bit 7 ~ 5FLMS2~FLMS0: ADC clock division ratio selection 000: Normal mode, ADC clock /30 010: Normal mode, ADC clock /12 Others: reserved Bit 4VRBUFN: VRN Buffer Enable 0: Disable 1: Enable Bit 3VRBUFP: VRP Buffer Enable 0: Disable 1: Enable Bit 2ADCDL: ADC converted data latch function 0: Disable data latch 1: Enable data latch If the ADC converted data latch function is enabled, the latest converted data value will be latched and not be updated by any subsequent converted results until this function is disabled. Although the converted data is latched into the data registers, the ADC circuits remain operational, but will not generate interrupt and EOC will not change. It is recommended that this bit should be set high before reading the converted data in the ADRL, ADRM and ADRH registers. After the converted data has been read out, the bit can then be cleared to low to disable the ADC data latch function and allow further conversion values to be stored. In this way, the possibility of obtaining undesired data during ADC conversions can be prevented. Bit 1EOC: End of A/D conversion flag 0: A/D conversion in progress 1: A/D conversion ended This bit must be cleared by software. Bit 0 Unimplemented, read as "0" ADCS Register Bit 7 6 5 4 3 2 1 0 Name — — — ADCK4 ADCK3 ADCK2 ADCK1 ADCK0 R/W — — — R/W R/W R/W R/W R/W POR — — — 0 0 0 0 0 Bit 7~5 Unimplemented, read as "0" Bit 4~0ADCK4~ADCK0: Select ADC clock source (FMCLK) 00000~11110: fSYS/2 / (ADCK[4:0]+1) 11111: fSYS Due to the ADC clock source, FMCLK, is typically designed as 4MHz and the MCU might be selected to work at different system clock, therefore, the designer should use the ADCK4~ADCK0 bits to get the fixed 4MHz ADC working clock source. For example, if the system clock is 8 MHz, the ADCK [4:0] must be 0 to get the FMCLK= 4MHz. Rev. 1.10 106 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU A/D Operation The ADC provides three operational modes, which are Power down mode, Sleep mode and Reset mode, controlled respectively by the ADOFF, ADSLP and ADRST bits in the ADCR0 register. The following table illustrates the operating mode selection. ADOFF ADSLP ADRST Operating mode 1 × × Power down mode PGA off, ADC off Description 0 1 × Sleep mode PGA on, ADC off 0 0 1 Reset mode PGA on, ADC on, SINC Reset A/D operation mode selection "x" unknown To enable the ADC, the first step is to disable the ADC power down and sleep mode, to make sure the ADC is powered up. The ADRST bit in the ADCR0 register is used to start and reset the A/D converter after power on. When the microcontroller sets this bit from low to high and then low again, an analog to digital converted data in SINC filter will be initiated. After this setup is complete, the ADC is ready for operation. These three bits are used to control the overall start operation of the internal analog to digital converter. The EOC bit in the ADCR1 register is used to indicate when the analog to digital conversion process is complete. This bit will be automatically set high by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOC bit in the ADCR1 register to check whether it has been set "1" as an alternative method of detecting the end of an A/D conversion cycle. The ADC converted data will be updated continuously by the new converted data. If the ADC converted data latch function is enabled, the latest converted data will be latched and the following new converted data will be discarded until this data latch function is disabled. The clock source for the A/D converter should be typically fixed at a value of 4MHz, which originates from the system clock fSYS, and can be chosen to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the ADCK4~ADCK0 bits in the ADCS register to obtain a 4MHz clock source for the ADC. The differential reference voltage supply to the A/D Converter can be supplied from either the internal power supply pins, VCM and AVSS, or from an external reference source supplied on pins, VREFP and VREFN. The desired selection is made using the VREFS bit in the ADCR0 register. Rev. 1.10 107 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/D conversion process. • Step 1 Enable power LDO, VCM for PGA and ADC. • Step 2 Select PGA, ADC and VREF gains by PGAC0 register. • Step 3 Select PGA setting for input pins connection, VCM option by PGAC1 register. • Step 4 Select the required A/D conversion clock 4MHz by correctly programming bits ADCK4~ADCK0 in the ADCS register. • Step 5 Select output data rate. • Step 6 Select which channel is to be connected to the internal PGA by correctly programming the CHSP2~CHSP0 and CHSN2~CHSN0 bits which are also contained in the PGACS register. • Step 7 Release power down mode and sleep mode by ADOFF and ADSLP bits in ADCR0 register. • Step 8 Reset the A/D by setting the ADRST to high in the ADCR0 register and clearing this bit to zero to release reset status. • Step 9 If the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, and the A/D converter interrupt bit, ADE, must both be set high to do this. • Step 10 To check when the analog to digital conversion process is complete, the EOC bit in the ADCR1 register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D data registers ADRL, ADRM and ADRH can be read to obtain the conversion value. As an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur. Note: When checking for the end of the conversion process, if the method of polling the EOC bit in the ADCR1 register is used, the interrupt enable step above can be omitted. Rev. 1.10 108 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D internal circuitry can be switched off to reduce power consumption, by setting bit ADOFF high in the ADCR0 register. When this happens, the internal A/D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. A/D Transfer Function This device contains a 20-bit ΔΣA/D converter, its full-scale converted digitised value is from 524287 to -524288 in decimal value. The converted data format is formed by a two’s complement binary value. The MSB of the converted data is the signed bit. Since the full-scale analog input value is equal to the VCM or ΔVREF voltage, selected by the VREFS bit in ADCR0 register, this gives a single bit analog input value of VCM or ΔVREF divided by 524288. 1 LSB= (VCM or ΔVREF) /524288 The A/D Converter input voltage value can be calculated using the following equation: ΔSI_I = (PGAGN × ADGN × ΔDI±) + (DCSET × ΔVR_I) ΔVR_I = VREGN × ΔVR± ADC_Conversion_Data = (ΔSI_I ÷ ΔVR_I) × K Where K is equal to 219 Note: The PGAGN, ADGN, VREGN values are decided by PGS, AGS, VGS control bits. ΔSI_I: Differential Input Signal after process PGAGN: Programmable Gain Amplifier gain ADGN: ADC gain ΔDI ±: Differential Input signal DCSET: Offset voltage ΔVR ±: Differential Reference voltage ΔVR_I: Differential Reference input voltage after process VREGN: Reference voltage gain Due to the digital system design of the ΔΣADC, the maximum number of the ADC converted value is 524287 and the minimum value is -524288, therefore, we can have the middle number 0. The ADC_Conversion_Data equation illustrates this range of converted data variation. A/D conversion data (2’s compliment, Hexadecimal) Decimal Value 0x7FFFF 524287 0x80000 -524288 The above ADC conversion data table illustrates the range of ADC conversion data. The following diagram shows the relationship between the DC input value and the ADC converted data which is presented by the Two’s Complement. Rev. 1.10 109 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU �0 Digital output Two's �omplement 0111 1111 1111 1111 1111 DC input value 0 PGAGN× ADGN AIP − AIN DCSET × + VREGN VREFP − VREFN VREGN 1000 0000 0000 0000 0000 A/D Converted Data The ADC converted data is related to the input voltage and the PGA selections. The format of the ADC output is a two’s complement binary code. The length of this output code is 20 bits and the MSB is a signed bit. When the MSB is "0", which represents the input is "positive" , on the other hand, as the MSB is "1", it represents the input is "negative". The maximum value is 524287 and the minimum value is -524288. If the input signal is over the maximum value, the converted data is limited by the 524287, and if the input signal is less than the minimum value, the converted data is limited by -524288. A/D Converted data to voltage The designer can recover the converted data by the following equations: If MSB=0 (Positive Converted data): Input Voltage = (Converted data-0) × (LSB/ PGA) If the MSB=1(Negative Converted data): Input voltage= (Two’s complement of converted data-0) × (LSB/PGA) Note: Two’s complement=One’s complement +1 Rev. 1.10 110 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU A/D Programming Example Example: using an EOC polling method to detect the end of conversion #includeht67f5640.inc data.section 'data' adc_result_data_ldb ? adc_result_data_mdb ? adc_result_data_hdb ? code.section 'code' start: clr ADE ;disable ADC interrupt mov a, 0C3H ;Power control for PGA, ADC mov PWRC, a ;PWRC=11000011, LDO enable, VCM enable, ;LDO output voltage:3.3V mov a, 000H mov PGAC0, a ;PGA gain=1, ADC gain=1, Vref gain=1 mov a, 080H mov PGAC1, a ;VCM=1.2V, INIS, INX, DCSET in default value set VRBUFP ;enable buffer for Vref+ set VRBUFN ;enable buffer for Vref set VREFS ;for using external reference clr ADOR2 ;for 10Hz output data rate, ADOR[2:0]=001, ;FLMS[2:0]=000 clr ADOR1 set ADOR0 clr FLMS2 clr FLMS1 clr FLMS0 clr ADOFF ;ADC exit power down mode. set ADRST ;ADC in reset mode clr ADRST ;ADC in convertsion (continuos mode) clr EOC ;Clear “EOC” flag loop: snz EOC ;Polling “EOC” flag jmp loop ;Wait for read data clr adc_result_data_h clr adc_result_data_m clr adc_result_data_l mov a, ADRL mov adc_result_data_l, a ;Get Low byte ADC value mov a, ADRM mov adc_result_data_m, a ;Get Middle byte ADC value mov a, ADRH mov adc_result_data_h, a ;Get High byte ADC value get_adc_value_ok: clr EOC ;Clearing read flag jmp loop ;for next data read end Rev. 1.10 111 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Temperature sensor This device provides an internal temperature sensor to compensate the device performance. By selecting the PGA input channels to VTSO+ and VTSO-, the ADC can get the temperature information and the designer can do some compensation to the A/D converted data. The following block diagram illustrates the functional operation for the temperature sensor. AVDD I VTS�+ ADC PGA VTS�- AVSS Comparators Two independent analog comparators are contained within the device. These functions offer flexibility via its register controlled features such as power-down, polarity select, hysteresis etc. In sharing its pins with normal I/O pins the comparator does not waste precious I/O pins if there functions are otherwise unused. Comparator Comparator Operation The device contains two comparator functions which are used to compare two analog voltages and provide an output based on their difference. Full control over the internal comparators is provided via two control registers, CP0C and CP1C, one assigned to each comparator. The comparator output is recorded via a bit in their respective control register, but can also be transferred out onto a shared I/O pin. Additional comparator functions include, output polarity, hysteresis functions and power down control. Any pull-high resistors connected to the shared comparator input pins will be automatically disconnected when the comparator is enabled. As the comparator inputs approach their switching level, some spurious output signals may be generated on the comparator output due to the slow rising or falling nature of the input signals. This can be minimised by selecting the hysteresis function will apply a small amount of positive feedback to the comparator. Ideally the comparator should switch at the point where the positive and negative inputs signals are at the same voltage level, however, unavoidable input offsets introduce some uncertainties here. The hysteresis function, if enabled, also increases the switching offset value. Rev. 1.10 112 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Comparator Register There are two registers for overall comparator operation, one for each comparator. As corresponding bits in the two registers have idendical functions, they following register table applies to both registers. Bit Register Name 7 6 5 4 3 2 1 0 CP0C C0SEL C0EN C0POL C0OUT C0OS — — C0HYEN CP1C C1SEL C1EN C1POL C1OUT C1OS — — C1HYEN Comparator Registers List CP0C Register Bit 7 6 5 4 3 2 1 0 Name C0SEL C0EN C0POL C0OUT C0OS — — C0HYEN R/W R/W R/W R/W R R/W — — R/W POR 1 0 0 0 0 — — 1 Bit 7 C0SEL: Select Comparator pins or I/O pins 0: I/O pin select 1: Comparator pin select This is the Comparator pin or I/O pin select bit. If the bit is high the comparator will be selected and the two comparator input pins will be enabled. As a result, these two pins will lose their I/O pin functions. Any pull-high configuration options associated with the comparator shared pins will also be automatically disconnected. Bit 6 C0EN: Comparator On/Off control 0: Off 1: On This is the Comparator on/off control bit. If the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. For power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the SLEEP or IDLE mode. Bit 5 C0POL: Comparator output polarity 0: Output not inverted 1: Output inverted This is the comparator polarity bit. If the bit is zero then the C0OUT bit will reflect the non-inverted output condition of the comparator. If the bit is high the comparator C0OUT bit will be inverted. Bit 4C0OUT: Comparator output bit C0POL=0 0: C0P < C0N 1: C0P > C0N C0POL=1 0: C0P > C0N 1: C0P < C0N This bit stores the comparator output bit. The polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the C0POL bit. Rev. 1.10 Bit 3 C0OS: Output path select 0: C0OUT pin 1: Internal use This is the comparator output path select control bit. If the bit is cleared to zero and the C0SEL bit is 1 the comparator output is connected to an external C0OUT pin. If the bit is set high or the C0SEL bit is 0 the comparator output signal is only used internally by the device allowing the shared comparator output pin to retain its normal I/O operation. Bit 2~1 Unimplemented, read as "0" 113 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Bit 0C0HYEN: Hysteresis Control 0: Off 1: On This is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specified in the Comparator Electrical Characteristics table. The positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. CP1C Register Bit 7 6 5 4 3 2 1 0 Name C1SEL C1EN C1POL C1OUT C1OS — — C1HYEN R/W R/W R/W R/W R R/W — — R/W 1 0 0 0 0 — — 1 POR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2~1 Bit 0 Rev. 1.10 C1SEL: Select Comparator pins or I/O pins 0: I/O pin select 1: Comparator pin select This is the Comparator pin or I/O pin select bit. If the bit is high the comparator will be selected and the two comparator input pins will be enabled. As a result, these two pins will lose their I/O pin functions. Any pull-high configuration options associated with the comparator shared pins will also be automatically disconnected. C1EN: Comparator On/Off control 0: Off 1: On This is the Comparator on/off control bit. If the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. For power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the SLEEP or IDLE mode. C1POL: Comparator output polarity 0: output not inverted 1: output inverted This is the comparator polarity bit. If the bit is zero then the C1OUT bit will reflect the non-inverted output condition of the comparator. If the bit is high the comparator C1OUT bit will be inverted. C1OUT: Comparator output bit C1POL=0 0: C1P < C1N 1: C1P > C1N C1POL=1 0: C1P > C1N 1: C1P < C1N This bit stores the comparator output bit. The polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the C1POL bit. C1OS: Output path select 0: C1OUT pin 1: Internal use This is the comparator output path select control bit. If the bit is cleared to zero and the C1SEL bit is 1 the comparator output is connected to an external C1OUT pin. If the bit is set high or the C1SEL bit is 0 the comparator output signal is only used internally by the device allowing the shared comparator output pin to retain its normal I/O operation. Unimplemented, read as "0" C1HYEN: Hysteresis Control 0: Off 1: On This is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specified in the Comparator Electrical Characteristics table. The positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. 114 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Comparator Interrupt Each also possesses its own interrupt function. When any one of the changes state, its relevant interrupt flag will be set, and if the corresponding interrupt enable bit is set, then a jump to its relevant interrupt vector will be executed. Note that it is the changing state of the CnO signal and generates an interrupt. If the microcontroller is in the SLEEP or IDLE Mode and the Comparator is enabled, then if the external input lines cause the Comparator output to change state, the resulting generated interrupt flag will also generate a wake-up. If it is required to disable a wake-up from occurring, then the interrupt flag should be first set high before entering the SLEEP or IDLE Mode. Programming Considerations If the comparator is enabled, it will remain active when the microcontroller enters the SLEEP or IDLE Mode, however as it will consume a certain amount of power, the user may wish to consider disabling it before the SLEEP or IDLE Mode is entered. As comparator pins are shared with normal I/O pins the I/O registers for these pins will be read as zero (port control register is "1") or read as port data register value (port control register is "0") if the comparator function is enabled. Serial Interface Module – SIM This device contains a Serial Interface Module, which includes both the four line SPI interface and the two line I2C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash memory, etc. As both interface types share the same pins and registers, the choice of whether the SPI or I2C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 register. These pull-high resistors of the SIM pin-shared I/O pins are selected using pull-high control registers when the SIM function is enabled and the corresponding pins are used as SIM input pins. SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash memory devices etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the device can be either master or slave. Although the SPI interface specification can control multiple slave devices from a single master, but this device is provided only one SCS pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pin to select the slave devices. SPI Interface Operation The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pinshared with normal I/O pins and with the I2C function pins, the SPI interface must first be enabled by setting the correct bits in the SIMC0 and SIMC2 registers. The SPI can be disabled or enabled using the SIMEN bit in the SIMC0 register. Communication between devices connected to the SPI interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The Master also controls the clock signal. As the device only contains a single SCS pin only one slave device can be utilized. The SCS pin is controlled by software, set CSEN bit to "1" to enable SCS pin function, set CSEN bit to "0" the SCS pin will be floating state. Rev. 1.10 115 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU SPI Master/Slave Connection SPI Block Diagram The SPI function in this device offers the following features: • Full duplex synchronous data transfer • Both Master and Slave modes • LSB first or MSB first data transmission modes • Transmission complete flag • Rising or falling active clock edge The status of the SPI interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN. SPI Registers There are three internal registers which control the overall operation of the SPI interface. These are the SIMD data register and two registers SIMC0 and SIMC2. Note that the SIMC1 register is only used by the I2C interface. Bit Register Name 7 6 5 SIMC0 SIM2 SIM1 SIM0 — SIMD D7 D6 D5 D4 D3 D2 SIMC2 D7 D6 CKPOLB CKEG MLS CSEN 4 3 2 SIMDBC1 SIMDBC0 1 0 SIMEN SIMICF D1 D0 WCOL TRF SIM Registers List The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register. Rev. 1.10 116 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2 register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used by the SPI function, only by the I2C function. Register SIMC0 is used to control the enable/disable function and to set the data transmission clock frequency. Although not connected with the SPI function, the SIMC0 register is also used to control the Peripheral Clock Prescaler. Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag etc. SIMC0 Register Bit 7 6 5 4 3 2 Name SIM2 SIM1 SIM0 — R/W R/W R/W R/W — R/W R/W POR 1 1 1 — 0 0 SIMDBC1 SIMDBC0 1 0 SIMEN SIMICF R/W R/W 0 0 Bit 7~5SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fSUB 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Unused mode These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 Unimplemented, read as "0" Bit 3~2SIMDBC1~SIMDBC0: I2C Debounce Time Selection 00: No debounce 01: 2 system clock debounce 1x: 4 system clock debounce Bit 1SIMEN: SIM Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be in a floating condition and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Rev. 1.10 117 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Bit 0SIMICF: SIM Incompleted Flag 0: SIM incompleted is not occurred 1: SIM incompleted is occurred The SIMICF bit is determined by SCS pin. When SCS pin is set high, it will clear the SPI counter. Meanwhile, the interrupt is occurred and the incompleted flag, SIMICF, is set high. SIMC2 Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6D7~D6: Undefined bit This bit can be read or written by user software program. Bit 5CKPOLB: Determines the base condition of the clock line 0: The SCK line will be high when the clock is inactive 1: The SCK line will be low when the clock is inactive The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. Bit 4CKEG: Determines SPI SCK active clock edge type CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit. Bit 3MLS: SPI Data shift order 0: LSB 1: MSB This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Bit 2CSEN: SPI SCS pin Control 0: Disable 1: Enable The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the SCS pin will be disabled and placed into a floating condition. If the bit is high the SCS pin will be enabled and used as a select pin. Note that using the CSEN bit can be disabled or enabled via configuration option. Bit 1WCOL: SPI Write Collision flag 0: No collision 1: Collision The WCOL flag is used to detect if a data collision has occurred. If this bit is high it means that data has been attempted to be written to the SIMD register during a data transfer operation. This writing operation will be ignored if data is being transferred. The bit can be cleared by the application program. Note that using the WCOL bit can be disabled or enabled via configuration option. Rev. 1.10 118 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Bit 0TRF: SPI Transmit/Receive Complete flag 0: Data is being transferred 1: SPI data transmission is completed The TRF bit is the Transmit/Receive Complete flag and is set high automatically when an SPI data transmission is completed, but must cleared to zero by the application program. It can be used to generate an interrupt. SPI Communication After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output an SCS signal to enable the slave device before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI will continue to function even in the IDLE Mode. SPI Master Mode Timing SPI Slave Mode Timing – CKEG=0 Rev. 1.10 119 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU SPI Slave Mode Timing – CKEG=1 SPI Transfer Control Flowchart Rev. 1.10 120 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU I2C Interface The I2C interface is used to communicate with external peripheral devices such as sensors etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. I2C Master/Slave Bus Connection I2C Interface Operation The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two devices communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For this device, which only operates in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. The pull-up control function pin-shared with SCL/SDA pin is still applicable even if I2C device is activated and the related internal pull-up register could be controlled by its corresponding pull-up control register. S T A R T s ig n a l fro m M a s te r S e n d s la v e a d d r e s s a n d R /W b it fr o m M a s te r A c k n o w le d g e fr o m s la v e S e n d d a ta b y te fro m M a s te r A c k n o w le d g e fr o m s la v e S T O P s ig n a l fro m M a s te r Rev. 1.10 121 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU I C Block Diagram 2 I2C Registers There are three control registers associated with the I2C bus, SIMC0, SIMC1 and SIMTOC, one address register, SIMA and one data register, SIMD. The SIMD register, which is shown in the above SPI section, is used to store the data being transmitted and received on the I2C bus. Before the microcontroller writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the microcontroller can read it from the SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD register. Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface. The SIMTOC register is used for I2C time-out control. Bit Register Name 7 6 5 4 SIMC0 SIM2 SIM1 SIM0 — SIMC1 HCF HAAS HBB HTX TXAK SIMD D7 D6 D5 D4 D3 SIMA IICA6 IICA5 IICA4 IICA3 IICA2 3 2 1 0 SIMEN SIMICF SRW RNIC RXAK D2 D1 D0 IICA1 IICA0 D0 SIMDBC1 SIMDBC0 SIMTOC SIMTOEN SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0 I2C Registers List Rev. 1.10 122 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU SIMC0 Register Bit 7 6 5 4 Name SIM2 SIM1 SIM0 — 3 R/W R/W R/W R/W — R/W POR 1 1 1 — 0 2 1 0 SIMEN SIMICF R/W R/W R/W 0 0 0 SIMDBC1 SIMDBC0 Bit 7~5SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fSUB 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Unused mode These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 Unimplemented, read as "0" Bit 3~2SIMDBC1~SIMDBC0: I2C Debounce Time Selection 00: No debounce 01: 2 system clock debounce 1x: 4 system clock debounce Bit 1SIMEN: SIM Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be in a floating condition and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0SIMICF: SIM Incompleted Flag SIMICF is of no used in I2C mode of SIM, please ignore this flag when operate in I2C mode. Rev. 1.10 123 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU SIMC1 Register Bit 7 6 5 4 3 2 1 0 Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R/W R R R R/W R/W R R/W R POR 1 0 0 0 0 0 0 1 Bit 7HCF: I2C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Bit 6HAAS: I2C Bus address match flag 0: Not address match 1: Address match The HASS flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. Bit 5HBB: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The HBB flag is the I2C busy flag. This flag will be "1" when the I2C bus is busy which will occur when a START signal is detected. The flag will be cleared to zero when the bus is free which will occur when a STOP signal is detected. Bit 4HTX: Select I2C slave device is transmitter or receivera 0: Slave device is the receiver 1: Slave device is the transmitter Bit 3TXAK: I2C Bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave do not send acknowledge flag The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always set TXAK bit to "0" before further data is received. Bit 2SRW: I2C Slave Read/Write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SRW flag is the I 2C Slave Read/Write flag. This flag determines whether the master device wishes to transmit or receive data from the I2C bus. When the transmitted address and slave address is match, that is when the HAAS flag is set high, the slave device will check the SRW flag to determine whether it should be in transmit mode or receive mode. If the SRW flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SRW flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1IAMWU: I2C Address Match Wake-up Control 0: Disable 1: Enable This bit should be set high to enable I2C address match wake up from SLEEP or IDLE Mode. Bit 0RXAK: I2C Bus Receive acknowledge flag 0: Slave receive acknowledge flag 1: Slave do not receive acknowledge flag Rev. 1.10 124 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register. SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown SIMA Register Bit 7 6 5 4 3 2 1 0 Name IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~1IICA6~IICA0: I2C slave address IICA6~ IICA0 is the I2C slave address bit 6 ~ bit 0. The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~ 1 of the SIMA register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the SIMA register, the slave device will be selected. Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface. Bit 0 Undefined bit This bit can be read or written by user software program. SIMTOC Register Bit Name R/W POR Bit 7 Bit 6 Bit 5~0 Rev. 1.10 7 6 5 4 3 2 1 0 SIMTOEN SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 SIMTOEN: I2C interface Time-out control 0: Disable 1: Enable SIMTOF: I2C interface Time-out flag 0: No occurred 1: Occurred The SIMTOF flag is set by the time-out circuitry when the time-out event occurs and cleared by software program. SIMTOS5~SIMTOS0: I2C interface Time-out period selection The I2C Time-Out clock source is fSUB/32. The I2C Time-Out time is ([SIMTOS5:SIMTOS0] + 1) × (32/fSUB) 125 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU I2C Bus Communication Communication on the I2C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this: • Step 1 Set the SIM2~SIM0 and SIMEN bits in the SIMC0 register to "1" to enable the I2C bus. • Step 2 Write the slave address of the device to the I2C bus address register SIMA. • Step 3 Set the SIE and SIM Muti-Function interrupt enable bit of the interrupt control register to enable the SIM interrupt and Multi-function interrupt. I2C Bus Initialisation Flow Chart Rev. 1.10 126 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU I2C Bus Start Signal The START signal can only be generated by the master device connected to the I2C bus and not by the slave device. This START signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. Slave Address The transmission of a START signal by the master will be detected by all devices on the I2C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag HAAS when the addresses match. As an I 2C bus interrupt can come from two sources, when the program enters the interrupt subroutine, the HAAS bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I2C Bus Read/Write Signal The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW flag is "1" then this indicates that the master device wishes to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a transmitter. If the SRW flag is "0" then this indicates that the master wishes to send data to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver. I2C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address, any slave device on the I 2C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAAS flag is high, the addresses have matched and the slave device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register should be set high. If the SRW flag is low, then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1 register should be cleared to zero. Rev. 1.10 127 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU I2C Bus Data and Acknowledge Signal The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the SIMD register. If setup as a transmitter, the slave device must first write the data to be transmitted into the SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD register. When the slave receiver receives the data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. I2C Communication Timing Diagram Note: *When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. Rev. 1.10 128 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU I2C Bus ISR Flow Chart I2C Time Out function In order to reduce the I2C lockup problem due to reception of erroneous clock sources, a time-out function is provided. If the clock source connected to the I2C bus is not received for a while, then the I2C circuitry and the SIMC1 register will be reset, the SIMTOF bit in the SIMTOC register will be set high after a certain time-out period. The Time Out function eable/disable and the time-out period are managed by the SIMTOC register. I2C Time Out operation The time-out counter starts to count on an I2C bus "START" & "address match"condition, and is cleared by an SCL falling edge. Before the next SCL falling edge arrives, if the time elapsed is greater than the time-out period specified by the SIMTOC register, then a time-out condition will occur. The time-out function will stop when an I2C "STOP" condition occurs. There are 64 time-out period selections which can be selected using the SIMTOS0~SIMTOS5 bits in the SIMTOC register. Rev. 1.10 129 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU S C L S ta rt S R W S la v e A d d r e s s 0 1 S D A 1 1 0 1 0 A C K 1 0 I2 C t i m e - o u t c o u n te r s ta rt S to p S C L 1 0 0 1 0 1 0 0 S D A I2 C t im e - o u t c o u n t e r r e s e t o n S C L n e g a tiv e tr a n s itio n I2C Time-out Diagram When an I2C time-out counter overflow occurs, the counter will stop and the SIMTOEN bit will be cleared to zero and the SIMTOF bit will be set high to indicate that a time-out condition has occurred. The time-out condition will also generate an interrupt which uses the I2C interrrupt vector. When an I2C time-out occurs, the I2C internal circuitry will be reset and the registers will be reset into the following condition: Register After I2C Tiome-out SIMD, SIMA, SIMC0 No change SIMC1 Reset to POR condition I C Registers after Time-out 2 Rev. 1.10 130 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU UART Module Serial Interface with IR Carrier UART Module features • Full-duplex, Universal Asynchronous Receiver and Transmitter (UART) communication • 8 or 9 bits character length • Even, odd or no parity options • One or two stop bits • Baud rate generator with 8-bit prescaler • Parity, framing, noise and overrun error detection • Support for interrupt on address detect (last character bit=1) • Transmitter and receiver enabled independently • 2-byte Deep FIFO Receive Data Buffer • Transmit and Receive Multiple Interrupt Generation Sources: ♦♦ Transmitter Empty ♦♦ Transmitter Idle ♦♦ Receiver Full ♦♦ Receiver Overrun ♦♦ Address Mode Detect UART Module Overview The embedded UART Module is full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. The UART function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. UART external pin interfacing To communicate with an external serial interface, the internal UART has two external pins known as TX and RX. The TX pin is the UART transmitter pin, which can be used as a general purpose I/O or other pin-shared functional pin if the pin is not configured as a UART transmitter, which occurs when the TXEN bit in the UCR2 control register is equal to zero. Similarly, the RX pin is the UART receiver pin, which can also be used as a general purpose I/O or other pin-shared functional pin, if the pin is not configured as a receiver, which occurs if the RXEN bit in the UCR2 register is equal to zero. Along with the UARTEN bit, the TXEN and RXEN bits, if set, will automatically setup these I/O or other pin-shared functional pins to their respective TX output and RX input conditions and disable any pull-high resistor option which may exist on the RX pin. Rev. 1.10 131 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU UART data transfer scheme The block diagram shows the overall data transfer structure arrangement for the UART. The actual data to be transmitted from the MCU is first transferred to the TXR register by the application program. The data will then be transferred to the Transmit Shift Register from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only the TXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped and is therefore inaccessible to the application program. Data to be received by the UART is accepted on the external RX pin, from where it is shifted in, LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the shift register is full, the data will then be transferred from the shift register to the internal RXR register, where it is buffered and can be manipulated by the application program. Only the RXR register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is therefore inaccessible to the application program. It should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate TXR and RXR registers, only exists as a single shared register in the Data Memory. This shared register known as the TXR/RXR register is used for both data transmission and data reception. Transmitter Shift Register (TSR) MSB ………………………… LSB TX Pin RX Pin Receiver Shift Register (RSR) MSB ………………………… LSB Buffer 3 Buffer 2 Buffer 1 Baud Rate Generator TX Register (TXR) RX Register (RXR) Data to be transmitted Data received UART Data Transfer Scheme UART status and control registers There are five control registers associated with the UART function. The USR, UCR1 and UCR2 registers control the overall function of the UART, while the BRG register controls the Baud rate. The actual data to be transmitted and received on the serial interface is managed through the TXR/ RXR data registers. Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 USR PERR NF FERR OERR RIDLE RXIF TIDLE TXIF UCR1 UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8 UCR2 TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE TXR/RXR TXRX7 TXRX6 TXRX5 TXRX4 TXRX3 TXRX2 TXRX1 TXRX0 BRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 UART Register Summary Rev. 1.10 132 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU USR register The USR register is the status register for the UART, which can be read by the program to determine the present status of the UART. All flags within the USR register are read only. Further explanation on each of the flags is given below: Bit 7 6 5 4 3 2 1 0 Name PERR NF FERR OERR RIDLE RXIF TIDLE TXIF R/W R R R R R R R R POR 0 0 0 0 1 0 1 1 Bit 7PERR: Parity error flag 0: No parity error is detected 1: Parity error is detected The PERR flag is the parity error flag. When this read only flag is "0", it indicates a parity error has not been detected. When the flag is "1", it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can also be cleared by a software sequence which involves a read to the status register USR followed by an access to the RXR data register. Bit 6NF: Noise flag 0: No noise is detected 1: Noise is detected The NF flag is the noise flag. When this read only flag is "0", it indicates no noise condition. When the flag is "1", it indicates that the UART has detected noise on the receiver input. The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of as overrun. The NF flag can be cleared by a software sequence which will involve a read to the status register USR followed by an access to the RXR data register. Bit 5FERR: Framing error flag 0: No framing error is detected 1: Framing error is detected The FERR flag is the framing error flag. When this read only flag is "0", it indicates that there is no framing error. When the flag is "1", it indicates that a framing error has been detected for the current character. The flag can also be cleared by a software sequence which will involve a read to the status register USR followed by an access to the RXR data register. Bit 4OERR: Overrun error flag 0: No overrun error is detected 1: Overrun error is detected The OERR flag is the overrun error flag which indicates when the receiver buffer has overflowed. When this read only flag is "0", it indicates that there is no overrun error. When the flag is "1", it indicates that an overrun error occurs which will inhibit further transfers to the RXR receive data register. The flag is cleared by a software sequence, which is a read to the status register USR followed by an access to the RXR data register. Bit 3RIDLE: Receiver status 0: Data reception is in progress (data being received) 1: No data reception is in progress (receiver is idle) The RIDLE flag is the receiver status flag. When this read only flag is "0", it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. When the flag is "1", it indicates that the receiver is idle. Between the completion of the stop bit and the detection of the next start bit, the RIDLE bit is "1" indicating that the UART receiver is idle and the RX pin stays in logic high condition. Bit 2RXIF: Receive RXR data register status 0: RXR data register is empty 1: RXR data register has available data Rev. 1.10 133 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU The RXIF flag is the receive data register status flag. When this read only flag is "0", it indicates that the RXR read data register is empty. When the flag is "1", it indicates that the RXR read data register contains new data. When the contents of the shift register are transferred to the RXR register, an interrupt is generated if RIE=1 in the UCR2 register. If one or more errors are detected in the received word, the appropriate receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the RXR register, and if the RXR register has no data available. Bit 1TIDLE: Transmission idle 0: Data transmission is in progress (data being transmitted) 1: No data transmission is in progress (transmitter is idle) The TIDLE flag is known as the transmission complete flag. When this read only flag is "0", it indicates that a transmission is in progress. This flag will be set high when the TXIF flag is "1" and when there is no transmit data or break character being transmitted. When TIDLE is equal to "1", the TX pin becomes idle with the pin state in logic high condition. The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR register. The flag is not generated when a data character or a break is queued and ready to be sent. Bit 0TXIF: Transmit TXR data register status 0: Character is not transferred to the transmit shift register 1: Character has transferred to the transmit shift register (TXR data register is empty) The TXIF flag is the transmit data register empty flag. When this read only flag is "0", it indicates that the character is not transferred to the transmitter shift register. When the flag is "1", it indicates that the transmitter shift register has received a character from the TXR data register. The TXIF flag is cleared by reading the UART status register (USR) with TXIF set and then writing to the TXR data register. Note that when the TXEN bit is set, the TXIF flag bit will also be set since the transmit data register is not yet full. UCR1 register The UCR1 register together with the UCR2 register are the two UART control registers that are used to set the various options for the UART function, such as overall on/off control, parity control, data transfer bit length etc. Further explanation on each of the bits is given below: Bit 7 6 5 4 3 2 1 0 Name UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8 R/W R/W R/W R/W R/W R/W R/W R W POR 0 0 0 0 0 0 x 0 "x" unknown Bit 7UARTEN: UART function enable control 0: Disable UART. TX and RX pins are used as I/O or other pin-shared functional pins 1: Enable UART. TX and RX pins function as UART pins The UARTEN bit is the UART enable bit. When this bit is equal to "0", the UART will be disabled and the RX pin as well as the TX pin will be as General Purpose I/ O or other pin-shared functional pins. When the bit is equal to "1", the UART will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN enable control bits. When the UART is disabled, it will empty the buffer so any character remaining in the buffer will be discarded. In addition, the value of the baud rate counter will be reset. If the UART is disabled, all error and status flags will be reset. Also the TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2 and BRG registers will remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. When the UART is re-enabled, it will restart in the same configuration. Rev. 1.10 134 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Bit 6BNO: Number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer This bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. When this bit is equal to "1", a 9-bit data length format will be selected. If the bit is equal to "0", then an 8-bit data length format will be selected. If 9-bit data length format is selected, then bits RX8 and TX8 will be used to store the 9th bit of the received and transmitted data respectively. Bit 5PREN: Parity function enable control 0: Parity function is disabled 1: Parity function is enabled This is the parity enable bit. When this bit is equal to "1", the parity function will be enabled. If the bit is equal to "0", then the parity function will be disabled. Replace the most significant bit position with a parity bit. Bit 4PRT: Parity type selection bit 0: Even parity for parity generator 1: Odd parity for parity generator This bit is the parity type selection bit. When this bit is equal to "1", odd parity type will be selected. If the bit is equal to "0", then even parity type will be selected. Bit 3STOPS: Number of Stop bits selection 0: One stop bit format is used 1: Two stop bits format is used This bit determines if one or two stop bits are to be used. When this bit is equal to "1", two stop bits are used. If this bit is equal to "0", then only one stop bit is used. Bit 2TXBRK: Transmit break character 0: No break character is transmitted 1: Break characters transmit The TXBRK bit is the Transmit Break Character bit. When this bit is "0", there are no break characters and the TX pin operates normally. When the bit is "1", there are transmit break characters and the transmitter will send logic zeros. When this bit is equal to "1", after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset. Bit 1RX8: Receive data bit 8 for 9-bit data transfer format (read only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as RX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. Bit 0TX8: Transmit data bit 8 for 9-bit data transfer format (write only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data known as TX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. Rev. 1.10 135 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU UCR2 register The UCR2 register is the second of the two UART control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation of the UART Transmitter and Receiver as well as enabling the various UART interrupt sources. The register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. Further explanation on each of the bits is given below: Bit 7 6 5 4 3 2 1 0 Name TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7TXEN: UART Transmitter enabled control 0: UART transmitter is disabled 1: UART transmitter is enabled The bit named TXEN is the Transmitter Enable Bit. When this bit is equal to "0", the transmitter will be disabled with any pending data transmissions being aborted. In addition the buffers will be reset. In this situation the TX pin will be used as an I/O or other pin-shared functional pin. If the TXEN bit is equal to "1" and the UARTEN bit is also equal to "1", the transmitter will be enabled and the TX pin will be controlled by the UART. Clearing the TXEN bit during a transmission will cause the data transmission to be aborted and will reset the transmitter. If this situation occurs, the TX pin will be used as an I/O or other pin-shared functional pin. Bit 6RXEN: UART Receiver enabled control 0: UART receiver is disabled 1: UART receiver is enabled The bit named RXEN is the Receiver Enable Bit. When this bit is equal to "0", the receiver will be disabled with any pending data receptions being aborted. In addition the receive buffers will be reset. In this situation the RX pin will be used as an I/O or other pin-shared functional pin. If the RXEN bit is equal to "1" and the UARTEN bit is also equal to "1", the receiver will be enabled and the RX pin will be controlled by the UART. Clearing the RXEN bit during a reception will cause the data reception to be aborted and will reset the receiver. If this situation occurs, the RX pin will be used as an I/O or other pin-shared functional pin. Bit 5BRGH: Baud Rate speed selection 0: Low speed baud rate 1: High speed baud rate The bit named BRGH selects the high or low speed mode of the Baud Rate Generator. This bit, together with the value placed in the baud rate register BRG, controls the Baud Rate of the UART. If this bit is equal to "1", the high speed mode is selected. If the bit is equal to "0", the low speed mode is selected. Bit 4ADDEN: Address detect function enable control 0: Address detect function is disabled 1: Address detect function is enabled The bit named ADDEN is the address detect function enable control bit. When this bit is equal to "1", the address detect function is enabled. When it occurs, if the 8th bit, which corresponds to RX7 if BNO=0 or the 9th bit, which corresponds to RX8 if BNO=1, has a value of "1", then the received word will be identified as an address, rather than data. If the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit depending on the value of BNO. If the address bit known as the 8th or 9th bit of the received word is "0" with the address detect function being enabled, an interrupt will not be generated and the received data will be discarded. Rev. 1.10 136 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Bit 3WAKE: RX pin falling edge wake-up function enable control 0: RX pin wake-up function is disabled 1: RX pin wake-up function is enabled This bit enables or disables the receiver wake-up function. If this bit is equal to "1" and the MCU is in IDLE or SLEEP mode, a falling edge on the RX input pin will wake-up the device. Please reference the UART RX pin wake-up functions in different operating mode for the detail. If this bit is equal to "0" and the MCU is in IDLE or SLEEP mode, any edge transitions on the RX pin will not wake-up the device. Bit 2RIE: Receiver interrupt enable control 0: Receiver related interrupt is disabled 1: Receiver related interrupt is enabled This bit enables or disables the receiver interrupt. If this bit is equal to "1" and when the receiver overrun flag OERR or receive data available flag RXIF is set, the UART interrupt request flag will be set. If this bit is equal to "0", the UART interrupt request flag will not be influenced by the condition of the OERR or RXIF flags. Bit 1TIIE: Transmitter Idle interrupt enable control 0: Transmitter idle interrupt is disabled 1: Transmitter idle interrupt is enabled This bit enables or disables the transmitter idle interrupt. If this bit is equal to "1" and when the transmitter idle flag TIDLE is set, due to a transmitter idle condition, the UART interrupt request flag will be set. If this bit is equal to "0", the UART interrupt request flag will not be influenced by the condition of the TIDLE flag. Bit 0TEIE: Transmitter Empty interrupt enable control 0: Transmitter empty interrupt is disabled 1: Transmitter empty interrupt is enabled This bit enables or disables the transmitter empty interrupt. If this bit is equal to "1" and when the transmitter empty flag TXIF is set, due to a transmitter empty condition, the UART interrupt request flag will be set. If this bit is equal to "0", the UART interrupt request flag will not be influenced by the condition of the TXIF flag. TXR/RXR register Bit 7 6 5 4 3 2 1 0 Name TXRX7 TXRX6 TXRX5 TXRX4 TXRX3 TXRX2 TXRX1 TXRX0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown Bit 7~0TXRX7~TXRX0: UART Transmit/Receive Data bit 7 ~ bit 0 BRG Register Bit 7 6 5 4 3 2 1 0 Name BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown Bit 7~0BRG7~BRG0: Baud Rate values By programming the BRGH bit in UCR2 Register which allows selection of the related formula described above and programming the required value in the BRG register, the required baud ratecan be setup. Note: Baud rate= fSYS/[64×(N+1)] if BRGH=0. Baud rate= fSYS/[16×(N+1)] if BRGH=1. Rev. 1.10 137 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Baud Rate Generator To setup the speed of the serial data communication, the UART function contains its own dedicated baud rate generator. The baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. The first of these is the value placed in the baud rate register BRG and the second is the value of the BRGH bit with the control register UCR2. The BRGH bit decides if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. The value N in the BRG register which is used in the following baud rate calculation formula determines the division factor. Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. UCR2 BRGH Bit 0 1 Baud Rate (BR) fSYS / [64 (N+1)] fSYS / [16 (N+1)] By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register, the required baud rate can be setup. Note that because the actual baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error associated between the actual and requested value. The following example shows how the BRG register value N and the error value can be calculated. Calculating the register and error values For a clock frequency of 4MHz, and with BRGH cleared to zero determine the BRG register value N, the actual baud rate and the error value for a desired baud rate of 4800. From the above table the desired baud rate BR = fSYS / [64 (N+1)] Re-arranging this equation gives N = [fSYS / (BR×64)] - 1 Giving a value for N = [4000000 / (4800×64)] - 1 = 12.0208 To obtain the closest value, a decimal value of 12 should be placed into the BRG register. This gives an actual or calculated baud rate value of BR = 4000000 / [64×(12 + 1)] = 4808 Therefore the error is equal to (4808 - 4800) / 4800 = 0.16% The following tables show actual values of baud rate and error values for the two values of BRGH. Baud Rate K/BPS Baud Rates for BRGH=0 fSYS=4MHz BRG Kbaud fSYS=3.579545MHz Error (%) BRG Kbaud Error (%) fSYS=7.159MHz BRG Kbaud Error (%) 0.3 207 0.300 0.16 185 0.300 0.00 — — — 1.2 51 1.202 0.16 46 1.190 -0.83 92 1.203 0.23 2.4 25 2.404 0.16 22 2.432 1.32 46 2.380 -0.83 4.8 12 4.808 0.16 11 4.661 -2.90 22 4.863 1.32 9.6 6 8.929 -6.99 5 9.321 -2.90 11 9.332 -2.90 19.2 2 20.833 8.51 2 18.643 -2.90 5 18.643 -2.90 38.4 — — — — — — 2 32.286 -2.90 57.6 0 62.500 8.51 0 55.930 -2.90 1 55.930 -2.90 115.2 — — — — — — 0 111.859 -2.90 Baud Rates and Error Values for BRGH = 0 Rev. 1.10 138 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Baud Rate K/BPS Baud Rates for BRGH=0 fSYS=4MHz fSYS=3.579545MHz fSYS=7.159MHz BRG Kbaud Error (%) BRG Kbaud Error (%) BRG Kbaud Error (%) 0.3 — — — — — — — — — 1.2 207 1.202 0.16 185 1.203 0.23 — — — 2.4 103 2.404 0.16 92 2.406 0.23 185 2.406 0.23 4.8 51 4.808 0.16 46 4.76 -0.83 92 4.811 0.23 9.6 25 9.615 0.16 22 9.727 1.32 46 9.520 -0.83 19.2 12 19.231 0.16 11 18.643 -2.90 22 19.454 1.32 38.4 6 35.714 -6.99 5 37.286 -2.90 11 37.286 -2.90 57.6 3 62.5 8.51 3 55.930 -2.90 7 55.930 -2.90 115.2 1 125 8.51 1 111.86 -2.90 3 111.86 -2.90 250 0 250 0 — — — — — — Baud Rates and Error Values for BRGH = 1 UART Setup and Control For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ, format. This is composed of one start bit, eight or nine data bits, and one or two stop bits. Parity is supported by the UART hardware, and can be setup to be even, odd or no parity. For the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as the default setting, which is the setting at power-on. The number of data bits and stop bits, along with the parity, are setup by programming the corresponding BNO, PRT, PREN, and STOPS bits in the UCR1 register. The baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received LSB first. Although the UART transmitter and receiver are functionally independent, they both use the same data format and baud rate. In all cases stop bits will be used for data transmission. Enabling/disabling the UART The basic on/off function of the internal UART function is controlled using the UARTEN bit in the UCR1 register. If the UARTEN, TXEN and RXEN bits are set, then these two UART pins will act as normal TX output pin and RX input pin respectively. If no data is being transmitted on the TX pin, then it will default to a logic high value. Clearing the UARTEN bit will disable the TX and RX pins and allow these two pins to be used as normal I/O or other pin-shared functional pins. When the UART function is disabled the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. Disabling the UART will also reset the error and status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF being cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaffected. If the UARTEN bit in the UCR1 register is cleared while the UART is active, then all pending transmissions and receptions will be immediately suspended and the UART will be reset to a condition as defined above. If the UART is then subsequently re-enabled, it will restart again in the same configuration. Rev. 1.10 139 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Data, parity and stop bit selection The format of the data to be transferred, is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. These factors are determined by the setup of various bits within the UCR1 register. The BNO bit controls the number of data bits which can be set to either 8 or 9, the PRT bit controls the choice of odd or even parity, the PREN bit controls the parity on/off function and the STOPS bit decides whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address bit identifies the frame as an address character. The number of stop bits, which can be either one or two, is independent of the data length. Start Bit Data Bits Address Bits Parity Bits Stop Bit Example of 8-bit Data Formats 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 Example of 9-bit Data Formats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 Transmitter Receiver Data Format The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. UART transmitter Data word lengths of either 8 or 9 bits, can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, needs to be stored in the TX8 bit in the UCR1 register. At the transmitter core lies the Transmitter Shift Register, more commonly known as the TSR, whose data is obtained from the transmit data register, which is known as the TXR register. The data to be transmitted is loaded into this TXR register by the application program. The TSR register is not written to with new data until the stop bit from the previous transmission has been sent out. As soon as this stop bit has been transmitted, the TSR can then be loaded with new data from the TXR register, if it is available. It should be noted that the TSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. An actual transmission of data will normally be enabled when the TXEN bit is set, but the data will not be transmitted until the TXR register has been loaded with data and the baud rate generator has defined a shift clock source. However, the transmission can also be initiated by first loading data into the TXR register, after which the TXEN bit can be set. When a transmission of data begins, the TSR is normally empty, in which case a transfer to the TXR register will result in an immediate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission will immediately cease and the transmitter will be reset. The TX output pin will then return to the I/O or other pin-shared function. Rev. 1.10 140 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Transmitting data When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with the least significant bit first. In the transmit mode, the TXR register forms a buffer between the internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a data transfer can be summarized as follows: • Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. • Setup the BRG register to select the desired baud rate. • Set the TXEN bit to ensure that the TX pin is used as a UART transmitter pin. • Access the USR register and write the data that is to be transmitted into the TXR register. Note that this step will clear the TXIF bit. • This sequence of events can now be repeated to send additional data. It should be noted that when TXIF=0, data will be inhibited from being written to the TXR register. Clearing the TXIF flag is always achieved using the following software sequence: 1. A USR register access 2. A TXR register write execution The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is empty and that other data can now be written into the TXR register without overwriting the previous data. If the TEIE bit is set then the TXIF flag will generate an interrupt. During a data transmission, a write instruction to the TXR register will place the data into the TXR register, which will be copied to the shift register at the end of the present transmission. When there is no data transmission in progress, a write instruction to the TXR register will place the data directly into the shift register, resulting in the commencement of data transmission, and the TXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the TIDLE bit will be set. To clear the TIDLE bit the following software sequence is used: 1. A USR register access 2. A TXR register write execution Note that both the TXIF and TIDLE bits are cleared by the same software sequence. Transmit break If the TXBRK bit is set then break characters will be sent on the next transmission. Break character transmission consists of a start bit, followed by 13×N ‘0’ bits and stop bits, where N=1, 2, etc. If a break character is to be transmitted then the TXBRK bit must be first set by the application program, then cleared to generate the stop bits. Transmitting a break character will not generate a transmit interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. The automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized. Rev. 1.10 141 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU UART receiver The UART is capable of receiving word lengths of either 8 or 9 bits. If the BNO bit is set, the word length will be set to 9 bits with the MSB being stored in the RX8 bit of the UCR1 register. At the receiver core lies the Receive Serial Shift Register, commonly known as the RSR. The data which is received on the RX external input pin, is sent to the data recovery block. The data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the receive data register, if the register is empty. The data which is received on the external RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted that the RSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. Receiving data When the UART receiver is receiving data, the data is serially shifted in on the external RX input pin, LSB first. In the read mode, the RXR register forms a buffer between the internal bus and the receiver shift register. The RXR register is a two byte deep FIFO data buffer, where two bytes can be held in the FIFO while a third byte can continue to be received. Note that the application program must ensure that the data is read from RXR before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows: • Make the correct selection of BNO, PRT, PREN and STOPS bits to define the word length, parity type and number of stop bits. • Setup the BRG register to select the desired baud rate. • Set the RXEN bit to ensure that the RX pin is used as a UART receiver pin. • At this point the receiver will be enabled which will begin to look for a start bit. • When a character is received the following sequence of events will occur: • The RXIF bit in the USR register will be set when RXR register has data available, at least one more character can be read. • When the contents of the shift register have been transferred to the RXR register, then if the RIE bit is set, an interrupt will be generated. • If during reception, a frame error, noise error, parity error, or an overrun error has been detected, then the error flags can be set. The RXIF bit can be cleared using the following software sequence: 1. A USR register access 2. An RXR register read execution Rev. 1.10 142 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Receive break Any break character received by the UART will be managed as a framing error. The receiver will count and expect a certain number of bit times as specified by the values programmed into the BNO and STOPS bits. If the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by BNO and STOPS. The RXIF bit is set, FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the RIDLE bit is set. If a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not make the assumption that the break condition on the line is the next start bit. A break is regarded as a character that contains only zeros with the FERR flag set. The break character will be loaded into the buffer and no further data will be received until stop bits are received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received. The reception of a break character on the UART registers will result in the following: • The framing error flag, FERR, will be set. • The receive data register, RXR, will be cleared. • The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set. Idle status When the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition. Receiver interrupt The read only receive interrupt flag RXIF in the USR register is set by an edge generated by the receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift Register, RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if RIE=1. Managing receiver errors Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART. Overrun Error – OERR flag The RXR register is composed of a two byte deep FIFO data buffer, where two bytes can be held in the FIFO register, while a third byte can continue to be received. Before this third byte has been entirely shifted in, the data should be read from the RXR register. If this is not done, the overrun error flag OERR will be consequently indicated. In the event of an overrun error occurring, the following will happen: • The OERR flag in the USR register will be set. • The RXR contents will not be lost. • The shift register will be overwritten. • An interrupt will be generated if the RIE bit is set. The OERR flag can be cleared by an access to the USR register followed by a read to the RXR register. Rev. 1.10 143 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Noise Error – NF Flag Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is detected within a frame the following will occur: • The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit. • Data will be transferred from the Shift register to the RXR register. • No interrupt will be generated. However this bit rises at the same time as the RXIF bit which itself generates an interrupt. Note that the NF flag is reset by a USR register read operation followed by an RXR register read operation. Framing Error – FERR Flag The read only framing error flag, FERR, in the USR register, is set if a zero is detected instead of stop bits. If two stop bits are selected, both stop bits must be high, otherwise the FERR flag will be set. The FERR flag is buffered along with the received data and is cleared on any reset. Parity Error – PERR Flag The read only parity error flag, PERR, in the USR register, is set if the parity of the received word is incorrect. This error flag is only applicable if the parity is enabled, PREN = 1, and if the parity type, odd or even is selected. The read only PERR flag is buffered along with the received data bytes. It is cleared on any reset. It should be noted that the FERR and PERR flags are buffered along with the corresponding word and should be read before reading the data word. UART Module Interrupt Structure Several individual UART conditions can generate a UART interrupt. When these conditions exist, a low pulse will be generated to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. When any of these conditions are created, if the global interrupt enable bit, multi-function interrupt enable bit and its corresponding interrupt control bit are enabled and the stack is not full, the program will jump to its corresponding interrupt vector where it can be serviced before returning to the main program. Four of these conditions have the corresponding USR register flags which will generate a UART interrupt if its associated interrupt enable control bit in the UCR2 register is set. The two transmitter interrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. These enable bits can be used to mask out individual UART interrupt sources. The address detect condition, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt when an address detect condition occurs if its function is enabled by setting the ADDEN bit in the UCR2 register. An RX pin wake-up, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt if the microcontroller is woken up by a falling edge on the RX pin, if the WAKE and RIE bits in the UCR register are set. Note that in the event of an RX wake-up interrupt occurring, there will be a certain period of delay, commonly known as the System Start-up Time, for the oscillator to restart and stabilize before the system resumes normal operation. Note that the USR register flags are read only and cannot be cleared or set by the application program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the case for some of the other interrupts. The flags will be cleared automatically when certain actions are taken by the UART, the details of which are given in the UART register section. The overall UART interrupt can be disabled or enabled by the related interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the UART module is masked out or allowed. Rev. 1.10 144 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU USR Registe� UCR� Registe� T�ansmitte� Empty Flag TXIF TEIE T�ansmitte� Idle Flag TIDLE TIIE 0 1 RIE 0 1 Re�eive� �ve��un Flag �ERR �R Re�eive� Data Availa�le RXIF RX Pin Wake-up WAKE ADDEN 0 1 UART Inte��upt Request Flag UIF MFI1 Registe� UIE INTC0 Registe� INTC1 Registe� EMI MF1E 0 1 0 1 0 1 RX7 if BN�=0 RX8 if BN�=1 UCR� Registe� UART Interrupt Scheme Address detect mode Setting the Address Detect Mode bit, ADDEN, in the UCR2 register, enables this special mode. If this bit is enabled then an additional qualifier will be placed on the generation of a Receiver Data Available interrupt, which is requested by the RXIF flag. If the ADDEN bit is enabled, then when data is available, an interrupt will only be generated, if the highest received bit has a high value. Note that the MFnE, UIE and EMI interrupt enable bits must also be enabled for correct interrupt generation. This highest address bit is the 9th bit if BNO=1 or the 8th bit if BNO=0. If this bit is high, then the received word will be defined as an address rather than data. A Data Available interrupt will be generated every time the last bit of the received word is set. If the ADDEN bit is not enabled, then a Receiver Data Available interrupt will be generated each time the RXIF flag is set, irrespective of the data last bit status. The address detect mode and parity enable are mutually exclusive functions. Therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity enable bit to zero. ADDEN Bit 9 if BNO=1, Bit 8 if BNO=0 UART Interrupt Generated 0 √ 1 √ 0 × 1 √ 0 1 ADDEN Bit Function Rev. 1.10 145 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU UART Module Power Down and Wake-up When the MCU is in the Power Down Mode, the UART will cease to function. When the device enters the Power Down Mode, all clock sources to the module are shutdown. If the MCU enters the Power Down Mode while a transmission is still in progress, then the transmission will be paused until the UART clock source derived from the microcontroller is activated. In a similar way, if the MCU enters the Power Down Mode while receiving data, then the reception of data will likewise be paused. When the MCU enters the Power Down Mode, note that the USR, UCR1, UCR2, transmit and receive registers, as well as the BRG register will not be affected. It is recommended to make sure first that the UART data transmission or reception has been finished before the microcontroller enters the Power Down mode. The UART function contains a receiver RX pin wake-up function, which is enabled or disabled by the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit, UARTEN, the receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set before the MCU enters the Power Down Mode, then a falling edge on the RX pin will wake up the MCU from the Power Down Mode. Note that as it takes certain system clock cycles after a wake-up, before normal microcontroller operation resumes, any data received during this time on the RX pin will be ignored. For a UART wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global interrupt enable bit, EMI, and the UART interrupt enable bit, UIE, must also be set. If these two bits are not set then only a wake up event will occur and no interrupt will be generated. Note also that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes, the UART interrupt will not be generated until after this time has elapsed. IR Modulation Interface The UART interface has an integrated IR modulation interface. Infrared modulation frequency control by register IRCTRL0, its value is any integer between 0 and 127. Infrared modulation: When TXD = 0 only, the IR modulation will produce infrared mixing and output data. To meet the needs of both PNP and NPN infrared driver tube, located in the register IRCTRL0 bit7 IRTC, control the polarity of the output of the infrared modulation. IRTC = 0 for positive polarity output, suitable for PNP transistor driver; IRTC = 1 for a negative output, suitable for the NPN driver. See below: Rev. 1.10 146 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU IRCTRL0 Register Bit 7 6 5 4 3 2 1 0 Name IRTC IRDC6 IRDC5 IRDC4 IRDC3 IRDC2 IRDC1 IRDC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 IRTC: IR modulation output polarity select 0: Negative 1: Positive Bit 6~0 IRDC6~IRDC0: IR modulation frequency divider coefficient Fcarry = (fSYS/(IRDC+1))/2 IRCTRL1 Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — — IRME0 R/W — — — — — — — R/W POR — — — — — — — 0 Bit 7~1 Unimplemented, read as "0" Bit 0 IRME0: UART0 TX IR modulation control 0: UART0 TX IR modulation disable 1: UART0 TX IR modulation enable Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains several external interrupt and internal interrupts functions. The external interrupts are generated by the action of the external INT0~INT1 and PINTB pins, while the internal interrupts are generated by various internal functions such as the TMs, Time Base, LVD, EEPROM and the A/D converter. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory. The first is the INTC0~INTC2 registers which setup the primary interrupts, the second is the MFI0~MFI3 registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "E" for enable/disable bit or "F" for request flag. Rev. 1.10 147 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Function Enable Bit Request Flag Notes Global EMI — — INTn Pin INTnE INTnF n=0~1 Multi-function MFnE MFnF n=0~3 A/D Converter ADE ADF — Time Base TBnE TBnF n=0~1 LVD LVE LVF — EEPROM DEE DEF — SIM SIE SIF — I2C time out I2CTOE I2CTOF — UART UIE UIF — TM TnPE TnPF TnAE TnAF n=0~2 Interrupt Register Bit Naming Conventions Bit Register Name 7 6 5 4 3 2 1 0 INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0 INTC0 — MF0F INT1F INT0F MF0E INT1E INT0E EMI INTC1 MF1F TB1F TB0F ADF MF1E TB1E TB0E ADE INTC2 CP1F CP0F MF3F MF2F CP1E CP0E MF3E MF2E MFI0 — — T0AF T0PF — — T0AE T0PE MFI1 UIF SIF DEF LVF UIE SIE DEE LVE MFI2 I2CTOF — T1AF T1PF I2CTOE — T1AE T1PE MFI3 — — T2AF T2PF — — T2AE T2PE Interrupt Register Contents INTEG Register Bit 7 6 5 4 3 2 1 0 Name — — — — INT1S1 INT1S0 INT0S1 INT0S0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3~2INT1S1~INT1S0: interrupt edge control for INT1 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges Bit 1~0INT0S1~INT0S0: interrupt edge control for INT0 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges Rev. 1.10 148 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU INTC0 Register Bit 7 6 5 4 3 2 1 0 Name — MF0F INT1F INT0F MF0E INT1E INT0E EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6MF0F: Multi-function Interrupt 0 Request Flag 0: No request 1: Interrupt request Bit 5INT1F: INT1 interrupt request flag 0: No request 1: Interrupt request Bit 4INT0F: INT0 interrupt request flag 0: No request 1: Interrupt request Bit 3MF0E: Multi-function Interrupt 0 Control 0: Disable 1: Enable Bit 2INT1E: INT1 interrupt control 0: Disable 1: Enable Bit 1INT0E: INT0 interrupt control 0: Disable 1: Enable Bit 0EMI: Global interrupt control 0: Disable 1: Enable INTC1 Register Bit 7 6 5 4 3 2 1 0 Name MF1F TB1F TB0F ADF MF1E TB1E TB0E ADE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7MF1F: Multi-function Interrupt 1 Request Flag 0: No request 1: Interrupt request Bit 6TB1F: Time Base 1 Interrupt Request Flag 0: No request 1: Interrupt request Bit 5TB0F: Time Base 0 Interrupt Request Flag 0: No request 1: Interrupt request Bit 4ADF: A/D Converter Interrupt Request Flag 0: No request 1: Interrupt request Bit 3MF1E: Multi-function Interrupt 1 Control 0: Disable 1: Enable Bit 2TB1E: Time Base 1 Interrupt Control 0: Disable 1: Enable Bit 1TB0E: Time Base 0 Interrupt Control 0: Disable 1: Enable Bit 0ADE: A/D Converter Interrupt Control 0: Disable 1: Enable Rev. 1.10 149 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU INTC2 Register Bit 7 6 5 4 3 2 1 0 Name CP1F CP0F MF3F MF2F CP1E CP0E MF3E MF2E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 CP1F: Comparator 1 Interrupt Control 0: No request 1: Interrupt request Bit 6 CP0F: Comparator 0 Interrupt Control 0: No request 1: Interrupt request Bit 5MF3F: Multi-function Interrupt 3 Request Flag 0: No request 1: Interrupt request Bit 4MF2F: Multi-function Interrupt 2 Request Flag 0: No request 1: Interrupt request Bit 3 CP1E: Comparator 1 Interrupt Control 0: Disable 1: Enable Bit 2 CP0E: Comparator 0 Interrupt Control 0: Disable 1: Enable Bit 1MF3E: Multi-function Interrupt 3 Control 0: Disable 1: Enable Bit 0MF2E: Multi-function Interrupt 2 Control 0: Disable 1: Enable MFI0 Register Bit 7 6 5 4 3 2 1 0 Name — — T0AF T0PF — — T0AE T0PE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5T0AF: TM0 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4T0PF: TM0 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1T0AE: TM0 Comparator A match interrupt control 0: Disable 1: Enable Bit 0T0PE: TM0 Comparator P match interrupt control 0: Disable 1: Enable Rev. 1.10 150 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU MFI1 Register Bit 7 6 5 4 3 2 1 0 Name UIF SIF DEF LVF UIE SIE DEE LVE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 UIF: UART interrupt request flag 0: No request 1: Interrupt request Bit 6SIF: SIM interrupt request flag 0: No request 1: Interrupt request Bit 5 DEF: Data EEPROM interrupt request flag 0: No request 1: Interrupt request Bit 4LVF: LVD interrupt request flag 0: No request 1: Interrupt request Bit 3 UIE: UART interrupt control 0: Disable 1: Enable Bit 2SIE: SIM Interrupt Control 0: Disable 1: Enable Bit 1 DEE: Data EEPROM interrupt control 0: Disable 1: Enable Bit 0LVE: LVD Interrupt Control 0: Disable 1: Enable Bit 7 MFI2 Register Bit 7 6 5 4 3 2 1 0 Name I2CTOF — T1AF T1PF I2CTOE — T1AE T1PE R/W R/W — R/W R/W R/W — R/W R/W POR 0 — 0 0 0 — 0 0 I2CTOF: I C Time Out interrupt request flag 0: No request 1: Interrupt request Bit 6 Unimplemented, read as "0" Bit 5T1AF: TM1 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4T1PF: TM1 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3 I2CTOE: I2C Time Out interrupt control 0: Disable 1: Enable Bit 2 Unimplemented, read as "0" Bit 1T1AE: TM1 Comparator A match interrupt control 0: Disable 1: Enable Bit 0T1PE: TM1 Comparator P match interrupt control 0: Disable 1: Enable Bit 7 Rev. 1.10 2 151 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU MFI3 Register Bit 7 6 5 4 3 2 1 0 Name — — T2AF T2PF — — T2AE T2PE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5T2AF: TM2 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4T2PF: TM2 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1T2AE: TM2 Comparator A match interrupt control 0: Disable 1: Enable Bit 0T2PE: TM2 Comparator P match interrupt control 0: Disable 1: Enable Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P, Comparator A match or A/D conversion completion etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a "JMP" which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a "RETI", which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. Rev. 1.10 152 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Legend xxF Request Flag – no auto reset in ISR xxF EMI auto disabled in ISR Request Flag – auto reset in ISR Interrupt Request Name Flags xxE Enable Bit Interrupt Name Enable Bits Master Enable Vector INT0 Pin INT0F INT0E EMI 04H Request Flags Enable Bits INT1 Pin INT1F INT1E EMI 08H TM0 P T0PF T0PE M. Funct. 0 MF0F MF0E EMI 0CH TM0 A T0AF T0AE A/D ADF ADE EMI 10H Time Base 0 TB0F TB0E EMI 14H Time Base 1 TB1F TB1E EMI 18H LVD LVF LVE EEPROM DEF DEE UART UIF UIE SIM SIF SIE M. Funct. 1 MF1F MF1E EMI 1CH I2CTO I2CTOF I2CTOE M. Funct. 2 MF2F MF2E EMI 20H TM1 P T1PF T1PE TM1 A T1AF T1AE TM2 P T2PF T2PE M. Funct. 3 MF3F MF3E EMI 24H TM2 A T2AF T2AE Comp.0 CP0F CP0E EMI 28H Comp.1 CP1F CP1E EMI 2CH Interrupts contained within Multi-Function Interrupts Priority High Low Interrupt Structure External Interrupt The external interrupts are controlled by signal transitions on the pins INT0~INT1. An external interrupt request will take place when the external interrupt request flags, INT0F~INT1F, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E~INT1E, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flags, INT0F~INT1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the Rev. 1.10 153 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU external interrupt pins will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Comparator Interrupt The comparator interrupts are controlled by the two internal comparators. A comparator interrupt request will take place when the comparator interrupt request flags, CP0F or CP1F, are set, a situation that will occur when the comparator output changes state. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and comparator interrupt enable bits, CP0E and CP1E, must first be set. When the interrupt is enabled, the stack is not full and the comparator inputs generate a comparator output transition, a subroutine call to the comparator interrupt vector, will take place. When the interrupt is serviced, the comparator interrupt request flags will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. A/D Converter Interrupt The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/ D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs when the A/D conversion process finishes. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the A/D Converter Interrupt vector, will take place. When the interrupt is serviced, the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Multi-function Interrupt Within this device there are up to four Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM Interrupts, LVD interrupt, UART interrupt, SIM Interrupt, I2C time out Interrupt and EEPROM Interrupt. A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags, MFnF are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related MultiFunction request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts, namely the TM Interrupts, LVD interrupt, UART interrupt, SIM Interrupt, I2C time out Interrupt and EEPROM Interrupt will not be automatically reset and must be manually reset by the application program. Rev. 1.10 154 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Serial Interface Module Interrupt The Serial Interface Module Interrupt, also known as the SIM interrupt, is contained within the Multi-function Interrupt. An SIM Interrupt request will take place when the SIM Interrupt request flag, SIF, is set, which occurs when a byte of data has been received or transmitted by the SIM interface. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface Interrupt enable bit, SIE, and Muti-function interrupt enable bits, must first be set. When the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the SIM interface, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the Serial Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the SIF flag will not be automatically cleared, it has to be cleared by the application program. Time Base Interrupts The function of the Time Base Interrupts is to provide regular time signal in the form of an internal interrupt. They are controlled by the overflow signals from their respective timer functions. When these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to their respective vector locations will take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their clock sources originate from the internal clock source fTB. This fTB input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges. The clock source that generates fTB, which in turn controls the Time Base interrupt period, can originate from several different sources, as shown in the System Operating Mode section. Time Base Interrupt Rev. 1.10 155 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU TBC Register Bit 7 6 5 4 3 2 1 0 Name TBON TBCK TB11 TB10 LXTLP TB02 TB01 TB00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 1 1 0 1 1 1 Bit 7TBON: TB0 and TB1 Control 0: Disable 1: Enable Bit 6TBCK: Select fTB Clock 0: fSUB 1: fSYS/4 Bit 5~4TB11~TB10: Select Time Base 1 Time-out Period 00: 4096/fTB 01: 8192/fTB 10: 16384/fTB 11: 32768/fTB Bit 3LXTLP: LXT Low Power Control 0: Disable (LXT quick start-up) 1: Enable (LXT slow start-up) Bit 2~0TB02~TB00: Select Time Base 0 Time-out Period 000: 256/fTB 001: 512/fTB 010: 1024/fTB 011: 2048/fTB 100: 4096/fTB 101: 8192/fTB 110: 16384/fTB 111: 32768/fTB I2C Time Out Interrupt The I2C Time Out Interrupt operates is contained within the Multi-function Interrupt. An I2C Time Out Interrupt request will take place when the I2C Time Out Interrupt request flag, I2CTOF, is set, which occurs when an I2C time-out counter overflows. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, I2C time out interrupt enable bit, I2CTOE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and an I2C time-out counter overflow occurs, a subroutine call to the respective Multi-function Interrupt, will take place. When the I2C time out interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multifunction interrupt request flag will be also automatically cleared. As the I2CTOF flag will not be automatically cleared, it has to be cleared by the application program. Rev. 1.10 156 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU UART Interrupt The UART interrupt is contained within the Multi-function Interrupt. Several individual UART conditions can generate a UART interrupt. When these conditions exist, a low pulse will be generated to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. To allow the program to branch to the respective interrupt vector addresses, the global interrupt enable bit, EMI, multi-function enable bit, MFnE and UART interrupt enable bit, UIE, must first be set. When the interrupt is enabled, the stack is not full and any of these conditions are created, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, the Multifunction interrupt request flag will be also automatically cleared. However, the USR register flags will be cleared automatically when certain actions are taken by the UART, the details of which are given in the UART section. EEPROM Interrupt The EEPROM interrupt is contained within the Multi-function Interrupt. An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit, DEE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective EEPROM Interrupt vector will take place. When the EEPROM Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the DEF flag will not be automatically cleared, it has to be cleared by the application program. LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the Multi-function Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically cleared, it has to be cleared by the application program. Rev. 1.10 157 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU TM Interrupts The Compact and Periodic Type TMs have two interrupts each. All of the TM interrupts are contained within the Multi-function Interrupts. For each of the Compact and Periodic Type TMs there are two interrupt request flags TnPF and TnAF and two enable bits TnPE and TnAE. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or A match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MFnF, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the "CALL" instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Rev. 1.10 158 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Low Voltage Detector – LVD Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage conditionwill be determined. A low voltage condition is indicatedwhen the LVDO bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Bit 7 6 5 4 3 2 1 0 Name — — LVDO LVDEN — VLVD2 VLVD1 VLVD0 R/W — — R R/W — R/W R/W R/W POR — — 0 0 — 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5LVDO: LVD Output Flag 0: No Low Voltage Detect 1: Low Voltage Detect Bit 4LVDEN: Low Voltage Detector Control 0: Disable 1: Enable Bit 3 Unimplemented, read as "0" Bit 2~0VLVD2~VLVD0: Select LVD Voltage 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.0V Rev. 1.10 159 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V. When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltagewhich will be automatically enabled.When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multifunction interrupts, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of tLVDS after the LVDO bit has been set high by a low voltage condition. When the device is powered down the Low Voltage Detector will remain active if the LVDEN bit is high. In this case, the LVF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is not required then the LVF flag should be first set high before the device enters the SLEEP or IDLE Mode. When LVD function is enabled, it is recommenced to clear LVD flag first, and then enables interrupt function to avoid mistake action. Rev. 1.10 160 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU LCD Driver For large volume applications, which incorporate an LCD in their design, the use of a custom display rather than a more expensive character based display reduces costs significantly. However, the corresponding COM and SEG signals required, which vary in both amplitude and time, to drive such a custom display require many special considerations for proper LCD operation to occur. The device contains an LCD Driver function, which with their internal LCD signal generating circuitry and various options, will automatically generate these time and amplitude varying signals to provide a means of direct driving and easy interfacing to a range of custom LCDs. This device includes a wide range of options to enable LCD displays of various types to be driven. The table shows the range of options available across the device range. Driver No. Bias Duty Bias Type 28×4 1/3 1/4 C or R LCD Selections VA = VDD VB = 2/3 x VDD VC = 1/3 x VDD VMAX R VLCD R VA C1 C2 0.1µF V1 0.1µF VB R VC V2 0.1µF R type and 1/3 Bias C type and 1/3 Bias VDD = VMAX = VLCD VA = VDD VB = 2/3 ´ VDD VC = 1/3 ´ VDD R Type Bias Voltage Levels C Type Bias Voltage Levels LCD Display Memory The device provides an area of embedded data memory for the LCD display. This area is located at 80H to 9BH in Bank 1 of the Data Memory. The bank pointer BP enables either the General Purpose Data Memory or LCD Memory to be chosen. When BP is set to "01H", any data written into location range 80H~9BH will affect the LCD display. When the BP is cleared to "00H", any data written into 80H~9BH will access the General Purpose Data Memory. The LCD display memory can be read and written to only indirectly using MP1. When data is written into the display data area, it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. To turn the display on or off, a "1" or a "0" is written to the corresponding bit of the display memory, respectively. The figure illustrates the mapping between the display memory and LCD pattern for the device. Rev. 1.10 161 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU b3 b2 b1 b0 9AH SEG26 9BH SEG27 COM0 SEG1 COM1 81H COM2 SEG0 COM3 80H LCD Memory Map Clock Source The LCD clock source is the internal clock signal, fSUB, divided by 8, using an internal divider circuit. The fSUB internal clock is supplied by either the LIRC or LXT oscillator, the choice of which is determined by a configuration option. For proper LCD operation, this arrangement is provided to generate an ideal LCD clock source frequency of 4kHz. fSUB Clock Source LCD Clock Frequency LIRC 4kHz LXT 4kHz LCD Clock Source LCD Registers Control Registers in the Data Memory, are used to control the various setup features of the LCD Driver. There are five control registers for the LCD function, LCDC, LCD1, LCD2, LCD3 and LCD4. Various bits in the LCDC register control functions such as bias type, bias current selection, overall LCD enable and disable. The LCDEN bit in the LCDC register, which provides the overall LCD enable/disable function, will only be effective when the device is in the Normal, Slow or Idle Mode. If the device is in the Sleep Mode then the display will always be disabled. Bits LCDIS0 and LCDIS1 in the LCDC register are used to select the internal bias current to supply the LCD panel with the correct bias voltages. A choice to best match the LCD panel used in the application can be selected also to minimise bias current. The RCS bit in the same register is used to select whether R type or C type LCD drive bias. Four registers, LCD1~LCD4, are used to determine if the output function of display pins SEG0~SEG27 are used as segment drivers or I/O functions, COM0~COM3 are used as common drivers or I/O functions. Rev. 1.10 162 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU LCDC Register Bit 7 6 5 4 3 2 1 0 Name LCDEN RCS — — — — LCDIS1 LCDIS0 R/W R/W R/W — — — — R/W R/W POR 0 0 — — — — 0 0 Bit 7LCDEN: LCD Enable Control 0: Disable 1: Enable In the Normal, Slow or Idle mode, the LCD on/off function can be controlled by this bit. In the Sleep mode, the LCD is always off. Bit 6 RCS: LCD Bias Type Control 0: R type 1: C type Bit 5~2 Unimplemented, read as "0" Bit 1~0LCDIS1~LCDIS0: LCD Bias Current Select 00: 25μA 01: 50μA 10: 100μA 11: 200μA LCD1 Register Bit 7 6 5 4 3 2 1 0 Name LCDS7 LCDS6 LCDS5 LCDS4 LCDS3 LCDS2 LCDS1 LCDS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0LCDS7~LCDS0: SEG7~SEG0 Output Control 0: Disable 1: Enable LCD2 Register Bit 7 6 5 4 3 2 1 0 Name LCDS15 LCDS14 LCDS13 LCDS12 LCDS11 LCDS10 LCDS9 LCDS8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0LCDS15~LCDS8: SEG15~SEG8 Output Control 0: Disable 1: Enable LCD3 Register Bit 7 6 5 4 3 2 1 0 Name LCDS23 LCDS22 LCDS21 LCDS20 LCDS19 LCDS18 LCDS17 LCDS16 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0LCDS23~LCDS16: SEG23~SEG16 Output Control 0: Disable 1: Enable Rev. 1.10 163 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU LCD4 Register Bit 7 6 5 4 3 2 1 0 Name COM3 COM2 COM1 COM0 LCDS27 LCDS26 LCDS25 LCDS24 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~4COM3~COM0: COM3~COM0 Output Control 0: Disable 1: Enable Bit 3~0LCDS27~LCDS24: SEG27~SEG24 Output Control 0: Disable 1: Enable Note: During HALT, LCD off (LCDEN=0), MCU enters HALT, RCS=1(C type), all COMs/SEGs’ Level will be in a floating state. LCD Driver Output The output structure of the device LCD driver can be 28×4. The LCD driver bias type has R and C type. The C/R type and number of COM and SEG is selected by software option. The LCD driver has a fixed 1/3 value. LCD Waveform Timing Diagrams The device generates 1/4 duty and 1 /3 bias LCD signals, as shown below. Note: For R type / C type, VA=VDD, VB=VDD×2/3 and VC=VDD×1/3 LCD Driver Output – 1/4 Duty, 1/3 Bias Rev. 1.10 164 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Programming Considerations Certain precautions must be taken when programming the LCD. One of these is to ensure that the LCD Memory is properly initialised after the microcontroller is powered on. Like the General Purpose Data Memory, the contents of the LCD Memory are in an unknown condition after poweron. As the contents of the LCD Memory will be mapped into the actual display, it is important to initialise this memory area into a known condition soon after applying power to obtain a proper display pattern. Consideration must also be given to the capacitive load of the actual LCD used in the application. As the load presented to the microcontroller by LCD pixels can be generally modeled as mainly capacitive in nature, it is important that this is not excessive, a point that is particularly true in the case of the COM lines which may be connected to many LCD pixels. The accompanying diagram depicts the equivalent circuit of the LCD. One additional consideration that must be taken into account is what happens when the microcontroller enters the Idle or Slow Mode. The LCDEN control bit in the LCDC register permits the display to be powered off to reduce power consumption. If this bit is zero, the driving signals to the display will cease, producing a blank display pattern but reducing any power consumption associated with the LCD. After Power-on, note that as the LCDEN bit will be cleared to zero, the display function will be disabled. LCD Panel Equivalent Circuit Rev. 1.10 165 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Configuration Option Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. All options must be defined for proper system function, the details of which are shown in the table. No. Options Oscillator Options 1 High Speed System Oscillator Selection – fH: 1. HXT 2. HIRC 2 HIRC Frequency Selection: 1. 4.9152MHz 2. 9.8304MHz 3. 14.7456MHz 3 Low Speed System Oscillator Selection – fSUB: 1. LXT 2. LIRC Watchdog Timer Options Rev. 1.10 4 WDT function: 1. Always enable 2. Controlled by WDT Control Register 5 WDT Clock Selection – fS: 1. fSUB 2. fSYS/4 166 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Application Circuit VDD/VIN VDD 0.1µF VREG VSS V�UT/AVDD 1µF (Ele�t�olyti� o� tantalum �apa�ito�) PB3/XT1 PB�/XT� AVSS VDD The�misto� LXT �SC PB�/�SC� AN� PB1/�SC1 AN� PB0 VREG 0.1µF VSS PB�/TP0_0/C1P Load �ell AN0 AN1 PB6/INT0/C0P VREG PB7/INT1/C0N �.�V 0.1µF 1V VREFP VREFN PF0/C1N C�M0/PC0~ C�M3/PC3 VCM 10µF PA0~PA7 PC�~PC7 PD0~PD7 PE0~PE7 0.1µF LCD Panel (�x�8) HT67F5640 Rev. 1.10 167 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.10 168 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction "RET" in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m]. i" instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the "HALT" instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.10 169 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 1.10 170 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Mnemonic Description Cycles Flag Affected Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Read table (specific page) to TBLH and Data Memory Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note 2Note None None None No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRD [m] TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the "CLR WDT1" and "CLR WDT2" instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both "CLR WDT1" and "CLR WDT2" instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.10 171 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Instruction Definition ADC A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C ADCM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC ADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C ADD A,x Description Operation Affected flag(s) Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C ADDM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C AND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z AND A,x Description Operation Affected flag(s) Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z ANDM A,[m] Description Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z Rev. 1.10 172 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU CALL addr Description Operation Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Affected flag(s) Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT1 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT2 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CPL [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z Rev. 1.10 173 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU CPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z DAA [m] Description Operation Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z HALT Description Operation Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Operation Affected flag(s) Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z Rev. 1.10 174 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU JMP addr Description Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Operation Affected flag(s) Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z OR A,x Description Operation Affected flag(s) Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z ORM A,[m] Description Operation Affected flag(s) Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z RET Description Operation Affected flag(s) Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None Rev. 1.10 175 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU RET A,x Description Operation Affected flag(s) Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None RETI Description Operation Affected flag(s) Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None RL [m] Description Operation Affected flag(s) Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None RLA [m] Description Operation Affected flag(s) Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None RLC [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C RLCA [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C RR [m] Description Operation Affected flag(s) Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None Rev. 1.10 176 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU RRA [m] Description Operation Affected flag(s) Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None RRC [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C RRCA [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C SBC A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C SBCM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C SDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None Rev. 1.10 177 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU SDZA [m] Description Operation Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Operation Affected flag(s) Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None SIZA [m] Description Operation Affected flag(s) Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None SNZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None SUB A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C Rev. 1.10 178 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C SUB A,x Description Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Operation Affected flag(s) Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SZ [m] Description Operation Affected flag(s) Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None SZA [m] Description Operation Affected flag(s) Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None SZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None Rev. 1.10 179 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU TABRD [m] Description Operation Affected flag(s) Read table (specific page) to TBLH and Data Memory The low byte of the program code addressed by the table pointer pair (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDC [m] Description Operation Affected flag(s) Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDL [m] Description Operation Affected flag(s) Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None XOR A,[m] Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z XORM A,[m] Description Operation Affected flag(s) Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z XOR A,x Description Operation Affected flag(s) Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z Rev. 1.10 180 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.10 181 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU 64-pin LQFP (7mm×7mm) Outline Dimensions Symbol Min. Nom. Max. A — 0.354 BSC — B — 0.276 BSC — C — 0.354 BSC — D — 0.276 BSC — E — 0.016 BSC — F 0.005 0.007 0.009 G 0.053 0.055 0.057 H — — 0.063 I 0.002 — 0.006 J 0.018 0.024 0.030 K 0.004 — 0.008 α 0° — 7° Symbol Rev. 1.10 Dimensions in inch Dimensions in mm Min. Nom. Max. A — 9.00 BSC — B — 7.00 BSC — C — 9.00 BSC — D — 7.00 BSC — E — 0.40 BSC — F 0.13 0.18 0.23 G 1.35 1.4 1.45 H — — 1.60 I 0.05 — 0.15 J 0.45 0.60 0.75 K 0.09 — 0.20 α 0° — 7° 182 October 15, 2014 HT67F5640 20-Bit Delta Sigma A/D + LCD Flash MCU Copyright© 2014 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 183 October 15, 2014