Enhanced Voice 8-Bit Flash MCU HT66FV130/HT66FV140 HT66FV150/HT66FV160 Revision: V1.20 Date: ������������� July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Table of Contents Features............................................................................................................ 7 CPU Features.......................................................................................................................... 7 Peripheral Features.................................................................................................................. 8 General Description.......................................................................................... 9 Selection Table.................................................................................................. 9 Block Diagram................................................................................................. 10 Pin Assignment............................................................................................... 10 Pin Descriptions............................................................................................. 14 Absolute Maximum Ratings........................................................................... 24 D.C. Characteristics........................................................................................ 25 A.C. Characteristics........................................................................................ 27 A/D Converter Characteristics....................................................................... 28 LVD/LVR Electrical Characteristics............................................................... 29 Audio D/A Converter Electrical Characteristics........................................... 30 Power Amplifier Electrical Characteristics................................................... 30 Power-on Reset Characteristics.................................................................... 30 System Architecture....................................................................................... 31 Clocking and Pipelining.......................................................................................................... 31 Program Counter.................................................................................................................... 32 Stack...................................................................................................................................... 33 Arithmetic and Logic Unit – ALU............................................................................................ 33 Flash Program Memory.................................................................................. 34 Structure................................................................................................................................. 34 Special Vectors...................................................................................................................... 34 Look-up Table......................................................................................................................... 35 Table Program Example......................................................................................................... 35 In Circuit Programming – ICP................................................................................................ 36 On-Chip Debug Support – OCDS.......................................................................................... 37 In Application Programming – IAP......................................................................................... 38 Data Memory................................................................................................... 49 Structure................................................................................................................................. 49 Data Memory Addressing....................................................................................................... 50 General Purpose Data Memory............................................................................................. 50 Special Purpose Data Memory.............................................................................................. 50 Rev. 1.20 2 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Special Function Register Description......................................................... 55 Indirect Addressing Registers – IAR0, IAR1, IAR2................................................................ 55 Memory Pointers – MP0, MP1H/MP1L, MP2H/MP2L............................................................ 55 Program Memory Bank Pointer – PBP................................................................................... 57 Accumulator – ACC................................................................................................................ 57 Program Counter Low Register – PCL................................................................................... 57 Look-up Table Registers – TBLP, TBHP, TBLH...................................................................... 57 Status Register – STATUS..................................................................................................... 58 EEPROM Data Memory................................................................................... 60 EEPROM Data Memory Structure......................................................................................... 60 EEPROM Registers............................................................................................................... 60 Reading Data from the EEPROM.......................................................................................... 62 Writing Data to the EEPROM................................................................................................. 63 Write Protection...................................................................................................................... 63 EEPROM Interrupt................................................................................................................. 63 Programming Considerations................................................................................................. 63 Oscillator......................................................................................................... 65 Oscillator Overview................................................................................................................ 65 System Clock Configurations................................................................................................. 65 External Crystal/Ceramic Oscillator – HXT............................................................................ 66 Internal High Speed RC Oscillator – HIRC............................................................................ 67 External 32.768 kHz Crystal Oscillator – LXT........................................................................ 67 Internal 32kHz Oscillator – LIRC............................................................................................ 69 Supplementary Oscillators..................................................................................................... 69 Operating Modes and System Clocks.......................................................... 69 System Clocks....................................................................................................................... 69 System Operation Modes....................................................................................................... 72 Control Registers................................................................................................................... 73 Operating Mode Switching..................................................................................................... 77 Standby Current Considerations............................................................................................ 81 Wake-up................................................................................................................................. 81 Watchdog Timer.............................................................................................. 82 Watchdog Timer Clock Source............................................................................................... 82 Watchdog Timer Control Register.......................................................................................... 82 Watchdog Timer Operation.................................................................................................... 83 Reset and Initialisation................................................................................... 85 Reset Functions..................................................................................................................... 85 Reset Initial Conditions.......................................................................................................... 89 Rev. 1.20 3 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Input/Output Ports.......................................................................................... 94 Pull-high Resistors................................................................................................................. 96 Port A Wake-up...................................................................................................................... 96 I/O Port Control Registers...................................................................................................... 96 I/O Port Source Current Control............................................................................................. 96 Pin-shared Functions............................................................................................................. 98 I/O Pin Structures................................................................................................................. 107 Programming Considerations............................................................................................... 108 Timer Modules – TM..................................................................................... 109 Introduction.......................................................................................................................... 109 TM Operation....................................................................................................................... 109 TM Clock Source.................................................................................................................. 109 TM Interrupts.........................................................................................................................110 TM External Pins...................................................................................................................110 TM Input/Output Pin Control Register...................................................................................111 Programming Considerations................................................................................................112 Compact Type TM – CTM..............................................................................113 Compact TM Operation.........................................................................................................113 Compact Type TM Register Description...............................................................................114 Compact Type TM Operation Modes....................................................................................118 Standard Type TM – STM............................................................................. 124 Standard TM Operation........................................................................................................ 124 Standard Type TM Register Description.............................................................................. 125 Standard Type TM Operation Modes................................................................................... 129 Periodic Type TM – PTM............................................................................... 139 Periodic TM Operation......................................................................................................... 139 Periodic Type TM Register Description................................................................................ 140 Periodic Type TM Operation Modes..................................................................................... 144 Analog to Digital Converter......................................................................... 153 A/D Overview....................................................................................................................... 153 A/D Converter Register Description..................................................................................... 154 A/D Operation...................................................................................................................... 159 A/D Reference Voltage......................................................................................................... 160 A/D Input Pins...................................................................................................................... 160 Conversion Rate and Timing Diagram................................................................................. 160 Summary of A/D Conversion Steps...................................................................................... 161 Programming Considerations............................................................................................... 162 A/D Transfer Function.......................................................................................................... 162 A/D Programming Examples................................................................................................ 163 Serial Interface Module – SIM...................................................................... 165 SPI Interface........................................................................................................................ 165 I2C Interface......................................................................................................................... 171 Rev. 1.20 4 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Serial Interface – SPIA.................................................................................. 181 SPIA Interface Operation..................................................................................................... 181 SPIA Registers..................................................................................................................... 182 SPIA Communication........................................................................................................... 184 SPIA Bus Enable/Disable..................................................................................................... 186 SPIA Operation.................................................................................................................... 187 Error Detection..................................................................................................................... 188 SCOM Function for LCD – HT66FV150/HT66FV160................................... 189 LCD Operation..................................................................................................................... 189 LCD Bias Control................................................................................................................. 189 Voice Playing Controller.............................................................................. 190 Voice Controller Registers.................................................................................................... 190 Interrupts....................................................................................................... 193 Interrupt Registers................................................................................................................ 193 Interrupt Operation............................................................................................................... 203 External Interrupt.................................................................................................................. 206 Multi-function Interrupt......................................................................................................... 206 A/D Converter Interrupt........................................................................................................ 206 Time Base Interrupt.............................................................................................................. 207 UART Transfer Interrupt – HT66FV150/HT66FV160........................................................... 208 Serial Interface Module Interrupt – HT66FV140/HT66FV150/HT66FV160.......................... 209 SPIA Interface Interrupt........................................................................................................ 209 LVD Interrupt........................................................................................................................ 209 EEPROM Interrupt............................................................................................................... 210 TM Interrupt.......................................................................................................................... 210 Interrupt Wake-up Function.................................................................................................. 210 Programming Considerations................................................................................................211 Low Voltage Detector – LVD........................................................................ 212 LVD Register........................................................................................................................ 212 LVD Operation...................................................................................................................... 213 UART Interface – HT66FV150/HT66FV160.................................................. 214 UART External Pin............................................................................................................... 215 UART Data Transfer Scheme.............................................................................................. 215 UART Status and Control Registers.................................................................................... 215 Baud Rate Generator........................................................................................................... 220 UART Setup and Control..................................................................................................... 221 UART Transmitter................................................................................................................ 223 UART Receiver.................................................................................................................... 224 Managing Receiver Errors................................................................................................... 225 UART Interrupt Structure..................................................................................................... 226 UART Power Down and Wake-up........................................................................................ 228 Rev. 1.20 5 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Application Circuits...................................................................................... 229 Digital Volume Control Application Circuit (5V).................................................................... 229 Digital Volume Control Application Circuit (3V).................................................................... 230 Variable Resistor (VR) Volume Control Application Circuit (5V)........................................... 231 Variable Resistor (VR) Volume Control Application Circuit (3V)........................................... 232 Instruction Set............................................................................................... 233 Introduction.......................................................................................................................... 233 Instruction Timing................................................................................................................. 233 Moving and Transferring Data.............................................................................................. 233 Arithmetic Operations........................................................................................................... 233 Logical and Rotate Operation.............................................................................................. 234 Branches and Control Transfer............................................................................................ 234 Bit Operations...................................................................................................................... 234 Table Read Operations........................................................................................................ 234 Other Operations.................................................................................................................. 234 Instruction Set Summary............................................................................. 235 Table Conventions................................................................................................................ 235 Extended Instruction Set...................................................................................................... 237 Instruction Definition.................................................................................... 239 Extended Instruction Definition............................................................................................ 248 Package Information.................................................................................... 255 20-pin SOP (300mil) Outline Dimensions............................................................................ 256 24-pin SOP(300mil) Outline Dimensions............................................................................. 257 28-pin SOP(300mil) Outline Dimensions............................................................................. 258 44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions............................................ 259 Rev. 1.20 6 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Features CPU Features • Operating voltage ♦♦ fSYS= 8MHz: 2.2V~5.5V ♦♦ fSYS=12MHz: 2.7V~5.5V ♦♦ fSYS=16MHz: 3.6V~5.5V ♦♦ fSYS=20MHz: 4.5V~5.5V • Up to 0.2μs instruction cycle with 20MHz system clock at VDD=5V • Power down and wake-up functions to reduce power consumption • Oscillator type ♦♦ External High Speed Crystal – HXT ♦♦ Internal High Speed RC – HIRC ♦♦ External 32.768kHz Crystal – LXT (available in HT66FV140/HT66FV150/HT66FV160) ♦♦ Internal 32kHz RC – LIRC • Fully integrated internal 8/12/16 MHz oscillator requires no external components • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • All instructions executed in one to three instruction cycles • Table read instructions • 115 powerful instructions • Up to 8-level subroutine nesting • Bit manipulation instruction Rev. 1.20 7 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Peripheral Features • Program Memory: Up to 16K x 16 • Data Memory: Up to 1024 x 8 • EEPROM Memory: Up to 256 x 8 • Watchdog Timer function • Up to 35 bidirectional I/O lines • Two external interrupt lines shared with I/O pins • Multiple Timer Modules for time measure, input capture, compare match output, PWM output function or single pulse output function • Serial Interfaces Module – SIM for SPI or I2C (available in HT66FV140/HT66FV150/HT66FV160) • Serial Peripheral Interface – SPIA • Software controlled 4-SCOM lines LCD driver with 1/2 bias (available in HT66FV150/ HT66FV160) • Fully-duplex Universal Asynchronous Receiver and Transmitter Interface – UART (available in HT66FV150/HT66FV160) • Dual Time-Base functions for generation of fixed time interrupt signals • 8-channel 12-bit resolution A/D converter • In Application Programming function – IAP • Class AB power amplifier for speaker driving • High performance 16-bit audio D/A converter • Digital volume control for audio playback function • Low voltage reset function • Low voltage detect function • Flash program memory can be re-programmed up to 100,000 times • Flash program memory data retention > 10 years • EEPROM data memory can be re-programmed up to 1,000,000 times • EEPROM data memory data retention > 10 years • Wide range fo available package types Rev. 1.20 8 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU General Description The series of devices are Flash Memory A/D type 8-bit high performance RISC architecture microcontroller which is designed for voice playing product applications. Each device integrates a 16-bit DAC and a Power Amplifier. For the D/A Converter, the device has a digital programmable volume control with a wide range. Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM generation functions. Communication with the outside world is catered for by including fully integrated SPI or I2C interface functions, two popular interfaces which provide designers with a means of easy communication with external peripheral hardware. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of HXT, HIRC, LXT and LIRC oscillator functions are provided including a fully integrated system oscillator. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. Selection Table Most features are common to all devices. The main features distinguishing them are Memory capacity, I/O count, A/D converter inputs, Timer Module features, SIM, LXT, SCOM, UART and package types. The following table summarises the main features of each device. Part No. Program Data Data I/O Memory Memory EEPROM External Interrupt A/D Timer Module Time SPIA SIM LXT UART SCOM D/A Base 10-bit CTMx1 10-bit PTMx1 2 √ — — — — Power Amplifier Stacks Package √ √ 4 20/24 SOP HT66FV130 2Kx16 128x8 32x8 15 2 12-bit x4 HT66FV140 4Kx16 256x8 64x8 19 2 12-bit x8 10-bit CTMx1 10-bit PTMx2 2 √ √ √ — — √ √ 8 20/24/28 SOP HT66FV150 8Kx16 512x8 128x8 27 2 12-bit x8 10-bit CTMx2 10-bit PTMx2 2 √ √ √ √ √ √ √ 8 28SOP 44LQFP HT66FV160 16Kx16 1024x8 256x8 35 2 12-bit x8 10-bit CTMx2 10-bit PTMx2 16-bit STMx1 2 √ √ √ √ √ √ √ 8 44LQFP Note: As devices exist in more than one package format, the table reflects the situation for the package with the most pins. Rev. 1.20 9 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Block Diagram F�ash/EEPROM Programming Circ�itr� EEPROM Data Memor� Low Vo�tage Detect F�ash Program Memor� 8-bit RISC MCU Core Low Vo�tage Reset RAM Data Memor� IAP Reset Circ�it Interna� HIRC/LIRC Osci��ators Watchdog Timer Interr�pt Contro��er Externa� HXT Osci��ator Externa� LXT Osci��ator Time Bases For HT66FV140/1�0/160 12-bit A/D Converter I/O Timer Mod��es SPIA SIM (SPI/I2C) Digita� Vo��me Contro� UART 16-bit D/A Converter SCOM Power Amp�ifier For HT66FV1�0/160 For HT66FV140/1�0/160 Pin Assignment PA1/PTP0I/PTP0/AN2 1 20 VSS PC0/VREFI/AN0 PC4/SDOA 2 19 3 18 VDD BIAS PC�/SCKA 4 17 AUD PC6/SDIA � 16 AUD_IN PC7/SCSA 6 1� SP+ PB0/VDDIO 7 14 AVDD_PA PA2/PTCK0/ICPCK/OCDSCK 8 9 13 12 SP- 10 11 PB2/INT0/OSC2 PA0/PTP0I/PTP0/ICPDA/OCDSDA PB1/OSC1 AVSS_PA HT66FV130/HT66VV130 20 SOP-A PA1/PTP0I/PTP0/AN2 1 24 PA6/INT1/CTP0/AN6 PC0/VREFI/AN0 PC1/VREF 2 23 PA7/CTCK0/AN7 3 22 VSS PC2 4 21 VDD PC4/SDOA � 20 BIAS PC�/SCKA 6 19 AUD PC6/SDIA 7 18 AUD_IN PC7/SCSA 8 9 SP+ PA2/PTCK0/ICPCK/OCDSCK 10 17 16 1� PA0/PTP0I/PTP0/ICPDA/OCDSDA 11 14 SP- PB1/OSC1 12 13 PB2/INT0/OSC2 PB0/VDDIO AVDD_PA AVSS_PA HT66FV130/HT66VV130 24 SOP-A Rev. 1.20 10 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU PA1/PTP0I/PTP0/AN2 1 20 VSS PC0/SDO/VREFI/AN0 PC4/SDOA 2 19 3 18 VDD BIAS PC�/SCKA 4 17 AUD PC6/SDIA � 16 AUD_IN PC7/SCSA 6 1� SP+ PB0/VDDIO 7 14 AVDD_PA PA2/PTCK0/ICPCK/OCDSCK 8 9 13 12 11 SP- PA0/PTP0I/PTP0/ICPDA/OCDSDA PB1/PTCK1/OSC1 10 AVSS_PA PB2/INT0/OSC2 HT66FV140/HT66VV140 20 SOP-A PA1/PTP0I/PTP0/AN2 1 24 PA6/INT1/CTP0/AN6/XT2 PC0/SDO/VREFI/AN0 PC1/SCK/SCL/AN1/VREF 2 3 23 22 VSS PC2/SDI/SDA 4 21 VDD PC4/SDOA � 20 BIAS PC�/SCKA 6 19 AUD PC6/SDIA 7 18 AUD_IN PC7/SCSA 8 9 17 16 SP+ PA2/PTCK0/ICPCK/OCDSCK 10 1� AVSS_PA PA0/PTP0I/PTP0/ICPDA/OCDSDA 11 14 SP- PB1/PTCK1/OSC1 12 13 PB2/INT0/OSC2 PB0/VDDIO PA7/CTCK0/AN7/XT1 AVDD_PA HT66FV140/HT66VV140 24 SOP-A PA1/PTP0I/PTP0/AN2 1 28 PC0/SDO/VREFI/AN0 2 27 PA4/PTP1I//PTP1AN4 3 26 PA�/CTP0/AN� PA6/INT1/CTP0/AN6/XT2 PA7/CTCK0/AN7/XT1 PA3/PTP1I/PTP1/AN3 4 2� VSS PC1/SCK/SCL/AN1/VREF � 24 VDD PC2/SDI/SDA 6 23 BIAS PC3/SCS 7 22 AUD PC4/SDOA PC6/SDIA 10 21 20 19 AUD_IN PC�/SCKA 8 9 PC7/SCSA 11 18 AVSS_PA PB0/VDDIO PA2/PTCK0/ICPCK/OCDSCK 12 17 13 16 SPPB2/INT0/OSC2 PA0/PTP0I/PTP0/ICPDA/OCDSDA 14 1� PB1/PTCK1/OSC1 SP+ AVDD_PA HT66FV140/HT66VV140 28 SOP-A Rev. 1.20 11 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU PA1/PTP0I/PTP0/AN2 1 28 PA�/CTP0/AN� PC0/SDO/VREFI/AN0 2 27 PA4/PTP1I/PTP1/AN4 3 26 PA6/INT1/CTP0/AN6/XT2 PA7/CTCK0/AN7/XT1 PA3/PTP1I/PTP1/AN3 4 2� VSS PC1/SCK/SCL/AN1/VREF � 24 VDD PC2/SDI/SDA/RX 6 23 BIAS PC3/SCS/TX 7 22 AUD PC4/SDOA 21 20 AUD_IN PC�/SCKA 8 9 PC6/SDIA 10 19 AVDD_PA PC7/SCSA 11 18 AVSS_PA PB0/VDDIO PA2/PTCK0/ICPCK/OCDSCK 12 17 13 16 SPPB2/INT0/OSC2 PA0/PTP0I/PTP0/ICPDA/OCDSDA 14 1� PB1/PTCK1/OSC1 SP+ HT66FV150/HT66VV150 28 SOP-A NC NC NC NC PE3/CTP1 PE2/CTCK1 PE1/RX PE0/TX PA1/PTP0I/PTP0/AN2 PC0/SDO/VREFI/AN0 PA4/PTP1I/PTP1/AN4 PA3/PTP1I/PTP1/AN3 PC1/SCK/SCL/AN1/VREF PC2/SDI/SDA/RX PC3/SCS/TX PC4/SDOA PC�/SCKA PC6/SDIA PC7/SCSA PB0/VDDIO PA2/PTCK0/ICPCK/OCDSCK PA0/PTP0I/PTP0/ICPDA/OCDSDA 44 43 42 41 40 39 38 37 36 3� 34 1 33 2 32 3 31 4 30 � 29 HT66FV150/HT66VV150 6 28 44 LQFP-A 7 27 8 26 9 2� 10 24 11 23 12 13 14 1� 16 17 18 19 20 21 22 PA�/CTP0/AN� PA6/INT1/CTP0/AN6/XT2 PA7/CTCK0/AN7/XT1 VSS VDD BIAS AUD AUD_IN SP+ AVDD_PA AVSS_PA SPPB2/INT0/OSC2 PB1/PTCK1/OSC1 PD0/SCOM0 PD1/SCOM1 PD2/SCOM2 PD3/SCOM3 NC NC NC NC Rev. 1.20 12 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU PE7 PE6/STP0I/STP0 PE�/STP0I/STP0 PE4/STCK0 PE3/CTP1 PE2/CTCK1 PE1/RX PE0/TX PA1/PTP0I/PTP0/AN2 PC0/SDO/VREFI/AN0 PA4/PTP1I/PTP1/AN4 PA3/PTP1I/PTP1/AN3 PC1/SCK/SCL/AN1/VREF PC2/SDI/SDA/RX PC3/SCS/TX PC4/SDOA PC�/SCKA PC6/SDIA PC7/SCSA PB0/VDDIO PA2/PTCK0/ICPCK/OCDSCK PA0/PTP0I/PTP0/ICPDA/OCDSDA 44 43 42 41 40 39 38 37 36 3� 34 1 33 2 32 3 31 4 30 � HT66FV160/HT66VV160 29 6 28 44 LQFP-A 7 27 8 26 9 2� 10 24 11 23 12 13 14 1� 16 17 18 19 20 21 22 PA�/CTP0/AN� PA6/INT1/CTP0/AN6/XT2 PA7/CTCK0/AN7/XT1 VSS VDD BIAS AUD AUD_IN SP+ AVDD_PA AVSS_PA SPPB2/INT0/OSC2 PB1/PTCK1/OSC1 PD0/SCOM0 PD1/SCOM1 PD2/SCOM2 PD3/SCOM3 PD4 PD� PD6 PD7 Note: The OCDSDA and OCDSCK pins are the OCDS dedicated pins and only available for the HT66VV1x0 device which is the OCDS EV chip for the HT66FV1x0 device. Rev. 1.20 13 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Pin Descriptions With the exception of the power pins and some relevant transformer control pins, all pins on these devices can be referenced by their Port name, e.g. PA.0, PA.1 etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Analog to Digital Converter, Timer Module pins etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. HT66FV130 Pad Name PA0/PTP0I/ PTP0/ICPDA/ OCDSDA PA1/PTP0I/ PTP0/AN2 PA2/PTCK0/ ICPCK/OCDSCK PA6/INT1/ CTP0/AN6 Function OPT I/T O/T PA0 PAWU PAPU PAS0 ST CMOS PTP0I PAS0 IFS ST — PTP0 PAS0 — CMOS PTM0 output ICPDA — ST CMOS ICP Data/Address pin OCDSDA — ST CMOS OCDS Data/Address pin, for EV chip only. PA1 PAWU PAPU PAS0 ST CMOS PTP0I PAS0 IFS ST — PB1/OSC1 Rev. 1.20 General purpose I/O. Register enabled pull-up and wake-up. PTM0 capture input General purpose I/O. Register enabled pull-up and wake-up. PTM0 capture input PTP0 PAS0 — AN2 PAS0 AN — PA2 PAWU PAPU PAS0 ST CMOS PTCK0 — ST ICPCK — ST OCDSCK — ST — PA6 PAWU PAPU PAS1 ST CMOS INT1 PAS1 INTEG INTC2 ST — CTP0 PAS1 — AN6 PAS1 AN — PA7 PAWU PAPU PAS1 ST CMOS CTCK0 PAS1 ST — CTM0 clock input AN7 PAS1 AN — A/D Converter analog input PB0 PBPU PBS0 ST VDDIO PBS0 PWR PB1 PBPU PBS0 ST OSC1 PBS0 HXT PA7/CTCK0/AN7 PB0/VDDIO Description CMOS PTM0 output — A/D Converter analog input General purpose I/O. Register enabled pull-up and wake-up. PTM0 clock input CMOS ICP Clock pin OCDS Clock pin, for EV chip only. General purpose I/O. Register enabled pull-up and wake-up. External Interrupt 1 CMOS CTM0 output A/D Converter analog input General purpose I/O. Register enabled pull-up and wake-up. CMOS General purpose I/O. Register enabled pull-up. — PC0~PC7 I/O power for level shift CMOS General purpose I/O. Register enabled pull-up. — 14 HXT oscillator pin July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Pad Name Function OPT I/T PB2 PBPU PBS0 ST INT0 PBS0 INTEG INTC0 ST — OSC2 PBS0 — HXT PC0 PCPU PCS0 ST VREFI PCS0 AN — A/D Converter reference voltage input AN0 PCS0 AN — A/D Converter analog input PC1 PCPU PCS0 ST VREF PCS0 — PC2 PCPU PCS0 ST CMOS General purpose I/O. Register enabled pull-up. PC4 PCPU PCS1 ST CMOS General purpose I/O. Register enabled pull-up. SDOA PCS1 — CMOS SPIA data output PC5 PCPU PCS1 ST CMOS General purpose I/O. Register enabled pull-up. SCKA PCS1 ST CMOS SPIA serial clock PC6 PCPU PCS1 ST CMOS General purpose I/O. Register enabled pull-up. SDIA PCS1 ST PC7 PCPU PCS1 ST CMOS General purpose I/O. Register enabled pull-up. SCSA PCS1 ST CMOS SPIA slave select VDD VDD — PWR VSS VSS — SP+ SP+ — PB2/INT0/OSC2 PC0/VREFI/AN0 PC1/VREF PC2 PC4/SDOA PC5/SCKA PC6/SDIA PC7/SCSA SPAUD_IN O/T Description CMOS General purpose I/O. Register enabled pull-up. External Interrupt 0 HXT oscillator pin CMOS General purpose I/O. Register enabled pull-up. CMOS General purpose I/O. Register enabled pull-up. AN — A/D Converter reference voltage output SPIA data input — Positive power supply PWR — Negative power supply, ground. — AO Power amplifier output SP- — — AO Power amplifier output AUD_IN — AN — Power amplifier input BIAS BIAS — — AO Power amplifier voltage bias reference AUD AUD — — AO D/A converter output AVDD_PA AVDD_PA — PWR — Audio Power Amplifier positive power supply AVSS_PA AVSS_PA — PWR — Audio Power Amplifier negative power supply Rev. 1.20 15 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU HT66FV140 Pad Name PA0/PTP0I/ PTP0/ICPDA/ OCDSDA PA1/PTP0I/ PTP0/AN2 PA2/PTCK0/ ICPCK/OCDSCK PA3/PTP1I/ PTP1/AN3 PA4/PTP1I/ PTP1/AN4 Function OPT I/T O/T PA0 PAWU PAPU PAS0 ST CMOS PTP0I PAS0 IFS ST — PTP0 PAS0 — CMOS PTM0 output ICPDA — ST CMOS ICP Data/Address pin OCDSDA — ST CMOS OCDS Data/Address pin, for EV chip only. PA1 PAWU PAPU PAS0 ST CMOS PTP0I PAS0 IFS ST — PTP0 PAS0 — AN2 PAS0 AN — PA2 PAWU PAPU PAS0 ST CMOS PTCK0 — ST ICPCK — ST OCDSCK — ST — PA3 PAWU PAPU PAS0 ST CMOS PTP1I PAS0 IFS ST — PTP1 PAS0 — AN3 PAS0 AN — PA4 PAWU PAPU PAS1 ST CMOS PTP1I PAS1 IFS ST — Rev. 1.20 General purpose I/O. Register enabled pull-up and wake-up. PTM0 capture input General purpose I/O. Register enabled pull-up and wake-up. PTM0 capture input CMOS PTM0 output — A/D Converter analog input General purpose I/O. Register enabled pull-up and wake-up. PTM0 clock input CMOS ICP Clock pin OCDS Clock pin, for EV chip only. General purpose I/O. Register enabled pull-up and wake-up. PTM1 capture input CMOS PTM1 output A/D Converter analog input General purpose I/O. Register enabled pull-up and wake-up. PTM1 capture input PTP1 PAS1 — AN4 PAS1 AN — PA5 PAWU PAPU PAS1 ST CMOS CTP0 PAS1 — CMOS CTM0 output AN5 PAS1 AN — PA6 PAWU PAPU PAS1 ST CMOS INT1 PAS1 INTEG INTC2 ST — CTP0 PAS1 — AN6 PAS1 AN — XT2 PAS1 — LXT PA5/CTP0/AN5 PA6/INT1/ CTP0/AN6/XT2 Description CMOS PTM1 output A/D Converter analog input General purpose I/O. Register enabled pull-up and wake-up. A/D Converter analog input General purpose I/O. Register enabled pull-up and wake-up. External Interrupt 1 CMOS CTM0 output 16 A/D Converter analog input LXT oscillator pin July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Pad Name PA7/CTCK0/ AN7/XT1 PB0/VDDIO PB1/PTCK1/OSC1 PB2/INT0/OSC2 PC0/SDO/ VREFI/AN0 PC1/SCK/SCL/ AN1/VREF PC2/SDI/SDA PC3/SCS PC4/SDOA PC5/SCKA PC6/SDIA PC7/SCSA Rev. 1.20 Function OPT I/T O/T PA7 PAWU PAPU PAS1 Description ST CMOS CTCK0 PAS1 ST — CTM0 clock input General purpose I/O. Register enabled pull-up and wake-up. AN7 PAS1 AN — A/D Converter analog input XT1 PAS1 LXT — LXT oscillator pin PB0 PBPU PBS0 ST VDDIO PBS0 PWR PB1 PBPU PBS0 ST PTCK1 PBS0 ST — PTM1 clock input OSC1 PBS0 HXT — HXT oscillator pin PB2 PBPU PBS0 ST INT0 PBS0 INTEG INTC0 ST — OSC2 PBS0 — HXT PC0 PCPU PCS0 ST CMOS General purpose I/O. Register enabled pull-up. SDO PCS0 — CMOS SPI data output CMOS General purpose I/O. Register enabled pull-up. — PC0~PC7 I/O power for level shift CMOS General purpose I/O. Register enabled pull-up. CMOS General purpose I/O. Register enabled pull-up. External Interrupt 0 HXT oscillator pin VREFI PCS0 AN — A/D Converter reference voltage input AN0 PCS0 AN — A/D Converter analog input PC1 PCPU PCS0 ST CMOS General purpose I/O. Register enabled pull-up. SCK PCS0 ST CMOS SPI serial clock SCL PCS0 ST NMOS I2C clock line AN1 PCS0 AN — A/D Converter analog input VREF PCS0 — AN A/D Converter reference voltage output PC2 PCPU PCS0 ST SDI PCS0 ST SDA PCS0 ST NMOS I2C data line PC3 PCPU PCS0 ST CMOS General purpose I/O. Register enabled pull-up. SCS PCS0 ST CMOS SPI slave select PC4 PCPU PCS1 ST CMOS General purpose I/O. Register enabled pull-up. SDOA PCS1 — CMOS SPIA data output PC5 PCPU PCS1 ST CMOS General purpose I/O. Register enabled pull-up. SCKA PCS1 ST CMOS SPIA serial clock PC6 PCPU PCS1 ST CMOS General purpose I/O. Register enabled pull-up. SDIA PCS1 ST PC7 PCPU PCS1 ST CMOS General purpose I/O. Register enabled pull-up. SCSA PCS1 ST CMOS SPIA slave select CMOS General purpose I/O. Register enabled pull-up. — — 17 SPI data input SPIA data input July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Function OPT I/T O/T VDD Pad Name VDD — PWR — Positive power supply VSS VSS — PWR — Negative power supply, ground. SP+ SP+ — — AO Power amplifier output SP- SP- — — AO Power amplifier output AUD_IN — AN — Power amplifier input BIAS — — AO Power amplifier voltage bias reference AUD_IN BIAS Description AUD — — AO D/A converter output AVDD_PA AVDD_PA — PWR — Audio Power Amplifier positive power supply AVSS_PA AVSS_PA — PWR — Audio Power Amplifier negative power supply Function OPT I/T O/T PA0 PAWU PAPU PAS0 ST CMOS PTP0I PAS0 IFS ST — PTP0 PAS0 — CMOS PTM0 output AUD HT66FV150 Pad Name PA0/PTP0I/ PTP0/ICPDA/ OCDSDA PA1/PTP0I/ PTP0/AN2 PA2/PTCK0/ ICPCK/OCDSCK PA3/PTP1I/ PTP1/AN3 PA4/PTP1I/ PTP1/AN4 Rev. 1.20 Description General purpose I/O. Register enabled pull-up and wake-up. PTM0 capture input ICPDA — ST CMOS ICP Data/Address pin OCDSDA — ST CMOS OCDS Data/Address pin, for EV chip only. PA1 PAWU PAPU PAS0 ST CMOS PTP0I PAS0 IFS ST — PTP0 PAS0 — AN2 PAS0 AN — PA2 PAWU PAPU PAS0 ST CMOS PTCK0 — ST — ICPCK — ST OCDSCK — ST — PA3 PAWU PAPU PAS0 ST CMOS PTP1I PAS0 IFS ST — General purpose I/O. Register enabled pull-up and wake-up. PTM0 capture input CMOS PTM0 output A/D Converter analog input General purpose I/O. Register enabled pull-up and wake-up. PTM0 clock input CMOS ICP Clock pin PTP1 PAS0 — AN3 PAS0 AN — PA4 PAWU PAPU PAS1 ST CMOS PTP1I PAS1 IFS ST — PTP1 PAS1 — AN4 PAS1 AN OCDS Clock pin, for EV chip only. General purpose I/O. Register enabled pull-up and wake-up. PTM1 capture input CMOS PTM1 output A/D Converter analog input General purpose I/O. Register enabled pull-up and wake-up. PTM1 capture input CMOS PTM1 output — 18 A/D Converter analog input July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Pad Name Function OPT I/T O/T PA5 PAWU PAPU PAS1 ST CMOS CTP0 PAS1 — CMOS CTM0 output AN5 PAS1 AN — PA6 PAWU PAPU PAS1 ST CMOS INT1 PAS1 INTEG INTC2 ST — CTP0 PAS1 — AN6 PAS1 AN — XT2 PAS1 — LXT PA7 PAWU PAPU PAS1 ST CMOS PA5/CTP0/AN5 PA6/INT1/CTP0/ AN6/XT2 PA7/CTCK0/ AN7/XT1 PB0/VDDIO PB1/PTCK1/OSC1 PB2/INT0/OSC2 PC0/SDO/ VREFI/AN0 PC1/SCK/SCL/ AN1/VREF Rev. 1.20 Description General purpose I/O. Register enabled pull-up and wake-up. A/D Converter analog input General purpose I/O. Register enabled pull-up and wake-up. External Interrupt 1 CMOS CTM0 output A/D Converter analog input LXT oscillator pin General purpose I/O. Register enabled pull-up and wake-up. CTCK0 PAS1 ST — CTM clock input AN7 PAS1 AN — A/D Converter analog input XT1 PAS1 LXT — LXT oscillator pin PB0 PBPU PBS0 ST VDDIO PBS0 PWR PB1 PBPU PBS0 ST PTCK1 PBS0 ST — PTM1 clock input OSC1 PBS0 HXT — HXT oscillator pin PB2 PBPU PBS0 ST INT0 PBS0 INTEG INTC0 ST — OSC2 PBS0 — HXT PC0 PCPU PCS0 ST CMOS General purpose I/O. Register enabled pull-up. SDO PCS0 — CMOS SPI data output VREFI PCS0 AN — A/D Converter reference voltage input AN0 PCS0 AN — A/D Converter analog input PC1 PCPU PCS0 ST CMOS General purpose I/O. Register enabled pull-up. — PC0~PC7 I/O power for level shift CMOS General purpose I/O. Register enabled pull-up. CMOS General purpose I/O. Register enabled pull-up. External Interrupt 0 HXT oscillator pin CMOS General purpose I/O. Register enabled pull-up. SCK PCS0 ST CMOS SPI serial clock SCL PCS0 ST NMOS I2C clock line AN1 PCS0 AN — A/D Converter analog input VREF PCS0 — AN A/D Converter reference voltage output 19 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Pad Name PC2/SDI/SDA/RX PC3/SCS/TX PC4/SDOA PC5/SCKA PC6/SDIA PC7/SCSA PD0/SCOM0 PD1/SCOM1 PD2/SCOM2 PD3/SCOM3 PE0/TX Function OPT I/T PC2 PCPU PCS0 ST SDI PCS0 ST SDA PCS0 ST RX PCS0 IFS ST PC3 PCPU PCS0 ST CMOS General purpose I/O. Register enabled pull-up. SCS PCS0 ST CMOS SPI slave select TX PCS0 — CMOS UART TX serial data output PC4 PCPU PCS1 ST CMOS General purpose I/O. Register enabled pull-up. SDOA PCS1 — CMOS SPIA data output PC5 PCPU PCS1 ST CMOS General purpose I/O. Register enabled pull-up. SCKA PCS1 ST CMOS SPIA serial clock PC6 PCPU PCS1 ST CMOS General purpose I/O. Register enabled pull-up. SDIA PCS1 ST PC7 PCPU PCS1 ST CMOS General purpose I/O. Register enabled pull-up. SCSA PCS1 ST CMOS SPIA slave select PD0 PDPU PDS0 ST CMOS General purpose I/O. Register enabled pull-up. SCOM0 PDS0 — SCOM LCD common output PD1 PDPU PDS0 ST CMOS General purpose I/O. Register enabled pull-up. SCOM1 PDS0 — SCOM LCD common output PD2 PDPU PDS0 ST CMOS General purpose I/O. Register enabled pull-up. SCOM2 PDS0 — SCOM LCD common output PD3 PDPU PDS0 ST CMOS General purpose I/O. Register enabled pull-up. SCOM3 PDS0 — SCOM LCD common output PE0 PEPU PES0 ST CMOS General purpose I/O. Register enabled pull-up. TX PES0 — CMOS UART TX serial data output PE1 PEPU PES0 ST CMOS General purpose I/O. Register enabled pull-up. RX PES0 IFS ST PE2 PEPU PES0 ST CTCK1 PES0 ST PE3 PEPU PES0 ST CMOS General purpose I/O. Register enabled pull-up. CMOS CTM1 output PE1/RX PE2/CTCK1 PE3/CTP1 O/T Description CMOS General purpose I/O. Register enabled pull-up. — SPI data input NMOS I2C data line — — — UART RX serial data input SPIA data input UART RX serial data input CMOS General purpose I/O. Register enabled pull-up. — CTM1 clock input CTP1 PES0 — VDD VDD — PWR — Positive power supply VSS VSS — PWR — Negative power supply, ground. Rev. 1.20 20 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Function OPT I/T O/T SP+ Pad Name SP+ — — AO Power amplifier output SP- SP- — — AO Power amplifier output AUD_IN — AN — Power amplifier input BIAS — — AO Power amplifier voltage bias reference AUD_IN BIAS Description AUD — — AO D/A converter output AVDD_PA AVDD_PA — PWR — Audio Power Amplifier positive power supply AVSS_PA AVSS_PA — PWR — Audio Power Amplifier negative power supply NC — — — Not connected Function OPT I/T O/T PA0 PAWU PAPU PAS0 ST CMOS PTP0I PAS0 IFS ST — PTP0 PAS0 — CMOS PTM0 output ICPDA — ST CMOS ICP Data/Address pin OCDSDA — ST CMOS OCDS Data/Address pin, for EV chip only. PA1 PAWU PAPU PAS0 ST CMOS PTP0I PAS0 IFS ST — AUD NC HT66FV160 Pad Name PA0/PTP0I/ PTP0/ICPDA/ OCDSDA PA1/PTP0I/ PTP0/AN2 PA2/PTCK0/ ICPCK/OCDSCK PA3/PTP1I/ PTP1/AN3 PA4/PTP1I/ PTP1/AN4 Rev. 1.20 PTP0 PAS0 — AN2 PAS0 AN — PA2 PAWU PAPU PAS0 ST CMOS PTCK0 — ST ICPCK — ST OCDSCK — ST — PA3 PAWU PAPU PAS0 ST CMOS PTP1I PAS0 IFS ST — PTP1 PAS0 — AN3 PAS0 AN — PA4 PAWU PAPU PAS1 ST CMOS PTP1I PAS1 IFS ST — PTP1 PAS1 — AN4 PAS1 AN Description General purpose I/O. Register enabled pull-up and wake-up. PTM0 capture input General purpose I/O. Register enabled pull-up and wake-up. PTM0 capture input CMOS PTM0 output — A/D Converter analog input General purpose I/O. Register enabled pull-up and wake-up. PTM0 clock input CMOS ICP Clock pin OCDS Clock pin, for EV chip only. General purpose I/O. Register enabled pull-up and wake-up. PTM1 capture input CMOS PTM1 output A/D Converter analog input General purpose I/O. Register enabled pull-up and wake-up. PTM1 capture input CMOS PTM1 output — 21 A/D Converter analog input July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Pad Name Function OPT I/T O/T PA5 PAWU PAPU PAS1 ST CMOS CTP0 PAS1 — CMOS CTM0 output AN5 PAS1 AN — PA6 PAWU PAPU PAS1 ST CMOS INT1 PAS1 INTEG INTC2 ST — CTP0 PAS1 — AN6 PAS1 AN — XT2 PAS1 — LXT PA7 PAWU PAPU PAS1 ST CMOS PA5/CTP0/AN5 PA6/INT1/CTP0/ AN6/XT2 PA7/CTCK0/ AN7/XT1 PB0/VDDIO PB1/PTCK1/OSC1 PB2/INT0/OSC2 PC0/SDO/ VREFI/AN0 PC1/SCK/SCL/ AN1/VREF Rev. 1.20 Description General purpose I/O. Register enabled pull-up and wake-up. A/D Converter analog input General purpose I/O. Register enabled pull-up and wake-up. External Interrupt 1 CMOS CTM0 output A/D Converter analog input LXT oscillator pin General purpose I/O. Register enabled pull-up and wake-up. CTCK0 PAS1 ST — CTM0 clock input AN7 PAS1 AN — A/D Converter analog input XT1 PAS1 LXT — LXT oscillator pin PB0 PBPU PBS0 ST VDDIO PBS0 PWR PB1 PBPU PBS0 ST PTCK1 PBS0 ST — PTM1 clock input OSC1 PBS0 HXT — HXT oscillator pin PB2 PBPU PBS0 ST INT0 PBS0 INTEG INTC0 ST — OSC2 PBS0 — HXT PC0 PCPU PCS0 ST CMOS General purpose I/O. Register enabled pull-up. SDO PCS0 — CMOS SPI data output VREFI PCS0 AN — A/D Converter reference voltage input AN0 PCS0 AN — A/D Converter analog input PC1 PCPU PCS0 ST CMOS General purpose I/O. Register enabled pull-up. — PC0~PC7 I/O power for level shift CMOS General purpose I/O. Register enabled pull-up. CMOS General purpose I/O. Register enabled pull-up. External Interrupt 0 HXT oscillator pin CMOS General purpose I/O. Register enabled pull-up. SCK PCS0 ST CMOS SPI serial clock SCL PCS0 ST NMOS I2C clock line AN1 PCS0 AN — A/D Converter analog input VREF PCS0 — AN A/D Converter reference voltage output 22 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Pad Name PC2/SDI/SDA/RX PC3/SCS/TX PC4/SDOA PC5/SCKA PC6/SDIA PC7/SCSA PD0/SCOM0 PD1/SCOM1 PD2/SCOM2 PD3/SCOM3 PD4~PD7 PE0/TX Function OPT I/T PC2 PCPU PCS0 ST SDI PCS0 ST SDA PCS0 ST RX PCS0 IFS ST PC3 PCPU PCS0 ST CMOS General purpose I/O. Register enabled pull-up. SCS PCS0 ST CMOS SPI slave select TX PCS0 — CMOS UART TX serial data output PC4 PCPU PCS1 ST CMOS General purpose I/O. Register enabled pull-up. SDOA PCS1 — CMOS SPIA data output PC5 PCPU PCS1 ST CMOS General purpose I/O. Register enabled pull-up. SCKA PCS1 ST CMOS SPIA serial clock PC6 PCPU PCS1 ST CMOS General purpose I/O. Register enabled pull-up. SDIA PCS1 ST PC7 PCPU PCS1 ST CMOS General purpose I/O. Register enabled pull-up. SCSA PCS1 ST CMOS SPIA slave select PD0 PDPU PDS0 ST CMOS General purpose I/O. Register enabled pull-up. SCOM0 PDS0 — SCOM LCD common output PD1 PDPU PDS0 ST CMOS General purpose I/O. Register enabled pull-up. SCOM1 PDS0 — SCOM LCD common output PD2 PDPU PDS0 ST CMOS General purpose I/O. Register enabled pull-up. SCOM2 PDS0 — SCOM LCD common output PD3 PDPU PDS0 ST CMOS General purpose I/O. Register enabled pull-up. SCOM3 PDS0 — SCOM LCD common output PDn PDPU ST CMOS General purpose I/O. Register enabled pull-up. PE0 PEPU PES0 ST CMOS General purpose I/O. Register enabled pull-up. TX PES0 — CMOS UART TX serial data output PE1 PEPU PES0 ST CMOS General purpose I/O. Register enabled pull-up. RX PES0 IFS ST PE2 PEPU PES0 ST CTCK1 PES0 ST PE3 PEPU PES0 ST CMOS General purpose I/O. Register enabled pull-up. CTP1 PES0 — CMOS CTM1 output PE1/RX PE2/CTCK1 PE3/CTP1 Rev. 1.20 O/T Description CMOS General purpose I/O. Register enabled pull-up. — SPI data input NMOS I2C data line — — — UART RX serial data input SPIA data input UART RX serial data input CMOS General purpose I/O. Register enabled pull-up. — 23 CTM1 clock input July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Pad Name Function OPT I/T PE4 PEPU PES1 ST STCK0 PES1 ST PE5 PEPU PES1 ST STP0I PES1 IFS ST STP0 PES1 — CMOS STM0 output PE6 PEPU PES1 ST CMOS General purpose I/O. Register enabled pull-up. STP0I PES1 IFS ST STP0 PES1 — CMOS STM0 output PE7 PE7 PEPU ST CMOS General purpose I/O. Register enabled pull-up. VDD VDD — PWR VSS VSS — PWR — Negative power supply, ground. SP+ SP+ — — AO Power amplifier output PE4/STCK0 PE5/STP0I/STP0 PE6/STP0I/STP0 SPAUD_IN BIAS O/T Description CMOS General purpose I/O. Register enabled pull-up. — STM0 clock input CMOS General purpose I/O. Register enabled pull-up. — — — STM0 capture input STM0 capture input Positive power supply SP- — — AO Power amplifier output AUD_IN — AN — Power amplifier input BIAS — — AO Power amplifier voltage bias reference AUD — — AO D/A converter output AVDD_PA AVDD_PA — PWR — Audio Power Amplifier positive power supply AVSS_PA AVSS_PA — PWR — Audio Power Amplifier negative power supply NC — — — Not connected AUD NC Legend: I/T: Input type; O/T: Output type; OPT: Optional by register option; PWR: Power; ST: Schmitt Trigger input; AN: Analog input; CMOS: CMOS output; NMOS: NMOS output; SCOM: Software controlled LCD COM; HXT: High frequency crystal oscillator; LXT: Low frequency crystal oscillator AO: Analog output; Absolute Maximum Ratings Supply Voltage.................................................................................................VSS−0.3V to VSS+6.0V Input Voltage...................................................................................................VSS−0.3V to VDD+0.3V Storage Temperature.....................................................................................................-50˚C to 125˚C Operating Temperature...................................................................................................-40˚C to 85˚C IOL Total...................................................................................................................................... 80mA IOH Total.....................................................................................................................................-80mA Total Power Dissipation.......................................................................................................... 500mW Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to these devices. Functional operation of these devices at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect devices reliability. Rev. 1.20 24 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU D.C. Characteristics Ta=25˚C Symbol Parameter Operating Voltage (HXT) Test Conditions ─ VDD Operating Voltage (HIRC) VDDIO I/O Port C Supply Voltage ─ 5V 3V 5V 3V ─ 5.5 V 2.7 ─ 5.5 V fSYS=16MHz 3.6 ─ 5.5 V fSYS=20MHz 4.5 ─ 5.5 V fSYS=8MHz 2.2 ─ 5.5 V fSYS=12MHz 2.7 ─ 5.5 V fSYS=16MHz 3.6 ─ 5.5 V ─ fSYS=fH=4MHz No load, all peripherals off fSYS=fH=8MHz No load, all peripherals off fSYS=fH=12MHz No load, all peripherals off 2.2 ─ VDD V ─ 500 750 μA ─ 1.0 1.5 mA ─ 1.0 1.5 mA ─ 2.0 3.0 mA ─ 1.5 2.75 mA mA 5V ─ 6 8 mA 5V fSYS=fH=20MHz, No load, all peripherals off ─ 7 9 mA ─ 1.0 1.5 mA ─ 2.0 3.0 mA ─ 1.5 2.2 mA ─ 3.0 4.5 mA ─ 4 6 mA ─ 10 20 μA ─ 30 50 μA ─ 10 20 μA ─ 30 50 μA 3V 5V Rev. 1.20 2.2 fSYS=12MHz 4.5 5V Operating Current (LIRC) fSYS=8MHz 3.0 5V Operating Current (LXT)* Unit ─ 3V Operating Current (HIRC) Max. fSYS=fH=16MHz, No load, all peripherals off 5V IDD Typ. ─ 3V Operating Current (HXT) Min. Conditions VDD 3V 5V 3V 5V fSYS=fH=8MHz No load, all peripherals off fSYS=fH=12MHz No load, all peripherals off fSYS=fH=16MHz, No load, all peripherals off fSYS=fSUB=fLXT=32.768kHz No load, all peripherals off fSYS=fSUB=fLIRC=32kHz No load, all peripherals off 25 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Symbol Parameter Standby Current (IDLE0 Mode) Test Conditions 3V 5V 3V 5V 3V 5V 3V Standby Current (IDLE1 Mode) 5V 3V ISTB 5V 3V 5V 5V Standby Current (SLEEP Mode) Standby Current (SLEEP Mode) VIL VIH IOL 3V 5V 3V 5V fSYS=fHXT=4MHz on, fSUB on No load, all peripherals off fSYS=fHXT=8MHz on, fSUB on No load, all peripherals off fSYS=fHXT=12MHz on, fSUB on No load, all peripherals off fSYS=fHIRC=8MHz on, fSUB on No load, all peripherals off fSYS=fHIRC=12MHz on, fSUB on No load, all peripherals off fSYS=fHIRC=16MHz on, fSUB on No load, all peripherals off LIRC off, WDT disable No load, all peripherals off LIRC on, WDT enable No load, all peripherals off ─ Typ. Max. Unit ─ 3 5 μA ─ 5 10 μA ─ 0.2 0.4 mA ─ 0.6 0.8 mA ─ 0.4 0.8 mA ─ 1.2 1.6 mA ─ 0.6 1.25 mA ─ 2.0 2.5 mA ─ 0.28 0.35 mA ─ 0.55 0.7 mA ─ 0.4 0.5 mA ─ 0.8 1.0 mA ─ 1.1 1.4 mA ─ 0.2 0.8 μA ─ 0.5 1.0 μA ─ ─ 3.0 μA ─ ─ 5.0 μA 0 ─ 1.5 V Input Low Voltage for I/O Ports or Input Pins ─ ─ 0 ─ 0.2VDD V Input High Voltage for I/O Ports or Input Pins 5V ─ 3.5 ─ 5.0 V ─ 0.8VDD ─ VDD V 17 34 ─ mA Sink Current for I/O Port ─ 3V VOL = 0.1VDD 5V VOL = 0.1VDD 5V 3V Source Current for I/O Port 5V 5V 3V 3V 5V RPH No load, all peripherals off, fSUB on Min. 5V 3V IOH Conditions VDD Pull-high Resistance for I/O Ports 34 68 ─ mA VOH = 0.9VDD, SLEDC [n+1, n] = 00 -0.7 -1.5 ─ mA -1.5 -2.9 ─ mA VOH = 0.9VDD, SLEDC [n+1, n] = 01 -1.3 -2.5 ─ mA -2.5 -5.1 ─ mA VOH = 0.9VDD, SLEDC [n+1, n] = 10 -1.8 -3.6 ─ mA -3.6 -7.3 ─ mA VOH = 0.9VDD, SLEDC [n+1, n] = 11 -4 -8 ─ mA -8 -16 ─ mA 3V ─ 20 60 100 kΩ 5V ─ 10 30 50 kΩ *: The LXT oscillator is not available for the HT66FV130 device. Rev. 1.20 26 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU A.C. Characteristics Ta=25˚C Symbol Parameter Test Condition Condition VDD Typ. Max. Unit 2.2~5.5V fSYS=fHXT=8MHz ─ 8 ─ MHz 2.7~5.5V fSYS=fHXT=12MHz ─ 12 ─ MHz 3.6~5.5V fSYS=fHXT=16MHz ─ 16 ─ MHz 4.5~5.5V fSYS=fHXT=20MHz ─ 20 ─ MHz 2.2~5.5V fSYS=fHIRC=8MHz ─ 8 ─ MHz 2.7~5.5V fSYS=fHIRC=12MHz ─ 12 ─ MHz 3.6~5.5V fSYS=fHIRC=16MHz ─ 16 ─ MHz System Clock (LXT)* 2.2~5.5V fSYS=fLXT=32.768kHz ─ 32.768 ─ kHz System Clock (LIRC) 2.2~5.5V fSYS=fLIRC=32kHz ─ 32 ─ kHz -2% 12 +2% MHz -5% 12 +5% MHz 2.7V~5.5V Ta = 0°C ~ 70°C -7% 12 +7% MHz 2.7V~5.5V Ta = -40°C ~ 85°C 10% 12 +10% MHz 8 +20% MHz System Clock (HXT) fSYS System Clock (HIRC) Ta = 25°C 3V 3V ± 0.3V Ta = 0°C ~ 70°C fHIRC Min. High Speed Internal RC Oscillator (HIRC) 3V Ta = 25°C 20% 3V Ta = 25°C 20% 16 +20% MHz 5V Ta = 25°C -2% 12 +2% MHz 5V ± 0.5V Ta = 0°C ~ 70°C -5% 12 +5% MHz 2.7V~5.5V Ta = 0°C ~ 70°C -7% 12 +7% MHz 2.7V~5.5V Ta = -40°C ~ 85°C -10% 12 +10% MHz 5V Ta = 25°C -20% 8 +20% MHz 5V Ta = 25°C -20% 16 +20% MHz 5V Ta = 25°C -10% 32 +10% kHz -40% 32 +40% kHz fLIRC Low Speed Internal RC Oscillator (LIRC) tTPI CTPnI, STPnI, PTPnI Pin Minimum Input Pulse Width ─ ─ 0.3 ─ ─ μs tINT Interrupt Pin Minimum Input Pulse Width ─ ─ 10 ─ ─ μs System Start-up Timer Period (Wake-up from Power Down Mode and fSYS off) tSST System Start-up Timer Period (Wake-up from Power Down Mode and fSYS on) System Start-up Timer Period (SLOW Mode → NORMAL Mode) (NORMAL Mode → SLOW Mode) System Start-up Timer Period (WDT Hardware Reset) Rev. 1.20 2.2V~5.5V Ta = -40°C ~ 85°C ─ fSYS = fH = fHXT ~ fHXT/64 128 ─ ─ tHXT ─ fSYS = fH =fHIRC ~ fHIRC/64 16 ─ ─ tHIRC ─ fSYS = fSUB = fLXT 1024 ─ ─ tLXT ─ fSYS = fSUB = fLIRC 2 ─ ─ tLIRC ─ fSYS = fH ~ fH/64, fH = fHXT or fHIRC 2 ─ ─ tH ─ fSYS = fSUB = fLXT or fLIRC 2 ─ ─ tSUB ─ fHXT off → on (HXTF = 1) 1024 ─ ─ tHXT ─ fHIRC off → on (HIRCF = 1) 16 ─ ─ tHIRC ─ fLXT off → on (LXTF = 1) 1024 ─ ─ tLXT 0 ─ ─ tSYS ─ ─ 27 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Symbol Parameter Test Condition Min. Typ. Max. Unit ─ 25 50 100 ms ─ ─ 8.3 16.7 33.3 ms EEPROM Read Time ─ ─ ─ ─ 4 tSYS EEPROM Write Time ─ ─ ─ 2 4 ms VDD Condition System Reset Delay Time (Power-on Reset, LVR Hardware Reset, LVRC/WDTC/RSTC Software Reset) ─ System Reset Delay Time (WDT Hardware Reset) tEERD tEEWR tRSTD *: The LXT oscillator is not available for the HT66FV130 device. Note: tSYS= 1/fSYS A/D Converter Characteristics Ta=25˚C Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit VDD Operating Voltage ─ ─ 2.7 ─ 5.5 V VADI Input Voltage ─ ─ 0 ─ VDD/VREF V VREF Reference Voltage ─ ─ 2 ─ VDD V VREF=VDD, tADCK =0.5μs ─ ─ ±3 LSB VREF=VDD, tADCK =0.5μs ─ ─ ±4 LSB ─ 1.0 2.0 mA 3V DNL Differential Non-linearity INL Integral Non-linearity IADC Additional Current Consumption for A/D Converter Enable 3V ─ 1.5 3.0 mA tADCK Clock Period ─ ─ 0.5 ─ 10 μs tADC Conversion Time (A/D Sample and Hold Time) ─ ─ ─ 16 ─ tADCK tON2ST A/D Converter On-to-Start Time ─ ─ 4 ─ ─ μs VREFI VREFI Pin Input Voltage Range 5V ─ 0.2 ─ VDD - 1.4 V Ga Programmable Gain Amplifier (PGA) Gain Accuracy 5V Gain=1, 2, 3 or 4 (Note) - 5% ─ + 5% % IPGA Additional Current Consumption for PGA Enable 5V No load ─ 200 350 μA 5V 3V 5V 5V No load, tADCK =0.5μs Note: The PGA input voltage on VREFI pin must be in the range of VREFI and the PGA output voltage must not exceed (VDD – 0.2V) with a selected gain to make sure that the PGA operates in the linear region. Rev. 1.20 28 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU LVD/LVR Electrical Characteristics Ta=25˚C Symbol VDD Parameter Operating Voltage Test Conditions Conditions VDD ─ ─ Min. 1.9 LVR Enable, voltage select 2.1V VLVR VLVD Low Voltage Reset Voltage Low Voltage Detector Voltage VBG Bandgap Reference Voltage IOP LVD/LVR Operating Current tBGS VBG Turn on Stable Time tLVDS ─ ─ LVR Enable, voltage select 2.55V LVR Enable, voltage select 3.15V Typ. Max. Unit ─ 5.5 V + 5% V + 5% V + 5% V 2.1 - 5% 2.55 3.15 LVR Enable, voltage select 3.8V 3.8 LVD Enable, voltage select 2.0V 2.0 LVD Enable, voltage select 2.2V 2.2 LVD Enable, voltage select 2.4V 2.4 LVD Enable, voltage select 2.7V LVD Enable, voltage select 3.0V - 5% 2.7 3.0 LVD Enable, voltage select 3.3V 3.3 LVD Enable, voltage select 3.6V 3.6 LVD Enable, voltage select 4.0V 4.0 ─ ─ - 5% 1.04 5V LVD/LVR Enable, VBGEN=0 ─ 20 25 μA 5V LVD/LVR Enable, VBGEN=1 ─ 180 200 μA ─ No load ─ ─ 150 μs ─ For LVR enable, VBGEN=0, LVD off→on ─ ─ 15 μs ─ For LVR disable, VBGEN=0, LVD off→on ─ ─ 150 μs LVDO stable time tLVR Minimum Low Voltage Width to Reset ─ ─ 120 240 480 μs tLVD Minimum Low Voltage Width to Interrupt ─ ─ 60 120 240 μs Rev. 1.20 29 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Audio D/A Converter Electrical Characteristics Ta=25˚C Symbol Test Conditions Parameter ─ Operating Voltage VDD (THD+N)/S Conditions VDD (THD+N)/S(Note) ─ Min. Typ. Max. Unit 2.2 ─ 5.5 V 3V 10KΩ Load ─ -50 ─ dB 5V 10KΩ Load ─ -55 ─ dB Note: sine wave input @ 1kHz, -6dB. Power Amplifier Electrical Characteristics Ta=25˚C Symbol AVDD_PA Test Conditions Parameter VDD Audio Power Amplifier Operating Voltage (THD+N)/S (THD+N)/S(Note) Min. Typ. Max. Unit ─ ─ 2.2 ─ 5.5 V 5V 8Ω Load, Output power=500mW ─ 0.2 ─ % 8Ω Load, (THD+N)/S = 1% ─ 410 ─ mW 8Ω Load, (THD+N)/S = 10% ─ 550 ─ mW 8Ω Load, (THD+N)/S = 1% ─ 1200 ─ mW 8Ω Load, (THD+N)/S = 10% ─ 1500 ─ mW 3V POUT Conditions Output Power 5V Note: sine wave input @ 1kHz, -6dB. Power-on Reset Characteristics Ta=25˚C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to Ensure Power-on Reset ─ ─ ─ ─ 100 mV RRPOR VDD Raising Rate to Ensure Power-on Reset ─ ─ 0.035 ─ ─ V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset ─ ─ 1 ─ ─ ms Rev. 1.20 30 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. This makes these devices suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a HXT, LXT, HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. Note that the LXT oscillator is not available for the HT66FV130 device. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. System Clocking and Pipelining Rev. 1.20 31 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as "JMP" or "CALL" that demand a jump to a nonconsecutive Program Memory address. For the device whose memory capacity is greater than 8K words the Program Memory address may be located in a certain program memory bank which is selected by the program memory bank pointer bit, PMBP0. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Program Counter Device High Byte Low Byte (PCL) HT66FV130 PC10~PC8 PC7~PC0 HT66FV140 PC11~PC8 PC7~PC0 HT66FV150 PC12~PC8 PC7~PC0 HT66FV160 PMBP0, PC12~PC8 PC7~PC0 Program Counter The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly; however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Rev. 1.20 32 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has multiple levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. Program Co�nter Top of Stack Stack Leve� 1 Stack Leve� 2 Stack Pointer Stack Leve� 3 : : : Bottom of Stack Program Memor� Stack Leve� N Note: N=4 for HT66FV130 while N=8 for HT66FV140/HT66FV150/HT66FV160 Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA LADD, LADDM, LADC, LADCM, LSUB, LSUBM, LSBC, LSBCM, LDAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA LAND, LOR, LXOR, LANDM, LORM, LXORM, LCPL, LCPLA • Rotation: RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC LRRA, LRR, LRRCA, LRRC, LRLA, LRL, LRLCA, LRLC • Increment and Decrement: INCA, INC, DECA, DEC LINCA, LINC, LDECA, LDEC • Branch decision: JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI LSZ, LSZA, LSNZ, LSIZ, LSDZ, LSIZA, LSDZA Rev. 1.20 33 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Flash Program Memory The Program Memory is the location where the user code or program is stored. For these devices series the Program Memory are Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, these Flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Device Capacity HT66FV130 2K x 16 Banks — HT66FV140 4K x 16 — HT66FV150 8K x 16 — HT66FV160 16K x 16 0~1 Structure The Program Memory has a capacity of 2K×16 to 16K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer registers. 000H HT66FV130 HT66FV140 HT66FV150 HT66FV160 Initia�isation Vector Initia�isation Vector Initia�isation Vector Initia�isation Vector Interr�pt Vectors Interr�pt Vectors Interr�pt Vectors Interr�pt Vectors Look-�p Tab�e Look-�p Tab�e Look-�p Tab�e Look-�p Tab�e 16 bits 16 bits 004H 024H 028H n00H nFFH 7FFH 16 bits FFFH 16 bits 1FFFH 2000H Bank 1 3FFFH Program Memory Structure Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by these devices reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Rev. 1.20 34 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the "TABRD [m]" or "TABRDL [m]" instructions respectively when the memory [m] is located in sector 0. If the memory [m] is located in other sectors, the data can be retrieved from the program memory using the corresponding extended table read instruction such as "LTABRD [m]" or "LTABRDL [m]" respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as "0". The accompanying diagram illustrates the addressing data flow of the look-up table. A d d re s s L a s t p a g e o r T B H P R e g is te r T B L P R e g is te r D a ta 1 6 b its R e g is te r T B L H U s e r S e le c te d R e g is te r H ig h B y te L o w B y te Table Program Example The accompanying example shows how the table pointer and table data is defined and retrieved from the device. This example uses raw table data located in the last page which is stored there using the ORG statement. The value at this ORG statement is "0F00H" which refers to the start address of the last page within the 4K Program Memory of the device. The table pointer low byte register is setup here to have an initial value of "06H". This will ensure that the first data read from the data table will be at the Program Memory address "0F06H" or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the page that TBHP pointed if the "TABRD [m]" instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the "TABRD [m] instruction is executed. Because the TBLH register is a read/write register and can be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Rev. 1.20 35 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a ; to the last page or the page that tbhp pointed mov a,0fh ; initialise high table pointer movtbhp,a : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address "0F06H" transferred to tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address "0F05H" transferred to tempreg2 and TBLH in this ; example the data "1AH" is transferred to tempreg1 and data "0FH" to ; register tempreg2 : org 0F00h ; sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller incircuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and reinsertion of the device. Holtek Writer Pins MCU Programming Pins ICPDA PA0 Programming Serial Data/Address Pin Description ICPCK PA2 Programming Clock VDD VDD Power Supply VSS VSS Ground The Program Memory and EEPROM data memory can be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply. The technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. During the programming process, the user must take care of the ICPDA and ICPCK pins for data and clock programming purposes to ensure that no other outputs are connected to these two pins. Rev. 1.20 36 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU W r ite r C o n n e c to r S ig n a ls M C U W r ite r _ V D D V D D IC P D A P A 0 IC P C K P A 2 W r ite r _ V S S V S S * P r o g r a m m in g P in s * T o o th e r C ir c u it Note: * may be resistor or capacitor. The resistance of * must be greater than 1k or the capacitance of * must be less than 1nF. On-Chip Debug Support – OCDS There is an EV chip named HT66VV1x0 which is used to emulate the real MCU device named HT66FV1x0. The EV chip device also provides the "On-Chip Debug" function to debug the real MCU device during development process. The EV chip and real MCU devices, HT66VV1x0 and HT66FV1x0, are almost functional compatible except the "On-Chip Debug" function. Users can use the EV chip device to emulate the real MCU device behaviors by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip device for debugging, the corresponding pin functions shared with the OCDSDA and OCDSCK pins in the real MCU device will have no effect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For more detailed OCDS information, refer to the corresponding document named "Holtek e-Link for 8-bit MCU OCDS User’s Guide". Rev. 1.20 Holtek e-Link Pins EV Chip OCDS Pins Pin Description OCDSDA OCDSDA On-Chip Debug Support Data/Address input/output OCDSCK OCDSCK On-Chip Debug Support Clock input VDD VDD Power Supply VSS VSS Ground 37 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU In Application Programming – IAP These devices offer IAP function to update data or application program to flash ROM. Users can define any ROM location for IAP, but there are some features which user must notice in using IAP function. Note that the HT66FV130 and HT66FV140 devices support the "Block Erase" function instead of the "Page Erase" function. HT66FV130/HT66FV140 Configurations HT66FV150 Configurations HT66FV160 Configurations Erase Block 256 words / block Erase Page 32 words / page Erase Page 64 words / page Writing Word 4 words / time Writing Word 32 words / time Writing Word 64 words / time Reading Word 1 word / time Reading Word 1 word / time Reading Word 1 word / time In Application Programming Control Registers The Address register, FARL and FARH, the Data registers, FD0L/FD0H, FD1L/FD1H, FD2L/FD2H and FD3L/FD3H, and the Control registers, FC0, FC1 and FC2, are the corresponding Flash access registers located in Data Memory sector 1 for IAP. If using the indirect addressing method to access the FC0, FC1 and FC2 registers, all read and write operations to the registers must be performed using the Indirect Addressing Register, IAR1 or IAR2, and the Memory Pointer pair, MP1L/MP1H or MP2L/MP2H. Because the FC0, FC1 and FC2 control registers are located at the address of 50H~52H in Data Memory sector 1, the desired value ranged from 50H to 52H must first be written into the MP1L or MP2L Memory Pointer low byte and the value "01H" must also be written into the MP1H or MP2H Memory Pointer high byte. Register Name FC0 Bit 7 6 5 4 2 1 0 CFWEN FMOD2 FMOD1 FMOD0 FWPEN 3 FWT FRDEN FRD FC1 D7 D6 D5 D4 D3 D2 D1 D0 FC2 (HT66FV150/160) — — — — — — — CLWB FARL A7 A6 A5 A4 A3 A2 A1 A0 FARH (HT66FV130) — — — — — A10 A9 A8 FARH (HT66FV140) — — — — A11 A10 A9 A8 FARH (HT66FV150) — — — A12 A11 A10 A9 A8 FARH (HT66FV160) — — A13 A12 A11 A10 A9 A8 FD0L D7 D6 D5 D4 D3 D2 D1 D0 FD0H D15 D14 D13 D12 D11 D10 D9 D8 FD1L D7 D6 D5 D4 D3 D2 D1 D0 FD1H D15 D14 D13 D12 D11 D10 D9 D8 FD2L D7 D6 D5 D4 D3 D2 D1 D0 FD2H D15 D14 D13 D12 D11 D10 D9 D8 FD3L D7 D6 D5 D4 D3 D2 D1 D0 FD3H D15 D14 D13 D12 D11 D10 D9 D8 IAP Registers List Rev. 1.20 38 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU • FC0 Register Bit 7 6 5 4 3 2 1 0 Name CFWEN FMOD2 FMOD1 FMOD0 FWPEN FWT FRDEN FRD R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 1 1 0 0 0 0 Bit 7CFWEN: Flash Memory Write enable control 0: Flash memory write function is disabled 1: Flash memory write function has been successfully enabled When this bit is cleared to 0 by application program, the Flash memory write function is disabled. Note that writing a "1" into this bit results in no action. This bit is used to indicate that the Flash memory write function status. When this bit is set to 1 by hardware, it means that the Flash memory write function is enabled successfully. Otherwise, the Flash memory write function is disabled as the bit content is zero. Bit 6~4FMOD2~FMOD0: Mode selection 000: Write program memory 001: Block/Page erase program memory 010: Reserved 011: Read program memory 10x: Reserved 110: FWEN mode – Flash memory Write function Enabled mode 111: Reserved When these bits are set to "001", the "Block erase" mode is selected for HT66FV130/ HT66FV140 while the "Page erase" mode is selected for HT66FV150/HT66FV160. Bit 3FWPEN: Flash memory Write Procedure Enable control 0: Disable 1: Enable When this bit is set to 1 and the FMOD field is set to "110", the IAP controller will execute the "Flash memory write function enable" procedure. Once the Flash memory write function is successfully enabled, it is not necessary to set the FWPEN bit any more. Bit 2FWT: Flash memory Write Initiate control 0: Do not initiate Flash memory write or Flash memory write process is completed 1: Initiate Flash memory write process This bit is set by software and cleared by hardware when the Flash memory write process is completed. Bit 1FRDEN: Flash memory Read Enable control 0: Flash memory read disable 1: Flash memory read enable Bit 0FRD: Flash memory Read Initiate control 0: Do not initiate Flash memory read or Flash memory read process is completed 1: Initiate Flash memory read process This bit is set by software and cleared by hardware when the Flash memory read process is completed. • FC1 Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0D7~D0: Whole chip reset pattern When user writes a specific value of "55H" to this register, it will generate a reset signal to reset whole chip. Rev. 1.20 39 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU • FC2 Register – HT66FV150/HT66FV160 Bit 7 6 5 4 3 2 1 0 Name — — — — — — — CLWB R/W — — — — — — — R/W POR — — — — — — — 0 Bit 7~1 Unimplemented, read as 0. Bit 0CLWB: Flash memory Write Buffer Clear control 0: Do not initiate Write Buffer Clear process or Write Buffer Clear process is completed 1: Initiate Write Buffer Clear process This bit is set by software and cleared by hardware when the Write Buffer Clear process is completed. • FARL Register Bit 7 6 5 4 3 2 1 0 Name A7 A6 A5 A4 A3 A2 A1 A0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Flash Memory Address bit 7 ~ bit 0 • FARH Register – HT66FV130 Bit 7 6 5 4 3 2 1 0 Name — — — — — A10 A9 A8 R/W — — — — — R/W R/W R/W POR — — — — — 0 0 0 Bit 7~3 Unimplemented, read as 0. Bit 2~0 Flash Memory Address bit 10 ~ bit 8 • FARH Register – HT66FV140 Bit 7 6 5 4 3 2 1 0 Name — — — — A11 A10 A9 A8 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 3 2 1 0 Bit 7~4 Unimplemented, read as 0. Bit 3~0 Flash Memory Address bit 11 ~ bit 8 • FARH Register – HT66FV150 Rev. 1.20 Bit 7 6 5 4 Name — — — A12 A11 A10 A9 A8 R/W — — — R/W R/W R/W R/W R/W POR — — — 0 0 0 0 0 Bit 7~5 Unimplemented, read as 0. Bit 4~0 Flash Memory Address bit 12 ~ bit 8 40 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU • FARH Register – HT66FV160 Bit 7 6 5 4 3 2 1 0 Name — — A13 A12 A11 A10 A9 A8 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as 0. Bit 5~0 Flash Memory Address bit 13 ~ bit 8 • FD0L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The first Flash Memory data bit 7 ~ bit 0 • FD0H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The first Flash Memory data bit 15 ~ bit 8 • FD1L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The second Flash Memory data bit 7 ~ bit 0 • FD1H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The second Flash Memory data bit 15 ~ bit 8 • FD2L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The third Flash Memory data bit 7 ~ bit 0 • FD2H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.20 The third Flash Memory data bit 15 ~ bit 8 41 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU • FD3L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The fourth Flash Memory data bit 7 ~ bit 0 • FD3H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The fourth Flash Memory data bit 15 ~ bit 8 Flash Memory Write Function Enable Procedure In order to allow users to change the Flash memory data through the IAP control registers, users must first enable the Flash memory write operation by the following procedure: 1. Write "110" into the FMOD2~FMOD0 bits to select the FWEN mode. 2. Set the FWPEN bit to "1". The step 1 and step 2 can be executed simultaneously. 3. The pattern data with a sequence of 00H, 04H, 0DH, 09H, C3H and 40H must be written into the FD1L, FD1H, FD2L, FD2H, FD3L and FD3H registers respectively. 4. A counter with a time-out period of 300μs will be activated to allow users writing the correct pattern data into the FD1L/FD1H ~ FD3L/FD3H register pairs. The counter clock is derived from LIRC oscillator. 5. If the counter overflows or the pattern data is incorrect, the Flash memory write operation will not be enabled and users must again repeat the above procedure. Then the FWPEN bit will automatically be cleared to 0 by hardware. 6. If the pattern data is correct before the counter overflows, the Flash memory write operation will be enabled and the FWPEN bit will automatically be cleared to 0 by hardware. The CFWEN bit will also be set to 1 by hardware to indicate that the Flash memory write operation is successfully enabled. 7. Once the Flash memory write operation is enabled, the user can change the Flash ROM data through the Flash control register. 8. To disable the Flash memory write operation, the user can clear the CFWEN bit to 0. Rev. 1.20 42 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Flash Memory Write Function Enable Procedure Set FMOD [2:0] =110 & FWPEN=1 Ò Select FWEN mode & Start Flash write Hardware activate a counter Wrtie the following pattern to Flash Data registers FD1L= 00h , FD1H = 04h FD2L= 0Dh , FD2H = 09h FD3L= C3h , FD3H = 40h Is counter overflow ? No Yes FWPEN=0 No Is pattern correct ? Yes CFWEN = 1 CFWEN=0 Success Failed END Flash Memory Write Function Enable Procedure Rev. 1.20 43 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Flash Memory Read/Write Procedure After the Flash memory write function is successfully enabled through the preceding IAP procedure, users must first erase the corresponding Flash memory block or page and then initiate the Flash memory write operation. For the HT66FV130/HT66FV140 devices the number of the block erase operation is 256 words per block, the available block erase address is only specified by FARH register and the content in the FARL register is not used to specify the block address. For the HT66FV150 and HT66FV160 devices the number of the page erase operation is 32 and 64 words per page respectively, the available page erase address is specified by FARH register and the content of FARL [7:5] and FARL [7:6] bit field respectively. Erase Block FARH [2:0] FARL [7:0] 0 000 xxxx xxxx 1 001 xxxx xxxx 2 010 xxxx xxxx 3 011 xxxx xxxx 4 100 xxxx xxxx 5 101 xxxx xxxx 6 110 xxxx xxxx 7 111 xxxx xxxx "x": don’t care HT66FV130 Erase Block Number and Selection Erase Block FARH [3:0] FARL [7:0] 0 0000 xxxx xxxx 1 0001 xxxx xxxx 2 0010 xxxx xxxx 3 0011 xxxx xxxx 4 0100 xxxx xxxx 5 0101 xxxx xxxx 6 0110 xxxx xxxx 7 0111 xxxx xxxx 8 1000 xxxx xxxx 9 1001 xxxx xxxx 10 1010 xxxx xxxx 11 1011 xxxx xxxx 12 1100 xxxx xxxx 13 1101 xxxx xxxx 14 1110 xxxx xxxx 15 1111 xxxx xxxx "x": don’t care HT66FV140 Erase Block Number and Selection Rev. 1.20 44 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Erase Page FARH FARL [7:5] 0 0000 0000 000 FARL [4:0] x xxxx 1 0000 0000 001 x xxxx x xxxx 2 0000 0000 010 3 0000 0000 011 x xxxx 4 0000 0000 100 x xxxx 5 0000 0000 101 x xxxx 6 0000 0000 110 x xxxx 7 0000 0000 111 x xxxx 8 0000 0001 000 x xxxx 9 0000 0001 001 x xxxx : : : : : : : : 126 0000 1111 110 x xxxx 127 0000 1111 111 x xxxx 128 0001 0000 000 x xxxx 129 0001 0000 001 x xxxx : : : : : : : : 254 0001 1111 110 x xxxx 255 0001 1111 111 x xxxx "x": don’t care HT66FV150 Erase Page Number and Selection Erase Page FARH FARL [7:6] 0 0000 0000 00 FARL [5:0] xx xxxx 1 0000 0000 01 xx xxxx 2 0000 0000 10 xx xxxx 3 0000 0000 11 xx xxxx 4 0000 0001 00 xx xxxx 5 0000 0001 01 xx xxxx : : : : : : : : 126 0001 1111 10 xx xxxx 127 0001 1111 11 xx xxxx 128 0010 0000 00 xx xxxx 129 0010 0000 01 xx xxxx : : : : : : : : 254 0011 1111 10 xx xxxx 255 0011 1111 11 xx xxxx "x": don’t care HT66FV160 Erase Page Number and Selection Rev. 1.20 45 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Read F�ash Memor� Set FMOD [2:0]=011 & FRDEN=1 Set F�ash Address registers FARH=xxh� FARL=xxh Set FRD=1 No FRD=0 ? Yes Read data va��e: FD0L=xxh� FD0H=xxh No Read Finish ? Yes C�ear FRDEN bit END Read Flash Memory Procedure Rev. 1.20 46 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Write Flash Memory Flash Memory Write Function Enable Procedure Set Block Erase address: FARH/FARL Set FMOD [2:0]=001 & FWT=1 Ò Select “Block Erase mode” & Initiate write operation No FWT=0 ? Yes Set FMOD [2:0]=000 ÒSelect “Write Flash Mode” Set Write starting address: FARH/FARL Write data to data register: FD0L/FD0H, FD1L/FD1H, FD2L/FD2H, FD3L/FD3H, Set FWT=1 No FWT=0 ? Yes Write Finish ? No Yes Clear CFWEN=0 END Write Flash Memory Procedure – HT66FV130/HT66FV140 Rev. 1.20 47 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Write Flash Memory Flash Memory Write Function Enable Procedure Set Page Erase address: FARH/FARL Set FMOD [2:0]=001 & FWT=1 ÒSelect “Page Erase mode” & Initiate write operation No FWT=0 ? Yes Set FMOD [2:0]=000 ÒSelect “Write Flash Mode” Set Write starting address: FARH/FARL Write data to data register: FD0L/FD0H No Page data Write finish Yes Set FWT=1 No FWT=0 ? Yes Write Finish ? No Yes Clear CFWEN=0 END Write Flash Memory Procedure – HT66FV150/HT66FV160 Note: When the FWT or FRD bit is set to 1, the MCU is stopped. Rev. 1.20 48 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Data Memory The Data Memory is an 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two types, the first of Data Memory is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. Switching between the different Data Memory sectors is achieved by properly setting the Memory Pointers to correct value. Structure The Data Memory is subdivided into several sectors, all of which are implemented in 8-bit wide Memory. Each of the Data Memory sectors is categorized into two types, the Special Purpose Data Memory and the General Purpose Data Memory. The address range of the Special Purpose Data Memory for the device is from 00H to 7FH while the address range of the General Purpose Data Memory is from 80H to FFH. Device Special Purpose Data Memory General Purpose Data Memory Available Sectors Capacity Sectors HT66FV130 0, 1 128 x 8 0: 80H~FFH HT66FV140 0, 1 256 x 8 0: 80H~FFH 1: 80H~FFH 512 x 8 0: 80H~FFH 1: 80H~FFH 2: 80H~FFH 3: 80H~FFH 1024 x 8 0: 80H~FFH 1: 80H~FFH : 7: 80H~FFH HT66FV150 0, 1 0, 1 HT66FV160 Data Memory Summary 00H 27H 36H Specia� P�rpose Data Memor� 40H �0H �CH 7FH 80H Genera� P�rpose Data Memor� FFH Sector 0 Sector 1 Sector N Note: N=0 for HT66FV130; N=1 for HT66FV140; N=3 for HT66FV1�0; N=7 for HT66FV160 Data Memory Structure Rev. 1.20 49 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Data Memory Addressing For these devices support the extended instructions, there is no Bank Pointer for Data Memory. The Bank Pointer, PBP, is only available for Program Memory. For Data Memory the desired Sector is pointed by the MP1H or MP2H register and the certain Data Memory address in the selected sector is specified by the MP1L or MP2L register when using indirect addressing access. Direct Addressing can be used in all sectors using the corresponding instruction which can address all available data memory space. For the accessed data memory which is located in any data memory sectors except sector 0, the extended instructions can be used to access the data memory instead of using the indirect addressing access. The main difference between standard instructions and extended instructions is that the data memory address "m" in the extended instructions can be from 9 bits to 11 bits depending upon which device is selected, the high byte indicates a sector and the low byte indicates a specific address. General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user programing for both reading and writing operations. By using the bit operation instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value "00H". Rev. 1.20 50 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU 00H 01H 02H 03H 04H 0�H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 1�H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 2�H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 3�H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Sector 0 IAR0 MP0 IAR1 MP1L MP1H ACC PCL TBLP TBLH TBHP STATUS Sector 1 40H 41H 42H 43H 44H 4�H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH �0H �1H �2H �3H �4H ��H �6H �7H �8H �9H �AH �BH �CH �DH �EH �FH 60H 61H 62H 63H 64H 6�H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 7�H 76H 77H IAR2 MP2L MP2H INTC0 PA PAC PAPU PAWU RSTFC PB PBC PBPU PSCR TB0C TB1C SCC HIRCC HXTC RSTC CTM0C0 CTM0C1 CTM0DL CTM0DH CTM0AL CTM0AH LVDC LVRC PTM0C0 PTM0C1 PTM0DL PTM0DH PTM0AL PTM0AH PTM0RPL PTM0RPH INTEG INTC1 INTC2 MFI0 MFI1 Sector 0 SADC2 EEA EED PTM1C0 PTM1C1 PTM1DL PTM1DH PTM1AL PTM1AH PTM1RPL PTM1RPH WDTC PCPU PC PCC SADOL SADOH SADC0 SADC1 PAS0 PAS1 PBS0 PCS0 PCS1 Sector 1 EEC FC0 FC1 FC2 FARL FARH FD0L FD0H FD1L FD1H FD2L FD2H FD3L FD3H IFS SIMTOC SIMC0 SIMC1 SIMD SIMA/SIMC2 SPIAC0 SPIAC1 SPIAD SLEDC0 USVC PLAC PLADL PLADH 7FH : Un�sed� read as 00H MFI3 Speciap Purpose Data Memory Structure – HT66FV130 Rev. 1.20 51 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU 00H 01H 02H 03H 04H 0�H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 1�H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 2�H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 3�H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Sector 0 IAR0 MP0 IAR1 MP1L MP1H ACC PCL TBLP TBLH TBHP STATUS Sector 1 40H 41H 42H 43H 44H 4�H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH �0H �1H �2H �3H �4H ��H �6H �7H �8H �9H �AH �BH �CH �DH �EH �FH 60H 61H 62H 63H 64H 6�H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 7�H 76H 77H IAR2 MP2L MP2H INTC0 PA PAC PAPU PAWU RSTFC PB PBC PBPU PSCR TB0C TB1C SCC HIRCC HXTC LXTC RSTC CTM0C0 CTM0C1 CTM0DL CTM0DH CTM0AL CTM0AH LVDC LVRC PTM0C0 PTM0C1 PTM0DL PTM0DH PTM0AL PTM0AH PTM0RPL PTM0RPH INTEG INTC1 INTC2 MFI0 MFI1 MFI2 MFI3 Sector 0 SADC2 EEA EED PTM1C0 PTM1C1 PTM1DL PTM1DH PTM1AL PTM1AH PTM1RPL PTM1RPH WDTC PCPU PC PCC SADOL SADOH SADC0 SADC1 PAS0 PAS1 PBS0 PCS0 PCS1 Sector 1 EEC FC0 FC1 FC2 FARL FARH FD0L FD0H FD1L FD1H FD2L FD2H FD3L FD3H IFS SIMTOC SIMC0 SIMC1 SIMD SIMA/SIMC2 SPIAC0 SPIAC1 SPIAD SLEDC0 USVC PLAC PLADL PLADH 7FH : Un�sed� read as 00H Speciap Purpose Data Memory Structure – HT66FV140 Rev. 1.20 52 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU 00H 01H 02H 03H 04H 0�H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 1�H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 2�H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 3�H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Sector 0 IAR0 MP0 IAR1 MP1L MP1H ACC PCL TBLP TBLH TBHP STATUS Sector 1 Sector 2 ~ Sector 3 40H 41H 42H 43H 44H 4�H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH �0H �1H �2H �3H �4H ��H �6H �7H �8H �9H �AH �BH �CH �DH �EH �FH 60H 61H 62H 63H 64H 6�H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 7�H 76H 77H 78H 79H 7AH IAR2 MP2L MP2H INTC0 PA PAC PAPU PAWU PEPU RSTFC PE PEC PB PBC PBPU PSCR TB0C TB1C SCC HIRCC HXTC LXTC RSTC CTM0C0 CTM0C1 CTM0DL CTM0DH CTM0AL CTM0AH CTM1C0 CTM1C1 CTM1DL CTM1DH CTM1AL CTM1AH LVDC LVRC PTM0C0 PTM0C1 PTM0DL PTM0DH PTM0AL PTM0AH PTM0RPL PTM0RPH INTEG INTC1 INTC2 MFI0 MFI1 MFI2 MFI3 SCOMC Sector 0 SADC2 EEA EED PTM1C0 PTM1C1 PTM1DL PTM1DH PTM1AL PTM1AH PTM1RPL PTM1RPH WDTC PCPU PC PCC PDPU PD PDC SADOL SADOH SADC0 SADC1 PAS0 PAS1 PBS0 PCS0 PCS1 PDS0 Sector 1 EEC Sector 2 ~ Sector 3 FC0 FC1 FC2 FARL FARH FD0L FD0H FD1L FD1H FD2L FD2H FD3L FD3H IFS SIMTOC SIMC0 SIMC1 SIMD SIMA/SIMC2 SPIAC0 SPIAC1 SPIAD USR UCR1 UCR2 TXR_RXR BRG SLEDC0 SLEDC1 USVC PLAC PLADL PLADH PES0 7FH : Un�sed� read as 00H Speciap Purpose Data Memory Structure – HT66FV150 Rev. 1.20 53 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU 00H 01H 02H 03H 04H 0�H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 1�H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 2�H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 3�H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Sector 0 IAR0 MP0 IAR1 MP1L MP1H ACC PCL TBLP TBLH TBHP STATUS PBP IAR2 MP2L MP2H Sector 1 Sector 2 ~ Sector 7 40H 41H 42H 43H 44H 4�H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH �0H �1H �2H �3H �4H ��H �6H �7H �8H �9H �AH �BH �CH �DH �EH �FH 60H 61H 62H 63H 64H 6�H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 7�H 76H 77H 78H 79H 7AH 7BH 7CH INTC0 PA PAC PAPU PAWU PEPU RSTFC PE PEC PB PBC PBPU PSCR TB0C TB1C SCC HIRCC HXTC LXTC RSTC CTM0C0 CTM0C1 CTM0DL CTM0DH CTM0AL CTM0AH LVDC LVRC PTM0C0 PTM0C1 PTM0DL PTM0DH PTM0AL PTM0AH PTM0RPL PTM0RPH INTEG INTC1 INTC2 MFI0 MFI1 MFI2 MFI3 SCOMC CTM1C0 CTM1C1 CTM1DL CTM1DH CTM1AL CTM1AH STM0C0 STM0C1 STM0DL STM0DH STM0AL STM0AH STM0RP Sector 0 SADC2 EEA EED PTM1C0 PTM1C1 PTM1DL PTM1DH PTM1AL PTM1AH PTM1RPL PTM1RPH WDTC PCPU PC PCC PDPU PD PDC SADOL SADOH SADC0 SADC1 PAS0 PAS1 PBS0 PCS0 PCS1 PDS0 PDS1 IFS SIMTOC SIMC0 SIMC1 SIMD SIMA/SIMC2 SPIAC0 SPIAC1 SPIAD USR UCR1 UCR2 TXR_RXR BRG SLEDC0 SLEDC1 USVC Sector 1 EEC Sector 2 ~ Sector 7 FC0 FC1 FC2 FARL FARH FD0L FD0H FD1L FD1H FD2L FD2H FD3L FD3H PLAC PLADL PLADH PES0 PES1 7FH : Un�sed� read as 00H Speciap Purpose Data Memory Structure – HT66FV160 Rev. 1.20 54 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section. However, several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1, IAR2 The Indirect Addressing Registers, IAR0, IAR1 and IAR2, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0, IAR1 and IAR2 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0, MP1L/ MP1H or MP2L/MP2H. Acting as a pair, IAR0 and MP0 can together access data only from Sector 0 while the IAR1 register together with MP1L/MP1H register pair and IAR2 register together with MP2L/MP2H register pair can access data from any Data Memory sector. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of "00H" and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1H/MP1L, MP2H/MP2L Five Memory Pointers, known as MP0, MP1L, MP1H, MP2L and MP2H, are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Sector 0, while MP1L/MP1H together with IAR1 and MP2L/MP2H together with IAR2 are used to access data from all data sectors according to the corresponding MP1H or MP2H register. Direct Addressing can be used in all data sectors using the corresponding instruction which can address all available data memory space. Indirect Addressing Program Example Example 1 data .section ‘data’ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; mov block,a mov a,offset adres1 ; mov mp0,a ; loop: clr IAR0 ; inc mp0; sdz block ; jmp loop continue: : Rev. 1.20 setup size of block Accumulator loaded with first RAM address setup memory pointer with first RAM address clear the data at address defined by MP0 increment memory pointer check if last memory location has been cleared 55 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Example 2 data .section ‘data’ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ‘code’ org 00h start: mov a,04h ; setup size of block mov block,a mov a,01h ; setup the memory sector mov mp1h,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp1l,a ; setup memory pointer with first RAM address loop: clr IAR1 ; clear the data at address defined by MP1 inc mp1l ; increment memory pointer MP1L sdz block ; check if last memory location has been cleared jmp loop continue: : The important point to note here is that in the example shown above, no reference is made to specific RAM addresses. Direct Addressing Program Example using extended instructions data .section ‘data’ temp db ? code .section at 0 code org 00h start: lmova,[m] ; move [m] data to acc lsuba, [m+1] ; compare [m] and [m+1] data snz c; [m]>[m+1]? jmp continue ; no lmova,[m] ; yes, exchange [m] and [m+1] data movtemp,a lmova,[m+1] lmov[m],a mova,temp lmov[m+1],a continue: : Note: Here "m" is a data memory address located in any data memory sectors. For example, m=1F0H, it indicates address 0F0H in Sector 1. Rev. 1.20 56 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Program Memory Bank Pointer – PBP For the HT66FV160 device the Program Memory is divided into several banks. Selecting the required Program Memory area is achieved using the Program Memory Bank Pointer, PBP. The PBP register should be properly configured before the device executes the "Branch" operation using the "JMP" or "CALL" instruction. After that a jump to a non-consecutive Program Memory address which is located in a certain bank selected by the program memory bank pointer bits will occur. PBP Register – HT66FV160 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 PBP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~1D7~D1: General data bits and can be read or written. Bit 0PBP0: Program Memory Bank Point bit 0 0: Bank 0 1: Bank 1 Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the "INC" or "DEC" instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Rev. 1.20 57 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), SC flag, CZ flag, power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/ logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up. The Z, OV, AC, C, SC and CZ flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the "CLR WDT" instruction. PDF is set by executing the "HALT" instruction. • TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" instruction. TO is set by a WDT time-out. • SC is the result of the "XOR" operation which is performed by the OV flag and the MSB of the current instruction operation result. • CZ is the operational result of different flags for different instuctions. Refer to register definitions for more details. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Rev. 1.20 58 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU STATUS Register Bit 7 6 5 4 3 2 1 0 Name SC CZ TO PDF OV Z AC C R/W R R R R R/W R/W R/W R/W POR x x 0 0 x x x x "x": unknown Bit 7SC: The result of the "XOR" operation which is performed by the OV flag and the MSB of the instruction operation result. Bit 6CZ: The the operational result of different flags for different instuctions. For SUB/SUBM/LSUB/LSUBM instructions, the CZ flag is equal to the Z flag. For SBC/ SBCM/ LSBC/ LSBCM instructions, the CZ flag is the "AND" operation result which is performed by the previous operation CZ flag and current operation zero flag. For other instructions, the CZ flag willl not be affected. Bit 5TO: Watchdog Time-out flag 0: After power up ow executing the "CLR WDT" or "HALT" instruction 1: A watchdog time-out occurred Bit 4PDF: Power down flag 0: After power up ow executing the "CLR WDT" instruction 1: By executing the "HALT" instructin Bit 3OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa Bit 2Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1AC: Auxiliary flag 0: No auxiliary carry 1: An operation results in a carry out of the low nibbles, in addition, or no borrow from the high nibble into the low nibble in substraction Bit 0C: Carry flag 0: No carry-out 1: An operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation The "C" flag is also affected by a rotate through carry instruction. Rev. 1.20 59 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU EEPROM Data Memory These devices contain an area of internal EEPROM Data Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of re-programmable memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. Device Capacity Address HT66FV130 32 x 8 00H ~ 1FH HT66FV140 64 x 8 00H ~ 3FH HT66FV150 128 x 8 00H ~ 7FH HT66FV160 256 x 8 00H ~ FFH EEPROM Data Memory Structure The EEPROM Data Memory capacity is up to 256×8 bits for the series of devices. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. Read and Write operations to the EEPROM are carried out in single byte operations using an address and data register in sector 0 and a single control register in sector 1. EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory. These are the address register, EEA, the data register, EED and a single control register, EEC. As both the EEA and EED registers are located in sector 0, they can be directly accessed in the same was as any other Special Function Register. The EEC register, however, being located in sector 1, can be read from or written to indirectly using the MP1H/MP1L or MP2H/MP2L Memory Pointer pair and Indirect Addressing Register, IAR1 or IAR2. Because the EEC control register is located at address 40H in sector 1, the Memory Pointer low byte register, MP1L or MP2L, must first be set to the value 40H and the Memory Pointer high byte register, MP1H or MP2H, set to the value, 01H, before any operations on the EEC register are executed. Register Name EEA (HT66FV130) Bit 7 6 5 4 3 2 1 0 — — — EEA4 EEA3 EEA2 EEA1 EEA0 EEA (HT66FV140) — — EEA5 EEA4 EEA3 EEA2 EEA1 EEA0 EEA (HT66FV150) — EEA6 EEA5 EEA4 EEA3 EEA2 EEA1 EEA0 EEA (HT66FV160) EEA7 EEA6 EEA5 EEA4 EEA3 EEA2 EEA1 EEA0 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC — — — — WREN WR RDEN RD EEPROM Registers List Rev. 1.20 60 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU EEA Register – HT66FV130 Bit 7 6 5 4 3 2 1 0 Name — — — EEA4 EEA3 EEA2 EEA1 EEA0 R/W — — — R/W R/W R/W R/W R/W POR — — — 0 0 0 0 0 Bit 7~5 Unimplemented, read as 0. Bit 4~0EEA4~EEA0: Data EEPROM address bit 4 ~ bit0 EEA Register – HT66FV140 Bit 7 6 5 4 3 2 1 0 Name — — EEA5 EEA4 EEA3 EEA2 EEA1 EEA0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as 0. Bit 5~0EEA5~EEA0: Data EEPROM address bit 5 ~ bit0 EEA Register – HT66FV150 Bit 7 6 5 4 3 2 1 0 Name — EEA6 EEA5 EEA4 EEA3 EEA2 EEA1 EEA0 R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as 0. Bit 6~0EEA6~EEA0: Data EEPROM address bit 6 ~ bit0 EEA Register – HT66FV160 Bit 7 6 5 4 3 2 1 0 Name EEA7 EEA6 EEA5 EEA4 EEA3 EEA2 EEA1 EEA0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0EEA7~EEA0: Data EEPROM address bit 7 ~ bit0 EED Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0D7~D0: Data EEPROM data bit 7~bit0 Rev. 1.20 61 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU EEC Register Bit 7 6 5 4 3 2 1 0 Name — — — — WREN WR RDEN RD R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as 0. Bit 3WREN: Data EEPROM write enable 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2WR: EEPROM write control 0: Write cycle has finished 1: Activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high. Bit 1RDEN: Data EEPROM read enable 0: Disable 1: Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations. Bit 0RD: EEPROM read control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high. Note: The WREN, WR, RDEN and RD can not be set to "1" at the same time in one instruction. The WR and RD can not be set to "1" at the same time. Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Rev. 1.20 62 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Writing Data to the EEPROM To write data to the EEPROM, the EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. Then the write enable bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered on, the Write Enable bit in the control register will be cleared preventing any write operations. Also at power-on the Memory Pointer high byte register, MP1H or MP2H, will be reset to zero, which means that Data Memory sector 0 will be selected. As the EEPROM control register is located in sector 1, this adds a further measure of protection against spurious write operations. During normal program operation, ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. However, as the EEPROM is contained within a Multi-function Interrupt, the associated multi-function interrupt enable bit must also be set. When an EEPROM write cycle ends, the DEF request flag and its associated multi-function interrupt request flag will both be set. If the global, EEPROM and Multifunction interrupts are enabled and the stack is not full, a jump to the associated Multi-function Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag will be automatically reset, the EEPROM interrupt flag must be manually reset by the application program. Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be Periodic by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Memory Pointer high byte register could be normally cleared to zero as this would inhibit access to sector 1 where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete. Otherwise, the EEPROM read or write operation will fail. Rev. 1.20 63 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Programming Example Reading data from the EEPROM – polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, 040H MOV MP1L, A MOV A, 01H MOV MP1H, A SET IAR1.1 SET IAR1.0 BACK: SZ IAR1.0 JMP BACK CLR IAR1 CLR MP1H MOV A, EED MOV READ_DATA, A ; user defined address ; setup memory pointer low byte MP1L ; MP1L points to EEC register ; setup Memory Pointer high byte MP1H ; set RDEN bit, enable read operations ; start Read Cycle - set RD bit ; check for read cycle end ; disable EEPROM write ; move read data to register Writing Data to the EEPROM – polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, EEPROM_DATA MOV EED, A MOV A, 040H MOV MP1L, A MOV A, 01H MOV MP1H, A CLR EMI SET IAR1.3 SET IAR1.2 SET EMI BACK: SZ IAR1.2 JMP BACK CLR IAR1 CLR MP1H Rev. 1.20 ; user defined address ; user defined data ; setup memory pointer low byte MP1L ; MP1L points to EEC register ; setup Memory Pointer high byte MP1H ; set WREN bit, enable write operations ; start Write Cycle - set WR bit ; check for write cycle end ; disable EEPROM write 64 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Oscillator Various oscillator types offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of application program and relevant control registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. External oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. All oscillator options are selected through register programming. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. Note that the LXT oscillator is not integrated in the HT66FV130 device. All of the mentioned functions related to the LXT oscillator in this chapter is not available in the HT66FV130 device. Type Name Frequency Pins External High Speed Crystal HXT 400 kHz~20 MHz OSC1/OSC2 Internal High Speed RC HIRC 8/12/16 MHz — External Low Speed Crystal LXT * 32.768 kHz XT1/XT2 Internal Low Speed RC LIRC 32 kHz — Oscillator Types Device Oscillator HXT HIRC LIRC LXT HT66FV130 √ √ √ — HT66FV140 √ √ √ √ HT66FV150 √ √ √ √ HT66FV160 √ √ √ √ Oscillator Configurations System Clock Configurations There are four methods of generating the system clock, two high speed oscillators for all devices and two low speed oscillators for specific devices. The high speed oscillator is the external crystal/ ceramic oscillator, HXT, and the internal 8/12/16 MHz RC oscillator, HIRC. The two low speed oscillators are the internal 32 kHz RC oscillator, LIRC, and the external 32.768 kHz crystal oscillator, LXT. Note that the LXT oscillator is not integrated in the HT66FV130 device. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the CKS2~CKS0 bits in the SCC register and as the system clock can be dynamically selected. The actual source clock used for the low speed oscillators is chosen via the FSS bit in the SCC register while for the high speed oscillator the source clock is selected by the FHS bit in the SCC register. The frequency of the slow speed or high speed system clock is determined using the CKS2~CKS0 bits in the SCC register. Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection for either the high or low speed oscillator. Rev. 1.20 65 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU High Speed Osci��ation fH FHS fH/2 fH/4 HIRCEN HIRC fH/8 Presca�er HXTEN fH HXT fSYS fH/16 fH/32 fH/64 Low Speed Osci��ation CKS2~CKS0 fLIRC fSUB LIRC fSUB fLIRC System Clock Configurations – HT66FV130 High Speed Osci��ation fH FHS fH/2 fH/4 HIRCEN HIRC fH/8 Presca�er HXTEN fH HXT fSYS fH/16 fH/32 fH/64 Low Speed Osci��ation FSS CKS2~CKS0 LXTEN LXT fSUB fLIRC fSUB LIRC fLIRC System Clock Configurations – HT66FV140/HT66FV150/HT66FV160 External Crystal/Ceramic Oscillator – HXT The External Crystal/Ceramic System Oscillator is the high frequency oscillator, which is the default oscillator clock source after power on. For most crystal oscillator configurations, the simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. However, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer’s specification. For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the MCU as possible. Rev. 1.20 66 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Crystal/Resonator Oscillator HXT Oscillator C1 and C2 Values Crystal Frequency C1 C2 12MHz 0 pF 0 pF 8MHz 0 pF 0 pF 4MHz 0 pF 0 pF 1MHz 100 pF 100 pF Note: C1 and C2 values are for guidance only. Crystal Recommended Capacitor Values Internal High Speed RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a fixed frequency of 8/12/16 MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of 25°C degrees, the fixed oscillation frequency of 8MHz, 12MHz or 16MHz will have a tolerance within 2%. Note that if this internal system clock option is selected, as it requires no external pins for its operation, I/O pins are free for use as normal I/O pins. External 32.768 kHz Crystal Oscillator – LXT The External 32.768 kHz Crystal System Oscillator is one of the low frequency oscillator choices, which is selected via a software control bit, FSS. Note that the LXT oscillator is not integrated in the HT66FV130 device. This clock source has a fixed frequency of 32.768 kHz and requires a 32.768 kHz crystal to be connected between pins XT1 and XT2. The external resistor and capacitor components connected to the 32.768 kHz crystal are necessary to provide oscillation. For applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. After the LXT oscillator is enabled by setting the LXTEN bit to 1, there is a time delay associated with the LXT oscillator waiting for it to start-up. When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the SLEEP or IDLE Mode. To do this, another clock, independent of the system clock, must be provided. Rev. 1.20 67 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer’s specification. The external parallel feedback resistor, Rp, is required. The pin-shared software control bits determine if the XT1/XT2 pins are used for the LXT oscillator or as I/O or other pin-shared functional pins. • If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/O or other pin-shared functional pins. • If the LXT oscillator is used for any clock source, the 32.768 kHz crystal should be connected to the XT1/XT2 pins. For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the MCU as possible. External LXT Oscillator LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes, the Speed-Up Mode and the Low-Power Mode. The mode selection is executed using the LXTSP bit in the LXTC register. LXTSP LXT Operating Mode 0 Low-Power 1 Speed-Up When the LXTSP bit is set to high, the LXT Quick Start Mode will be enabled. In the Speed-Up Mode the LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has fully powered up, it can be placed into the Low-Power Mode by clearing the LXTSP bit to zero and the oscillator will continue to run bit with reduced current consumption. It is important to note that the LXT operating mode switching must be properly controlled before the LXT oscillator clock is selected as the system clock source. Once the LXT oscillator clock is selected as the system clock source using the CKS bit field and FSS bit in the SCC register, the LXT oscillator operating mode can not be changed. It should be note, that no matter what condition the LXTSP is set to, the LXT oscillator will always function normally. The only difference is that it will take more time to start up if in the Low Power Mode. Rev. 1.20 68 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Internal 32kHz Oscillator – LIRC The Internal 32 kHz System Oscillator is one of the low frequency oscillator choices, which is selected via a software control bit, FSS. It is a fully integrated RC oscillator with a typical frequency of 32 kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of 25˚C degrees, the fixed oscillation frequency of 32 kHz will have a tolerance within 10%. Supplementary Oscillators The low speed oscillators, in addition to providing a system clock source are also used to provide a clock source to two other device functions. These are the Watchdog Timer and the Time Base Interrupts. Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks Each device has different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock selections using register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency, fH, or low frequency, fSUB, source, and is selected using the CKS2~CKS0 bits in the SCC register. The high speed system clock is sourced from an HXT or HIRC oscillator, selected via configuring the FHS bit in the SCC register. The low speed system clock source can be sourced from the internal clock fSUB. If fSUB is selected then it can be sourced by either the LXT or LIRC oscillators, selected via configuring the FSS bit in the SCC register. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. Rev. 1.20 69 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU High Speed Osci��ation fH FHS fH/2 fH/4 HIRCEN HIRC fH/8 Presca�er HXTEN fH HXT fSYS fH/16 fH/32 fH/64 fLIRC CKS2~CKS0 fSUB LIRC fSUB fSYS Low Speed Osci��ation fSYS/4 fSUB fTP Presca�er Time Base fH TB0 [2:0] TB1 [2:0] CLKS0[1:0] fSYS fSYS/4 fSUB fP Presca�er Periphera� C�ock O�tp�t (PCK) fH TB2 [2:0] CLKS1[1:0] fLIRC fLIRC WDT LVR Device Clock Configurations – HT66FV130 Rev. 1.20 70 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU fH High Speed Osci��ation FHS fH/2 fH/4 HIRCEN HIRC fH/8 Presca�er HXTEN fH HXT fSYS fH/16 fH/32 fH/64 FSS LXTEN CKS2~CKS0 LXT fSUB fLIRC fSUB fSYS LIRC fSYS/4 fTP Time Base Presca�er fSUB Low Speed Osci��ation fH TB0 [2:0] TB1 [2:0] CLKS0[1:0] fSYS fSYS/4 fP Presca�er fSUB fH Periphera� C�ock O�tp�t (PCK) TB2 [2:0] CLKS1[1:0] fLIRC fLIRC WDT LVR Device Clock Configurations – HT66FV140/HT66FV150/HT66FV160 Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillation can be stopped to conserve the power or continue to oscillate to provide the clock source, fH~fH/64, for peripheral circuit to use, which is determined by configuring the corresponding high speed oscillator enable control bit. Rev. 1.20 71 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP, IDLE0, IDLE1 and IDLE2 Mode are used when the microcontroller CPU is switched off to conserve power. Operation Mode CPU NORMAL On SLOW On Register Setting FHIDEN FSIDEN CKS2~CKS0 x x x x IDLE0 Off 0 1 IDLE1 Off 1 1 IDLE2 Off 1 0 SLEEP Off 0 0 000~110 fSYS fH fH~fH/64 On 111 fSUB 000~110 Off 111 On xxx On 000~110 On 111 Off xxx Off fSUB fLIRC On On On On Off On On On On On On Off On Off Off On/Off (1) On/Off (2) Note: 1. The fH clock will be switched on or off by configuring the corresponding oscillator enable bit in the SLOW mode. 2. The fLIRC clock can be switched on or off which is controlled by the WDT function being enabled or disabled. NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. This mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the HXT or HIRC oscillators. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 bits in the SCC register.Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from fSUB. The fSUB clock is derived from either the LIRC or LXT oscillator. Note that the LXT oscillator is not integrated in the HT66FV130 device. SLEEP Mode The SLEEP Mode is entered when an HALT instruction is executed and when the FHIDEN and FSIDEN bit are low. In the SLEEP mode the CPU will be stopped. However the fLIRC clock can still continue to operate if the WDT function is enabled. IDLE0 Mode The IDLE0 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is low and the FSIDEN bit in the SCC register is high. In the IDLE0 Mode the CPU will be switched off but the low speed oscillator will be turned on to drive some peripheral functions. Rev. 1.20 72 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is high and the FSIDEN bit in the SCC register is high. In the IDLE1 Mode the CPU will be switched off but both the high and low speed oscillators will be turned on to provide a clock source to keep some peripheral functions operational. IDLE2 Mode The IDLE2 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is high and the FSIDEN bit in the SCC register is low. In the IDLE2 Mode the CPU will be switched off but the high speed oscillator will be turned on to provide a clock source to keep some peripheral functions operational. Control Registers The registers, SCC, HIRCC, HXTC and LXTC, are used to control the system clock and the corresponding oscillator configurations. Note that the LXTC register does not exist in the HT66FV130 device as the LXT oscillator is not integrated in this device. Bit Register Name 7 6 5 4 3 2 1 0 SCC CKS2 CKS1 CKS0 — FHS — FHIDEN FSIDEN HIRCC — — — — HIRC1 HIRC0 HIRCF HIRCEN HXTC — — — — — HXTM HXTF HXTEN System Operating Mode Control Registers List – HT66FV130 Bit Register Name 7 6 5 4 3 2 1 0 SCC CKS2 CKS1 CKS0 — FHS FSS FHIDEN FSIDEN HIRCC — — — — HIRC1 HIRC0 HIRCF HIRCEN HXTC — — — — — HXTM HXTF HXTEN LXTC — — — — — LXTSP LXTF LXTEN System Operating Mode Control Registers List – HT66FV140/HT66FV150/ HT66FV160 SCC Register – HT66FV130 Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 — FHS — FHIDEN FSIDEN R/W R/W R/W R/W — R/W — R/W R/W POR 0 0 0 — 0 — 0 0 Bit 7~5CKS2~CKS0: System clock selection 000: fH 001: fH/2 010: fH/4 011: fH/8 100: fH/16 101: fH/32 110: fH/64 111: fSUB These three bits are used to select which clock is used as the system clock source. In addition to the system clock source directly derived from fH or fSUB, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4 Unimplemented, read as 0. Bit 3FHS: High Frequency clock selection 0: HIRC 1: HXT Rev. 1.20 73 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Bit 2 Unimplemented, read as 0. Bit 1FHIDEN: High Frequency oscillator control when CPU is switched off 0: Disable 1: Enable This bit is used to control whether the high speed oscillator is activated or stopped when the CPU is switched off by executing an "HALT" instruction. Bit 0FSIDEN: Low Frequency oscillator control when CPU is switched off 0: Disable 1: Enable This bit is used to control whether the low speed oscillator is activated or stopped when the CPU is switched off by executing an "HALT" instruction. The LIRC oscillator is controlled by this bit together with the WDT function enable control when the LIRC is selected to be the low speed oscillator clock source or the WDT function is enabled respectively. If this bit is cleared to 0 but the WDT function is enabled, the LIRC oscillator will also be enabled. SCC Register – HT66FV140/HT66FV150/HT66FV160 Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 — FHS FSS FHIDEN FSIDEN R/W R/W R/W R/W — R/W R/W R/W R/W POR 0 0 0 — 0 0 0 0 Bit 7~5CKS2~CKS0: System clock selection 000: fH 001: fH/2 010: fH/4 011: fH/8 100: fH/16 101: fH/32 110: fH/64 111: fSUB These three bits are used to select which clock is used as the system clock source. In addition to the system clock source directly derived from fH or fSUB, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4 Unimplemented, read as 0. Bit 3FHS: High Frequency clock selection 0: HIRC 1: HXT Bit 2FSS: Low Frequency clock selection 0: LIRC 1: LXT Bit 1FHIDEN: High Frequency oscillator control when CPU is switched off 0: Disable 1: Enable This bit is used to control whether the high speed oscillator is activated or stopped when the CPU is switched off by executing an "HALT" instruction. Bit 0FSIDEN: Low Frequency oscillator control when CPU is switched off 0: Disable 1: Enable This bit is used to control whether the low speed oscillator is activated or stopped when the CPU is switched off by executing an "HALT" instruction. The LIRC oscillator is controlled by this bit together with the WDT function enable control when the LIRC is selected to be the low speed oscillator clock source or the WDT function is enabled respectively. If this bit is cleared to 0 but the WDT function is enabled, the LIRC oscillator will also be enabled. Rev. 1.20 74 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU HIRCC Register Bit 7 6 5 4 3 2 1 0 Name — — — — HIRC1 HIRC0 HIRCF HIRCEN R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 1 Bit 7~2 Unimplemented, read as 0. Bit 3~2HIRC1~HIRC0: HIRC frequency selection 00: 8 MHz 01: 12 MHz 10: 16 MHz 11: 8 MHz When the HIRC oscillator is enabled or the HIRC frequency selection is changed by application program, the clock frequency will automatically be changed after the HIRCF flag is set to 1. Bit 1HIRCF: HIRC oscillator stable flag 0: HIRC unstable 1: HIRC stable This bit is used to indicate whether the HIRC oscillator is stable or not. When the HIRCEN bit is set to 1 to enable the HIRC oscillator or the HIRC frequency selection is changed by application program, the HIRCF bit will first be cleared to 0 and then set to 1 after the HIRC oscillator is stable. Bit 0HIRCEN: HIRC oscillator enable control 0: Disable 1: Enable HXTC Register Bit 7 6 5 4 3 2 1 0 Name — — — — — HXTM HXTF HXTEN R/W — — — — — R/W R R/W POR — — — — — 0 0 0 Bit 7~3 Unimplemented, read as 0. Bit 2HXTM: HXT mode selection 0: HXT frequency ≤ 10 MHz 1: HXT frequency >10 MHz This bit is used to select the HXT oscillator operating mode. Note that this bit must be properly configured before the HXT is enabled. When the HXTEN bit is set to 1 to enable the HXT oscillator, it is invalid to change the value of this bit. Bit 1HXTF: HXT oscillator stable flag 0: HXT unstable 1: HXT stable This bit is used to indicate whether the HXT oscillator is stable or not. When the HXTEN bit is set to 1 to enable the HXT oscillator, the HXTF bit will first be cleared to 0 and then set to 1 after the HXT oscillator is stable. Bit 0HXTEN: HXT oscillator enable control 0: Disable 1: Enable Rev. 1.20 75 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU LXTC Register – HT66FV140/HT66FV150/HT66FV160 Bit 7 6 5 4 3 2 1 0 Name — — — — — LXTSP LXTF LXTEN R/W — — — — — RW R R/W POR — — — — — 0 0 0 Bit 7~3 Unimplemented, read as 0. Bit 2LXTSP: LXT oscillator speed-up control 0: Disable – Low power 1: Enable – Speed up This bit is used to control whether the LXT oscillator is operating in the low power or quick start mode. When the LXTSP bit is set to 1, the LXT oscillator will oscillate quickly but consume more power. If the LXTSP bit is cleared to 0, the LXT oscillator will consume less power but take longer time to stablise. It is important to note that this bit can not be changed after the LXT oscillator is selected as the system clock source using the CKS2~CKS0 and FSS bits in the SCC register. Bit 1LXTF: LXT oscillator stable flag 0: LXT unstable 1: LXT stable This bit is used to indicate whether the LXT oscillator is stable or not. When the LXTEN bit is set to 1 to enable the LXT oscillator, the LXTF bit will first be cleared to 0 and then set to 1 after the LXT oscillator is stable. Bit 0LXTEN: LXT oscillator enable control 0: Disable 1: Enable Rev. 1.20 76 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Operating Mode Switching The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the CKS2~CKS0 bits in the SCC register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When an HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the FHIDEN and FSIDEN bits in the SCC register. SLOW fSYS=fSUB fSUB on CPU r�n fSYS on fH on/off NORMAL fSYS=fH~fH/64 fH on CPU r�n fSYS on fSUB on SLEEP HALT instr�ction exec�ted CPU stop FHIDEN=0 FSIDEN=0 fH off fSUB off IDLE0 HALT instr�ction exec�ted CPU stop FHIDEN=0 FSIDEN=1 fH off fSUB on IDLE2 HALT instr�ction exec�ted CPU stop FHIDEN=1 FSIDEN=0 fH on fSUB off Rev. 1.20 77 IDLE1 HALT instr�ction exec�ted CPU stop FHIDEN=1 FSIDEN=1 fH on fSUB on July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the CKS2~CKS0 bits to "111" in the SCC register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LXT or LIRC oscillator determined by the FSS bit in the SCC register and therefore requires this oscillator to be stable before full mode switching occurs. NORMAL Mode CKS2~CKS0 = 111 SLOW Mode FHIDEN=0� FSIDEN=0 HALT instr�ction is exec�ted SLEEP Mode FHIDEN=0� FSIDEN=1 HALT instr�ction is exec�ted IDLE0 Mode FHIDEN=1� FSIDEN=1 HALT instr�ction is exec�ted IDLE1 Mode FHIDEN=1� FSIDEN=0 HALT instr�ction is exec�ted IDLE2 Mode Rev. 1.20 78 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU SLOW Mode to NORMAL Mode Switching In SLOW mode the system clock is derived from fSUB. When system clock is switched back to the NORMAL mode from fSUB, the CKS2~CKS0 bits should be set to "000" ~"110" and then the system clock will respectively be switched to fH~ fH/64. However, if fH is not used in SLOW mode and thus switched off, it will take some time to reoscillate and stabilise when switching to the NORMAL mode from the SLOW Mode. This is monitored using the HXTF bit in the HXTC register or the HIRCF bit in the HIRCC register. The time duration required for the high speed system oscillator stabilization is specified in the A.C. characteristics. SLOW Mode CKS2~CKS0 = 000~110 NORMAL Mode FHIDEN=0� FSIDEN=0 HALT instr�ction is exec�ted SLEEP Mode FHIDEN=0� FSIDEN=1 HALT instr�ction is exec�ted IDLE0 Mode FHIDEN=1� FSIDEN=1 HALT instr�ction is exec�ted IDLE1 Mode FHIDEN=1� FSIDEN=0 HALT instr�ction is exec�ted IDLE2 Mode Entering the SLEEP Mode There is only one way for the device to enter the SLEEP Mode and that is to execute the "HALT" instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register equal to "0". In this mode all the clocks and functions will be switched off except the WDT function. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting if the WDT function is enabled. If the WDT function is disabled, the WDT will be cleared and stopped. Rev. 1.20 79 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT" instruction in the application program with the FHIDEN bit in the SCC register equal to "0" and the FSIDEN bit in the SCC register equal to "1". When this instruction is executed under the conditions described above, the following will occur: • The fH clock will be stopped and the application program will stop at the "HALT" instruction, but the fSUB clock will be on. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting if the WDT function is enabled. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the "HALT" instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register equal to "1". When this instruction is executed under the conditions described above, the following will occur: • The fH and fSUB clocks will be on but the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting if the WDT function is enabled. Entering the IDLE2 Mode There is only one way for the device to enter the IDLE2 Mode and that is to execute the "HALT" instruction in the application program with the FHIDEN bit in the SCC register equal to "1" and the FSIDEN bit in the SCC register equal to "0". When this instruction is executed under the conditions described above, the following will occur: • The fH clock will be on but the fSUB clock will be off and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting if the WDT function is enabled. Rev. 1.20 80 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 and IDLE2 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the LIRC oscillator has enabled. In the IDLE1 and IDLE 2 Mode the high speed oscillator is on, if the peripheral function clock source is derived from the high speed oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. Wake-up To minimise power consumption the device can enter the SLEEP or any IDLE Mode, where the CPU will be switched off. However, when the device is woken up again, it will take a considerable time for the original system oscillator to restart, stablise and allow normal operation to resume. After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external falling edge on Port A • A system interrupt • A WDT overflow When the device executes the "HALT" instruction, the PDF flag will be set to 1. The PDF flag will be cleared to 0 if the device experiences a system power-up or executes the clear Watchdog Timer instruction. If the system is woken up by a WDT overflow, a Watchdog Timer reset will be initiated and the TO flag will be set to 1. The TO flag is set if a WDT time-out occurs and causes a wake-up that only resets the Program Counter and Stack Pointer, other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HALT" instruction. In this situation, the interrupt which woke up the device will not be immediately serviced, but wukk rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Rev. 1.20 81 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal RC oscillator, fLIRC. The LIRC internal oscillator has an approximate frequency of 32 kHz and this specified internal clock period can vary with VDD, temperature and process variations. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable operation. This register controls the overall operation of the Watchdog Timer. WDTC Register Bit Register Name 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~3WE4~WE0: WDT function enable control 10101: Disabled 01010: Enabled Other values: Reset MCU If these bits are changed due to adverse environmental conditions, the microcontroller will be reset. The reset operation will be activated after 2~3 LIRC clock cycles and the WRF bit in the RSTFC register will be set to 1. Bit 2~0WS2~WS0: WDT time-out period selection 000: 28/fLIRC 001: 210/fLIRC 010: 212/fLIRC 011: 214/fLIRC 100: 215/fLIRC 101: 216/fLIRC 110: 217/fLIRC 111: 218/fLIRC These three bits determine the division ratio of the watchdog timer source clock, which in turn determines the time-out period. Rev. 1.20 82 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU RSTFC Register Bit Register Name 7 6 5 4 3 2 1 0 Name — — — — RSTF LVRF LRF WRF R/W — — — — R/W R/W R/W R/W POR — — — — 0 x 0 0 "x": unknown Bit 7~4 Unimplemented, read as "0" Bit 3RSTF: Reset control register software reset flag Described elsewhere. Bit 2LVRF: LVR function reset flag Described elsewhere. Bit 1LRF: LVR control register software reset flag Described elsewhere. Bit 0WRF: WDT control register software reset flag 0: Not occurred 1: Occurred This bit is set to 1 by the WDT control register software reset and cleared by the application program. Note that this bit can only be cleared to 0 by the application program. Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instruction. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, the clear instruction will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. With regard to the Watchdog Timer enable/disable function, there are five bits, WE4~WE0, in the WDTC register to offer the enable/disable control and reset control of the Watchdog Timer. The WDT function will be disabled when the WE4~WE0 bits are set to a value of 10101B while the WDT function will be enabled if the WE4~WE0 bits are equal to 01010B. If the WE4~WE0 bits are set to any other values, other than 01010B and 10101B, it will reset the device after 2~3 fLIRC clock cycles. After power on these bits will have a value of 01010B. WE4 ~ WE0 Bits WDT Function 10101B Disable 01010B Enable Any other value Reset MCU Watchdog Timer Enable/Disable Control Rev. 1.20 83 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is a WDT reset, which means a certain value except 01010B and 10101B written into the WE4~WE0 field, the second is using the Watchdog Timer software clear instruction and the third is via a HALT instruction. There is only one method of using software instruction to clear the Watchdog Timer. That is to use the single "CLR WDT" instruction to clear the WDT contents. The maximum time out period is when the 218 division ratio is selected. As an example, with a 32 kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 218 division ratio and a minimum timeout of 7.8ms for the 28 division ration. WDTC WE4~WE0 bits Register Reset MCU CLR “HALT”Instr�ction “CLR WDT”Instr�ction LIRC fLIRC 8-stage Divider fLIRC/28 WS2~WS0 (fLIRC/28 ~ fLIRC/218) WDT Presca�er 8-to-1 MUX WDT Time-o�t (28/fLIRC ~ 218/fLIRC ) Watchdog timer Rev. 1.20 84 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, another reset exists in the form of a Low Voltage Reset, LVR, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both internally and externally. Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. VDD Power-on Reset tRSTD SST Time-o�t Note: tRSTD is power-on delay with typical time = 50 ms Power-On Reset Timing Chart Internal Reset Control There is an internal reset control register, RSTC, which is used to provide a reset when the device operates abnormally due to the environmental noise interference. If the content of the RSTC register is set to any value other than 01010101B or 10101010B, it will reset the device after 2~3 fLIRC clock cycles. After power on the register will have a value of 01010101B. RSTC7 ~ RSTC0 Bits Reset Function 01010101B No operation 10101010B No operation Any other value Reset MCU Internal Reset Function Control Rev. 1.20 85 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU • RSTC Register Bit Register Name 7 6 5 4 3 2 1 0 Name RSTC7 RSTC6 RSTC5 RSTC4 RSTC3 RSTC2 RSTC1 RSTC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7~0RSTC7~RSTC0: Reset function control 01010101: No operation 10101010: No operation Other values: Reset MCU If these bits are changed due to adverse environmental conditions, the microcontroller will be reset. The reset operation will be activated after 2~3 LIRC clock cycles and the RSTF bit in the RSTFC register will be set to 1. • RSTFC Register Bit Register Name 7 6 5 4 3 2 1 0 Name — — — — RSTF LVRF LRF WRF R/W — — — — R/W R/W R/W R/W POR — — — — 0 x 0 0 "x": unknown Bit 7~4 Unimplemented, read as "0" Bit 3RSTF: Reset control register software reset flag 0: Not occurred 1: Occurred This bit is set to 1 by the RSTC control register software reset and cleared by the application program. Note that this bit can only be cleared to 0 by the application program. Bit 2LVRF: LVR function reset flag Described elsewhere. Bit 1LRF: LVR control register software reset flag Described elsewhere. Bit 0WRF: WDT control register software reset flag Described elsewhere. Rev. 1.20 86 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is always enabled with a specific LVR voltage, VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally and the LVRF bit in the RSTFC register will also be set to 1. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~ VLVR must exist for a time greater than that specified by tLVR in the LVD/LVR characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR value can be selected by the LVS bits in the LVRC register. If the LVS7~LVS0 bits have any other value, which may perhaps occur due to adverse environmental conditions such as noise, the LVR will reset the device after 2~3 fLIRC clock cycles. When this happens, the LRF bit in the RSTFC register will be set to 1. After power on the register will have the value of 01010101B. Note that the LVR function will be automatically disabled when the device enters the power down mode. Note: tRSTD is power-on delay with typical time = 50 ms Low Voltage Reset Timing Chart • LVRC Register Bit Register Name 7 6 5 4 3 2 1 0 Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7~0LVS7~LVS0: LVR voltage select 01010101: 2.1V 00110011: 2.55V 10011001: 3.15V 10101010: 3.8V Other values: Generates a MCU reset – register is reset to POR value When an actual low voltage condition occurs, as specified by one of the four defined LVR voltage value above, an MCU reset will generated. The reset operation will be activated after 2~3 fLIRC clock cycles. In this situation the register contents will remain the same after such a reset occurs. Any register value, other than the four defined register values above, will also result in the generation of an MCU reset. The reset operation will be activated after 2~3 fLIRC clock cycles. However in this situation the register contents will be reset to the POR value. Rev. 1.20 87 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU • RSTFC Register Bit Register Name 7 6 5 4 3 2 1 0 Name — — — — RSTF LVRF LRF WRF R/W — — — — R/W R/W R/W R/W POR — — — — 0 x 0 0 "x": unknown Bit 7~4 Unimplemented, read as "0" Bit 3RSTF: Reset control register software reset flag Described elsewhere. Bit 2LVRF: LVR function reset flag 0: Not occurred 1: Occurred This bit is set to 1 when a specific low voltage reset condition occurs. Note that this bit can only be cleared to 0 by the application program. Bit 1LRF: LVR control register software reset flag 0: Not occurred 1: Occurred This bit is set to 1 by the LVRC control register contains any undefined LVR voltage register values. This in effect acts like a software-reset function. Note that this bit can only be cleared to 0 by the application program. Bit 0WRF: WDT control register software reset flag Described elsewhere. Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as the hardware Low Voltage Reset except that the Watchdog time-out flag TO will be set to "1". Note: tRSTD is power-on delay with typical time = 16.7 ms WDT Time-out Reset during NORMAL Operation Timing Chart Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for tSST details. WDT Time-out Reset during SLEEP or IDLE Mode Timing Chart Rev. 1.20 88 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF Reset Function 0 0 Power-on reset u u LVR reset during NORMAL or SLOW Mode operation 1 u WDT time-out reset during NORMAL or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation "u" stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Reset Function Program Counter Reset to zero Interrupts All interrupts will be disabled WDT, Time Base Clear after reset, WDT begins counting Timer Modules Timer Modules will be turned off Input/Output Ports I/O ports will be setup as inputs Stack pointer Stack pointer will point to the top of the stack The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects the microcontroller internal registers. HT66FV130 HT66FV140 HT66FV150 HT66FV160 Reset (Power On) IAR0 ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP0 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu IAR1 ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP1L ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu MP1H ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ACC ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL ● ● ● ● 0000 0000 0000 0000 0000 0000 0000 0000 TBLP ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBHP ● ---- -xxx - - - - - uuu - - - - - uuu - - - - - uuu ---- xxxx - - - - uuuu - - - - uuuu - - - - uuuu ---x xxxx - - - u uuuu - - - u uuuu - - - u uuuu --xx xxxx - - uu uuuu - - uu uuuu - - uu uuuu Register ● TBHP ● TBHP ● TBHP LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP)* ● 0000 0000 0000 0000 0000 0000 uuuu uuuu STATUS ● ● ● ● xx00 xxxx uuuu uuuu x x 1 u uuuu uu 11 uuuu IAR2 ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP2L ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu MP2H ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PBP Rev. 1.20 89 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU HT66FV130 HT66FV140 HT66FV150 HT66FV160 Reset (Power On) INTC0 ● ● ● ● -000 0000 PA ● Register ● PA PAC ● ● ● ● ● ● PAWU RSTFC ● ● PAPU PAWU ● ● PAC PAPU ● ● LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP)* -000 0000 -000 0000 - uuu uuuu 11 - - - 111 11 - - - 111 11 - - - 111 uu - - - uuu 1111 1111 1111 1111 1111 1111 uuuu uuuu 11 - - - 111 11 - - - 111 11 - - - 111 uu - - - uuu 1111 1111 1111 1111 1111 1111 uuuu uuuu 00-- -000 00-- -000 00-- -000 uu - - - uuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 00-- -000 00-- -000 00-- -000 uu - - - uuu ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ● ● ● ---- 0x00 - - - - uuuu - - - - uuuu - - - - uuuu - - - - 1111 - - - - 1111 - - - - 1111 - - - - uuuu 1111 1111 1111 1111 1111 1111 uuuu uuuu - - - - 1111 - - - - 1111 - - - - 1111 - - - - uuuu 1111 1111 1111 1111 1111 1111 uuuu uuuu ● PE ● PE ● PEC ● PEC ● PEPU PEPU ---- 0000 ---- 0000 ---- 0000 - - - - uuuu ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PB ● ● ● ● - - - - - 111 - - - - - 111 - - - - - 111 - - - - - uuu PBC ● ● ● ● - - - - - 111 - - - - - 111 - - - - - 111 - - - - - uuu PBPU ● ● ● ● ---- -000 ---- -000 ---- -000 - - - - - uuu PSCR ● ● ● ● ---- --00 ---- --00 ---- --00 - - - - - - uu TB0C ● ● ● ● 0--- -000 0--- -000 0--- -000 u - - - - uuu TB1C ● ● ● ● 0--- -000 0--- -000 0--- -000 u - - - - uuu SCC ● 000- 0-00 000- 0-00 000- 0-00 uuu - u - uu SCC ● ● ● 000- 0000 000- 0000 000- 0000 uuu - uuuu HIRCC ● ● ● ● ---- 0001 ---- 0001 ---- 0001 - - - - uuuu HXTC ● ● ● ● ---- -000 ---- -001 ---- -001 - - - - - uuu ● ● ● ---- -000 ---- -000 ---- -000 - - - - - uuu LXTC RSTC ● ● ● ● 0101 0101 0101 0101 0101 0101 uuuu uuuu CTM0C0 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM0C1 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM0DL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM0DH ● ● ● ● ---- --00 ---- --00 ---- --00 - - - - - - uu CTM0AL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM0AH ● ● ● ● ---- --00 ---- --00 ---- --00 - - - - - - uu LVDC ● ● ● ● --00 -000 --00 -000 --00 -000 - - uu - uuu LVRC ● ● ● ● 0101 0101 0101 0101 0101 0101 uuuu uuuu PTM0C0 ● ● ● ● 0000 0--- 0000 0--- 0000 0--- uuuu u - - - PTM0C1 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM0DL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM0DH ● ● ● ● ---- --00 ---- --00 ---- --00 - - - - - - uu PTM0AL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM0AH ● ● ● ● ---- --00 ---- --00 ---- --00 - - - - - - uu PTM0RPL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM0RPH ● ● ● ● ---- --00 ---- --00 ---- --00 - - - - - - uu INTEG ● ● ● ● ---- 0000 ---- 0000 ---- 0000 - - - - uuuu Rev. 1.20 90 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU HT66FV150 HT66FV160 Reset (Power On) ● ● ● 0000 0000 ● INTC1 INTC2 HT66FV140 INTC1 HT66FV130 Register ● ● ● INTC2 MFI0 ● ● ● MFI0 MFI1 ● ● ● MFI3 ● ● MFI1 MFI2 ● ● ● SCOMC SADC2 ● EEA ● ● 000- 000- 000- 000- uuu - uuu - 0000 0000 0000 0000 uuuu uuuu --00 --00 --00 --00 --00 --00 - - uu - - uu -000 -000 -000 -000 -000 -000 - uuu - uuu --00 --00 --00 --00 --00 --00 - - uu - - uu 0000 0000 0000 0000 0000 0000 uuuu uuuu --00 --00 --00 --00 - - uu - - uu 0000 0000 0000 0000 uuuu uuuu ● --00 --00 --00 --00 --00 --00 - - uu - - uu 00-0 00-0 00-0 00-0 00-0 00-0 uu - u uu - u ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ● ● -000 ---- -000 ---- -000 ---- - uuu - - - - ● ● 00-- 0000 00-- 0000 00-- 0000 uu - - uuuu ---0 0000 ---0 0000 ---0 0000 - - - u uuuu --00 0000 --00 0000 --00 0000 - - uu uuuu -000 0000 -000 0000 -000 0000 - uuu uuuu ● 0000 0000 0000 0000 0000 0000 uuuu uuuu EEA ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM1C0 ● ● ● 0000 0--- 0000 0--- 0000 0--- uuuu u - - - PTM1C1 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM1DL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM1DH ● ● ● ---- --00 ---- --00 ---- --00 - - - - - - uu PTM1AL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM1AH ● ● ● ---- --00 ---- --00 ---- --00 - - - - - - uu PTM1RPL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM1RPH ● ● ● ---- --00 ---- --00 ---- --00 - - - - - - uu ● ● ● 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 uuuu uuuu 0000 -000 0000 -000 0000 -000 uuuu - uuu 0000 0000 0000 0000 uuuu uuuu EED ● 000- 000- 0000 0000 ● EEA WDT Time-out (IDLE or SLEEP)* --00 --00 ● EEA WDT Time-out (Normal Operation) ● ● MFI3 LVR Reset (Normal Operation) WDTC ● PCPU ● PCPU PC ● ● 0000 0000 1111 - 111 1111 - 111 1111 - 111 uuuu - uuu ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 - 111 1111 - 111 1111 - 111 uuuu - uuu 1111 1111 1111 1111 1111 1111 uuuu uuuu ---- 0000 ---- 0000 ---- 0000 - - - - uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu - - - - 1111 - - - - 1111 - - - - 1111 - - - - uuuu 1111 1111 1111 1111 1111 1111 uuuu uuuu - - - - 1111 - - - - 1111 - - - - 1111 - - - - uuuu ● 1111 1111 1111 1111 1111 1111 uuuu uuuu ● PC PCC ● ● ● PCC ● ● ● PDPU ● PDPU ● PD ● PD ● PDC PDC SADOL (ADRFS=0) ● ● ● ● xxxx ---- xxxx ---- xxxx ---- uuuu - - - - SADOL (ADRFS=1) ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu SADOH (ADRFS=0) ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu Rev. 1.20 91 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU HT66FV140 ● ● SADC0 ● ● SADC1 ● ● PAS0 ● ● PAS0 PAS1 Reset (Power On) LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP)* ● ● ---- xxxx - - - - uuuu - - - - uuuu - - - - uuuu ● ● 0000 -000 0000 -000 0000 -000 uuuu - uuu ● ● 000- -000 000- -000 000- -000 uuu - - uuu --00 0000 --00 0000 --00 0000 - - uu uuuu ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 ---- 0000 ---- 0000 ---- uuuu - - - - ● PAS1 PBS0 ● PCS0 ● PCS0 PCS1 HT66FV160 HT66FV130 SADOH (ADRFS=1) HT66FV150 Register ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ● ● ● --00 0000 --00 0000 --00 0000 - - uu uuuu --00 0000 --00 0000 --00 0000 - - uu uuuu ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ---- 00-- ---- 00-- ---- 00-- - - - - uu - - --00 00-- --00 00-- --00 00-- - - uu uu - - 000 00-- 0000 00-- 0000 00-- uuuu uu - - ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PDS0 PDS1 IFS ● ● IFS ● IFS IFS SIMTOC ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu SIMC0 ● ● ● 111 - - - 0 0 111 - - - 0 0 111 - - - 0 0 uuu - - - uu SIMC1 ● ● ● 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMD ● ● ● xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMA/ SIMC2 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu SPIAC0 ● ● ● ● 111 - - - 0 0 111 - - - 0 0 111 - - - 0 0 uuu - - - uu SPIAC1 ● ● ● ● --00 0000 --00 0000 --00 0000 - - uu uuuu SPIAD ● ● ● ● xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu USR ● ● 0--- 0000 0--- 0000 0--- 0000 u - - - uuuu UCR1 ● ● - 0 11 1111 - 0 11 1111 - 0 11 1111 - uuu uuuu UCR2 ● ● 1000 0000 1000 0000 1000 0000 1 uuu uuuu TXR_RXR ● ● 1000 0000 1000 0000 1000 0000 uuuu uuuu BRG ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu --00 0000 --00 0000 --00 0000 - - uu uuuu SLEDC0 ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu SLEDC1 ● ● ---- --00 ---- --00 ---- --00 - - - - - - uu SLEDC0 ● ● USVC ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu u 0 0 0 PLAC ● ● ● ● ---- --00 ---- --00 ---- --00 - - - - - - uu PLADL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PLADH ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM1C0 ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM1C1 ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM1DL ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM1DH ● ● ---- --00 ---- --00 ---- --00 - - - - - - uu CTM1AL ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PES0 PES1 Rev. 1.20 92 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU HT66FV150 HT66FV160 HT66FV140 HT66FV130 Reset (Power On) ● ● ---- --00 ---- --00 ---- --00 - - - - - - uu STM0C0 ● 0000 0--- 0000 0--- 0000 0--- uuuu u - - - STM0C1 ● 0000 0000 0000 0000 0000 0000 uuuu uuuu STM0DL ● 0000 0000 0000 0000 0000 0000 uuuu uuuu STM0DH ● 0000 0000 0000 0000 0000 0000 uuuu uuuu STM0AL ● 0000 0000 0000 0000 0000 0000 uuuu uuuu STM0AH ● 0000 0000 0000 0000 0000 0000 uuuu uuuu STM0RP ● 0000 0000 0000 0000 0000 0000 uuuu uuuu Register CTM1AH LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP)* EEC ● ● ● ● ---- 0000 ---- 0000 ---- 0000 - - - - uuuu FC0 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FC1 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ● ● ---- ---0 ---- ---0 ---- ---0 ---- ---u ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ---- -000 ---- -000 ---- -000 - - - - - uuu ---- 0000 ---- 0000 ---- 0000 - - - - uuuu ---0 0000 ---0 0000 ---0 0000 - - - u uuuu ● --00 0000 --00 0000 --00 0000 - - uu uuuu FC2 FARL ● FARH ● ● ● FARH ● FARH FARH FD0L ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FD0H ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FD1L ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FD1H ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FD2L ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FD2H ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FD3L ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FD3H ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu Note: "u" stands for unchanged "x" stands for "unknown" "-" stands for unimplemented Rev. 1.20 93 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. These devices provide bidirectional input/output lines labeled with port names PA~PE. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction "MOV A, [m]", where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Bit Register Name 7 6 5 4 3 2 1 0 PAWU PAWU7 PAWU6 — — — PAWU2 PAWU1 PAWU0 PA PA7 PA6 — — — PA2 PA1 PA0 PAC PAC7 PAC6 — — — PAC2 PAC1 PAC0 PAPU PAPU7 PAPU6 — — — PAPU2 PAPU1 PAPU0 PB — — — — — PB2 PB1 PB0 PBC — — — — — PBC2 PBC1 PBC0 PBPU — — — — — PBPU2 PBPU1 PBPU0 PC PC7 PC6 PC5 PC4 — PC2 PC1 PC0 PCC PCC7 PCC6 PCC5 PCC4 — PCC2 PCC1 PCC0 PCPU PCPU7 PCPU6 PCPU5 PCPU4 — PCPU2 PCPU1 PCPU0 I/O Registers List – HT66FV130 Bit Register Name 7 6 5 4 3 2 1 0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PB — — — — — PB2 PB1 PB0 PBC — — — — — PBC2 PBC1 PBC0 PBPU0 PBPU — — — — — PBPU2 PBPU1 PC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PCC PCC7 PCC6 PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 PCPU PCPU7 PCPU6 PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 I/O Registers List – HT66FV140 Rev. 1.20 94 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Bit Register Name 7 6 5 4 3 2 1 0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PB — — — — — PB2 PB1 PB0 PBC — — — — — PBC2 PBC1 PBC0 PBPU — — — — — PBPU2 PBPU1 PBPU0 PC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PCC PCC7 PCC6 PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 PCPU PCPU7 PCPU6 PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 PD — — — — PD3 PD2 PD1 PD0 PDC — — — — PDC3 PDC2 PDC1 PDC0 PDPU — — — — PDPU3 PDPU2 PDPU1 PDPU0 PE — — — — PE3 PE2 PE1 PE0 PEC — — — — PEC3 PEC2 PEC1 PEC0 PEPU — — — — PEPU3 PEPU2 PEPU1 PEPU0 I/O Registers List – HT66FV150 Bit Register Name 7 6 5 4 3 2 1 0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PB — — — — — PB2 PB1 PB0 PBC — — — — — PBC2 PBC1 PBC0 PBPU0 PBPU — — — — — PBPU2 PBPU1 PC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PCC PCC7 PCC6 PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 PCPU PCPU7 PCPU6 PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 PD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PDC PDC7 PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 PDPU PDPU7 PDPU6 PDPU5 PDPU4 PDPU3 PDPU2 PDPU1 PDPU0 PE PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PEC PEC7 PEC6 PEC5 PEC4 PEC3 PEC2 PEC1 PEC0 PEPU PEPU7 PEPU6 PEPU5 PEPU4 PEPU3 PEPU2 PEPU1 PEPU0 I/O Registers List – HT66FV160 "—": Unimplemented, read as "0". PAWUn: Port A Pin wake-up function control 0: Disable 1: Enable PAPUn/PBPUn/PCPUn/PDPUn/PEPUn: I/O Pin pull-high function control 0: Disable 1: Enable PAn/PBn/PCn/PDn/PEn: I/O Port Data bit 0: Data 0 1: Data 1 PACn/PBCn/PCCn/PDCn/PECn: I/O Pin type selection 0: Output 1: Input Rev. 1.20 95 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using the relevant pull-high control registers and are implemented using weak PMOS transistors. Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. I/O Port Control Registers Each Port has its own control register, known as PAC~PEC, which controls the input/output configuration. With this control register, each I/O pin with or without pull-high resistors can be reconfigured dynamically under software control. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a "1". This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a "0", the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. I/O Port Source Current Control These devices support different source current driving capability for each I/O port. With the corresponding selection register, SLEDC0 and SLEDC1, each I/O port can support four levels of the source current driving capability. Users should refer to the D.C. characteristics section to select the desired source current for different applications. Bit Register Name SLEDC0 (HT66FV130/HT66FV140) 7 6 — — 5 4 3 2 1 0 PCPS1 PCPS0 PBPS1 PBPS0 PAPS1 PAPS0 SLEDC0 PDPS1 PDPS0 PCPS1 PCPS0 PBPS1 PBPS0 PAPS1 PAPS0 (HT66FV150/HT66FV160) SLEDC1 (HT66FV150/HT66FV160) — — — — — — PEPS1 PEPS0 I/O Port Source Current Control Registers List Rev. 1.20 96 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU SLEDC0 Register – HT66FV130/HT66FV140 Bit Register Name 7 6 5 4 3 2 1 0 Name — — PCPS1 PCPS0 PBPS1 PBPS0 PAPS1 PAPS0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 "—" Unimplemented, read as 0 Bit 5~4PCPS1~PCP0: Port C source current selection 00: source current = Level 0 (min.) 01: source current = Level 1 10: source current = Level 2 11: source current = Level 3 (max.) Bit 3~2PBPS1~PBP0: Port B source current selection 00: source current = Level 0 (min.) 01: source current = Level 1 10: source current = Level 2 11: source current = Level 3 (max.) Bit 1~0PAPS1~PAP0: Port A source current selection 00: source current = Level 0 (min.) 01: source current = Level 1 10: source current = Level 2 11: source current = Level 3 (max.) SLEDC0 Register – HT66FV150/HT66FV160 Bit Register Name 7 6 5 4 3 2 1 0 Name PDPS1 PDPS0 PCPS1 PCPS0 PBPS1 PBPS0 PAPS1 PAPS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PDPS1~PDP0: Port D source current selection 00: source current = Level 0 (min.) 01: source current = Level 1 10: source current = Level 2 11: source current = Level 3 (max.) Bit 5~4PCPS1~PCP0: Port C source current selection 00: source current = Level 0 (min.) 01: source current = Level 1 10: source current = Level 2 11: source current = Level 3 (max.) Bit 3~2PBPS1~PBP0: Port B source current selection 00: source current = Level 0 (min.) 01: source current = Level 1 10: source current = Level 2 11: source current = Level 3 (max.) Bit 1~0PAPS1~PAP0: Port A source current selection 00: source current = Level 0 (min.) 01: source current = Level 1 10: source current = Level 2 11: source current = Level 3 (max.) Rev. 1.20 97 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU SLEDC1 Register – HT66FV150/HT66FV160 Bit Register Name 7 6 5 4 3 2 1 0 Name — — — — — — PEPS1 PEPS0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 "—" Unimplemented, read as 0 Bit 1~0PEPS1~PEP0: Port E source current selection 00: source current = Level 0 (min.) 01: source current = Level 1 10: source current = Level 2 11: source current = Level 3 (max.) Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For these pins, the desired function of the multi-function I/O pins is selected by a series of registers via the application program control. Pin-shared Function Selection Registers The limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. However by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. Each device includes Port "x" output function Selection register "n", labeled as PxSn, and Input Function Selection register, labeled as IFS, which can select the desired functions of the multi-function pin-shared pins. When the pin-shared input function is selected to be used, the corresponding input and output functions selection should be properly managed. For example, if the I2C SDA line is used, the corresponding output pin-shared function should be configured as the SDI/SDA function by configuring the PxSn register. However, if the external interrupt function is selected to be used, the relevant output pin-shared function should be selected as an INTn pin and the interrupt input signal should be selected. The most important point to note is to make sure that the desired pin-shared function is properly selected and also deselected. To select the desired pin-shared function, the pin-shared function should first be correctly selected using the corresponding pin-shared control register. After that the corresponding peripheral functional setting should be configured and then the peripheral function can be enabled. To correctly deselect the pin-shared function, the peripheral function should first be disabled and then the corresponding pin-shared function control register can be modified to select other pin-shared functions. Bit Register Name 7 6 5 4 3 2 1 0 PAS0 — — PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 PAS1 PAS17 PAS16 PAS15 PAS14 — — — — PBS0 — — PBS05 PBS04 PBS03 PBS02 PBS01 PBS00 PCS0 — — PCS05 PCS04 PCS03 PCS02 PCS01 PCS00 PCS1 PCS17 PCS16 PCS15 PCS14 PCS13 PCS12 PCS11 PCS10 IFS — — — — IFS3 IFS2 — — Pin-shared Function Selection Registers List – HT66FV130 Rev. 1.20 98 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Bit Register Name 7 6 5 4 3 2 1 0 PAS0 PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 PAS1 PAS17 PAS16 PAS15 PAS14 PAS13 PAS12 PAS11 PAS10 PBS0 — — PBS05 PBS04 PBS03 PBS02 PBS01 PBS00 PCS0 PCS07 PCS06 PCS05 PCS04 PCS03 PCS02 PCS01 PCS00 PCS1 PCS17 PCS16 PCS15 PCS14 PCS13 PCS12 PCS11 PCS10 IFS — — IFS5 IFS4 IFS3 IFS2 — — Pin-shared Function Selection Registers List – HT66FV140 Bit Register Name 7 6 5 4 3 2 1 0 PAS0 PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 PAS1 PAS17 PAS16 PAS15 PAS14 PAS13 PAS12 PAS11 PAS10 PBS0 — — PBS05 PBS04 PBS03 PBS02 PBS01 PBS00 PCS0 PCS07 PCS06 PCS05 PCS04 PCS03 PCS02 PCS01 PCS00 PCS1 PCS17 PCS16 PCS15 PCS14 PCS13 PCS12 PCS11 PCS10 PDS0 PDS07 PDS06 PDS05 PDS04 PDS03 PDS02 PDS01 PDS00 PES0 PES07 PES06 PES05 PES04 PES03 PES02 PES01 PES00 IFS IFS7 IFS6 IFS5 IFS4 IFS3 IFS2 — — 0 Pin-shared Function Selection Registers List – HT66FV150 Register Name Bit 7 6 5 4 3 2 1 PAS0 PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 PAS1 PAS17 PAS16 PAS15 PAS14 PAS13 PAS12 PAS11 PAS10 PBS0 — — PBS05 PBS04 PBS03 PBS02 PBS01 PBS00 PCS0 PCS07 PCS06 PCS05 PCS04 PCS03 PCS02 PCS01 PCS00 PCS10 PCS1 PCS17 PCS16 PCS15 PCS14 PCS13 PCS12 PCS11 PDS0 PDS07 PDS06 PDS05 PDS04 PDS03 PDS02 PDS01 PDS00 PDS1 PDS17 PDS16 PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PES0 PES07 PES06 PES05 PES04 PES03 PES02 PES01 PES00 PES1 PES17 PES16 PES15 PES14 PES13 PES12 PES11 PES10 IFS IFS7 IFS6 IFS5 IFS4 IFS3 IFS2 IFS1 IFS0 Pin-shared Function Selection Registers List – HT66FV160 Rev. 1.20 99 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU • PAS0 Register - HT66FV130 Bit Register Name 7 6 5 4 3 2 1 0 Name — — PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 "—" Unimplemented, read as 0 Bit 5~4PAS05~PAS04: PA2 pin function selection 00/01/10/11: PA2/PTCK0 Bit 3~2PAS03~PAS02: PA1 pin function selection 00/10: PA1/PTP0I 01: PTP0 11: AN2 Bit 1~0PAS01~PAS00: PA0 pin function selection 00/10/11: PA0/PTP0I 01: PTP0 • PAS0 Register – HT66FV140/HT66FV150/HT66FV160 Bit Register Name 7 6 5 4 3 2 1 0 Name PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PAS07~PAS06: PA3 pin function selection 00/10: PA3/PTP1I 01: PTP1 11: AN3 Bit 5~4PAS05~PAS04: PA2 pin function selection 00/01/10/11: PA2/PTCK0 Bit 3~2PAS03~PAS02: PA1 pin function selection 00/10: PA1/PTP0I 01: PTP0 11: AN2 Bit 1~0PAS01~PAS00: PA0 pin function selection 00/10/11: PA0/PTP0I 01: PTP0 • PAS1 Register – HT66FV130 Bit Register Name 7 6 5 4 3 2 1 0 Name PAS17 PAS16 PAS15 PAS14 — — — — R/W R/W R/W R/W R/W — — — — POR 0 0 0 0 — — — — Bit 7~6PAS17~PAS16: PA7 pin function selection 00/01: PA7/CTCK0 10: XT1 11: AN7 Bit 5~4PAS15~PAS14: PA6 pin function selection 00: PA6/INT1 01: CTP0 10: XT2 11: AN6 Bit 3~0 Rev. 1.20 "—" Unimplemented, read as 0 100 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU • PAS1 Register – HT66FV140/HT66FV150/HT66FV160 Bit Register Name 7 6 5 4 3 2 1 0 Name PAS17 PAS16 PAS15 PAS14 PAS13 PAS12 PAS11 PAS10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PAS17~PAS16: PA7 pin function selection 00/01: PA7/CTCK0 10: XT1 11: AN7 Bit 5~4PAS15~PAS14: PA6 pin function selection 00: PA6/INT1 01: CTP0 10: XT2 11: AN6 Bit 3~2PAS13~PAS12: PA5 pin function selection 00/10: PA5 01: CTP0 11: AN5 Bit 1~0PAS11~PAS10: PA4 pin function selection 00/10: PA4/PTP1I 01: PTP1 11: AN4 • PBS0 Register – HT66FV130/HT66FV140/HT66FV150/HT66FV160 Bit Register Name 7 6 5 4 3 2 1 0 Name — — PBS05 PBS04 PBS03 PBS02 PBS01 PBS00 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 "—" Unimplemented, read as 0 Bit 5~4PBS05~PBS04: PB2 pin function selection 00/01/10: PB2/INT0 11: OSC2 Bit 3~2PBS03~PBS02: PB1 pin function selection 00/01/10: PB1/PTCK1 11: OSC1 Bit 1~0PBS01~PBS00: PB0 pin function selection 00/01/10: PB0 11: VDDIO When this pin is selected as the VDDIO pin, the corresponding I/O and pull-high functions are all disabled. Then the I/O Port C power will be supplied by the VDDIO pin. Rev. 1.20 101 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU • PCS0 Register – HT66FV130 Bit Register Name 7 6 5 4 3 2 1 0 Name — — PCS05 PCS04 PCS03 PCS02 PCS01 PCS00 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 "—" Unimplemented, read as 0 Bit 5~4PCS05~PCS04: PC2 pin function selection 00/10/11: PC2 01: SDI/SDA Bit 3~2PCS03~PCS02: PC1 pin function selection 00: PC1 01: SCK/SCL 10: VREF 11: AN1 Bit 1~0PCS01~PCS00: PC0 pin function selection 00: PC0 01: SDO 10: VREFI 11: AN0 • PCS0 Register – HT66FV140 Bit Register Name 7 6 5 4 3 2 1 0 Name PCS07 PCS06 PCS05 PCS04 PCS03 PCS02 PCS01 PCS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PCS07~PCS06: PC3 pin function selection 00/10/11: PC3 01: SCS Bit 5~4PCS05~PCS04: PC2 pin function selection 00/10/11: PC2 01: SDI/SDA Bit 3~2PCS03~PCS02: PC1 pin function selection 00: PC1 01: SCK/SCL 10: VREF 11: AN1 Bit 1~0PCS01~PCS00: PC0 pin function selection 00: PC0 01: SDO 10: VREFI 11: AN0 Rev. 1.20 102 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU • PCS0 Register – HT66FV150/HT66FV160 Bit Register Name 7 6 5 4 3 2 1 0 Name PCS07 PCS06 PCS05 PCS04 PCS03 PCS02 PCS01 PCS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PCS07~PCS06: PC3 pin function selection 00/11: PC3 01:SCS 10: TX Bit 5~4PCS05~PCS04: PC2 pin function selection 00/11: PC2 01: SDI/SDA 10: RX Bit 3~2PCS03~PCS02: PC1 pin function selection 00: PC1 01: SCK/SCL 10: VREFO 11: AN1 Bit 1~0PCS01~PCS00: PC0 pin function selection 00: PC0 01: SDO 10: VREF 11: AN0 • PCS1 Register – HT66FV130/HT66FV140/HT66FV150/HT66FV160 Bit Register Name 7 6 5 4 3 2 1 0 Name PCS17 PCS16 PCS15 PCS14 PCS13 PCS12 PCS11 PCS10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PCS17~PCS16: PC7 pin function selection 00/10/11: PC7 01: SCSA Bit 5~4PCS15~PCS14: PC6 pin function selection 00/10/11: PC6 01: SDIA Bit 3~2PCS13~PCS12: PC5 pin function selection 00/10/11: PC5 01: SCKA Bit 1~0PCS11~PCS10: PC4 pin function selection 00/10/11: PC4 01: SDOA Rev. 1.20 103 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU • PDS0 Register – HT66FV150/HT66FV160 Bit Register Name 7 6 5 4 3 2 1 0 Name PDS07 PDS06 PDS05 PDS04 PDS03 PDS02 PDS01 PDS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PDS07~PDS06: PD3 pin function selection 00/01/11: PD3 10: SCOM3 Bit 5~4PDS05~PDS04: PD2 pin function selection 00/01/11: PD2 10: SCOM2 Bit 3~2PDS03~PDS02: PD1 pin function selection 00/01/11: PD1 10: SCOM1 Bit 1~0PDS01~PDS00: PD0 pin function selection 00/01/11: PD0 10: SCOM0 • PDS1 Register – HT66FV160 Bit Register Name 7 6 5 4 3 2 1 0 Name PDS17 PDS16 PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PDS17~PDS16: PD7 pin function selection 00/01/10/11: PD7 Bit 5~4PDS15~PDS14: PD6 pin function selection 00/01/10/11: PD6 Bit 3~2PDS13~PDS12: PD5 pin function selection 00/01/10/11: PD5 Bit 1~0PDS11~PDS10: PD4 pin function selection 00/01/10/11: PD4 • PES0 Register – HT66FV150/HT66FV160 Bit Register Name 7 6 5 4 3 2 1 0 Name PES07 PES06 PES05 PES04 PES03 PES02 PES01 PES00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PES07~PES06: PE3 pin function selection 00/10/11: PE3 01: CTP1 Bit 5~4PES05~PES04: PE2 pin function selection 00/01/10/11: PE2/CTCK1 Bit 3~2PES03~PES02: PE1 pin function selection 00/10/11: PE1 01: RX Bit 1~0PES01~PES00: PE0 pin function selection 00/10/11: PE0 01: TX Rev. 1.20 104 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU • PES1 Register – HT66FV160 Bit Register Name 7 6 5 4 3 2 1 0 Name PES17 PES16 PES15 PES14 PES13 PES12 PES11 PES10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PES17~PES16: PE7 pin function selection 00/01/10/11: PE7 Bit 5~4PES15~PES14: PE6 pin function selection 00/10/11: PE6/STP0I 01: STP0 Bit 3~2PES13~PES12: PE5 pin function selection 00/10/11: PE5/STP0 01: STP0 Bit 1~0PES11~PES10: PE4 pin function selection 00/01/10/11: PE4/STCK0 • IFS Register – HT66FV130 Bit Register Name 7 6 5 4 3 2 1 0 Name — — — — IFS3 IFS2 — — R/W — — — — R/W R/W — — POR — — — — 0 0 — — Bit 7~4 "—" Unimplemented, read as 0 Bit 3~2IFS3~IFS2: PTP0I input source pin selection 00: PA0 01/10/11: PA1 Bit 1~0 "—" Unimplemented, read as 0 • IFS Register – HT66FV140 Bit Register Name 7 6 5 4 3 2 1 0 Name — — IFS5 IFS4 IFS3 IFS2 — — R/W — — R/W R/W R/W R/W — — POR — — 0 0 0 0 — — Bit 7~6 "—" Unimplemented, read as 0 Bit 5~4IFS5~IFS4: PTP1I input source pin selection 00: PA3 01/10/11: PA4 Bit 3~2IFS3~IFS2: PTP0I input source pin selection 00: PA0 01/10/11: PA1 Bit 1~0 Rev. 1.20 "—" Unimplemented, read as 0 105 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU • IFS Register – HT66FV150 Bit Register Name 7 6 5 4 3 2 1 0 Name IFS7 IFS6 IFS5 IFS4 IFS3 IFS2 — — R/W R/W R/W R/W R/W R/W R/W — — POR 0 0 0 0 0 0 — — Bit 7~6IFS7~IFS6: UART RX input source pin selection 00: PC2 01/10/11: PE1 Bit 5~4IFS5~IFS4: PTP1I input source pin selection 00: PA3 01/10/11: PA4 Bit 3~2IFS3~IFS2: PTP0I input source pin selection 00: PA0 01/10/11: PA1 Bit 1~0 "—" Unimplemented, read as 0 • IFS Register – HT66FV160 Bit Register Name 7 6 5 4 3 2 1 0 Name IFS7 IFS6 IFS5 IFS4 IFS3 IFS2 IFS1 IFS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6IFS7~IFS6: UART RX input source pin selection 00: PC2 01/10/11: PE1 Bit 5~4IFS5~IFS4: PTP1I input source pin selection 00: PA3 01/10/11: PA4 Bit 3~2IFS3~IFS2: PTP0I input source pin selection 00: PA0 01/10/11: PA1 Bit 1~0IFS1~IFS0: STP0I input source pin selection 00: PE5 01/10/11: PE6 Rev. 1.20 106 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. Generic Input/Output Structure A/D Input/Output Structure Rev. 1.20 107 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Programming Considerations Within the user program, one of the things first to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set to high. This means that all I/O pins will be defaulted to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "SET [m].i" and "CLR [m].i" instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Rev. 1.20 108 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Timer Modules – TM One of the most fundamental functions in any microcontroller devices is the ability to control and measure time. To implement time related functions the device includes several Timer Modules, generally abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Compact, Standard and Periodic TM sections. Introduction These devices contain three TMs and each individual TM can be categorised as a certain type, namely Compact Type TM, Standard Type TM or Periodic Type TM. Although similar in nature, the different TM types vary in their feature complexity. The common features to all of the Compact, Standard and Periodic TMs will be described in this section and the detailed operation regarding each of the TM types will be described in separate sections. The main features and differences between the three types of TMs are summarised in the accompanying table. CTM STM PTM Timer/Counter TM Function √ √ √ Input Capture — √ √ Compare Match Output √ √ √ PWM Channels 1 1 1 Single Pulse Output — 1 1 PWM Alignment PWM Adjustment Period & Duty Edge Edge Edge Duty or Period Duty or Period Duty or Period TM Function Summary TM Operation The different types of TM offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running count-up counter whose value is then compared with the value of pre-programmed internal comparators. When the free running count-up counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the xTnCK2~xTnCK0 bits in the xTMn control registers, where "x" stands for C, S or P type TM and "n" stands for the specific TM serial number. The clock source can be a ratio of the system clock, fSYS, or the internal high clock, fH, the fSUB clock source or the external xTCKn pin. The xTCKn pin clock source is used to allow an external signal to drive the TM as an external clock source for event counting. Rev. 1.20 109 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU TM Interrupts The Compact, Standard or Periodic type TM has two internal interrupt, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated, it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has one or two TM input pins, with the label xTCKn and xTPnI respectively. The xTMn input pin, xTCKn, is essentially a clock source for the xTMn and is selected using the xTnCK2~xTnCK0 bits in the xTMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. The xTCKn input pin can be chosen to have either a rising or falling active edge. The STCKn and PTCKn pins are also used as the external trigger input pin in single pulse output mode for the STMn and PTMn respectively. The other xTMn input pin, xTPnI, is the capture input whose active edge can be a rising edge, a falling edge or both rising and falling edges and the active edge transition type is selected using the STnIO1~STnIO0 or PTnIO1~PTnIO0 bits in the STMnC1 or PTMnC1 register respectively. There is another capture input, PTCKn, for PTMn capture input mode, which can be used as the external trigger input source except the PTPnI pin. The TMs each have one output pin. The TM output pins can be selected using the corresponding pin-shared function selection bits described in the Pin-shared Function section. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external xTPn output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other functions, the TM output function must first be setup using relevant pin-shared function selection register. Device CTM STM PTM HT66FV130 CTCK0; CTP0 — PTCK0, PTP0I; PTP0 HT66FV140 CTCK0; CTP0 — PTCK0, PTP0I; PTP0 PTCK1, PTP1I; PTP1 HT66FV150 CTCK0; CTP0 CTCK1; CTP1 — PTCK0, PTP0I; PTP0 PTCK1, PTP1I; PTP1 HT66FV160 CTCK0; CTP0 CTCK1; CTP1 STCK0, STP0I; STP0 PTCK0, PTP0I; PTP0 PTCK1, PTP1I; PTP1 TM External Pins Rev. 1.20 110 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU TM Input/Output Pin Control Register Selecting to have a TM input/output or whether to retain its other shared function is implemented using the relevant pin-shared function selection registers, with the corresponding selection bits in each pin-shared function register corresponding to a TM input/output pin. Configuring the selection bits correctly will setup the corresponding pin as a TM input/output. The details of the pin-shared function selection are described in the pin-shared function section. CTCKn CTMn CCR o�tp�t CTPn CTM Function Pin Control Block Diagram – n = 0 or 1 STCK0 STM CCR capt�re inp�t CCR o�tp�t STP0I STP0 STM Function Pin Control Block Diagram – HT66FV160 only PTCKn PTMn CCR capt�re inp�t CCR o�tp�t PTPnI PTPn PTM Function Pin Control Block Diagram – n = 0 or 1 Rev. 1.20 111 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA and CCRP registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way as described above, it is recommended to use the "MOV" instruction to access the CCRA and CCRP low byte registers, named xTMnAL and PTMnRPL, using the following access procedures. Accessing the CCRA or CCRB low byte registers without following these access procedures will result in unpredictable values. xTMn Counter Register (Read only) xTMnDL xTMnDH 8-bit Buffer xTMnAL xTMnAH xTMn CCRA Register (Read/Write) PTMnRPL PTMnRPH PTMn CCRP Register (Read/Write) Data Bus The following steps show the read and write procedures: • Writing Data to CCRA or CCRP ♦♦ Step 1. Write data to Low Byte xTMnAL or PTMnRPL ––note that here data is only written to the 8-bit buffer. ♦♦ Step 2. Write data to High Byte xTMnAH or PTMnRPH ––here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. • Reading Data from the Counter Registers and CCRA or CCRP Rev. 1.20 ♦♦ Step 1. Read data from the High Byte xTMnDH, xTMnAH or PTMnRPH ––here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte xTMnDL, xTMnAL or PTMnRPL ––this step reads data from the 8-bit buffer. 112 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Compact Type TM – CTM Although the simplest form of the TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive one external output pin. Device CTM Core CTM Input Pin CTM Output Pin Note HT66FV130 10-bit CTM (CTM0) CTCK0 CTP0 n=0 HT66FV140 10-bit CTM (CTM0) CTCK0 CTP0 n=0 HT66FV150 10-bit CTM (CTM0, CTM1) CTCK0, CTCK1 CTP0, CTP1 n=0~1 HT66FV160 10-bit CTM (CTM0, CTM1) CTCK0, CTCK1 CTP0, CTP1 n=0~1 CCRP 3-bit Comparator P fSYS/4 fSYS fH/16 fH/64 fSUB fSUB 001 CTMnPF Interrupt CTnOC b7~b9 010 011 10-bit Count-up Counter 100 101 110 CTCKn Comparator P Match 000 CTnON CTnPAU Counter Clear 0 1 Polarity Control Pin Control CTnM1, CTnM0 CTnIO1, CTnIO0 CTnPOL PxSn CTPn CTnCCLR b0~b9 111 10-bit Comparator A Output Control Comparator A Match CTMnAF Interrupt CTnCK2~CTnCK0 CCRA Compact Type TM Block Diagram – n = 0 or 1 Compact TM Operation The Compact TM core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is three-bit wide whose value is compared with the highest three bits in the counter while the CCRA is ten-bit wide and therefore compares with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the CTnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Compact Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Rev. 1.20 113 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Compact Type TM Register Description Overall operation of the Compact TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes and as well as the three CCRP bits. Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CTMnC0 CTnPAU CTnCK2 CTnCK1 CTnCK0 CTnON CTnRP2 CTnRP1 CTnRP0 CTMnC1 CTnM1 CTnM0 CTnIO1 CTnIO0 CTnOC CTnPOL CTnDPX CTnCCLR CTMnDL D7 D6 D5 D4 D3 D2 D1 CTMnDH — — — — — — D9 D8 CTMnAL D7 D6 D5 D4 D3 D2 D1 D0 CTMnAH — — — — — — D9 D8 D0 10-bit Compact TM Registers List – n = 0 or 1 CTMnDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 CTMn Counter Low Byte Register bit 7 ~ bit 0 CTMn 10-bit Counter bit 7 ~ bit 0 CTMnDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 CTMn Counter High Byte Register bit 1 ~ bit 0 CTMn 10-bit Counter bit 9 ~ bit 8 CTMnAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 CTMn CCRA Low Byte Register bit 7 ~ bit 0 CTMn 10-bit CCRA bit 7 ~ bit 0 CTMnAH Register Rev. 1.20 Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 CTMn CCRA High Byte Register bit 1 ~ bit 0 CTMn 10-bit CCRA bit 9 ~ bit 8 114 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU CTMnC0 Register Bit 7 6 5 4 3 2 1 0 Name CTnPAU CTnCK2 CTnCK1 CTnCK0 CTnON CTnRP2 CTnRP1 CTnRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7CTnPAU: CTMn Counter Pause control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the CTMn will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4CTnCK2~CTnCK0: Select CTMn Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: CTCKn rising edge clock 111: CTCKn falling edge clock These three bits are used to select the clock source for the CTMn. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. Bit 3CTnON: CTMn Counter On/Off control 0: Off 1: On This bit controls the overall on/off function of the CTMn. Setting the bit high enables the counter to run while clearing the bit disables the CTMn. Clearing this bit to zero will stop the counter from counting and turn off the CTMn which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the CTMn is in the Compare Match Output Mode then the CTMn output pin will be reset to its initial condition, as specified by the CTnOC bit, when the CTnON bit changes from low to high. Bit 2~0CTnRP2~CTnRP0: CTMn CCRP 3-bit register, compared with the CTMn Counter bit 9 ~ bit 7 000: 1024 CTMn clocks 001: 128 CTMn clocks 010: 256 CTMn clocks 011: 384 CTMn clocks 100: 512 CTMn clocks 101: 640 CTMn clocks 110: 768 CTMn clocks 111: 896 CTMn clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the CTnCCLR bit is set to zero. Setting the CTnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. Rev. 1.20 115 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU CTMnC1 Register Bit 7 6 5 4 3 2 Name CTnM1 CTnM0 CTnIO1 CTnIO0 CTnOC CTnPOL 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 CTnDPX CTnCCLR Bit 7~6CTnM1~CTnM0: Select CTMn Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the CTMn. To ensure reliable operation the CTMn should be switched off before any changes are made to the CTnM1 and CTnM0 bits. In the Timer/Counter Mode, the CTMn output pin control will be disabled. Bit 5~4CTnIO1~CTnIO0: Select CTMn external pin (CTPn) function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Undefined Timer/Counter Mode Unused These two bits are used to determine how the CTMn output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the CTMn is running. In the Compare Match Output Mode, the CTnIO1 and CTnIO0 bits determine how the CTMn output pin changes state when a compare match occurs from the Comparator A. The CTMn output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the CTMn output pin should be setup using the CTnOC bit in the CTMnC1 register. Note that the output level requested by the CTnIO1 and CTnIO0 bits must be different from the initial value setup using the CTnOC bit otherwise no change will occur on the CTMn output pin when a compare match occurs. After the CTMn output pin changes state, it can be reset to its initial level by changing the level of the CTnON bit from low to high. In the PWM Mode, the CTnIO1 and CTnIO0 bits determine how the CTMn output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the CTnIO1 and CTnIO0 bits only after the CTMn has been switched off. Unpredictable PWM outputs will occur if the CTnIO1 and CTnIO0 bits are changed when the CTMn is running. Rev. 1.20 116 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Bit 3CTnOC: CTPn Output control Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode 0: Active low 1: Active high This is the output control bit for the CTMn output pin. Its operation depends upon whether CTMn is being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the CTMn is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the CTMn output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2CTnPOL: CTPn Output polarity control 0: Non-inverted 1: Inverted This bit controls the polarity of the CTPn output pin. When the bit is set high the CTMn output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1CTnDPX: CTMn PWM duty/period control 0: CCRP – period; CCRA – duty 1: CCRP – duty; CCRA – period This bit determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0CTnCCLR: CTMn Counter Clear condition selection 0: CTMn Comparator P match 1: CTMn Comparator A match This bit is used to select the method which clears the counter. Remember that the Compact TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the CTnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The CTnCCLR bit is not used in the PWM Mode. Rev. 1.20 117 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Compact Type TM Operation Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Mode or Timer/Counter Mode. The operating mode is selected using the CTnM1 and CTnM0 bits in the CTMnC1 register. Compare Match Output Mode To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register, should be set to "00" respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the CTnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both CTMnAF and CTMnPF interrupt request flags for the Comparator A and Comparator P respectively, will both be generated. If the CTnCCLR bit in the CTMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the CTMnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when CTnCCLR is high no CTMnPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the CTMnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the CTMn output pin will change state. The CTMn output pin condition however only changes state when a CTMnAF interrupt request flag is generated after a compare match occurs from Comparator A. The CTMnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the CTMn output pin. The way in which the CTMn output pin changes state are determined by the condition of the CTnIO1 and CTnIO0 bits in the CTMnC1 register. The CTMn output pin can be selected using the CTnIO1 and CTnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the CTMn output pin, which is setup after the CTnON bit changes from low to high, is setup using the CTnOC bit. Note that if the CTnIO1 and CTnIO0 bits are zero then no pin change will take place. Rev. 1.20 118 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Co�nter Va��e Co�nter overf�ow CCRP > 0 üüüüüüü=üüüüüü CCRP=0 0x3FF CTnCCLR = 0; CTnM [1:0] = 00 CCRP > 0 Co�nter Restart Res�me CCRP Pa�se Stop CCRA Time CTnON CTnPAU CTnPOL CCRP Int. f�ag CTMnPF CCRA Int. f�ag CTMnAF CTMn O/P Pin O�tp�t pin set to initia� Leve� Low if CTnOC=0 O�tp�t not affected b� CTMnAF f�ag. Remains High �nti� reset b� CTnON bit O�tp�t Togg�e with CTMnAF f�ag Here CTnIO [1:0] = 11 Togg�e O�tp�t se�ect Note CTnIO [1:0] = 10 Active High O�tp�t se�ect O�tp�t Inverts when CTnPOL is high O�tp�t Pin Reset to Initia� va��e O�tp�t contro��ed b� other pin-shared f�nction Compare Match Output Mode – CTnCCLR = 0 Note: 1. With CTnCCLR = 0, a Comparator P match will clear the counter 2. The CTMn output pin controlled only by CTMnAF flag 3. The output pin is reset to its initial state by CTnON bit rising edge 4. n = 0 or 1 Rev. 1.20 119 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Co�nter Va��e CTnCCLR = 1; CTnM [1:0] = 00 CCRA = 0 Co�nter overf�ow CCRA > 0 üüüüüüü=üüüüüü 0x3FF Res�me CCRA Pa�se CCRA=0 Stop Co�nter Restart CCRP Time CTnON CTnPAU CTnPOL No CTMnAF f�ag generated on CCRA overf�ow CCRA Int. f�ag CTMnAF CCRP Int. f�ag CTMnPF CTMn O/P Pin CTMnPF not generated O�tp�t pin set to initia� Leve� Low if CTnOC=0 O�tp�t does not change O�tp�t not affected b� CTMnAF f�ag. Remains High �nti� reset b� CTnON bit O�tp�t Togg�e with CTMnAF f�ag Here CTnIO [1:0] = 11 Togg�e O�tp�t se�ect Note CTnIO [1:0] = 10 Active High O�tp�t se�ect O�tp�t Inverts when CTnPOL is high O�tp�t Pin Reset to Initia� va��e O�tp�t contro��ed b� other pin-shared f�nction Compare Match Output Mode – CTnCCLR = 1 Note: 1. With CTnCCLR = 1, a Comparator A match will clear the counter 2. The CTMn output pin is controlled only by CTMnAF flag 3. The CTMn output pin is reset to initial state by CTnON rising edge 4. The CTMnPF flags is not generated when CTnCCLR = 1 5. n = 0 or 1 Rev. 1.20 120 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Timer/Counter Mode To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the CTMn output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the CTMn output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register should be set to 10 respectively. The PWM function within the CTMn is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the CTMn output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the CTnCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the CTnDPX bit in the CTMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The CTnOC bit in the CTMnC1 register is used to select the required polarity of the PWM waveform while the two CTnIO1 and CTnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The CTnPOL bit is used to reverse the polarity of the PWM output waveform. • 10-bit CTMn, PWM Mode, Edge-aligned Mode, CTnDPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA If fSYS = 16MHz, CTMn clock source is fSYS/4, CCRP = 2 and CCRA = 128, The CTMn PWM output frequency = (fSYS/4) / (2x256) = fSYS/2048 = 7.8125 kHz, duty = 128/ (2x256)= 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. • 10-bit CTMn, PWM Mode, Edge-aligned Mode, CTnDPX=1 CCRP 001b 010b 011b 100b Period Duty 101b 110b 111b 000b 768 896 1024 CCRA 128 256 384 512 640 The PWM output period is determined by the CCRA register value together with the CTMn clock while the PWM duty cycle is defined by the CCRP register value. Rev. 1.20 121 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Co�nter Va��e CTnDPX = 0; CTnM [1:0] = 10 Co�nter c�eared b� CCRP Co�nter Reset when CTnON ret�rns high CCRP Pa�se Res�me Co�nter Stop if CTnON bit �ow CCRA Time CTnON CTnPAU CTnPOL CCRA Int. f�ag CTMnAF CCRP Int. f�ag CTMnPF CTMn O/P Pin (CTnOC=1) CTMn O/P Pin (CTnOC=0) PWM D�t� C�c�e set b� CCRA PWM Period set b� CCRP PWM res�mes operation O�tp�t contro��ed b� O�tp�t Inverts other pin-shared f�nction when CTnPOL = 1 PWM Output Mode – CTnDXP = 0 Note: 1. Here CTnDPX = 0 – Counter cleared by CCRP 2. A counter clear sets PWM Period 3. The internal PWM function continues even when CTnIO1, CTnIO0 = 00 or 01 4. The CTnCCLR bit has no influence on PWM operation 5. n = 0 or 1 Rev. 1.20 122 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Co�nter Va��e CTnDPX = 1; CTnM [1:0] = 10 Co�nter c�eared b� CCRA Co�nter Reset when CTnON ret�rns high CCRA Pa�se Res�me Co�nter Stop if CTnON bit �ow CCRP Time CTnON CTnPAU CTnPOL CCRP Int. f�ag CTMnPF CCRA Int. f�ag CTMnAF CTMn O/P Pin (CTnOC=1) CTMn O/P Pin (CTnOC=0) PWM D�t� C�c�e set b� CCRP PWM Period set b� CCRA PWM res�mes operation O�tp�t contro��ed b� O�tp�t Inverts other pin-shared f�nction when CTnPOL = 1 PWM Output Mode – CTnDXP = 1 Note: 1. Here CTnDPX = 1 – Counter cleared by CCRA 2. A counter clear sets PWM Period 3. The internal PWM function continues even when CTnIO [1:0] = 00 or 01 4. The CTnCCLR bit has no influence on PWM operation 5. n = 0 or 1 Rev. 1.20 123 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Standard Type TM – STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with two external input pins and can drive one external output pin. Device STM Core STM Input Pin STM Output Pin HT66FV130 — — — HT66FV140 — — — HT66FV150 — — — HT66FV160 16-bit STM STCK0, STP0I STP0 CCRP 8-bit Comparator P fSYS/4 fSYS fH/16 fH/64 fSUB fSUB STCKn 000 001 010 011 100 101 110 111 Comparator P Match STnOC b8~b1� 16-bit Co�nt-�p Co�nter STnON STnPAU STnCK2~STnCK0 STMnPF Interr�pt Co�nter C�ear 0 1 O�tp�t Contro� Po�arit� Contro� Pin Contro� STnM1� STnM0 STnIO1� STnIO0 STnPOL PxSn STPn STnCCLR b0~b1� 16-bit Comparator A Comparator A Match STMnAF Interr�pt STnIO1� STnIO0 Edge Detector CCRA STPnI Standard Type TM Block Diagram – HT66FV160 only (n=0) Standard TM Operation The size of Standard TM is 16-bit wide and its core is a 16-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP comparator is 8-bit wide whose value is compared the with highest 8 bits in the counter while the CCRA is the sixteen bits and therefore compares all counter bits. The only way of changing the value of the 16-bit counter using the application program, is to clear the counter by changing the STnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a STM interrupt signal will also usually be generated. The Standard Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Rev. 1.20 124 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Standard Type TM Register Description Overall operation of the Standard TM is controlled using a series of registers. A read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit CCRA value. The STMnRP register is used to store the 8-bit CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 STMnC0 STnPAU Name Bit7 STnCK2 STnCK1 STnCK0 STnON — — — STMnC1 STnM0 STnIO1 STnIO0 STnOC STnPOL STnDPX STnCCLR STnM1 Bit0 STMnDL D7 D6 D5 D4 D3 D2 D1 D0 STMnDH D15 D14 D13 D12 D11 D10 D9 D8 STMnAL D7 D6 D5 D4 D3 D2 D1 D0 STMnAH D15 D14 D13 D12 D11 D10 D9 D8 STnRP6 STnRP5 STnRP4 STnRP3 STnRP2 STnRP1 STnRP0 STMnRP STnRP7 16-bit Standard TM Registers List − n=0 STMnDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 STMn Counter Low Byte Register bit 7 ~ bit 0 STMn 16-bit Counter bit 7 ~ bit 0 STMnDH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 STMn Counter High Byte Register bit 7 ~ bit 0 STMn 16-bit Counter bit 15 ~ bit 8 STMnAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 STMn CCRA Low Byte Register bit 7 ~ bit 0 STMn 16-bit CCRA bit 7 ~ bit 0 STMnAH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.20 STMn CCRA High Byte Register bit 7 ~ bit 0 STMn 16-bit CCRA bit 15 ~ bit 8 125 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU STMnC0 Register Bit 7 6 5 4 3 2 1 0 Name STnPAU STnCK2 STnCK1 STnCK0 STnON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7STnPAU: STMn Counter Pause control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the STMn will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4STnCK2~STnCK0: Select STMn Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: STCKn rising edge clock 111: STCKn falling edge clock These three bits are used to select the clock source for the STMn. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. Bit 3STnON: STMn Counter On/Off control 0: Off 1: On This bit controls the overall on/off function of the STMn. Setting the bit high enables the counter to run while clearing the bit disables the STMn. Clearing this bit to zero will stop the counter from counting and turn off the STMn which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the STMn is in the Compare Match Output Mode then the STMn output pin will be reset to its initial condition, as specified by the STnOC bit, when the STnON bit changes from low to high. Bit 2~0 Rev. 1.20 Unimplemented, read as "0" 126 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU STMnC1 Register Bit Register Name 7 6 5 4 3 Name STnM1 STnM0 STnIO1 STnIO0 STnOC R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 2 1 0 STnPOL STnDPX STnCCLR Bit 7~6STnM1~STnM0: Select STMn Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the STMn. To ensure reliable operation the STMn should be switched off before any changes are made to the STnM1 and STnM0 bits. In the Timer/Counter Mode, the STMn output pin control will be disabled. Bit 5~4STnIO1~STnIO0: Select STMn external pin (STPn or STPnI) function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single Pulse Output Capture Input Mode 00: Input capture at rising edge of STPnI 01: Input capture at falling edge of STPnI 10: Input capture at rising/falling edge of STPnI 11: Input capture disabled Timer/Counter Mode Unused These two bits are used to determine how the STMn output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the STMn is running. In the Compare Match Output Mode, the STnIO1 and STnIO0 bits determine how the STMn output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the STMn output pin should be setup using the STnOC bit in the STnMC1 register. Note that the output level requested by the STnIO1 and STnIO0 bits must be different from the initial value setup using the STnOC bit otherwise no change will occur on the STMn output pin when a compare match occurs. After the STMn output pin changes state, it can be reset to its initial level by changing the level of the STnON bit from low to high. In the PWM Mode, the STnIO1 and STnIO0 bits determine how the STMn output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the STnIO1 and STnIO0 bits only after the STMn has been switched off. Unpredictable PWM outputs will occur if the STnIO1 and STnIO0 bits are changed when the STMn is running. Rev. 1.20 127 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Bit 3STnOC: STMn STPn Output control Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the STMn output pin. Its operation depends upon whether STMn is being used in the Compare Match Output Mode or in the PWM Mode/Single Pulse Output Mode. It has no effect if the STMn is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the STMn output pin before a compare match occurs. In the PWM Mode/Single Pulse Output Mode it determines if the PWM signal is active high or active low. Bit 2STnPOL: STMn STPn Output polarity control 0: Non-inverted 1: Inverted This bit controls the polarity of the STPn output pin. When the bit is set high the STMn output pin will be inverted and not inverted when the bit is zero. It has no effect if the STMn is in the Timer/Counter Mode. Bit 1STnDPX: STMn PWM duty/period control 0: CCRP – period; CCRA – duty 1: CCRP – duty; CCRA – period This bit determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0STnCCLR: STMn Counter Clear condition selection 0: Comparator P match 1: Comparator A match This bit is used to select the method which clears the counter. Remember that the Standard TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the STnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The STnCCLR bit is not used in the PWM Output, Single Pulse Output or Capture Input Mode. STMnRP Register Bit Register Name 7 6 5 4 3 2 1 0 Name STnRP7 STnRP6 STnRP5 STnRP4 STnRP3 STnRP2 STnRP1 STnRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0STnRP7~STnRP0: STMn CCRP 8-bit register, compared with the STMn counter bit 15~bit 8 Comparator P match period = 0: 65536 STMn clocks 1~255: (1~255) x 256 STMn clocks These eight bits are used to setup the value on the internal CCRP 8-bit register, which are then compared with the internal counter’s highest eight bits. The result of this comparison can be selected to clear the internal counter if the STnCCLR bit is set to zero. Setting the STnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. Clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value. Rev. 1.20 128 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Standard Type TM Operation Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the STnM1 and STnM0 bits in the STMnC1 register. Compare Match Output Mode To select this mode, bits STnM1 and STnM0 in the STMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the STnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both STMnAF and STMnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the STnCCLR bit in the STMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the STMnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when STnCCLR is high no STMnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to "0". As the name of the mode suggests, after a comparison is made, the STMn output pin, will change state. The STMn output pin condition however only changes state when a STMnAF interrupt request flag is generated after a compare match occurs from Comparator A. The STMnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the STMn output pin. The way in which the STMn output pin changes state are determined by the condition of the STnIO1 and STnIO0 bits in the STMnC1 register. The STMn output pin can be selected using the STnIO1 and STnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the STMn output pin, which is setup after the STnON bit changes from low to high, is setup using the STnOC bit. Note that if the STnIO1 and STnIO0 bits are zero then no pin change will take place. Rev. 1.20 129 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Counter Value Counter overflow CCRP=0 0xFFFF STnCCLR = 0; STnM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value CCRP > 0 Counter Restart Resume CCRP Pause Stop CCRA Time STnON STnPAU STnPOL CCRP Int. flag STMnPF CCRA Int. flag STMnAF STMn O/P Pin Output pin set to initial Level Low if STnOC=0 Output not affected by STMnAF flag. Remains High until reset by STnON bit Output Toggle with STMnAF flag Here STnIO [1:0] = 11 Toggle Output select Note STnIO [1:0] = 10 Active High Output select Output Inverts when STnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – STnCCLR = 0 Note: 1. With STnCCLR=0 a Comparator P match will clear the counter 2. The STMn output pin is controlled only by the STMnAF flag 3. The output pin is reset to itsinitial state by a STnON bit rising edge 4. n=0 Rev. 1.20 130 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Counter Value STnCCLR = 1; STnM [1:0] = 00 CCRA = 0 Counter overflow CCRA > 0 Counter cleared by CCRA value 0xFFFF Resume CCRA Pause CCRA=0 Stop Counter Restart CCRP Time STnON STnPAU STnPOL No STMnAF flag generated on CCRA overflow CCRA Int. flag STMnAF CCRP Int. flag STMnPF STMn O/P Pin STMnPF not generated Output pin set to initial Level Low if STnOC=0 Output does not change Output Toggle with STMnAF flag Here STnIO [1:0] = 11 Toggle Output select Output not affected by STMnAF flag. Remains High until reset by STnON bit Note STnIO [1:0] = 10 Active High Output select Output Inverts when STnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – STnCCLR = 1 Note: 1. With STnCCLR=1 a Comparator A match will clear the counter 2. The STMn output pin is controlled only by the STMnAF flag 3. The output pin is reset to its initial state by a STnON bit rising edge 4. A STMnPF flag is not generated when STnCCLR=1 5. n=0 Rev. 1.20 131 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Timer/Counter Mode To select this mode, bits STnM1 and STnM0 in the STMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the STMn output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the STMn output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits STnM1 and STnM0 in the STMnC1 register should be set to 10 respectively and also the STnIO1 and STnIO0 bits should be set to 10 respectively. The PWM function within the STMn is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the STMn output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the STnCCLR bit has no effect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the STnDPX bit in the STMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The STnOC bit in the STMnC1 register is used to select the required polarity of the PWM waveform while the two STnIO1 and STnIO0 bits are used to enable the PWM output or to force the STMn output pin to a fixed high or low level. The STnPOL bit is used to reverse the polarity of the PWM output waveform. • 16-bit STMn, PWM Mode, Edge-aligned Mode, STnDPX=0 CCRP 1~255 0 Period CCRPx256 65536 Duty CCRA If fSYS = 16MHz, STMn clock source is fSYS/4, CCRP = 2 and CCRA = 128, The STMn PWM output frequency = (fSYS/4) / (2x256) = fSYS/2048 = 7.8125 kHz, duty = 128/(2x256)= 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. • 16-bit STMn, PWM Mode, Edge-aligned Mode, STnDPX=1 CCRP 1~255 Period 0 CCRA Duty CCRPx256 65536 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value except when the CCRP value is equal to 0. Rev. 1.20 132 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Counter Value STnDPX = 0; STnM [1:0] = 10 Counter cleared by CCRP Counter Reset when STnON returns high CCRP Pause Resume Counter Stop if STnON bit low CCRA Time STnON STnPAU STnPOL CCRA Int. flag STMnAF CCRP Int. flag STMnPF STMn O/P Pin (STnOC=1) STMn O/P Pin (STnOC=0) PWM Duty Cycle set by CCRA PWM Period set by CCRP PWM resumes operation Output controlled by Output Inverts other pin-shared function when STnPOL = 1 PWM Output Mode – STnDXP = 0 Note: 1. Here STnDPX=0 – Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when STnIO [1:0] = 00 or 01 4. The STnCCLR bit has no influence on PWM operation 5. n=0 Rev. 1.20 133 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Counter Value STnDPX = 1; STnM [1:0] = 10 Counter cleared by CCRA Counter Reset when STnON returns high CCRA Pause Resume Counter Stop if STnON bit low CCRP Time STnON STnPAU STnPOL CCRP Int. flag STMnPF CCRA Int. flag STMnAF STMn O/P Pin (STnOC=1) STMn O/P Pin (STnOC=0) PWM resumes operation PWM Duty Cycle set by CCRP Output controlled by other pin-shared function PWM Period set by CCRA Output Inverts when STnPOL = 1 PWM Output Mode – STnDXP = 1 Note: 1. Here STnDPX=1 – Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when STnIO [1:0] = 00 or 01 4. The STnCCLR bit has no influence on PWM operation 5. n=0 Rev. 1.20 134 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Single Pulse Output Mode To select this mode, bits STnM1 and STnM0 in the STMnC1 register should be set to 10 respectively and also the STnIO1 and STnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the STMn output pin. The trigger for the pulse output leading edge is a low to high transition of the STnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the STnON bit can also be made to automatically change from low to high using the external STCKn pin, which will in turn initiate the Single Pulse output. When the STnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The STnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the STnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the STnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a STMn interrupt. The counter can only be reset back to zero when the STnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The STnCCLR and STnDPX bits are not used in this Mode. S/W Command SET“STnON or ” STCKn Pin Transition CCRA Leading Edge CCRA Trailing Edge STnON bit 0à1 STnON bit 1à0 S/W Command CLR“STnON” or CCRA Compare Match STPn Output Pin Pulse Width = CCRA Value Single Pulse Generation Rev. 1.20 135 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Counter Value STnM [1:0] = 10 ; STnIO [1:0] = 11 Counter stopped by CCRA Counter Reset when STnON returns high CCRA Pause Counter Stops by software Resume CCRP Time STnON Software Trigger Auto. set by STCKn pin Cleared by CCRA match Software Trigger STCKn pin Software Trigger Software Clear Software Trigger STCKn pin Trigger STnPAU STnPOL No CCRP Interrupts generated CCRP Int. Flag STMnPF CCRA Int. Flag STMnAF STMn O/P Pin (STnOC=1) STMn O/P Pin (STnOC=0) Output Inverts when STnPOL = 1 Pulse Width set by CCRA Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse triggered by the STCKn pin or by setting the STnON bit high 4. A STCKn pin active edge will automatically set the STnON bit high. 5. In the Single Pulse Mode, STnIO [1:0] must be set to "11" and can not be changed. 6. n = 0 Rev. 1.20 136 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Capture Input Mode To select this mode bits STnM1 and STnM0 in the STMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the STPnI pin, whose active edge can be a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the STnIO1 and STnIO0 bits in the STMnC1 register. The counter is started when the STnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the STPnI pin the present value in the counter will be latched into the CCRA registers and a STMn interrupt generated. Irrespective of what events occur on the STPnI pin the counter will continue to free run until the STnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a STMn interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The STnIO1 and STnIO0 bits can select the active trigger edge on the STPnI pin to be a rising edge, falling edge or both edge types. If the STnIO1 and STnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the STPnI pin, however it must be noted that the counter will continue to run. The STnCCLR and STnDPX bits are not used in this Mode. Rev. 1.20 137 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Co�nter Va��e STnM [1:0] = 01 Co�nter c�eared b� CCRP Co�nter Co�nter Stop Reset CCRP Res�me YY Pa�se XX Time STnON STnPAU Active edge Active edge Active edge STMn capt�re pin STPnI CCRA Int. F�ag STMnAF CCRP Int. F�ag STMnPF CCRA Va��e STnIO [1:0] Va��e XX 00 – Rising edge YY 01 – Fa��ing edge XX 10 – Both edges YY 11 – Disab�e Capt�re Capture Input Mode Note: 1. STnM [1:0] = 01 and active edge set by the STnIO [1:0] bits 2. A STMn Capture input pin active edge transfers the counter value to CCRA 3. STnCCLR bit not used 4. No output function -- STnOC and STnPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. 6. n = 0 . Rev. 1.20 138 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Periodic Type TM – PTM The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can also be controlled with two external input pins and can drive one external output pin. Device PTM Core PTM Input Pin PTM Output Pin Note HT66FV130 10-bit PTM (PTM0) PTCK0, PTP0I PTP0 n=0 HT66FV140 10-bit PTM (PTM0, PTM1) PTCK0, PTP0I PTCK1, PTP1I PTP0, PTP1 n=0~1 HT66FV150 10-bit PTM (PTM0, PTM1) PTCK0, PTP0I PTCK1, PTP1I PTP0, PTP1 n=0~1 HT66FV160 10-bit PTM (PTM0, PTM1) PTCK0, PTP0I PTCK1, PTP1I PTP0, PTP1 n=0~1 CCRP 10-bit Comparator P fSYS/4 fSYS fH/16 fH/64 fSUB fSUB 001 PTMnPF Interrupt PTnOC b0~b9 010 011 10-bit Count-up Counter 100 101 110 PTCKn Comparator P Match 000 PTnON PTnPAU Counter Clear Polarity Control Pin Control PTnM1, PTnM0 PTnIO1, PTnIO0 PTnPOL PxSn PTPn PTnCCLR b0~b9 111 PTnCK2~PTnCK0 Output Control 0 1 10-bit Comparator A Comparator A Match PTnIO1, PTnIO0 CCRA Edge Detector PTMnAF Interrupt IFS PTnCAPTS 0 1 Pin Control PTPnI Periodic Type TM Block Diagram – n = 0 or 1 Periodic TM Operation The size of Periodic TM is 10-bit wide and its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP and CCRA comparators are 10-bit wide whose value is respectively compared with all counter bits. The only way of changing the value of the 10-bit counter using the application program is to clear the counter by changing the PTnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a PTM interrupt signal will also usually be generated. The Periodic Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control the output pins. All operating setup conditions are selected using relevant internal registers. Rev. 1.20 139 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Periodic Type TM Register Description Overall operation of the Periodic TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA and CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — — PTMnC0 PTnPAU PTnCK2 PTnCK1 PTnCK0 PTnON PTMnC1 PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC PTMnDL D7 D6 D5 D4 D3 D2 D1 PTMnDH — — — — — — D9 D8 PTMnAL D7 D6 D5 D4 D3 D2 D1 D0 PTMnAH — — — — — — PTnPOL PTnCAPTS PTnCCLR D0 D9 D8 PTMnRPL PTnRP7 PTnRP6 PTnRP5 PTnRP4 PTnRP3 PTnRP2 PTnRP1 PTnRP0 PTMnRPH PTnRP9 PTnRP8 — — — — — — Periodic TM Registers List – n = 0 or 1 PTMnDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 PTMn Counter Low Byte Register bit 7 ~ bit 0 PTMn 10-bit Counter bit 7 ~ bit 0 PTMnDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 PTMn Counter High Byte Register bit 1 ~ bit 0 PTMn 10-bit Counter bit 9 ~ bit 8 PTMnAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.20 PTMn CCRA Low Byte Register bit 7 ~ bit 0 PTMn 10-bit CCRA bit 7 ~ bit 0 140 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU PTMnAH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 PTMn CCRA High Byte Register bit 1 ~ bit 0 PTMn 10-bit CCRA bit 9 ~ bit 8 PTMnRPL Register Bit 7 6 5 4 3 2 1 0 Name PTnRP7 PTnRP6 PTnRP5 PTnRP4 PTnRP3 PTnRP2 PTnRP1 PTnRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0PTnRP7~PTnRP0: PTMn CCRP Low Byte Register bit 7 ~ bit 0 PTMn 10-bit CCRP bit 7 ~ bit 0 PTMnRPH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — PTnRP9 PTnRP8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0PTnRP9~PTnRP8: PTMn CCRP High Byte Register bit 1 ~ bit 0 PTMn 10-bit CCRP bit 9 ~ bit 8 PTMnC0 Register Bit 7 6 5 4 3 2 1 0 Name PTnPAU PTnCK2 PTnCK1 PTnCK0 PTnON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7PTnPAU: PTMn Counter Pause control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the PTMn will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4PTnCK2~PTnCK0: Select PTMn Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: PTCKn rising edge clock 111: PTCKn falling edge clock These three bits are used to select the clock source for the PTMn. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. Rev. 1.20 141 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Bit 3PTnON: PTMn Counter On/Off control 0: Off 1: On This bit controls the overall on/off function of the PTMn. Setting the bit high enables the counter to run while clearing the bit disables the PTMn. Clearing this bit to zero will stop the counter from counting and turn off the PTMn which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the PTMn is in the Compare Match Output Mode then the PTMn output pin will be reset to its initial condition, as specified by the PTnOC bit, when the PTnON bit changes from low to high. Bit 2~0 Unimplemented, read as "0" PTMnC1 Register Bit 7 6 5 4 3 Name PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 PTnPOL PTnCAPTS PTnCCLR Bit 7~6PTnM1~PTnM0: Select PTMn Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the PTMn. To ensure reliable operation the PTMn should be switched off before any changes are made to the PTnM1 and PTnM0 bits. In the Timer/Counter Mode, the PTMn output pin control will be disabled. Bit 5~4PTnIO1~PTnIO0: Select PTMn external pin PTPn, PTPnI or PTCKn function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single Pulse Output Capture Input Mode 00: Input capture at rising edge of PTPnI or PTCKn 01: Input capture at falling edge of PTPnI or PTCKn 10: Input capture at rising/falling edge of PTPnI or PTCKn 11: Input capture disabled Timer/Counter Mode Unused These two bits are used to determine how the PTMn output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the PTMn is running. In the Compare Match Output Mode, the PTnIO1 and PTnIO0 bits determine how the PTMn output pin changes state when a compare match occurs from the Comparator A. The PTMn output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the PTMn Rev. 1.20 142 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU output pin should be setup using the PTnOC bit in the PTMnC1 register. Note that the output level requested by the PTnIO1 and PTnIO0 bits must be different from the initial value setup using the PTnOC bit otherwise no change will occur on the PTMn output pin when a compare match occurs. After the PTMn output pin changes state, it can be reset to its initial level by changing the level of the PTnON bit from low to high. In the PWM Mode, the PTnIO1 and PTnIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PTMn output function is modified by changing these two bits. It is necessary to only change the values of the PTnIO1 and PTnIO0 bits only after the PTMn has been switched off. Unpredictable PWM outputs will occur if the PTnIO1 and PTnIO0 bits are changed when the PTMn is running. Bit 3PTnOC: PTMn PTPn Output control Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the PTMn output pin. Its operation depends upon whether PTMn is being used in the Compare Match Output Mode or in the PWM Mode/Single Pulse Output Mode. It has no effect if the PTMn is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the PTMn output pin before a compare match occurs. In the PWM Mode/Single Pulse Output Mode it determines if the PWM signal is active high or active low. Bit 2PTnPOL: PTMn PTPn Output polarity control 0: Non-inverted 1: Inverted This bit controls the polarity of the PTPn output pin. When the bit is set high the PTMn output pin will be inverted and not inverted when the bit is zero. It has no effect if the PTMn is in the Timer/Counter Mode. Bit 1PTnCAPTS: PTMn Capture Triiger Source selection 0: From PTPnI pin 1: From PTCKn pin Bit 0PTnCCLR: PTMn Counter Clear condition selection 0: Comparator P match 1: Comparator A match This bit is used to select the method which clears the counter. Remember that the Periodic TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the PTnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The PTnCCLR bit is not used in the PWM Output, Single Pulse Output or Capture Input Mode. Rev. 1.20 143 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Periodic Type TM Operation Modes The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the PTnM1 and PTnM0 bits in the PTMnC1 register. Compare Match Output Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the PTnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both PTMnAF and PTMnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the PTnCCLR bit in the PTMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the PTMnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when PTnCCLR is high no PTMnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to "0". As the name of the mode suggests, after a comparison is made, the PTMn output pin will change state. The PTMn output pin condition however only changes state when a PTMnAF interrupt request flag is generated after a compare match occurs from Comparator A. The PTMnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the PTMn output pin. The way in which the PTMn output pin changes state are determined by the condition of the PTnIO1 and PTnIO0 bits in the PTMnC1 register. The PTMn output pin can be selected using the PTnIO1 and PTnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the PTMn output pin, which is setup after the PTnON bit changes from low to high, is setup using the PTnOC bit. Note that if the PTnIO1 and PTnIO0 bits are zero then no pin change will take place. Rev. 1.20 144 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Counter Value Counter overflow CCRP=0 0x3FF PTnCCLR = 0; PTnM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value CCRP > 0 Counter Restart Resume CCRP Pause Stop CCRA Time PTnON PTnPAU PTnPOL CCRP Int. Flag PTMnPF CCRA Int. Flag PTMnAF PTMn O/P Pin Output pin set to initial Level Low if PTnOC=0 Output not affected by PTMnAF flag. Remains High until reset by PTnON bit Output Toggle with PTMnAF flag Here PTnIO [1:0] = 11 Toggle Output select Note PTnIO [1:0] = 10 Active High Output select Output Inverts when PTnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – PTnCCLR = 0 Note: 1. With PTnCCLR=0, a Comparator P match will clear the counter 2. The PTMn output pin is controlled only by the PTMnAF flag 3. The output pin is reset to its initial state by a PTnON bit rising edge 4. n = 0 or 1 Rev. 1.20 145 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Counter Value PTnCCLR = 1; PTnM [1:0] = 00 CCRA = 0 Counter overflow CCRA > 0 Counter cleared by CCRA value 0x3FF CCRA=0 Resume CCRA Pause Stop Counter Restart CCRP Time PTnON PTnPAU PTnPOL No PTMnAF flag generated on CCRA overflow CCRA Int. Flag PTMnAF CCRP Int. Flag PTMnPF PTMPF not generated Output does not change PTMn O/P Pin Output pin set to initial Level Low if PTnOC=0 Output Toggle with PTMnAF flag Here PTnIO [1:0] = 11 Toggle Output select Output not affected by PTMnAF flag. Remains High until reset by PTnON bit Note PTnIO [1:0] = 10 Active High Output select Output Inverts when PTnPOL is Output Pin high Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – PTnCCLR = 1 Note: 1. With PTnCCLR=1, a Comparator A match will clear the counter 2. The PTMn output pin is controlled only by the PTMnAF flag 3. The output pin is reset to its initial state by a PTnON bit rising edge 4. A PTMnPF flag is not generated when PTnCCLR =1 5. n = 0 or 1 Rev. 1.20 146 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Timer/Counter Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the PTMn output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the PTMn output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10 respectively and also the PTnIO1 and PTnIO0 bits should be set to 10 respectively. The PWM function within the PTMn is useful for applications which require functions such as motor control, heating control, illumination control, etc. By providing a signal of fixed frequency but of varying duty cycle on the PTMn output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the PTnCCLR bit has no effect as the PWM period. Both of the CCRP and CCRA registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The PTnOC bit in the PTMnC1 register is used to select the required polarity of the PWM waveform while the two PTnIO1 and PTnIO0 bits are used to enable the PWM output or to force the PTMn output pin to a fixed high or low level. The PTnPOL bit is used to reverse the polarity of the PWM output waveform. • 10-bit PTMn, PWM Mode, Period Duty CCRP = 0 CCRP = 1~1023 1024 1~1023 CCRA If fSYS=16MHz, TM clock source select fSYS/4, CCRP=512 and CCRA=128, The PTMn PWM output frequency = (fSYS/4)/512 = fSYS/2048 = 7.8125kHz, duty=128/512=25%, If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. Rev. 1.20 147 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Counter Value PTnM [1:0] = 10 Counter cleared by CCRP Counter Reset when PTnON returns high CCRP Pause Resume Counter Stop if PTnON bit low CCRA Time PTnON PTnPAU PTnPOL CCRA Int. Flag PTMnAF CCRP Int. Flag PTMnPF PTMn O/P Pin (PTnOC=1) PTMn O/P Pin (PTnOC=0) PWM Duty Cycle set by CCRA PWM Period set by CCRP PWM resumes operation Output controlled by Output Inverts other pin-shared function When PTnPOL = 1 PWM Mode Note: 1. The counter is cleared by CCRP. 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when PTnIO [1:0] = 00 or 01 4. The PTnCCLR bit has no influence on PWM operation 5. n = 0 or 1 Rev. 1.20 148 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Single Pulse Output Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10 respectively and also the PTnIO1 and PTnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the PTMn output pin. The trigger for the pulse output leading edge is a low to high transition of the PTnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the PTnON bit can also be made to automatically change from low to high using the external PTCKn pin, which will in turn initiate the Single Pulse output. When the PTnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The PTnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the PTnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the PTnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a PTMn interrupt. The counter can only be reset back to zero when the PTnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The PTnCCLR is not used in this Mode. S/W Command SET“PTnON” or PTCKn Pin Transition CCRA Leading Edge CCRA Trailing Edge PTnON bit 0à1 PTnON bit 1à0 S/W Command CLR“PTnON” or CCRA Compare Match PTPn Output Pin Pulse Width = CCRA Value Single Pulse Generation Rev. 1.20 149 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Counter Value PTnM [1:0] = 10 ; PTnIO [1:0] = 11 Counter stopped by CCRA Counter Reset when PTnON returns high CCRA Pause Counter Stops by software Resume CCRP Time PTnON Software Trigger Auto. set by PTCKn pin Cleared by CCRA match Software Trigger PTCKn pin Software Trigger Software Clear Software Trigger PTCKn pin Trigger PTnPAU PTnPOL No CCRP Interrupts generated CCRP Int. Flag PTMnPF CCRA Int. Flag PTMnAF PTMn O/P Pin (PTnOC=1) PTMn O/P Pin (PTnOC=0) Pulse Width set by CCRA Output Inverts when PTnPOL = 1 Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse triggered by the PTCKn pin or by setting the PTnON bit high 4. A PTCKn pin active edge will automatically set the PTnON bit high. 5. In the Single Pulse Mode, PTnIO [1:0] must be set to "11" and can not be changed. 6. n = 0 or 1 Rev. 1.20 150 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Capture Input Mode To select this mode bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the PTPnI or PTCKn pin, selected by the PTnCAPTS bit in the PTMnC1 register. The input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the PTnIO1 and PTnIO0 bits in the PTMnC1 register. The counter is started when the PTnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the PTPnI or PTCKn pin the present value in the counter will be latched into the CCRA registers and a PTMn interrupt generated. Irrespective of what events occur on the PTPnI or PTCKn pin the counter will continue to free run until the PTnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a PTMn interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The PTnIO1 and PTnIO0 bits can select the active trigger edge on the PTPnI or PTCKn pin to be a rising edge, falling edge or both edge types. If the PTnIO1 and PTnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the PTPnI or PTCKn pin, however it must be noted that the counter will continue to run. As the PTPnI or PTCKn pin is pin shared with other functions, care must be taken if the PTMn is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The PTnCCLR, PTnOC and PTnPOL bits are not used in this Mode. Rev. 1.20 151 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Co�nter Va��e PTnM [1:0] = 01 Co�nter c�eared b� CCRP Co�nter Co�nter Stop Reset CCRP Res�me YY Pa�se XX Time PTnON PTnPAU Active edge Active edge Active edge PTMn capt�re pin PTPnI or PTCKn CCRA Int. F�ag PTMnAF CCRP Int. F�ag PTMnPF CCRA Va��e PTnIO [1:0] Va��e XX 00 – Rising edge YY 01 – Fa��ing edge XX 10 – Both edges YY 11 – Disab�e Capt�re Capture Input Mode Note: 1. PTnM [1:0] = 01 and active edge set by the PTnIO [1:0] bits 2. A PTMn Capture input pin active edge transfers the counter value to CCRA 3. PTnCCLR bit not used 4. No output function – PTnOC and PTnPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. 6. n = 0 or 1 Rev. 1.20 152 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Overview These devices contain a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. It also can convert the internal signals, such as the Bandgap reference voltage, into a 12-bit digital value. The external or internal analog signal to be converted is determined by the SAINS2~SAINS0 bits together with the SACS2~SACS0 bits. Note that when the internal analog signal is to be converted, the pin-shared control bits should also be properly configured except the SAINS and SACS bit fields. More detailed information about the A/D input signal is described in the "A/D Converter Control Registers" and "A/D Converter Input Signal" sections respectively. The accompanying block diagram shows the internal structure of the A/D converter together with its associated registers. Device External Input Channel Input Pins A/D Channel Select Bits HT66FV130 4 AN0, AN2, AN6~AN7 SACS2~SACS0 HT66FV140 8 AN0~AN7 SACS2~SACS0 HT66FV150 8 AN0~AN7 SACS2~SACS0 HT66FV160 8 AN0~AN7 SACS2~SACS0 VDD fSYS Pin-shared Se�ection SACS2~SACS0 SACKS2~ SACKS0 ÷ 2N ADCEN (N=0~7) VSS AN0 AN1 A/D C�ock SADOL A/D Converter AN7 ADRFS SADOH A/D Data Registers A/D Reference Vo�tage START ADBZ ADCEN VREF SAINS2~SAINS0 SAVRS3~SAVRS0 VDD VDD/2 VDD/4 VR VR/2 VR/4 VBG VRI Pin-shared Se�ection VDD PGA (Gain=1~4) VREFI Pin-shared Se�ection VR ADPGAEN A/D Converter Structure Rev. 1.20 153 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU A/D Converter Register Description Overall operation of the A/D converter is controlled using five registers. A read only register pair exists to store the A/D Converter data 12-bit value. The remaining three registers are control registers which setup the operating and control function of the A/D converter. Bit Register Name 7 6 5 4 3 2 1 0 SADOL (ADRFS=0) D3 D2 D1 D0 — — — — SADOL (ADRFS=1) D7 D6 D5 D4 D3 D2 D1 D0 SADOH (ADRFS=0) D11 D10 D9 D8 D7 D6 D5 D4 SADOH (ADRFS=1) — — — — D11 D10 D9 D8 START ADBZ ADCEN ADRFS — SACS2 SACS1 SACS0 SADC1 SAINS2 SAINS10 SAINS0 — SADC2 ADPGAEN VBGEN — — SADC0 — SACKS2 SACKS1 SACKS0 SAVRS3 SAVRS2 SAVRS1 SAVRS0 A/D Converter Registers List A/D Converter Data Registers – SADOL, SADOH As these devices contain an internal 12-bit A/D converter, it requires two data registers to store the converted value. These are a high byte register, known as SADOH, and a low byte register, known as SADOL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the ADRFS bit in the SADC0 register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any unused bits will be read as zero. The A/D data registers contents will be kept unchanged if the A/D converter is disabled. ADRFS 0 1 SADOH 7 6 5 D11 D10 D9 0 0 0 SADOL 4 3 2 1 0 7 6 5 4 3 2 1 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 A/D Converter Data Registers Rev. 1.20 154 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU A/D Converter Control Registers – SADC0, SADC1, SADC2 To control the function and operation of the A/D converter, three control registers known as SADC0, SADC1 and SADC2 are provided. These 8-bit registers define functions such as the selection of which analog channel is connected to the internal A/D converter, the digitised data format, the A/D clock source as well as controlling the start function and monitoring the A/D converter busy status. As these devices contain only one actual analog to digital converter hardware circuit, each of the external and internal analog signals must be routed to the converter. The SACS2~SACS0 bits in the SADC0 register are used to determine which external channel input is selected to be converted. The SAINS2~SAINS0 bits in the SADC1 register are used to determine that the analog signal to be converted comes from the internal analog signal or external analog channel input. If the SAINS2~SAINS0 bits are set to "000", the external analog channel input is selected to be converted and the SACS2~SACS0 bits can deternine which external channel is selected to be converted. If the SAINS2~SAINS0 bits are set to any other values except "000" and "100", one of the internal analog signals is selected to be converted. The internal analog signals can be derived from the A/D converter supply power, VDD, or internal reference voltage, VR, with a specific ratio of 1, 1/2 or 1/4. If the internal analog signal is selected to be converted, the external channel signal input will automatically be switched off to avoid the signal contention. SAINS [2:0] SACS [2:0] Input Signals 000, 100 000~111 AN0~AN7 Description 001 xxx VDD 010 xxx VDD/2 A/D converter power supply voltage/2 A/D converter power supply voltage/4 External channel analog input A/D converter power supply voltage 011 xxx VDD/4 101 xxx VR 110 xxx VR/2 Internal reference voltage/2 111 xxx VR/4 Internal reference voltage/4 Internal reference voltage A/D Converter Input Signal Selection The relevant pin-shared function selection bits determine which pins on I/O Ports are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D converter input. When the pin is selected to be an A/D input, its original function whether it is an I/O or other pinshared function will be removed. In addition, any internal pull-high resistor connected to the pin will be automatically removed if the pin is selected to be an A/D converter input. SADC0 Register – HT66FV130 Bit 7 6 5 4 3 2 1 0 Name START ADBZ ADCEN ADRFS — SACS2 SACS1 SACS0 R/W R/W R R/W R/W — R/W R/W R/W POR 0 0 0 0 — 0 0 0 Bit 7START: Start the A/D Conversion 0→1→0: Start This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. Bit 6ADBZ: A/D Converter busy flag 0: No A/D conversion is in progress 1: A/D conversion is in progress This read only flag is used to indicate whether the A/D conversion is in progress or not. When the START bit is set from low to high and then to low again, the ADBZ flag will be set to 1 to indicate that the A/D conversion is initiated. The ADBZ flag will be cleared to 0 after the A/D conversion is complete. Rev. 1.20 155 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Bit 5ADCEN: A/D Converter function enable control 0: Disable 1: Enable This bit controls the A/D internal function. This bit should be set to one to enable the A/D converter. If the bit is set low, then the A/D converter will be switched off reducing the device power consumption. When the A/D converter function is disabled, the contents of the A/D data register pair, SADOH and SADOL, will be kept unchanged. Bit 4ADRFS: A/D conversion data format select 0: A/D converter data format → SADOH = D [11:4]; SADOL = D [3:0] 1: A/D converter data format → SADOH = D [11:8]; SADOL = D [7:0] This bit controls the format of the 12-bit converted A/D value in the two A/D data registers. Details are provided in the A/D converter data register section. Bit 3 Unimplemented, read as "0" Bit 2~0SACS2~SACS0: A/D converter external analog input channel select 000: AN0 001: Undefined 010: AN2 011: Undefined 100: Undefined 101: Undefined 110: AN6 111: AN7 SADC0 Register – HT66FV140/HT66FV150/HT66FV160 Bit 7 6 5 4 3 2 1 0 Name START ADBZ ADCEN ADRFS — SACS2 SACS1 SACS0 R/W R/W R R/W R/W — R/W R/W R/W POR 0 0 0 0 — 0 0 0 Bit 7START: Start the A/D Conversion 0→1→0: Start This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. Bit 6ADBZ: A/D Converter busy flag 0: No A/D conversion is in progress 1: A/D conversion is in progress This read only flag is used to indicate whether the A/D conversion is in progress or not. When the START bit is set from low to high and then to low again, the ADBZ flag will be set to 1 to indicate that the A/D conversion is initiated. The ADBZ flag will be cleared to 0 after the A/D conversion is complete. Bit 5ADCEN: A/D Converter function enable control 0: Disable 1: Enable This bit controls the A/D internal function. This bit should be set to one to enable the A/D converter. If the bit is set low, then the A/D converter will be switched off reducing the device power consumption. When the A/D converter function is disabled, the contents of the A/D data register pair, SADOH and SADOL, will be kept unchanged. Bit 4ADRFS: A/D conversion data format select 0: A/D converter data format → SADOH = D [11:4]; SADOL = D [3:0] 1: A/D converter data format → SADOH = D [11:8]; SADOL = D [7:0] This bit controls the format of the 12-bit converted A/D value in the two A/D data registers. Details are provided in the A/D converter data register section. Rev. 1.20 156 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Bit 3 Unimplemented, read as "0" Bit 2~0SACS2~SACS0: A/D converter external analog input channel select 000: AN0 001: AN1 010: AN2 011: AN3 100: AN4 101: AN5 110: AN6 111: AN7 SADC1 Register Bit 7 6 5 4 3 2 1 0 Name SAINS2 SAINS1 SAINS0 — — SACKS2 SACKS1 SACKS0 R/W R/W R/W R/W — — R/W R/W R/W POR 0 0 0 — — 0 0 0 Bit 7~5SAINS2~SAINS0: A/D Converter input signal select 000, 100: External signal – External analog channel input 001: Internal signal – Internal A/D converter power supply voltage VDD 010: Internal signal – Internal A/D converter power supply voltage VDD/2 011: Internal signal – Internal A/D converter power supply voltage VDD/4 101: Internal signal – Internal reference voltage VR 110: Internal signal – Internal reference voltage VR/2 111: Internal signal – Internal reference voltage VR/4 When the internal analog signal is selected to be converted, the external channel input signal will automatically be switched off regardless of the SACS2~SACS0 bit field value. The internal reference voltage can be derived from various sources selected using the SAVRS 3~SAVRS0 bits in the SADC2 register. Bit 4~3 Unimplemented, read as "0" Bit 2~0SACKS2~SACKS0: A/D conversion clock source select 000: fSYS 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: fSYS/128 These bits are used to select the clock source for the A/D converter. Rev. 1.20 157 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU SADC2 Register Bit Name 7 6 ADPGAEN VBGEN 5 4 3 2 1 0 — — SAVRS3 SAVRS2 SAVRS1 SAVRS0 R/W R/W R/W — — R/W R/W R/W R/W POR 0 0 — — 0 0 0 0 Bit 7ADPGAEN: A/D converter PGA function enable control 0: Disable 1: Enable This bit controls the internal PGA function to provide various reference voltage for the A/D converter. When the bit is set high, the internal reference voltage, VR, can be used as the internal converted signal or reference voltage by the A/D converter. If the internal reference voltage is not used by the A/D converter, then the PGA function should be properly configured to conserve power. Bit 6VBGEN: Internal Bandgap reference voltage enable control 0: Disable 1: Enable This bit controls the internal Bandgap circuit on/off function to the A/D converter. When the bit is set high, the Bandgap reference voltage can be used by the A/D converter. If the Bandgap reference voltage is not used by the A/D converter and the LVD or LVR function is disabled, then the bandgap reference circuit will be automatically switched off to conserve power. When the Bandgap reference voltage is switched on for use by the A/D converter, a time, tBGS, should be allowed for the Bandgap circuit to stabilise before implementing an A/D conversion. Bit 5~4 Unimplemented, read as "0" Bit 3~0SAVRS3~SAVRS0: A/D Converter reference voltage select 0000: VDD 0001: VREFI 0010: VREFI x 2 0011: VREFI x 3 0100: VREFI x 4 1001: Reserved, can not be used. 1010: VBG x 2 1011: VBG x 3 1100: VBG x 4 Others: VDD When the A/D converter reference voltage source is selected to derive from the internal VBG voltage, the reference voltage which comes from the VDD or VREFI pin will be automatically switched off. Rev. 1.20 158 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU A/D Operation The START bit in the SADC0 register is used to start the AD conversion. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. The ADBZ bit in the SADC0 register is used to indicate whether the analog to digital conversion process is in progress or not. This bit will be automatically set to 1 by the microcontroller after an A/D conversion is successfully initiated. When the A/D conversion is complete, the ADBZ will be cleared to 0. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can poll the ADBZ bit in the SADC0 register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the SACKS2~SACKS0 bits in the SADC1 register. Although the A/D clock source is determined by the system clock fSYS and by bits SACKS2~SACKS0, there are some limitations on the maximum A/D clock source speed that can be selected. As the recommended range of permissible A/D clock period, tADCK, is from 0.5μs to 10μ, care must be taken for system clock frequencies. For example, as the system clock operates at a frequency of 8MHz, the SACKS2~SACKS0 bits should not be set to 000, 001 or 111. Doing so will give A/D clock periods that are less than the minimum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum A/D Clock Period. A/D Clock Period (tADCK) fSYS SACKS [2:0]= 000 (fSYS) SACKS [2:0]= 001 (fSYS/2) SACKS [2:0]= 010 (fSYS/4) SACKS [2:0]= 011 (fSYS/8) SACKS [2:0]= 100 (fSYS/16) SACKS [2:0]= 101 (fSYS/32) SACKS [2:0]= 110 (fSYS/64) SACKS [2:0]= 111 (fSYS/128) 1 MHz 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs * 128μs * 2 MHz 500ns 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs * 4 MHz 250ns * 500ns 1μs 2μs 4μs 8μs 16μs * 32μs * 8 MHz 125ns * 250ns * 500ns 1μs 2μs 4μs 8μs 16μs * 10.67μs * 12 MHz 83ns * 167ns * 333ns * 667ns 1.33μs 2.67μs 5.33μs 16 MHz 62.5ns * 125ns * 250ns * 500ns 1μs 2μs 4μs 8μs 20 MHz 50ns * 100ns * 200ns * 400ns * 800ns 1.6μs 3.2μs 6.4μs A/D Clock Period Examples Controlling the power on/off function of the A/D converter circuitry is implemented using the ADCEN bit in the SADC0 register. This bit must be set high to power on the A/D converter. When the ADCEN bit is set high to power on the A/D converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no pins are selected for use as A/D inputs, if the ADCEN bit is high, then some power will still be consumed. In power conscious applications it is therefore recommended that the ADCEN is set low to reduce power consumption when the A/D converter function is not being used. Rev. 1.20 159 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU A/D Reference Voltage The reference voltage supply to the A/D Converter can be supplied from the positive power supply pin, VDD, an external reference source supplied on pin VREFI or an internal reference source derived from the Bandgap circuit. Then the selected reference voltage source can be amplified through a programmable gain amplifier except the one sourced from VDD. The PGA gain can be equal to 1, 2, 3 or 4. The desired selection is made using the SAVRS3~SAVRS0 bits in the SADC2 register and relevant pin-shared function selection bits. Note that the desired selected reference voltage will be output on the VREF pin which is pin-shared with other functions. As the VREFI and VREF pins both are pin-shared with other functions, when the VREFI or VREF pin is selected as the reference voltage supply pin, the VREFI or VREF pin-shared function control bits should be properly configured to disable other pin-shared functions. A/D Input Pins All of the A/D analog input pins are pin-shared with the I/O pins as well as other functions. The corresponding pin-shared function selection bits in the PxS0 and PxS1 registers, determine whether the external input pins are setup as A/D converter analog channel inputs or whether they have other functions. If the corresponding pin is setup to be an A/D converter analog channel input, the original pin functions will be disabled. In this way, pins can be changed under program control to change their function between A/D inputs and other functions. All pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note that it is not necessary to first setup the A/D pin as an input in the port control register to enable the A/D input as when the relevant A/D input function selection bits enable an A/D input, the status of the port control register will be overridden. The A/D converter has its own reference voltage pin, VREFI. However, the reference voltage can also be supplied from the power supply pin or an internal Bandgap circuit, a choice which is made through the SAVRS3~SAVRS0 bits in the SADC2 register. The selected A/D reference voltage can be output on the VREF pin. The analog input values must not be allowed to exceed the value of VREF. Conversion Rate and Timing Diagram A complete A/D conversion contains two parts, data sampling and data conversion. The data sampling which is defined as tADS takes 4 A/D clock cycles and the data conversion takes 12 A/D clock cycles. Therefore a total of 16 A/D clock cycles for an A/D conversion which is defined as tADC are necessary. Maximum single A/D conversion rate = A/D clock period / 16 (1) The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16 tADCK clock cycles where tADCK is equal to the A/D clock period. Rev. 1.20 160 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU tON2ST ADCEN off on off A/D sampling time tADS A/D sampling time tADS Start of A/D conversion Start of A/D conversion on START ADBZ SACS[2:0] End of A/D conversion 011B A/D channel switch Start of A/D conversion End of A/D conversion 010B 000B tADC A/D conversion time tADC A/D conversion time 001B tADC A/D conversion time A/D Conversion Timing Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/D conversion process. • Step 1 Select the required A/D conversion clock by properly programming the SACKS2~SACKS0 bits in the SADC1 register. • Step 2 Enable the A/D converter by setting the ADCEN bit in the SADC0 register to one. • Step 3 Select which signal is to be connected to the internal A/D converter by correctly configuring the SAINS2~SAINS0 bits Select the external channel input to be converted, go to Step 4. Select the internal analog signal to be converted, go to Step 5. • Step 4 If the A/D input signal comes from the external channel input selecting by configuring the SAINS bit field, the corresponding pins should first be configured as A/D input function by configuring the relevant pin-shared function control bits. The desired analog channel then should be selected by configuring the SACS bit field. After this step, go to Step 6. • Step 5 If the A/D input signal is selected to come from the internal analog signal, the SAINS bit field should be properly configured and then the external channel input will automatically be disconnected regardless of the SACS bit field value. After this step, go to Step 6. • Step 6 Select the reference voltgage source by configuring the SAVRS3~SAVRS0 bits. • Step 7 Select the A/D converter output data format by configuring the ADRFS bit. • Step 8 If A/D conversion interrupt is used, the interrupt control registers must be correctly configured to ensure the A/D interrupt function is active. The master interrupt bontrol bit, EMI, and the A/D conversion interrupt control bit, ADE, must both be set high in advance. Rev. 1.20 161 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU • Step 9 The A/D conversion procedure can now be initialized by setting the START bit from low to high and then low again. • Step 10 If A/D conversion is in progress, the ADBZ flag will be set high. After the A/D conversion process is complete, the ADBZ flag will go low and then the output data can be read from SADOH and SADOL registers. Note: When checking for the end of the conversion process, if the method of polling the ADBZ bit in the SADC0 register is used, the interrupt enable step above can be omitted. Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D internal circuitry can be switched off to reduce power consumption, by setting bit ADCEN low in the SADC0 register. When this happens, the internal A/D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. A/D Transfer Function As these devices contain a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the VREF voltage, this gives a single bit analog input value of VREF divided by 4096. 1 LSB = VREF ÷ 4096 The A/D Converter input voltage value can be calculated using the following equation: A/D input voltage = A/D output digital value × VREF ÷ 4096 The diagram shows the ideal transfer function between the analog input value and the digitised output value for the A/D converter. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 LSB below the VREF level. Ideal A/D Transfer Function Rev. 1.20 162 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU A/D Programming Examples The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the ADBZ bit in the SADC0 register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using an ADBZ polling method to detect the end of conversion clr ADE; disable ADC interrupt mov a,03H mov SADC1,a ; select fSYS/8 as A/D clock and switch off VBG voltage set ADCEN mov a,03H ; setup PCS0 to configure pin AN0 mov PCS0,a mov a,00H mov SADC0,a ; enable and connect AN0 channel to A/D converter : start_conversion: clr START ; high pulse on start bit to initiate conversion set START ; reset A/D clr START ; start A/D : polling_EOC: sz ADBZ ; poll the SADC0 register ADBZ bit to detect end of A/D conversion jmp polling_EOC ; continue polling : mov a,SADOL ; read low byte conversion result value mov SADOL_buffer,a ; save result to user defined register mov a,SADOH ; read high byte conversion result value mov SADOH_buffer,a ; save result to user defined register : jmp start_conversion ; start next A/D conversion Rev. 1.20 163 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Example: using the interrupt method to detect the end of conversion clr ADE; disable ADC interrupt mov a,03H mov SADC1,a ; select fSYS/8 as A/D clock and switch off VBG voltage set ADCEN mov a,03h ; setup PCS0 to configure pin AN0 mov PCS0,a mov a,00h mov SADC0,a ; enable and connect AN0 channel to A/D converter : Start_conversion: clr START ; high pulse on START bit to initiate conversion set START ; reset A/D clr START ; start A/D clr ADF ; clear ADC interrupt request flag set ADE; enable ADC interrupt set EMI ; enable global interrupt : : ADC_ISR: ; ADC interrupt service routine mov acc_stack,a ; save ACC to user defined memory mov a,STATUS mov status_stack,a ; save STATUS to user defined memory : mov a, SADOL ; read low byte conversion result value mov SADOL_buffer,a ; save result to user defined register mov a, SADOH ; read high byte conversion result value mov SADOH_buffer,a ; save result to user defined register : EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti Rev. 1.20 164 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Serial Interface Module – SIM • HT66FV140/HT66FV150/HT66FV160 These devices contain a Serial Interface Module, which includes both the four-line SPI interface or two-line I2C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins and therefore the SIM interface functional pins must first be selected using the corresponding pin-shared function selection bits. As both interface types share the same pins and registers, the choice of whether the SPI or I2C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 register. These pull-high resistors of the SIM pin-shared I/O pins are selected using pullhigh control registers when the SIM function is enabled and the corresponding pins are used as SIM input pins. SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices, etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the devices can be either master or slave. Although the SPI interface specification can control multiple slave devices from a single master, these devices provided only one SCS pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pin to select the slave devices. SPI Interface Operation The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface pins must first be selected by configuring the pin-shared function selection bits and setting the correct bits in the SIMC0 and SIMC2 registers. After the desired SPI configuration has been set it can be disabled or enabled using the SIMEN bit in the SIMC0 register. Communication between devices connected to the SPI interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The Master also controls the clock signal. As the device only contains a single SCS pin only one slave device can be utilized. The SCS pin is controlled by software, set CSEN bit to 1 to enable SCS pin function, set CSEN bit to 0 the SCS pin will be floating state. The SPI function in this device offers the following features: • Full duplex synchronous data transfer • Both Master and Slave modes • LSB first or MSB first data transmission modes • Transmission complete flag • Rising or falling active clock edge The status of the SPI interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN. Rev. 1.20 165 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU SPI Master/Slave Connection SPI Block Diagram SPI Registers There are three internal registers which control the overall operation of the SPI interface. These are the SIMD data register and two registers SIMC0 and SIMC2. Note that the SIMC1 register is only used by the I2C interface. Bit Register Name 7 6 5 4 SIMC0 SIM2 SIM1 SIM0 — 3 2 SIMDEB1 SIMDEB0 1 0 SIMEN SIMICF SIMC2 D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF SIMD D7 D6 D5 D4 D3 D2 D1 D0 SPI Registers List • SIMD Register The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register. Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown Rev. 1.20 166 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2 register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used by the SPI function, only by the I2C function. Register SIMC0 is used to control the enable/disable function and to set the data transmission clock frequency. Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag, etc. • SIMC0 Register Bit 7 6 5 4 Name SIM2 SIM1 SIM0 — 3 R/W R/W R/W R/W — R/W POR 1 1 1 — 0 2 1 0 SIMEN SIMICF R/W R/W R/W 0 0 0 SIMDEB1 SIMDEB0 Bit 7~5SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS /4 001: SPI master mode; SPI clock is fSYS /16 010: SPI master mode; SPI clock is fSYS /64 011: SPI master mode; SPI clock is fSUB 100: SPI master mode; SPI clock is CTM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Non SIM function These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock and fSUB but can also be chosen to be sourced from CTM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 Unimplemented, read as "0" Bit 3~2SIMDEB1~SIMDEB0: I2C Debounce Time Selection 00: No debounce 01: 2 system clock debounce 1x: 4 system clock debounce Bit 1SIMEN: SIM Enable Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I2C function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective.If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0SIMICF: SIM Incomplete Flag 0: SIM incomplete condition not occurred 1: SIM incomplete condition occured This bit is only available when the SIM is configured to operate in an SPI slave mode. If the SPI operates in the slave mode with the SIMEN and CSEN bits both being set to 1 but the SCS line is pulled high by the external master device before the SPI data transfer is completely finished, the SIMICF bit will be set to 1 together with the TRF bit. When this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. However, the TRF bit will not be set to 1 if the SIMICF bit is set to 1 by software application program. Rev. 1.20 167 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU • SIMC2 Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Undefined bits These bits can be read or written by the application program. Bit 5CKPOLB: SPI clock line base condition selection 0: The SCK line will be high when the clock is inactive. 1: The SCK line will be low when the clock is inactive. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. Bit 4CKEG: SPI SCK clock active edge type selection CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit. Bit 3MLS: SPI data shift order 0: LSB first 1: MSB first This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Bit 2CSEN: SPI SCS pin control 0: Disable 1: Enable The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the SCS pin will be disabled and placed into a floating condition. If the bit is high, the SCS pin will be enabled and used as a select pin. Bit 1WCOL: SPI write collision flag 0: No collision 1: Collision The WCOL flag is used to detect whether a data collision has occurred or not. If this bit is high, it means that data has been attempted to be written to the SIMD register duting a data transfer operation. This writing operation will be ignored if data is being transferred. This bit can be cleared by the application program. Bit 0TRF: SPI Transmit/Receive complete flag 0: SPI data is being transferred 1: SPI data transfer is completed The TRF bit is the Transmit/Receive Complete flag and is set to 1 automatically when an SPI data transfer is completed, but must cleared to 0 by the application program. It can be used to generate an interrupt. Rev. 1.20 168 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU SPI Communication After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output a SCS signal to enable the slave devices before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI will continue to function even in the IDLE Mode. SPI Master Mode Timing SPI Slave Mode Timing – CKEG = 0 Rev. 1.20 169 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Note: For SPI slave mode, if SIMEN=1 and CSEN=0, the SPI is always enabled and ignores the SCS level. SPI Slave Mode Timing – CKEG = 1 SPI Transfer Control Flow Chart Rev. 1.20 170 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU I2C Interface The I 2C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. I2C Master/Slave Bus Connection I2C interface Operation The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two devices communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For these devices, which only operate in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. 2 I C Block Diagram Rev. 1.20 171 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU S T A R T s ig n a l fro m M a s te r S e n d s la v e a d d r e s s a n d R /W b it fr o m M a s te r A c k n o w le d g e fr o m s la v e S e n d d a ta b y te fro m M a s te r A c k n o w le d g e fr o m s la v e S T O P s ig n a l fro m M a s te r The SIMDEB1 and SIMDEB0 bits determine the debounce time of the I2C interface. This uses the system clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be chosen to be either 2 or 4 system clocks. To achieve the required I2C data transfer speed, there exists a relationship between the system clock, fSYS, and the I2C debounce time. For either the I2C Standard or Fast mode operation, users must take care of the selected system clock frequency and the configured debounce time to match the criterion shown in the following table. I2C Debounce Time Selection I2C Standard Mode (100kHz) I2C Fast Mode (400kHz) No Devounce fSYS > 2 MHz fSYS > 5 MHz 2 system clock debounce fSYS > 4 MHz fSYS > 10 MHz 4 system clock debounce fSYS > 8 MHz fSYS > 20 MHz I2C Minimum fSYS Frequency I2C Registers There are three control registers associated with the I2C bus, SIMC0, SIMC1 and SIMA, and one data register, SIMD. The SIMD register, which is shown in the above SPI section, is used to store the data being transmitted and received on the I2C bus. Before the microcontroller writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the microcontroller can read it from the SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD register. Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface. Bit Register Name 7 6 5 4 SIMC0 SIM2 SIM1 SIM0 — SIMC1 HCF HAAS HBB HTX TXAK SIMA IICA6 IICA5 IICA4 IICA3 IICA2 SIMD D7 D6 D5 D4 D3 D2 3 2 1 0 SIMEN SIMICF SRW IAMWU RXAK IICA1 IICA0 D0 D1 D0 SIMDEB1 SIMDEB0 SIMTOC SIMTOEN SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0 I2C Registers List Rev. 1.20 172 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU • SIMD Register The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the device can read it from the SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD register. Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown • SIMA Register The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the SIMA register, the slave device will be selected. Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface. Bit 7 6 5 4 3 2 1 0 Name IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown Bit 7~1IICA6~IICA0: I2C slave address IICA6~IICA0 is the I2C slave address bit 6 ~ bit 0 Bit 0 Undefined bit The bit can be read or written by the application program. There are also two control registers for the I2C interface, SIMC0 and SIMC1. The register SIMC0 is used to control the enable/disable function and to set the data transmission clock frequency.The SIMC1 register contains the relevant flags which are used to indicate the I2C communication status. • SIMC0 Register Bit 7 6 5 4 Name SIM2 SIM1 SIM0 — 3 R/W R/W R/W R/W — R/W POR 1 1 1 — 0 2 1 0 SIMEN SIMICF R/W R/W R/W 0 0 0 SIMDEB1 SIMDEB0 Bit 7~5SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS /4 001: SPI master mode; SPI clock is fSYS /16 010: SPI master mode; SPI clock is fSYS /64 011: SPI master mode; SPI clock is fSUB 100: SPI master mode; SPI clock is CTM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Non SIM function These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock and fSUB but can also be chosen to be sourced from TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Rev. 1.20 173 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Bit 4 Unimplemented, read as "0" Bit 3~2SIMDEB1~SIMDEB0: I2C Debounce Time Selection 00: No debounce 01: 2 system clock debounce 1x: 4 system clock debounce Bit 1SIMEN: SIM Enable Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I2C function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective.If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0SIMICF: SIM Incomplete Flag 0: SIM incomplete condition not occurred 1: SIM incomplete condition occured This bit is only available when the SIM is configured to operate in an SPI slave mode. If the SPI operates in the slave mode with the SIMEN and CSEN bits both being set to 1 but the SCS line is pulled high by the external master device before the SPI data transfer is completely finished, the SIMICF bit will be set to 1 together with the TRF bit. When this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. However, the TRF bit will not be set to 1 if the SIMICF bit is set to 1 by software application program. • SIMC1 Register Bit 7 6 5 4 3 2 1 0 Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R/W R R R R/W R/W R/W R/W R POR 1 0 0 0 0 0 0 1 Bit 7HCF: I2C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Bit 6HAAS: I2C Bus data transfer completion flag 0: Not address match 1: Address match The HAAS flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. Rev. 1.20 174 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Bit 5HBB: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The HBB flag is the I2C busy flag. This flag will be "1" when the I2C bus is busy which will occur when a START signal is detected. The flag will be set to "0" when the bus is free which will occur when a STOP signal is detected. Bit 4HTX: I2C slave device transmitter/receiver selection 0: Slave device is the receiver 1: Slave device is the transmitter Bit 3TXAK: I2C bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave does not send acknowledge flag The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bit of data, this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always set TXAK bit to "0" before further data is received. Bit 2SRW: I2C slave read/write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SRW flag is the I 2C Slave Read/Write flag. This flag determines whether the master device wishes to transmit or receive data from the I2C bus. When the transmitted address and slave address is match, that is when the HAAS flag is set high, the slave device will check the SRW flag to determine whether it should be in transmit mode or receive mode. If the SRW flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SRW flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1IAMWU: I2C Address Match Wake-Up control 0: Disable 1: Enable – must be cleared by the application program after wake-up This bit should be set to 1 to enable the I2C address match wake up from the SLEEP or IDLE Mode. If the IAMWU bit has been set before entering either the SLEEP or IDLE mode to enable the I2C address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation. Bit 0RXAK: I2C bus receive acknowledge flag 0: Slave receives acknowledge flag 1: Slave does not receive acknowledge flag The RXAK flag is the receiver acknowledge flag. When the RXAK flag is "0", it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAK flag is "1". When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. Rev. 1.20 175 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU I2C Bus Communication Communication on the I2C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS bit and SIMTOF bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. During a data transfer, note that after the 7-bit slave address has been transmitted or I2C time-out, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this: • Step 1 Set the SIM2~SIM0 bits to "110" and SIMEN bit to "1" in the SIMC0 register to enable the I2C bus. • Step 2 Write the slave address of the device to the I2C bus address register SIMA. • Step 3 Set the SIME and SIM Muti-Function interrupt enable bit of the interrupt control register to enable the SIM interrupt and Multi-function interrupt. I2C Bus Initialisation Flow Chart Rev. 1.20 176 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU I2C Bus Start Signal The START signal can only be generated by the master device connected to the I2C bus and not by the slave device. This START signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. I2C Slave Address The transmission of a START signal by the master will be detected by all devices on the I2C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag HAAS when the addresses match. As an I2C bus interrupt can come from three sources, when the program enters the interrupt subroutine, the HAAS bit and SIMTOF bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer or I2C timeout. When a slave address is matched, the devices must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I2C Bus Read/Write Signal The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW flag is "1" then this indicates that the master device wishes to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a transmitter. If the SRW flag is "0" then this indicates that the master wishes to send data to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver. I2C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address, any slave device on the I 2C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAAS flag is high, the addresses have matched and the slave device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register should be set to "1". If the SRW flag is low, then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1 register should be set to "0". Rev. 1.20 177 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU I2C Bus Data and Acknowledge Signal The transmitted data is 8-bit wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8-bit of data, the receiver must transmit an acknowledge signal, level "0", before it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the SIMD register. If setup as a transmitter, the slave device must first write the data to be transmitted into the SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD register. When the slave receiver receives the data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. Note: *When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I2C Communication Timing Diagram Rev. 1.20 178 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU I2C Bus ISR Flow Chart I2C Time-out Control In order to reduce the I2C lockup problem due to reception of erroneous clock sources, a time-out function is provided. If the clock source connected to the I2C bus is not received for a while, then the I2C circuitry and registers will be reset after a certain time-out period. The time-out counter starts to count on an I2C bus "START" & "address match"condition, and is cleared by an SCL falling edge. Before the next SCL falling edge arrives, if the time elapsed is greater than the time-out period specified by the SIMTOC register, then a time-out condition will occur. The time-out function will stop when an I2C "STOP" condition occurs. Rev. 1.20 179 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU S ta rt S C L S R W S la v e A d d r e s s 0 1 S D A 1 1 0 1 0 A C K 1 0 I2 C t i m e - o u t c o u n te r s ta rt S to p S C L 1 0 0 1 0 1 0 0 S D A I2 C t im e - o u t c o u n t e r r e s e t o n S C L n e g a tiv e tr a n s itio n I2C Time-out When an I2C time-out counter overflow occurs, the counter will stop and the SIMTOEN bit will be cleared to zero and the SIMTOF bit will be set high to indicate that a time-out condition has occurred. The time-out condition will also generate an interrupt which uses the I2C interrrupt vector. When an I2C time-out occurs, the I2C internal circuitry will be reset and the registers will be reset into the following condition: After I2C Time-out Register SIMD, SIMA, SIMC0 No change SIMC1 Reset to POR condition I2C Register after Time-out The SIMTOF flag can be cleared by the application program. There are 64 time-out period selections which can be selected using the SIMTOS bits in the SIMTOC register. The time-out duration is calculated by the formula: ((1~64) × (32/fSUB)). This gives a time-out period which ranges from about 1ms to 64ms. • SIMTOC Register Bit 7 Name SIMTOEN 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0 Bit 7SIMTOEN: SIM I2C Time-out control 0: Disable 1: Enable Bit 6SIMTOF: SIM I2C Time-out flag 0: No time-out occurred 1: Time-out occurred Bit 5~0SIMTOS5~SIMTOS0: SIM I2C Time-out period selection I2C Time-out clock source is fSUB/32 I2C Time-out period is equal to (SIMTOS [5 : 0] + 1) × Rev. 1.20 180 32 f SUB July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Serial Interface – SPIA These devices contain an independent SPI function. It is important not to confuse this independent SPI function with the additional one contained within the combined SIM function, which is described in another section of this datasheet. This independent SPI function will carry the name SPIA to distinguish it from the other one in the SIM. This SPIA interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices, etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the device can be either master or slave. Although the SPIA interface specification can control multiple slave devices from a single master, this device is provided only one SCSA pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pins to select the slave devices. SPIA Interface Operation The SPIA interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDIA, SDOA, SCKA and SCSA. Pins SDIA and SDOA are the Serial Data Input and Serial Data Output lines, SCKA is the Serial Clock line and SCSA is the Slave Select line. As the SPIA interface pins are pin-shared with other functions, the SPIA interface pins must first be selected by configuring the corresponding selection bits in the pin-shared function selection registers. The SPIA interface function is disabled or enabled using the SPIAEN bit in the SPIAC0 register. Communication between devices connected to the SPIA interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The master also controls the clock/signal. As the device only contains a single SCSA pin only one slave device can be utilised. The SCSA pin is controlled by the application program, set the the SACSEN bit to "1" to enable the SCSA pin function and clear the SACSEN bit to "0" to place the SCSA pin into an a floating condition. SPIA Master/Slave Connection The SPIA Serial Interface function includes the following features: • Full-duplex synchronous data transfer • Both Master and Slave mode • LSB first or MSB first data transmission modes • Transmission complete flag • Rising or falling active clock edge The status of the SPIA interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as SACSEN and SPIAEN. Rev. 1.20 181 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU SPIA Block Diagram SPIA Registers There are three internal registers which control the overall operation of the SPIA interface. These are the SPIAD data register and two registers SPIAC0 and SPIAC1. Register Name SPIAC0 Bit 7 6 SASPI2 SASPI1 SPIAC1 — — SPIAD D7 D6 5 4 SASPI0 — SACKPOLB SACKEG D5 3 — SAMLS D4 D3 2 1 0 — SPIAEN SPIAICF SACSEN SAWCOL D2 D1 SATRF D0 SPIA Registers List SPIAD Register The SPIAD register is used to store the data being transmitted and received. Before the device writes data to the SPIA bus, the actual data to be transmitted must be placed in the SPIAD register. After the data is received from the SPIA bus, the device can read it from the SPIAD register. Any transmission or reception of data from the SPIA bus must be made via the SPIA register. Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown There are also two control registers for the SPIA interface, SPIAC0 and SPIAC1. Register SPIAC0 is used to control the enable/disable function and to set the data transmission clock frequency. Register SPIAC1 is used for other control functions such as LSB/MSB selection, write collision flag, etc. Rev. 1.20 182 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU SPIAC0 Register Bit 7 6 5 4 3 2 1 0 Name SASPI2 SASPI1 SASPI0 — — — SPIAEN SPIAICF R/W R/W R/W R/W — — — R/W R/W POR 1 1 1 — — — 0 0 Bit 7~5SASPI2~SASPI0: SPIA Master/Slave clock select 000: SPIA master mode with clock fSYS /4 001: SPIA master mode with clock fSYS /16 010: SPIA master mode with clock fSYS /64 011: SPIA master mode with clock fSUB 100: SPIA master mode with clock CTM0 CCRP match frequency/2 101: SPIA slave mode 11x: SPIA disable Bit 4~2 Unimplemented, read as "0" Bit 1SPIAEN: SPIA Enable Control 0: Disable 1: Enable The bit is the overall on/off control for the SPIA interface. When the SPIAEN bit is cleared to zero to disable the SPIA interface, the SDIA, SDOA, SCKA and SCSA lines will lose the SPIA function and the SPIA operating current will be reduced to a minimum value. When the bit is high the SPIA interface is enabled. Bit 0SPIAICF: SPIA Incomplete Flag 0: SPIA incomplete condition not occurred 1: SPIA incomplete condition occured This bit is only available when the SPIA is configured to operate in an SPIA slave mode. If the SPIA operates in the slave mode with the SPIAEN and SACSEN bits both being set to 1 but the SCSA line is pulled high by the external master device before the SPIA data transfer is completely finished, the SPIAICF bit will be set to 1 together with the SATRF bit. When this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. However, the SATRF bit will not be set to 1 if the SPIAICF bit is set to 1 by software application program. SPIAC1 Register Bit 7 6 Name — — R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 5 4 SACKPOLB SACKEG 3 SAMLS 2 1 0 SACSEN SAWCOL SATRF Unimplemented, read as "0" Bit 5SACKPOLB: SPIA clock line base condition selection 0: The SCKA line will be high when the clock is inactive. 1: The SCKA line will be low when the clock is inactive. The SACKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCKA line will be low when the clock is inactive. When the SACKPOLB bit is low, then the SCKA line will be high when the clock is inactive. Bit 4SACKEG: SPIA SCKA clock active edge type selection SACKPOLB=0 0: SCKA is high base level and data capture at SCKA rising edge 1: SCKA is high base level and data capture at SCKA falling edge SACKPOLB=1 0: SCKA is low base level and data capture at SCKA falling edge 1: SCKA is low base level and data capture at SCKA rising edge The SACKEG and SACKPOLB bits are used to setup the way that the clock signal Rev. 1.20 183 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU outputs and inputs data on the SPIA bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The SACKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCKA line will be low when the clock is inactive. When the SACKPOLB bit is low, then the SCKA line will be high when the clock is inactive. The SACKEG bit determines active clock edge type which depends upon the condition of SACKPOLB bit. Bit 3SAMLS: SPIA data shift order 0: LSB first 1: MSB first This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Bit 2SACSEN: SPIA SCSA pin control 0: Disable 1: Enable The SACSEN bit is used as an enable/disable for the SCSA pin. If this bit is low, then the SCSA pin function will be disabled and can be placed into a floating condition. If the bit is high, the SCSA pin will be enabled and used as a select pin. Bit 1SAWCOL: SPIA write collision flag 0: No collision 1: Collision The SAWCOL flag is used to detect whether a data collision has occurred or not. If this bit is high, it means that data has been attempted to be written to the SPIAD register duting a data transfer operation. This writing operation will be ignored if data is being transferred. This bit can be cleared by the application program. Bit 0SATRF: SPIA Transmit/Receive complete flag 0: SPIA data is being transferred 1: SPIA data transfer is completed The SATRF bit is the Transmit/Receive Complete flag and is set to 1 automatically when an SPIA data transfer is completed, but must cleared to 0 by the application program. It can be used to generate an interrupt. SPIA Communication After the SPIA interface is enabled by setting the SPIAEN bit high, then in the Master Mode, when data is written to the SPIAD register, transmission/reception will begin simultaneously. When the data transfer is complete, the SATRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SPIAD register will be transmitted and any data on the SDIA pin will be shifted into the SPIAD registers. The master should output a SCSA signal to enable the slave device before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCSA signal depending upon the configurations of the SACKPOLB bit and SACKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCSA signal for various configurations of the SACKPOLB and SACKEG bits. The SPIA will continue to function if the SPIA clock source is active. Rev. 1.20 184 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU SPIA Master/Slave Mode Timing Diagram Rev. 1.20 185 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU SPIA Transfer Control Flow Chart SPIA Bus Enable/Disable To enable the SPIA bus, set SACSEN=1 and SCSA =0, then wait for data to be written into the SPIAD (TXRX buffer) register. For the Master Mode, after data has been written to the SPIAD (TXRX buffer) register, then transmission or reception will start automatically. When all the data has been transferred the SATRF bit should be set. For the Slave Mode, when clock pulses are received on SCKA, data in the TXRX buffer will be shifted out or data on SDIA will be shifted in. When the SPIA bus is disabled, the SCKA, SDIA, SDOA and SCSA pins can become I/O pins or other pin-shared functions using the corresponding pin-shared function control bits. Rev. 1.20 186 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU SPIA Operation All communication is carried out using the 4-line interface for either Master or Slave Mode. The SACSEN bit in the SPIAC1 register controls the overall function of the SPIA interface. Setting this bit high will enable the SPIA interface by allowing the SCSA line to be active, which can then be used to control the SPIA interface. If the SACSEN bit is low, the SPIA interface will be disabled and the SCSA line will be in a floating condition and can therefore not be used for control of the SPIA interface. If the SACSEN bit and the SPIAEN bit in the SPIAC0 register are set high, this will place the SDIA line in a floating condition and the SDOA line high. If in Master Mode the SCKA line will be either high or low depending upon the clock polarity selection bit SACKPOLB in the SPIAC1 register. If in Slave Mode the SCKA line will be in a floating condition. If SPIAEN is low then the bus will be disabled and SCSA, SDIA, SDOA and SCKA pins will all become I/O pins or other pinshared functions using the corresponding pin-shared function control bits. In the Master Mode the Master will always generate the clock signal. The clock and data transmission will be initiated after data has been written into the SPIAD register. In the Slave Mode, the clock signal will be received from an external master device for both data transmission and reception. The following sequences show the order to be followed for data transfer in both Master and Slave Mode. Master Mode: • Step 1 Select the clock source and Master mode using the SASPI2~SASPI0 bits in the SPIAC0 control register. • Step 2 Setup the SACSEN bit and setup the SAMLS bit to choose if the data is MSB or LSB shifted first, this must be same as the Slave device. • Step 3 Setup the SPIAEN bit in the SPIAC0 control register to enable the SPIA interface. • Step 4 For write operations: write the data to the SPIAD register, which will actually place the data into the TXRX buffer. Then use the SCKA and SCSA lines to output the data. After this go to step 5. For read operations: the data transferred in on the SDIA line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SPIAD register. • Step 5 Check the SAWCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step. • Step 6 Check the SATRF bit or wait for a SPIA serial bus interrupt. • Step 7 • Read data from the SPIAD register. • Step 8 Clear SATRF. • Step 9 Go to step 4. Rev. 1.20 187 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Slave Mode: • Step 1 Select the SPI Slave mode using the SASPI2~SASPI0 bits in the SPIAC0 control register • Step 2 Setup the SACSEN bit and setup the SAMLS bit to choose if the data is MSB or LSB shifted first, this setting must be the same with the Master device. • Step 3 Setup the SPIAEN bit in the SPIAC0 control register to enable the SPIA interface. • Step 4 For write operations: write the data to the SPIAD register, which will actually place the data into the TXRX buffer. Then wait for the master clock SCKA and SCSA signal. After this, go to step 5. For read operations: the data transferred in on the SDIA line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SPIAD register. • Step 5 Check the SAWCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step. • Step 6 Check the SATRF bit or wait for a SPIA serial bus interrupt. • Step 7 Read data from the SPIAD register. • Step 8 Clear SATRF. • Step 9 Go to step 4. Error Detection The SAWCOL bit in the SPIAC1 register is provided to indicate errors during data transfer. The bit is set by the SPIA serial Interface but must be cleared by the application program. This bit indicates a data collision has occurred which happens if a write to the SPIAD register takes place during a data transfer operation and will prevent the write operation from continuing. Rev. 1.20 188 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU SCOM Function for LCD – HT66FV150/HT66FV160 These devices have the capability of driving external LCD panels. The common pins for LCD driving, SCOM0~SCOM3, are pin shared with the I/O pins. The LCD signals (COM and SEG) are generated using the application program. The SCOM function is integrated in the HT66FV150 and HT66FV160 devices. LCD Operation An external LCD panel can be driven using this device by configuring the I/O pins as common pins and using other output ports lines as segment pins. The LCD driver function is controlled using the SCOMC register which in addition to controlling the overall on/off function also controls the bias voltage setup function. This enables the LCD COM driver to generate the necessary VDD/2 voltage levels for LCD 1/2 bias operation. The SCOMEN bit in the SCOMC register is the overall master control for the LCD driver. The LCD SCOMn pin is selected to be used for LCD driving by the corresponding pin-shared function selection bits. Note that the Port Control register does not need to first setup the pins as outputs to enable the LCD driver operation. LCD COM Bias LCD Bias Control The LCD COM driver enables a range of selections to be provided to suit the requirement of the LCD panel which is being used. The bias resistor choice is implemented using the ISEL1 and ISEL0 bits in the SCOMC register. SCOMC Register Bit 7 6 5 4 3 2 1 0 Name — ISEL1 ISEL0 SCOMEN — — — — R/W — R/W R/W R/W — — — — POR — 0 0 0 — — — — Bit 7 Unimplemented, read as "0" Bit 6~5ISEL1~ISEL0: Select SCOM typical bias current (VDD=5V) 00: 25μA 01: 50μA 10: 100μA 11: 200μA Bit 4SCOMEN: SCOM Function enable control 0: Disable 1: Enable Bit 3~0 Rev. 1.20 Unimplemented, read as "0" 189 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Voice Playing Controller These devices contain a fully integrated 16-bit D/A converter complete with volume control together with a power amplifier. The voice data located in the PLADH and PLADL register pair can be output to the external speaker using the 16-bit D/A converter. The power amplifier offers the possibility of directly driving external speakers. The volume control can be adjusted using the USVC [6:0] bits. PLADH 8 PLADL 8 16-bit D/A + Power Amplifier Speaker DAEN PAEN USVC[6:0] Voice Playing Controller Block Diagram Voice Controller Registers The overall voice play function is controlled using a series of registers. Two control registers exist to control the 16-bit D/A converter and power amplifier functions together with the speaker mute control. Two data register pairs exist to store the data which is to be played. Bit Register Name 7 6 5 4 3 2 1 0 USVC MUTEB USVC6 USVC5 USVC4 USVC3 USVC2 USVC1 USVC0 PLAC — — — — — — PAEN DAEN PLADL P_D7 P_D6 P_D5 P_D4 P_D3 P_D2 P_D1 P_D0 PLADH P_D15 P_D14 P_D13 P_D12 P_D11 P_D10 P_D9 P_D8 Voice Playing Controller Registers List USVC Register Bit 7 6 5 4 3 2 1 0 Name MUTEB USVC6 USVC5 USVC4 USVC3 USVC2 USVC1 USVC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7MUTEB: Speaker Mute control 0: Mute speaker output 1: Enable speaker output This bit is used to enable the speaker function. When this bit is cleared to 0, the speaker function will be disabled. The D/A converter and power amplifier will also be disabled. Rev. 1.20 190 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Bit 6~0USVC6~USVC0: Speaker volume control 000_1100: Gain ≈ 6.0 dB 110_1110: Gain ≈ -9.0 dB 000_1011: Gain ≈ 5.5 dB 110_1101: Gain ≈ -9.5 dB 000_1010: Gain ≈ 5.0 dB 110_1100: Gain ≈ -10.0 dB 000_1001: Gain ≈ 4.5 dB 110_1011: Gain ≈ -10.5 dB 000_1000: Gain ≈ 4.0 dB 110_1010: Gain ≈ -11.0 dB 000_0111: Gain ≈ 3.5 dB 110_1001: Gain ≈ -11.5 dB 000_0110: Gain ≈ 3.0 dB 110_1000: Gain ≈ -12.0 dB 000_0101: Gain ≈ 2.5 dB 110_0111: Gain ≈ -13.0 dB 000_0100: Gain ≈ 2.0 dB 110_0110: Gain ≈ -14.0 dB Gain ≈ 1.5 dB 110_0101: Gain ≈ -15.0 dB 000_0010: Gain ≈ 1.0 dB 110_0100: Gain ≈ -16.0 dB 000_0001: Gain ≈ 0.5 dB 110_0011: Gain ≈ -17.0 dB 000_0000: Gain ≈ 0.0 dB 110_0010: Gain ≈ -18.0 dB 000_0011: 111_1111: Gain ≈ -0.5 dB 110_0001: Gain ≈ -19.0 dB 111_1110: Gain ≈ -1.0 dB 110_0000: Gain ≈ -20.0 dB 111_1101: Gain ≈ -1.5 dB 101_1111: Gain ≈ -21.0 dB 111_1100: Gain ≈ -2.0 dB 101_1110: Gain ≈ -22.0 dB 111_1011: Gain ≈ -2.5 dB 101_1101: Gain ≈ -23.0 dB 111_1010: Gain ≈ -3.0 dB 101_1100: Gain ≈ -24.0 dB 111_1001: Gain ≈ -3.5 dB 101_1011: Gain ≈ -25.0 dB 111_1000: Gain ≈ -4.0 dB 101_1010: Gain ≈ -26.0 dB 111_0111: Gain ≈ -4.5 dB 101_1001: Gain ≈ -27.0 dB 111_0110: Gain ≈ -5.0 dB 101_1000: Gain ≈ -28.0 dB 111_0101: Gain ≈ -5.5 dB 101_0111: Gain ≈ -29.0 dB 111_0100: Gain ≈ -6.0 dB 101_0110: Gain ≈ -30.0 dB 111_0011: Gain ≈ -6.5 dB 101_0101: Gain ≈ -31.0 dB 111_0010: Gain ≈ -7.0 dB 101_0100: Gain ≈ -32.0 dB 111_0001: Gain ≈ -7.5 dB Others: Reserved 111_0000: Gain ≈ -8.0 dB 110_1111: Gain ≈ -8.5 dB These bits are used to control the output volume which ranges from -32dB~6dB. Rev. 1.20 191 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU PLAC Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — PAEN DAEN R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1PAEN: Power Amplifier Enable control 0: Disable 1: Enable Bit 0DAEN: 16-bit D/A converter Enable control 0: Disable 1: Enable Note that the 16-bit D/A converter and power amplifier will all be disabled when the MCU enters the Power down Mode. PLADL Register Bit 7 6 5 4 3 2 1 0 Name P_D7 P_D6 P_D5 P_D4 P_D3 P_D2 P_D1 P_D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0P_D7~P_D0: Play data low byte register bit 7~bit 0 This register is used to store the 16-bit play data low byte. Note that the low byte play data register should first be modified followed by the high byte play data register being written if the 16-bit play data is necessary to be updated. PLADH Register Bit 7 6 5 4 3 2 1 0 Name P_D15 P_D14 P_D13 P_D12 P_D11 P_D10 P_D9 P_D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0P_D15~P_D8: Played data high byte register bit 7~bit 0 This register is used to store the 16-bit play data high byte data. Note that the low byte play data register should first be modified followed by the high byte play data register being written if the 16-bit play data is necessary to be updated. Rev. 1.20 192 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. These devices contain several external interrupt and internal interrupts functions. The external interrupts are generated by the action of the external INT0 and INT1 pins, while the internal interrupts are generated by various internal functions such as the TMs, Time Base, LVD, EEPROM, SIM, UART and the A/D converter, etc. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The number of registers depends upon the device chosen but fall into three categories. The first is the INTC0~INTC2 registers which setup the primary interrupts, the second is the MFI0~MFI3 registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual interrupts as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "E" for enable/disable bit or "F" for request flag. Function Enable Bit Global Request Flag Notes EMI — — INTn Pins INTnE INTnF n=0~1 Multi-function MFnE MFnF n = 0, 1, 3 A/D Converter ADE ADF — Time Base TBnE TBnF n=0~1 LVD LVE LVF — EEPROM write operation DEE DEF — — SPIA CTM PTM SPIAE SPIAF CTMnPE CTMnPF CTMnAE CTMnAF PTMnPE PTMnPF PTMnAE PTMnAF n=0 n=0 Interrupt Register Bit Naming Conventions – HT66FV130 Rev. 1.20 193 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Function Enable Bit Request Flag EMI — — INTn Pins INTnE INTnF n=0~1 Multi-function MFnE MFnF n=0~3 A/D Converter ADE ADF — Time Base Global Notes TBnE TBnF n=0~1 LVD LVE LVF — EEPROM write operation DEE DEF — SIM SIME SIMF — SPIA SPIAE SPIAF — CTMnPE CTMnPF CTMnAE CTMnAF PTMnPE PTMnPF PTMnAE PTMnAF CTM PTM n=0 n=0~1 Interrupt Register Bit Naming Conventions – HT66FV140 Function Enable Bit Request Flag Notes EMI — — INTn Pins INTnE INTnF n=0~1 Multi-function MFnE MFnF n=0~3 Global A/D Converter ADE ADF — Time Base TBnE TBnF n=0~1 UART URE URF — LVD LVE LVF — EEPROM write operation DEE DEF — SIM SIME SIMF — — SPIA CTM PTM SPIAE SPIAF CTMnPE CTMnPF CTMnAE CTMnAF PTMnPE PTMnPF PTMnAE PTMnAF n=0~1 n=0~1 Interrupt Register Bit Naming Conventions – HT66FV150 Rev. 1.20 194 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Function Enable Bit Request Flag EMI — — INTn Pins INTnE INTnF n=0~1 Multi-function MFnE MFnF n=0~3 A/D Converter ADE ADF — Time Base TBnE TBnF n=0~1 UART URE URF — LVD LVE LVF — EEPROM write operation DEE DEF — SIM SIME SIMF — SPIA SPIAE SPIAF — CTMnPE CTMnPF CTMnAE CTMnAF STMnPE STMnPF STMnAE STMnAF PTMnPE PTMnPF PTMnAE PTMnAF Global CTM STM PTM Notes n=0~1 n=0 n=0~1 Interrupt Register Bit Naming Conventions – HT66FV160 Bit Register Name 7 INTEG — — INTC0 — MF1F INTC1 TB0F ADF INTC2 — MFI0 MFI1 MFI3 6 5 4 3 2 1 0 — — INT1S1 INT1S0 INT0S1 INT0S0 MF0F INT0F MF1E MF0E INT0E EMI MF3F — TB0E ADE MF3E — — INT1F TB1F — — INT1E TB1E — — CTM0AF CTM0PF — — CTM0AE CTM0PE — — PTM0AF PTM0PF — — PTM0AE PTM0PE DEF SPIAF — LVF DEE SPIAE — LVE Interrupt Registers List – HT66FV130 Bit Register Name 7 6 5 4 3 2 1 0 INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0 INTC0 — MF1F MF0F INT0F MF1E MF0E INT0E EMI INTC1 TB0F ADF MF3F MF2F TB0E ADE MF3E MF2E INTC2 — — INT1F TB1F — — INT1E TB1E MFI0 — — CTM0AF CTM0PF — — CTM0AE CTM0PE MFI1 — — PTM0AF PTM0PF — — PTM0AE PTM0PE MFI2 — — PTM1AF PTM1PF — — PTM1AE PTM1PE MFI3 DEF SPIAF SIMF LVF DEE SPIAE SIME LVE Interrupt Registers List – HT66FV140 Rev. 1.20 195 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Bit Register Name 7 6 5 4 3 2 1 0 INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0 INTC0 — MF1F MF0F INT0F MF1E MF0E INT0E EMI INTC1 TB0F ADF MF3F MF2F TB0E ADE MF3E MF2E TB1F — URE INT1E TB1E INTC2 — URF INT1F MFI0 CTM1AF CTM1PF CTM0AF CTM0PF CTM1AE CTM1PE CTM0AE CTM0PE MFI1 — — PTM0AF PTM0PF — — PTM0AE PTM0PE MFI2 — — PTM1AF PTM1PF — — PTM1AE PTM1PE MFI3 DEF SPIAF SIMF LVF DEE SPIAE SIME LVE Interrupt Registers List – HT66FV150 Bit Register Name 7 6 5 4 3 2 1 0 INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0 INTC0 — MF1F MF0F INT0F MF1E MF0E INT0E EMI INTC1 TB0F ADF MF3F MF2F TB0E ADE MF3E MF2E TB1F — URE INT1E TB1E INTC2 — URF INT1F MFI0 CTM1AF CTM1PF CTM0AF CTM0PF CTM1AE CTM1PE CTM0AE CTM0PE MFI1 STM0AF STM0PF PTM0AF PTM0PF STM0AE STM0PE PTM0AE PTM0PE MFI2 — — PTM1AF PTM1PF — — PTM1AE PTM1PE MFI3 DEF SPIAF SIMF LVF DEE SPIAE SIME LVE Interrupt Registers List – HT66FV160 INTEG Register Bit 7 6 5 4 3 2 1 0 Name — — — — INT1S1 INT1S0 INT0S1 INT0S0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3~2INT1S1~INT1S0: Interrupt edge control for INT1 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges Bit 1~0INT0S1~INT0S0: Interrupt edge control for INT0 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges Rev. 1.20 196 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU INTC0 Register Bit 7 6 5 4 3 2 1 0 Name — MF1F MF0F INT0F MF1E MF0E INT0E EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6MF1F: Multi-function 1 interrupt request flag 0: no request 1: interrupt request Bit 5MF0F: Multi-function 0 interrupt request flag 0: no request 1: interrupt request Bit 4INT0F: INT0 interrupt request flag 0: no request 1: interrupt request Bit 3MF1E: Multi-function 1 interrupt control 0: Disable 1: Enable Bit 2MF0E: Multi-function 0 interrupt control 0: Disable 1: Enable Bit 1INT0E: INT0 interrupt control 0: Disable 1: Enable Bit 0EMI: Global interrupt control 0: Disable 1: Enable INTC1 Register – HT66FV130 Bit 7 6 5 4 3 2 1 0 Name TB0F ADF MF3F — TB0E ADE MF3E — R/W R/W R/W R/W — R/W R/W R/W — POR 0 0 0 — 0 0 0 — Bit 7TB0F: Time Base 0 interrupt request flag 0: no request 1: interrupt request Bit 6ADF: A/D Converter interrupt request flag 0: no request 1: interrupt request Bit 5MF3F: Multi-function 3 interrupt request flag 0: no request 1: interrupt request Bit 4 Unimplemented, read as "0" Bit 3TB0E: Time Base 0 interrupt control 0: Disable 1: Enable Bit 2ADE: A/D Converter interrupt control 0: Disable 1: Enable Bit 1MF3E: Multi-function 3 interrupt control 0: Disable 1: Enable Bit 0 Rev. 1.20 Unimplemented, read as "0" 197 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU INTC1 Register – HT66FV140/HT66FV150/HT66FV160 Bit 7 6 5 4 3 2 1 0 Name TB0F ADF MF3F MF2F TB0E ADE MF3E MF2E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7TB0F: Time Base 0 interrupt request flag 0: no request 1: interrupt request Bit 6ADF: A/D Converter interrupt request flag 0: no request 1: interrupt request Bit 5MF3F: Multi-function 3 interrupt request flag 0: no request 1: interrupt request Bit 4MF2F: Multi-function 2 interrupt request flag 0: no request 1: interrupt request Bit 3TB0E: Time Base 0 interrupt control 0: Disable 1: Enable Bit 2ADE: A/D Converter interrupt control 0: Disable 1: Enable Bit 1MF3E: Multi-function 3 interrupt control 0: Disable 1: Enable Bit 0MF2E: Multi-function 2 interrupt control 0: Disable 1: Enable INTC2 Register – HT66FV130/HT66FV140 Bit 7 6 5 4 3 2 1 0 Name — — INT1F TB1F — — INT1E TB1E R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5INT1F: INT1 interrupt request flag 0: no request 1: interrupt request Bit 4TB1F: Time Base 1 interrupt request flag 0: no request 1: interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1INT1E: INT1 interrupt control 0: Disable 1: Enable Bit 0TB1E: Time Base 1 interrupt control 0: Disable 1: Enable Rev. 1.20 198 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU INTC2 Register – HT66FV150/HT66FV160 Bit 7 6 5 4 3 2 1 0 Name — URF INT1F TB1F — URE INT1E TB1E R/W — R/W R/W R/W — R/W R/W R/W POR — 0 0 0 — 0 0 0 1 0 Bit 7 Unimplemented, read as "0" Bit 6URF: UART transfer interrupt request flag 0: No request 1: Interrupt request Bit 5INT1F: INT1 interrupt request flag 0: No request 1: Interrupt request Bit 4TB1F: Time Base 1 interrupt request flag 0: No request 1: Interrupt request Bit 3 Unimplemented, read as "0" Bit 2URE: UART transfer interrupt control 0: Disable 1: Enable Bit 1INT1E: INT1 interrupt control 0: Disable 1: Enable Bit 0TB1E: Time Base 1 interrupt control 0: Disable 1: Enable MFI0 Register – HT66FV130/HT66FV140 Bit 7 6 5 4 3 2 Name — — CTM0AF CTM0PF — — R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 CTM0AE CTM0PE Unimplemented, read as "0" Bit 5CTM0AF: CTM0 Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 4CTM0PF: CTM0 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1CTM0AE: CTM0 Comparator A match Interrupt control 0: Disable 1: Enable Bit 0CTM0PE: CTM0 Comparator P match Interrupt control 0: Disable 1: Enable Rev. 1.20 199 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU MFI0 Register – HT66FV150/HT66FV160 Bit 7 6 5 Name CTM1AF CTM1PF CTM0AF 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 CTM0PF CTM1AE CTM1PE CTM0AE CTM0PE Bit 7CTM1AF: CTM1 Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 6CTM1PF: CTM1 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 5CTM0AF: CTM0 Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 4CTM0PF: CTM0 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 3CTM1AE: CTM1 Comparator A match Interrupt control 0: Disable 1: Enable Bit 2CTM1PE: CTM1 Comparator P match Interrupt control 0: Disable 1: Enable Bit 1CTM0AE: CTM0 Comparator A match Interrupt control 0: Disable 1: Enable Bit 0CTM0PE: CTM0 Comparator P match Interrupt control 0: Disable 1: Enable MFI1 Register – HT66FV130/HT66FV140/HT66FV150 Bit 7 6 5 4 3 2 1 0 Name — — PTM0AF PTM0PF — — PTM0AE PTM0PE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5PTM0AF: PTM0 Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 4PTM0PF: PTM0 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1PTM0AE: PTM0 Comparator A match Interrupt control 0: Disable 1: Enable Bit 0PTM0PE: PTM0 Comparator P match Interrupt control 0: Disable 1: Enable Rev. 1.20 200 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU MFI1 Register – HT66FV160 Bit 7 6 5 4 3 2 1 0 Name STM0AF STM0PF PTM0AF PTM0PF STM0AE STM0PE PTM0AE PTM0PE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7STM0AF: STM0 Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 6STM0PF: STM0 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 5PTM0AF: PTM0 Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 4PTM0PF: PTM0 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 3STM0AE: STM0 Comparator A match Interrupt control 0: Disable 1: Enable Bit 2STM0PE: STM0 Comparator P match Interrupt control 0: Disable 1: Enable Bit 1PTM0AE: PTM0 Comparator A match Interrupt control 0: Disable 1: Enable Bit 0PTM0PE: PTM0 Comparator P match Interrupt control 0: Disable 1: Enable MFI2 Register – HT66FV140/HT66FV150/HT66FV160 Bit 7 6 5 4 3 2 1 0 Name — — PTM1AF PTM1PF — — PTM1AE PTM1PE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5PTM1AF: PTM1 Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 4PTM1PF: PTM1 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1PTM1AE: PTM1 Comparator A match Interrupt control 0: Disable 1: Enable Bit 0PTM1PE: PTM1 Comparator P match Interrupt control 0: Disable 1: Enable Rev. 1.20 201 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU MFI3 Register – HT66FV130 Bit 7 6 5 4 3 2 1 0 Name DEF SPIAF — LVF DEE SPIAE — LVE R/W R/W R/W — R/W R/W R/W — R/W POR 0 0 — 0 0 0 — 0 Bit 7DEF: Data EEPROM Interrupt request flag 0: No request 1: Interrupt request Bit 6SPIAF: SPIA Interrupt request flag 0: No request 1: Interrupt request Bit 5 Unimplemented, read as "0" Bit 4LVF: LVD Interrupt request flag 0: No request 1: Interrupt request Bit 3DEE: Data EEPROM Interrupt control 0: Disable 1: Enable Bit 2SPIAE: SPIA Interrupt control 0: Disable 1: Enable Bit 1 Unimplemented, read as "0" Bit 0LVE: LVD Interrupt control 0: Disable 1: Enable MFI3 Register – HT66FV140/HT66FV150/HT66FV160 Bit 7 6 5 4 3 2 1 0 Name DEF SPIAF SIMF LVF DEE SPIAE SIME LVE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7DEF: Data EEPROM Interrupt request flag 0: No request 1: Interrupt request Bit 6SPIAF: SPIA Interrupt request flag 0: No request 1: Interrupt request Bit 5SIMF: SIM Interrupt request flag 0: No request 1: Interrupt request Bit 4LVF: LVD Interrupt request flag 0: No request 1: Interrupt request Bit 3DEE: Data EEPROM Interrupt control 0: Disable 1: Enable Bit 2SPIAE: SPIA Interrupt control 0: Disable 1: Enable Bit 1SIME: SIM Interrupt control 0: Disable 1: Enable Bit 0LVE: LVD Interrupt control 0: Disable 1: Enable Rev. 1.20 202 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P or Comparator A or A/ D conversion completion, etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. Rev. 1.20 203 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Legend xxF Req�est F�ag� no a�to reset in ISR xxF Req�est F�ag� a�to reset in ISR xxE Enab�e Bits Interr�pts contained within M��ti-F�nction Interr�pts EMI a�to disab�ed in ISR Interr�pt Name Req�est F�ags Enab�e Bits Master Enab�e INT0 Pin INT0F INT0E EMI M. F�nct. 0 MF0F MF0E EMI 08H M. F�nct. 1 MF1F MF1E EMI 0CH Vector Priorit� High 04H CTM0 P CTM0PF CTM0PE CTM0 A CTM0AF CTM0AE PTM0 P PTM0PF PTM0PE PTM0 A PTM0AF PTM0AE M. F�nct. 3 MF3F MF3E EMI 14H A/D ADF ADE EMI 18H Time Base 0 TB0F TB0E EMI 1CH Time Base 1 TB1F TB1E EMI 20H INT1 Pin INT1F INT1E EMI 24H LVD LVF LVE SPIA SPIAF SPIAE EEPROM DEF DEE Low Interrupt Scheme – HT66FV130 Legend xxF Req�est F�ag� no a�to reset in ISR xxF Req�est F�ag� a�to reset in ISR xxE Enab�e Bits Interr�pts contained within M��ti-F�nction Interr�pts EMI a�to disab�ed in ISR Interr�pt Name Req�est F�ags Enab�e Bits Master Enab�e INT0 Pin INT0F INT0E EMI M. F�nct. 0 MF0F MF0E EMI 08H M. F�nct. 1 MF1F MF1E EMI 0CH Vector Priorit� High 04H CTM0 P CTM0PF CTM0PE CTM0 A CTM0AF CTM0AE PTM0 P PTM0PF PTM0PE PTM0 A PTM0AF PTM0AE M. F�nct. 2 MF2F MF2E EMI 10H PTM1 P PTM1PF PTM1PE M. F�nct. 3 MF3F MF3E EMI 14H PTM1 A PTM1AF PTM1AE A/D ADF ADE EMI 18H LVD LVF LVE Time Base 0 TB0F TB0E EMI 1CH SIM SIMF SIME SPIA SPIAF SPIAE Time Base 1 TB1F TB1E EMI 20H EEPROM DEF DEE INT1 Pin INT1F INT1E EMI 24H Low Interrupt Scheme – HT66FV140 Rev. 1.20 204 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Legend xxF Req�est F�ag� no a�to reset in ISR xxF Req�est F�ag� a�to reset in ISR xxE Enab�e Bits Interr�pts contained within M��ti-F�nction Interr�pts EMI a�to disab�ed in ISR Interr�pt Name Req�est F�ags Enab�e Bits Master Enab�e INT0 Pin INT0F INT0E EMI 04H M. F�nct. 0 MF0F MF0E EMI 08H M. F�nct. 1 MF1F MF1E EMI 0CH M. F�nct. 2 MF2F MF2E EMI 10H M. F�nct. 3 MF3F MF3E EMI 14H A/D ADF ADE EMI 18H Vector Priorit� CTM0 P CTM0PF CTM0PE CTM0 A CTM0AF CTM0AE CTM1 P CTM1PF CTM1PE CTM1 A CTM1AF CTM1AE PTM0 P PTM0PF PTM0PE PTM0 A PTM0AF PTM0AE PTM1 P PTM1PF PTM1PE PTM1 A PTM1AF PTM1AE Time Base 0 TB0F TB0E EMI 1CH Time Base 1 TB1F TB1E EMI 20H INT1 Pin INT1F INT1E EMI 24H UART URF URE EMI 28H LVD LVF LVE SIM SIMF SIME SPIA SPIAF SPIAE EEPROM DEF DEE High Low Interrupt Scheme – HT66FV150 Legend xxF Req�est F�ag� no a�to reset in ISR xxF Req�est F�ag� a�to reset in ISR xxE Enab�e Bits Interr�pts contained within M��ti-F�nction Interr�pts CTM0 P CTM0PF EMI a�to disab�ed in ISR Interr�pt Name Req�est F�ags Enab�e Bits Master Enab�e INT0 Pin INT0F INT0E EMI M. F�nct. 0 MF0F MF0E EMI 08H M. F�nct. 1 MF1F MF1E EMI 0CH M. F�nct. 2 MF2F MF2E EMI 10H M. F�nct. 3 MF3F MF3E EMI 14H A/D ADF ADE EMI 18H Time Base 0 TB0F TB0E EMI 1CH Time Base 1 TB1F TB1E EMI 20H INT1 Pin INT1F INT1E EMI 24H UART URF URE EMI 28H Vector Priorit� High 04H CTM0PE CTM0 A CTM0AF CTM0AE CTM1 P CTM1PF CTM1PE CTM1 A CTM1AF CTM1AE PTM0 P PTM0PF PTM0PE PTM0 A PTM0AF PTM0AE STM0 P STM0PF STM0PE STM0 A STM0AF STM0AE PTM1 P PTM1PF PTM1PE PTM1 A PTM1AF PTM1AE LVD LVF LVE SIM SIMF SIME SPIA SPIAF SPIAE EEPROM DEF DEE Low Interrupt Scheme – HT66FV160 Rev. 1.20 205 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU External Interrupt The external interrupts are controlled by signal transitions on the pins INT0~INT1. An external interrupt request will take place when the external interrupt request flags, INT0F~INT1F, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E~INT1E, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set and the external interrupt pin is selected by the corresponding pin-shared function selection bits. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flags, INT0F~INT1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Multi-function Interrupt Within the device there are up to four Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM interrupts, LVD interrupt, EEPROM write operation interrupt, SIM and SPIA interface interrupts. A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags MFnF are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related MultiFunction request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt request flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts will not be automatically reset and must be manually reset by the application program. A/D Converter Interrupt The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/ D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs when the A/D conversion process finishes. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the A/D Converter Interrupt vector, will take place. When the interrupt is serviced, the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Rev. 1.20 206 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Time Base Interrupt The function of the Time Base Interrupt is to provide regular time signal in the form of an internal interrupt. It is controlled by the overflow signal from its internal timer. When this happens its interrupt request flag, TBnF, will be set. To allow the program to branch to its respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bit, TBnE, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to its respective vector location will take place. When the interrupt is serviced, the interrupt request flag, TBnF, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Its clock source, fPSC, originates from the internal clock source fSYS, fSYS/4 or fSUB and then passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TB0C and TB1C registers to obtain longer interrupt periods whose value ranges. The clock source which in turn controls the Time Base interrupt period is selected using the CLKSEL1 and CLKSEL0 bits in the PSCR register. M U X TB0ON fSYS fSYS/4 fSUB M U X fPSC Presca�er Time Base 0 Interr�pt fPSC/28 ~ fPSC/21� TB0[2:0] M U X TB1ON CLKSEL[1:0] Time Base 1 Interr�pt TB1[2:0] Time Base Interrupts PSCR Register Bit 7 6 5 4 3 2 Name — — — — — — R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 1 0 CLKSEL1 CLKSEL0 unimplemented, read as "0" Bit 1~0CLKSEL1~CLKSEL0: Prescaler clock source selection 00: fSYS 01: fSYS/4 1x: fSUB Rev. 1.20 207 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU TB0C Register Bit 7 6 5 4 3 2 1 0 Name TB0ON — — — — TB02 TB01 TB00 R/W R/W — — — — R/W R/W R/W POR 0 — — — — 0 0 0 Bit 7TB0ON: Time Base 0 Enable Control 0: Disable 1: Enable Bit 6~3 unimplemented, read as "0" Bit 2~0TB02~TB00: Time Base 0 time-out period selection 000: 28/fPSC 001: 29/fPSC 010: 210/fPSC 011: 211/fPSC 100: 212/fPSC 101: 213/fPSC 110: 214/fPSC 111: 215/fPSC TB1C Register Bit 7 6 5 4 3 2 1 0 Name TB1ON — — — — TB12 TB11 TB10 R/W R/W — — — — R/W R/W R/W POR 0 — — — — 0 0 0 Bit 7TB1ON: Time Base 1 Enable Control 0: Disable 1: Enable Bit 6~3 unimplemented, read as "0" Bit 2~0TB12~TB10: Time Base 1 time-out period selection 000: 28/fPSC 001: 29/fPSC 010: 210/fPSC 011: 211/fPSC 100: 212/fPSC 101: 213/fPSC 110: 214/fPSC 111: 215/fPSC UART Transfer Interrupt – HT66FV150/HT66FV160 The UART Transfer Interrupt is controlled by several UART transfer conditions. When one of these conditions occurs, an interrupt pulse will be generated to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and UART Interrupt enable bit, URE, must first be set. When the interrupt is enabled, the stack is not full and any of the conditions described above occurs, a subroutine call to the UART Interrupt vector, will take place. When the interrupt is serviced, the UART Interrupt flag, URF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Rev. 1.20 208 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Serial Interface Module Interrupt – HT66FV140/HT66FV150/HT66FV160 The Serial Interface Module Interrupt, also known as the SIM interrupt, is contained within the Multi-function Interrupt. A SIM Interrupt request will take place when the SIM Interrupt request flag, SIMF, is set, which occurs when a byte of data has been received or transmitted by the SIM interface or I2C address match or I2C time-out. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, the Serial Interface Interrupt enable bit, SIME, and Muti-function interrupt enable bit must first be set. When the interrupt is enabled, the stack is not full and any of these situations occur, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the Serial Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the SIMF flag will not be automatically cleared, it has to be cleared by the application program. SPIA Interface Interrupt The SPIA Interface Module Interrupt is contained within the Multi-function Interrupt. A SPIA Interrupt request will take place when the SPIA Interrupt request flag, SPIAF, is set, which occurs when a byte of data has been received or transmitted by the SPIA interface. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, the Serial Interface Interrupt enable bit, SPIAE, and Muti-function interrupt enable bit must first be set. When the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the SPIA interface, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the SPIA Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the SPIAF flag will not be automatically cleared, it has to be cleared by the application program. LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the Multi-function Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts. However, only the Multi-function interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically cleared, it has to be cleared by the application program. Rev. 1.20 209 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU EEPROM Interrupt The EEPROM Write Interrupt is contained within the Multi-function Interrupt. An EEPROM Write Interrupt request will take place when the EEPROM Write Interrupt request flag, DEF, is set, which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, EEPROM Write Interrupt enable bit, DEE, and associated Multi-function interrupt enable bit must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective Multi-function Interrupt vector will take place. When the EEPROM Write Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts. However, only the Multi-function interrupt request flag will be automatically cleared. As the DEF flag will not be automatically cleared, it has to be cleared by the application program. TM Interrupt The Compact, Standard and Periodic TMs have two interrupts, one comes from the comparator A match situation and the other comes from the comparator P match situation. All of the TM interrupts are contained within the Multi-function Interrupts. For all of the TM types there are two interrupt request flags and two enable control bits. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or A match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts. However, only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though these devices are in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Rev. 1.20 210 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MFnF, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the "CALL" instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in the SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Rev. 1.20 211 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Low Voltage Detector – LVD Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be determined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Bit 7 6 5 4 3 2 1 0 Name — — LVDO LVDEN — VLVD2 VLVD1 VLVD0 R/W — — R R/W — R/W R/W R/W POR — — 0 0 — 0 0 0 Bit 7~6 unimplemented, read as "0" Bit 5LVDO: LVD output flag 0: No Low Voltage Detected 1: Low Voltage Detected Bit 4LVDEN: Low Voltage Detector Enable control 0: Disable 1: Enable Bit 3 unimplemented, read as "0" Bit 2~0VLVD2~VLVD0: LVD Voltage selection 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.0V Rev. 1.20 212 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V. When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multifunction interrupts, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set high by a low voltage condition. When the device is powered down the Low Voltage Detector will remain active if the LVDEN bit is high. In this case, the LVF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is not required then the LVF flag should be first set high before the device enters the SLEEP or IDLE Mode. Rev. 1.20 213 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU UART Interface – HT66FV150/HT66FV160 These devices contain an integrated full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. The UART function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. The integrated UART function contains the following features: • Full-duplex, asynchronous communication • 8 or 9 bits character length • Even, odd or no parity options • One or two stop bits • Baud rate generator with 8-bit prescaler • Parity, framing, noise and overrun error detection • Support for interrupt on address detect (last character bit=1) • Separately enabled transmitter and receiver • 2-byte Deep FIFO Receive Data Buffer • Transmit and receive interrupts • Interrupts can be initialized by the following conditions: ♦♦ Transmitter Empty ♦♦ Transmitter Idle ♦♦ Receiver Full ♦♦ Receiver Overrun ♦♦ Address Mode Detect Transmitter Shift Register (TSR) MSB ………………………… LSB TX Pin TX Register (TXR) RX Pin Receiver Shift Register (RSR) MSB ………………………… LSB RX Register (RXR) B�ffer Ba�d Rate Generator fSYS Data to be transmitted Data received MCU Data B�s UART Data Transfer Block Diagram Rev. 1.20 214 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU UART External Pin To communicate with an external serial interface, the internal UART has two external pins known as TX and RX. The TX and RX pins are the UART transmitter and receiver pins respectively. The TX and RX pin function should first be selected by the corresponding pin-shared function selection register before the UART function is used. Along with the UARTEN bit, the TXEN and RXEN bits, if set, will automatically setup these I/O or other pin-shared functional pins to their respective TX output and RX input conditions and disable any pull-high resistor option which may exist on the TX and RX pins. When the TX or RX pin function is disabled by clearing the UARTEN, TXEN or RXEN bit, the TX or RX pin will be set to a floating state. At this time whether the TX or RX pin is connected to an internal pull-high resistor or not is determined by the corresponding I/O pull-high function control bit. UART Data Transfer Scheme The above diagram shows the overall data transfer structure arrangement for the UART interface. The actual data to be transmitted from the MCU is first transferred to the TXR register by the application program. The data will then be transferred to the Transmit Shift Register from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only the TXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped and is therefore inaccessible to the application program. Data to be received by the UART is accepted on the external RX pin, from where it is shifted in, LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the shift register is full, the data will then be transferred from the shift register to the internal RXR register, where it is buffered and can be manipulated by the application program. Only the TXR register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is therefore inaccessible to the application program. It should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate TXR and RXR registers, only exists as a single shared register in the Data Memory. This shared register known as the TXR_RXR register is used for both data transmission and data reception. UART Status and Control Registers There are five control registers associated with the UART function. The USR, UCR1 and UCR2 registers control the overall function of the UART, while the BRG register controls the Baud rate. The actual data to be transmitted and received on the serial interface is managed through the TXR_ RXR data registers. TXR_RXR Register The TXR_RXR register is the data register which is used to store the data to be transmitted on the TX pin or being received from the RX pin. Bit 7 6 5 4 3 2 1 0 Name TXRX7 TXRX6 TXRX5 TXRX4 TXRX3 TXRX2 TXRX1 TXRX0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown Bit 7~0TXRX7~TXRX0: UART Transmit/Receive Data bits Rev. 1.20 215 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU USR Register The USR register is the status register for the UART, which can be read by the program to determine the present status of the UART. All flags within the USR register are read only and further explanations are given below. Bit 7 6 5 4 3 2 1 0 Name PERR NF FERR OERR RIDLE RXIF TIDLE TXIF R/W R R R R R R R R POR 0 0 0 0 1 0 1 1 Bit 7 PERR: Parity error flag 0: No parity error is detected 1: Parity error is detected The PERR flag is the parity error flag. When this read only flag is "0", it indicates a parity error has not been detected. When the flag is "1", it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can also be cleared by a software sequence which involves a read to the status register USR followed by an access to the RXR data register. Bit 6 NF: Noise flag 0: No noise is detected 1: Noise is detected The NF flag is the noise flag. When this read only flag is "0", it indicates no noise condition. When the flag is "1", it indicates that the UART has detected noise on the receiver input. The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of as overrun. The NF flag can be cleared by a software sequence which will involve a read to the status register USR followed by an access to the RXR data register. Bit 5 FERR: Framing error flag 0: No framing error is detected 1: Framing error is detected The FERR flag is the framing error flag. When this read only flag is "0", it indicates that there is no framing error. When the flag is "1", it indicates that a framing error has been detected for the current character. The flag can also be cleared by a software sequence which will involve a read to the status register USR followed by an access to the RXR data register. Bit 4OERR: Overrun error flag 0: No overrun error is detected 1: Overrun error is detected The OERR flag is the overrun error flag which indicates when the receiver buffer has overflowed. When this read only flag is "0", it indicates that there is no overrun error. When the flag is "1", it indicates that an overrun error occurs which will inhibit further transfers to the RXR receive data register. The flag is cleared by a software sequence, which is a read to the status register USR followed by an access to the RXR data register. Bit 3RIDLE: Receiver status 0: data reception is in progress (data being received) 1: no data reception is in progress (receiver is idle) The RIDLE flag is the receiver status flag. When this read only flag is "0", it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. When the flag is "1", it indicates that the receiver is idle. Between the completion of the stop bit and the detection of the next start bit, the RIDLE bit is "1" indicating that the UART receiver is idle and the RX pin stays in logic high condition. Rev. 1.20 216 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Bit 2RXIF: Receive RXR data register status 0: RXR data register is empty 1: RXR data register has available data The RXIF flag is the receive data register status flag. When this read only flag is "0", it indicates that the RXR read data register is empty. When the flag is "1", it indicates that the RXR read data register contains new data. When the contents of the shift register are transferred to the RXR register, an interrupt is generated if RIE=1 in the UCR2 register. If one or more errors are detected in the received word, the appropriate receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the RXR register, and if the RXR register has no data available. Bit 1TIDLE: Transmission status 0: Data transmission is in progress (data being transmitted) 1: No data transmission is in progress (transmitter is idle) The TIDLE flag is known as the transmission complete flag. When this read only flag is "0", it indicates that a transmission is in progress. This flag will be set to "1" when the TXIF flag is "1" and when there is no transmit data or break character being transmitted. When TIDLE is equal to 1, the TX pin becomes idle with the pin state in logic high condition. The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR register. The flag is not generated when a data character or a break is queued and ready to be sent. Bit 0TXIF: Transmit TXR data register status 0: Character is not transferred to the transmit shift register 1: Character has transferred to the transmit shift register (TXR data register is empty) The TXIF flag is the transmit data register empty flag. When this read only flag is "0", it indicates that the character is not transferred to the transmitter shift register. When the flag is "1", it indicates that the transmitter shift register has received a character from the TXR data register. The TXIF flag is cleared by reading the UART status register (USR) with TXIF set and then writing to the TXR data register. Note that when the TXEN bit is set, the TXIF flag bit will also be set since the transmit data register is not yet full. UCR1 Register The UCR1 register together with the UCR2 register are the UART control registers that are used to set the various options for the UART function such as overall on/off control, parity control, data transfer bit length, etc. Further explanation on each of the bits is given below. Bit 7 6 5 4 3 2 1 0 Name UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8 R/W R/W R/W R/W R/W R/W R/W R W POR 0 0 0 0 0 0 x 0 "x": unknown Bit 7 Rev. 1.20 UARTEN: UART function enable control 0: Disable UART; TX and RX pins are in a floating state. 1: Enable UART; TX and RX pins function as UART pins The UARTEN bit is the UART enable bit. When this bit is equal to "0", the UART will be disabled and the RX pin as well as the TX pin will be set in a floating state. When the bit is equal to "1", the UART will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN enable control bits. When the UART is disabled, it will empty the buffer so any character remaining in the buffer will be discarded. In addition, the value of the baud rate counter will be reset. If the UART is disabled, all error and status flags will be reset. Also the TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2 and BRG registers will remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending 217 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU transmissions and receptions will be terminated and the module will be reset as defined above. When the UART is re-enabled, it will restart in the same configuration. Rev. 1.20 Bit 6 BNO: Number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer This bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. When this bit is equal to "1", a 9-bit data length format will be selected. If the bit is equal to "0", then an 8-bit data length format will be selected. If 9-bit data length format is selected, then bits RX8 and TX8 will be used to store the 9th bit of the received and transmitted data respectively. Bit 5 PREN: Parity function enable control 0: Parity function is disabled 1: Parity function is enabled This bit is the parity function enable bit. When this bit is equal to 1, the parity function will be enabled. If the bit is equal to 0, then the parity function will be disabled. Bit 4 PRT: Parity type selection bit 0: Even parity for parity generator 1: Odd parity for parity generator This bit is the parity type selection bit. When this bit is equal to 1, odd parity type will be selected. If the bit is equal to 0, then even parity type will be selected. Bit 3 STOPS: Number of stop bits selection 0: One stop bit format is used 1: Two stop bits format is used This bit determines if one or two stop bits are to be used. When this bit is equal to "1", two stop bits format are used. If the bit is equal to "0", then only one stop bit format is used. Bit 2 TXBRK: Transmit break character 0: No break character is transmitted 1: Break characters transmit The TXBRK bit is the Transmit Break Character bit. When this bit is equal to "0", there are no break characters and the TX pin operats normally. When the bit is equal to "1", there are transmit break characters and the transmitter will send logic zeros. When this bit is equal to "1", after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset. Bit 1 RX8: Receive data bit 8 for 9-bit data transfer format (read only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as RX8. The BNO bit is used to determine whether data transfes are in 8-bit or 9-bit format. Bit 0 TX8: Transmit data bit 8 for 9-bit data transfer format (write only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data known as TX8. The BNO bit is used to determine whether data transfes are in 8-bit or 9-bit format. 218 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU UCR2 Register The UCR2 register is the second of the UART control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation if the UART Transmitter and Receiver as well as enabling the various UART interrupt sources. The register also serves to control the baud rate speed, receiver wake-up function enable and the address detect function enable. Further explanation on each of the bits is given below. Bit 7 6 5 4 3 2 1 0 Name TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 TXEN: UART Transmitter enable control 0: UART Transmitter is disabled 1: UART Transmitter is enabled The TXEN bit is the Transmitter Enable Bit. When this bit is equal to "0", the transmitter will be disabled with any pending data transmissions being aborted. In addition the buffers will be reset. In this situation the TX pin will be set in a floating state. If the TXEN bit is equal to "1" and the UARTEN bit is also equal to 1, the transmitter will be enabled and the TX pin will be controlled by the UART. Clearing the TXEN bit during a transmission will cause the data transmission to be aborted and will reset the transmitter. If this situation occurs, the TX pin will be set in a floating state. Bit 6RXEN: UART Receiver enable control 0: UART Receiver is disabled 1: UART Receiver is enabled The RXEN bit is the Receiver Enable Bit. When this bit is equal to "0", the receiver will be disabled with any pending data receptions being aborted. In addition the receiver buffers will be reset. In this situation the RX pin will be set in a floating state. If the RXEN bit is equal to "1" and the UARTEN bit is also equal to 1, the receiver will be enabled and the RX pin will be controlled by the UART. Clearing the RXEN bit during a reception will cause the data reception to be aborted and will reset the receiver. If this situation occurs, the RX pin will be set in a floating state. Bit 5BRGH: Baud Rate speed selection 0: Low speed baud rate 1: High speed baud rate The bit named BRGH selects the high or low speed mode of the Baud Rate Generator. This bit, together with the value placed in the baud rate register, BRG, controls the baud rate of the UART. If the bit is equal to 0, the low speed mode is selected. Bit 4ADDEN: Address detect function enable control 0: Address detection function is disabled 1: Address detection function is enabled The bit named ADDEN is the address detection function enable control bit. When this bit is equal to 1, the address detection function is enabled. When it occurs, if the 8th bit, which corresponds to RX7 if BNO=0, or the 9th bit, which corresponds to RX8 if BNO=1, has a value of "1", then the received word will be identified as an address, rather than data. If the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit depending on the value of the BNO bit. If the address bit known as the 8th or 9th bit of the received word is "0" with the address detection function being enabled, an interrupt will not be generated and the received data will be discarded. Rev. 1.20 219 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Bit 3WAKE: RX pin falling edge wake-up function enable control 0: RX pin wake-up function is disabled 1: RX pin wake-up function is enabled The bit enables or disables the receiver wake-up function. If this bit is equal to 1 and the device is in IDLE0 or SLEEP mode, a falling edge on the RX pin will wake up the device. If this bit is equal to 0 and the device is in IDLE or SLEEP mode, any edge transitions on the RX pin will not wake up the device. Bit 2RIE: Receiver interrupt enable control 0: Receiver related interrupt is disabled 1: Receiver related interrupt is enabled The bit enables or disables the receiver interrupt. If this bit is equal to 1 and when the receiver overrun flag OERR or received data available flag RXIF is set, the UART interrupt request flag will be set. If this bit is equal to 0, the UART interrupt request flag will not be influenced by the condition of the OERR or RXIF flags. Bit 1TIIE: Transmitter Idle interrupt enable control 0: Transmitter idle interrupt is disabled 1: Transmitter idle interrupt is enabled The bit enables or disables the transmitter idle interrupt. If this bit is equal to 1 and when the transmitter idle flag TIDLE is set, due to a transmitter idle condition, the UART interrupt request flag will be set. If this bit is equal to 0, the UART interrupt request flag will not be influenced by the condition of the TIDLE flag. Bit 0TEIE: Transmitter Empty interrupt enable control 0: Transmitter empty interrupt is disabled 1: Transmitter empty interrupt is enabled The bit enables or disables the transmitter empty interrupt. If this bit is equal to 1 and when the transmitter empty flag TXIF is set, due to a transmitter empty condition, the UART interrupt request flag will be set. If this bit is equal to 0, the UART interrupt request flag will not be influenced by the condition of the TXIF flag. Baud Rate Generator To setup the speed of the serial data communication, the UART function contains its own dedicated baud rate generator. The baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. The first of these is the value placed in the BRG register and the second is the value of the BRGH bit within the UCR2 control register. The BRGH bit decides, if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. The value in the BRG register, N, which is used in the following baud rate calculation formula determines the division factor. Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. UCR2 BRGH Bit 0 1 Baud Rate (BR) f SYS [64( N + 1)] fSYS [16( N + 1)] By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register, the required baud rate can be setup. Note that because the actual baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error associated between the actual and requested value. The following example shows how the BRG register value N and the error value can be calculated. Rev. 1.20 220 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU BRG Register Bit 7 6 5 4 3 2 1 0 Name BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown Bit 7~0 BRG7~BRG0: Baud Rate values By programming the BRGH bit in the UCR2 register which allows selection of the related formula described above and programming the required value in the BRG register, the required baud rate can be setup. Calculating the Baud Rate and Error Values For a clock frequency of 4MHz, and with BRGH set to 0 determine the BRG register value N, the actual baud rate and the error value for a desired baud rate of 4800. From the above table the desired baud rate BR = Re-arranging this equation gives N = Giving a value for N = f SYS [64( N + 1)] fSYS −1 (BR × 64) 4000000 − 1 = 12.0208 (4800 × 64) To obtain the closest value, a decimal value of 12 should be placed into the BRG register. This gives an actual or calculated baud rate value of BR= Therefore the error is equal to 4000000 = 4808 [64(12 + 1)] 4808 − 4800 = 0.16% 4800 UART Setup and Control For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ, format. This is composed of one start bit, eight or nine data bits and one or two stop bits. Parity is supported by the UART hardware and can be setup to be even, odd or no parity. For the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as the default setting, which is the setting at power-on. The number of data bits and stop bits, along with the parity, are setup by programming the corresponding BNO, PRT, PREN and STOPS bits in the UCR1 register. The baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received LSB first. Although the transmitter and receiver of the UART are functionally independent, they both use the same data format and baud rate. In all cases stop bits will be used for data transmission. Rev. 1.20 221 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Enabling/Disabling the UART Interface The basic on/off function of the internal UART function is controlled using the UARTEN bit in the UCR1 register. If the UARTEN, TXEN and RXEN bits are set, then these two UART pins will act as normal TX output pin and RX input pin respectively. If no data is being transmitted on the TX pin, then it will default to a logic high value. Clearing the UARTEN bit will disable the TX and RX pins and these two pins will be used as an I/O or other pin-shared functional pin. When the UART function is disabled, the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. Disabling the UART will also reset the enable control, the error and status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF being cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaffected. If the UARTEN bit in the UCR1 register is cleared while the UART is active, then all pending transmissions and receptions will be immediately suspended and the UART will be reset to a condition as defined above. If the UART is then subsequently re-enabled, it will restart again in the same configuration. Data, Parity and Stop Bit Selection The format of the data to be transferred is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. These factors are determined by the setup of various bits within the UCR1 register. The BNO bit controls the number of data bits which can be set to either 8 or 9. The PRT bit controls the choice if odd or even parity. The PREN bit controls the parity on/off function. The STOPS bit decides whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address detect mode control bit identifies the frame as an address character. The number of stop bits, which can be either one or two, is independent of the data length. Start Bit Data Bits Address Bits Parity Bit Stop Bit Example of 8-bit Data Formats 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 Example of 9-bit Data Formats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 Transmitter Receiver Data Format The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. 8-Bit Data Format 9-Bit Data Format Rev. 1.20 222 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU UART Transmitter Data word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, needs to be stored in the TX8 bit in the UCR1 register. At the transmitter core lies the Transmitter Shift Register, more commonly known as the TSR, whose data is obtained from the transmit data register, which is known as the TXR register. The data to be transmitted is loaded into this TXR register by the application program. The TSR register is not written to with new data until the stop bit from the previous transmission has been sent out. As soon as this stop bit has been transmitted, the TSR can then be loaded with new data from the TXR register, if it is available. It should be noted that the TSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. An actual transmission of data will normally be enabled when the TXEN bit is set, but the data will not be transmitted until the TXR register has been loaded with data and the baud rate generator has defined a shift clock source. However, the transmission can also be initiated by first loading data into the TXR register, after which the TXEN bit can be set. When a transmission of data begins, the TSR is normally empty, in which case a transfer to the TXR register will result in an immediate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission will immediately cease and the transmitter will be reset. The TX output pin will then return to the I/O or other pin-shared function. Transmitting Data When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with the least significant bit LSB first. In the transmit mode, the TXR register forms a buffer between the internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a data transfer can be summarized as follows: • Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. • Setup the BRG register to select the desired baud rate. • Set the TXEN bit to ensure that the UART transmitter is enabled and the TX pin is used as a UART transmitter pin. • Access the USR register and write the data that is to be transmitted into the TXR register. Note that this step will clear the TXIF bit. This sequence of events can now be repeated to send additional data. It should be noted that when TXIF=0, data will be inhibited from being written to the TXR register. Clearing the TXIF flag is always achieved using the following software sequence: 1. A USR register access 2. A TXR register write execution The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is empty and that other data can now be written into the TXR register without overwriting the previous data. If the TEIE bit is set, then the TXIF flag will generate an interrupt. During a data transmission, a write instruction to the TXR register will place the data into the TXR register, which will be copied to the shift register at the end of the present transmission. When there is no data transmission in progress, a write instruction to the TXR register will place the data directly into the shift register, resulting in the commencement of data transmission, and the TXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the TIDLE bit will be set. To clear the TIDLE bit the following software sequence is used: 1. A USR register access 2. A TXR register write execution Note that both the TXIF and TIDLE bits are cleared by the same software sequence. Rev. 1.20 223 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Transmitting Break If the TXBRK bit is set, then the break characters will be sent on the next transmission. Break character transmission consists of a start bit, followed by 13xN "0" bits, where N=1, 2, etc. If a break character is to be transmitted, then the TXBRK bit must be first set by the application program and then cleared to generate the stop bits. Transmitting a break character will not generate a transmit interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually kept at a logic high level, then the transmitter circuitry will transmit continuous break characters. After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. The automatic logic high at the end of the last break character will ensure that the start bit of the next frame is recognized. UART Receiver The UART is capable of receiving word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, will be stored in the RX8 bit in the UCR1 register. At the receiver core lies the Receiver Shift Register more commonly known as the RSR. The data which is received on the RX external input pin is sent to the data recovery block. The data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the receive data register, if the register is empty. The data which is received on the external RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted that the RSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. Receiving Data When the UART receiver is receiving data, the data is serially shifted in on the external RX input pin to the shift register, with the least significant bit LSB first. The RXR register is a two byte deep FIFO data buffer, where two bytes can be held in the FIFO while the 3rd byte can continue to be received. Note that the application program must ensure that the data is read from RXR before the 3rd byte has been completely shifted in, otherwise the 3rd byte will be discarded and an overrun error OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows: • Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. • Setup the BRG register to select the desired baud rate. • Set the RXEN bit to ensure that the UART receiver is enabled and the RX pin is used as a UART receiver pin. At this point the receiver will be enabled which will begin to look for a start bit. When a character is received, the following sequence of events will occur: • The RXIF bit in the USR register will be set then RXR register has data available, at least one more character can be read. • When the contents of the shift register have been transferred to the RXR register and if the RIE bit is set, then an interrupt will be generated. • If during reception, a frame error, noise error, parity error or an overrun error has been detected, then the error flags can be set. The RXIF bit can be cleared using the following software sequence: 1. A USR register access 2. A RXR register read execution Rev. 1.20 224 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Receiving Break Any break character received by the UART will be managed as a framing error. The receiver will count and expect a certain number of bit times as specified by the values programmed into the BNO and STOPS bits. If the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by BNO and STOPS. The RXIF bit is set, FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the RIDLE bit is set. If a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not make the assumption that the break condition on the line is the next start bit. A break is regarded as a character that contains only zeros with the FERR flag set. The break character will be loaded into the buffer and no further data will be received until stop bits are received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received. The reception of a break character on the UART registers will result in the following: • The framing error flag, FERR, will be set. • The receive data register, RXR, will be cleared. • The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set. Idle Status When the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition. Receiver Interrupt The read only receive interrupt flag, RXIF, in the USR register is set by an edge generated by the receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift Register, RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if RIE=1. Managing Receiver Errors Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART. Overrun Error – OERR The RXR register is composed of a two byte deep FIFO data buffer, where two bytes can be held in the FIFO register, while a 3th byte can continue to be received. Before the 3th byte has been entirely shifted in, the data should be read from the RXR register. If this is not done, the overrun error flag OERR will be consequently indicated. In the event of an overrun error occurring, the following will happen: • The OERR flag in the USR register will be set. • The RXR contents will not be lost. • The shift register will be overwritten. • An interrupt will be generated if the RIE bit is set. The OERR flag can be cleared by an access to the USR register followed by a read to the RXR register. Rev. 1.20 225 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Noise Error – NF Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is detected within a frame, the following will occur: • The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit. • Data will be transferred from the shift register to the RXR register. • No interrupt will be generated. However this bit rises at the same time as the RXIF bit which itself generates an interrupt. Note that the NF flag is reset by a USR register read operation followed by an RXR register read operation. Framing Error – FERR The read only framing error flag, FERR, in the USR register, is set if a zero is detected instead of stop bits. If two stop bits are selected, both stop bits must be high. Otherwise the FERR flag will be set. The FERR flag is buffered along with the received data and is cleared in any reset. Parity Error – PERR The read only parity error flag, PERR, in the USR register, is set if the parity of the received word is incorrect. This error flag is only applicable if the parity function is enabled, PREN=1, and if the parity type, odd or even, is selected. The read only PERR flag is buffered along with the received data bytes. It is cleared on any reset, it should be noted that the FERR and PERR flags are buffered along with the corresponding word and should be read before reading the data word. UART Interrupt Structure Several individual UART conditions can generate a UART interrupt. When these conditions exist, a low pulse will be generated to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. When any of these conditions are created, if its corresponding interrupt control is enabled and the stack is not full, the program will jump to its corresponding interrupt vector where it can be serviced before returning to the main program. Four of these conditions have the corresponding USR register flags which will generate a UART interrupt if its associated interrupt enable control bit in the UCR2 register is set. The two transmitter interrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. These enable bits can be used to mask out individual UART interrupt sources. The address detect condition, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt when an address detect condition occurs if its function is enabled by setting the ADDEN bit in the UCR2 register. An RX pin wake-up, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt if the microcontroller is woken up from IDLE0 or SLEEP mode by a falling edge on the RX pin, if the WAKE and RIE bits in the UCR2 register are set. Note that in the event of an RX wake-up interrupt occurring, there will be a certain period of delay, commonly known as the System Start-up Time, for the oscillator to restart and stabilize before the system resumes normal operation. Note that the USR register flags are read only and cannot be cleared or set by the application program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the case for some of the other interrupts. The flags will be cleared automatically when certain actions are taken by the UART, the details of which are given in the UART register section. The overall UART interrupt can be disabled or enabled by the related interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the UART module is masked out or allowed. Rev. 1.20 226 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU USR Register UCR2 Register Transmitter Empt� F�ag TXIF TEIE Transmitter Id�e F�ag TIDLE TIIE 0 1 0 1 Receiver Overr�n F�ag OERR RIE OR 0 UART Interr�pt Req�est F�ag URF URE 0 1 EMI 0 Interr�pt signa� to MCU 1 1 0 Receiver Data Avai�ab�e RXIF ADDEN 1 0 1 RX7 if BNO=0 RX8 if BNO=1 RX Pin Wake-�p WAKE 0 1 UCR2 Register UART Interrupt Structure Address Detect Mode Setting the Address Detect function enable control bit, ADDEN, in the UCR2 register, enables this special function. If this bit is set to 1, then an additional qualifier will be placed on the generation of a Receiver Data Available interrupt, which is requested by the RXIF flag. If the ADDEN bit is equal to 1, then when the data is available, an interrupt will only be generated, if the highest received bit has a high value. Note that the related interrupt enable control bit and the EMI bit of the microcontroller must also be enabled for correct interrupt generation. The highest address bit is the 9th bit if the bit BNO=1 or the 8th bit if the bit BNO=0. If the highest bit is high, then the received word will be defined as an address rather than data. A Data Available interrupt will be generated every time the last bit of the received word is set. If the ADDEN bit is equal to 0, then a Receive Data Available interrupt will be generated each time the RXIF flag is set, irrespective of the data last but status. The address detection and parity functions are mutually exclusive functions. Therefore, if the address detect function is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity function enable bit PREN to zero. ADDEN Bit 9 if BNO=1 Bit 8 if BNO=0 UART Interrupt Generated 0 √ 1 √ 0 X 1 √ 0 1 ADDEN Bit Function Rev. 1.20 227 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU UART Power Down and Wake-up When the MCU system clock is switched off, the UART will cease to function. If the MCU executes the "HALT" instruction and switches off the system clock while a transmission is still in progress, then the transmission will be paused until the UART clock source derived from the microcontroller is activated. In a similar way, if the MCU executes the "HALT" instruction and switches off the system clock while receiving data, then the reception of data will likewise be paused. When the MCU enters the IDLE or SLEEP Mode, note that the USR, UCR1, UCR2, transmit and receive registers, as well as the BRG register will not be affected. It is recommended to make sure first that the UART data transmission or reception has been finished before the microcontroller enters the IDLE or SLEEP mode. The UART function contains a receiver RX pin wake-up function, which is enabled or disabled by the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit, UARTEN, the receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set before the MCU enters the IDLE0 or SLEEP Mode, then a falling edge on the RX pin will wake up the MCU from the IDLE0 or SLEEP Mode. Note that as it takes certain system clock cycles after a wake-up, before normal microcontroller operation resumes, any data received during this time on the RX pin will be ignored. For a UART wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global interrupt enable bit, EMI, and the UART interrupt enable bit, URE, must be set. If the EMI and URE bits are not set then only a wake up event will occur and no interrupt will be generated. Note also that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes, the UART interrupt will not be generated until after this time has elapsed. Rev. 1.20 228 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Application Circuits Digital Volume Control Application Circuit (5V) VCC(�V) Optiona� for digita� power stabi�it� req�irement d�ring voice p�a� 10 22µF 10µF 0.1µF AVDD_PA VDD BIAS ANx 10µF I/O Note: Digita� Vo��me Contro� Witho�t VR PB1/OSC1 AUD S�stem Cr�sta� 1µF PB2/OSC2 2.7k AUD_IN F/W enab�e VDDIO f�nction b� PBS0 register HT7133-1 1nF HT66FV1x0 V33 VCC(�V) PB0/VDDIO LDO SP＋ SP– PA7/AN7/XT1 4 SPI FLASH ROM PC4/SDA PC�/SCKA PC6/SDIA PC7/SCSA PA6/AN6//XT2 VSS Speaker 8 LXT 32768Hz HT66FV140/1�0/160 AVSS_PA SPI F�ash ROM maxim�m operating vo�tage is 3.6V VSS: Digita� Gro�nd AVSS_PA: Power Amp�ifier Gro�nd For Sing�e Point Gro�nding Rev. 1.20 229 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Digital Volume Control Application Circuit (3V) VDD VCC(3V) Optiona� for digita� power stabi�it� req�irement d�ring voice p�a� 10 22µF 10µF 0.1µF AVDD_PA VDD BIAS ANx 10µF I/O AUD 1µF 2.7k AUD_IN Note: Digita� Vo��me Contro� Witho�t VR PB1/OSC1 1nF S�stem Cr�sta� HT66FV1x0 PB2/OSC2 F/W disab�e VDDIO f�nction b� PBS0 register SP＋ PB0/VDDIO SP– PA7/AN7/XT1 4 VDD SPI FLASH ROM PC4/SDA PC�/SCKA PC6/SDIA PC7/SCSA PA6/AN6//XT2 VSS Speaker 8 LXT 32768Hz HT66FV140/1�0/160 AVSS_PA SPI F�ash ROM maxim�m operating vo�tage is 3.6V VSS: Digita� Gro�nd AVSS_PA: Power Amp�ifier Gro�nd For Sing�e Point Gro�nding Rev. 1.20 230 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Variable Resistor (VR) Volume Control Application Circuit (5V) VCC(�V) 10 Optiona� for digita� power stabi�it� req�irement d�ring voice p�a� 22µF 10µF 0.1µF AVDD_PA VDD ANx BIAS 10µF Note: VR(Variab�e Resistor) For Vo��me Contro� I/O PB1/OSC1 AUD S�stem Cr�sta� 1µF PB2/OSC2 10k AUD_IN F/W enab�e VDDIO f�nction b� PBS0 register 1nF HT66FV1x0 HT7133-1 VR(Variab�e Resistor) 1k V33 VCC(�V) PB0/VDDIO LDO SP＋ SP– PA7/AN7/XT1 4 SPI FLASH ROM PC4/SDA PC�/SCKA PC6/SDIA PC7/SCSA PA6/AN6//XT2 VSS Speaker 8 LXT 32768Hz HT66FV140/1�0/160 AVSS_PA SPI F�ash ROM maxim�m operating vo�tage is 3.6V VSS: Digita� Gro�nd AVSS_PA: Power Amp�ifier Gro�nd For Sing�e Point Gro�nding Rev. 1.20 231 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Variable Resistor (VR) Volume Control Application Circuit (3V) VCC(3V) VDD Optiona� for digita� power stabi�it� req�irement d�ring voice p�a� 10 22µF 10µF 0.1µF VDD AVDD_PA BIAS ANx 10µF Note: VR(Variab�e Resistor) For Vo��me Contro� I/O AUD 1µF VR(Variab�e Resistor) 1k AUD_IN PB1/OSC1 S�stem Cr�sta� 10k 1nF HT66FV1x0 PB2/OSC2 F/W disab�e VDDIO f�nction b� PBS0 register SP＋ PB0/VDDIO 4 VDD SPI FLASH ROM SP– PA7/AN7/XT1 PC4/SDA PC�/SCKA PC6/SDIA PC7/SCSA PA6/AN6//XT2 VSS Speaker 8 LXT 32768Hz HT66FV140/1�0/160 AVSS_PA SPI F�ash ROM maxim�m operating vo�tage is 3.6V VSS: Digita� Gro�nd AVSS_PA: Power Amp�ifier Gro�nd For Sing�e Point Gro�nding Rev. 1.20 232 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.20 233 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction "RET" in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m]. i" instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be set as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the "HALT" instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.20 234 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Instruction Set Summary The instructions related to the data memory access in the following table can be used when the desired data memory is located in Data Memory sector 0. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected 1 1Note 1 1 1Note 1 1 1Note 1 1 1Note 1Note Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic Add Data Memory to ACC ADD A,[m] ADDM A,[m] Add ACC to Data Memory ADD A,x Add immediate data to ACC ADC A,[m] Add Data Memory to ACC with Carry ADCM A,[m] Add ACC to Data memory with Carry SUB A,x Subtract immediate data from the ACC SUB A,[m] Subtract Data Memory from ACC SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory SBC A,x Subtract immediate data from ACC with Carry SBC A,[m] Subtract Data Memory from ACC with Carry SBCM A,[m] Subtract Data Memory from ACC with Carry, result in Data Memory DAA [m] Decimal adjust ACC for Addition with result in Data Memory Logic Operation AND A,[m] Logical AND Data Memory to ACC OR A,[m] Logical OR Data Memory to ACC XOR A,[m] Logical XOR Data Memory to ACC ANDM A,[m] Logical AND ACC to Data Memory ORM A,[m] Logical OR ACC to Data Memory XORM A,[m] Logical XOR ACC to Data Memory AND A,x Logical AND immediate Data to ACC OR A,x Logical OR immediate Data to ACC XOR A,x Logical XOR immediate Data to ACC CPL [m] Complement Data Memory CPLA [m] Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 1.20 235 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Mnemonic Description Cycles Flag Affected Data Move MOV A,[m] MOV [m],A MOV A,x Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None None 2Note 2Note 2Note None None None 2Note None 1 1Note 1Note 1 1Note 1 1 None None None TO, PDF None None TO, PDF Bit Operation CLR [m].i SET [m].i Branch Operation JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m] SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if Data Memory is not zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt Table Read Operation TABRD [m] Read table (specific page) to TBLH and Data Memory TABRDL [m] Read table (last page) to TBLH and Data Memory ITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory Increment table pointer TBLP first and Read table (last page) to TBLH and ITABRDL [m] Data Memory Miscellaneous NOP CLR [m] SET [m] CLR WDT SWAP [m] SWAPA [m] HALT No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode Note: 1. For skip instructions, if the result of the comparison involves a skip then up to three cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the "CLR WDT" instruction the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after the "CLR WDT" instructions is executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.20 236 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Extended Instruction Set The extended instructions are used to support the full range address access for the data memory. When the accessed data memory is located in any data memory sections except sector 0, the extended instruction can be used to access the data memory instead of using the indirect addressing access to improve the CPU firmware performance. Mnemonic Description Cycles Flag Affected 2 2Note 2 2Note 2 2Note 2 2Note 2Note Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ C 2 2 2 2Note 2Note 2Note 2Note 2 Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 2 2Note 2 2Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 2 2Note 2 2Note 2 2Note 2 2Note None None C C None None C C Move Data Memory to ACC Move ACC to Data Memory 2 2Note None None Clear bit of Data Memory Set bit of Data Memory 2Note 2Note None None Arithmetic Add Data Memory to ACC LADD A,[m] LADDM A,[m] Add ACC to Data Memory LADC A,[m] Add Data Memory to ACC with Carry LADCM A,[m] Add ACC to Data memory with Carry LSUB A,[m] Subtract Data Memory from ACC LSUBM A,[m] Subtract Data Memory from ACC with result in Data Memory LSBC A,[m] Subtract Data Memory from ACC with Carry LSBCM A,[m] Subtract Data Memory from ACC with Carry, result in Data Memory LDAA [m] Decimal adjust ACC for Addition with result in Data Memory Logic Operation LAND A,[m] Logical AND Data Memory to ACC LOR A,[m] Logical OR Data Memory to ACC LXOR A,[m] Logical XOR Data Memory to ACC LANDM A,[m] Logical AND ACC to Data Memory LORM A,[m] Logical OR ACC to Data Memory LXORM A,[m] Logical XOR ACC to Data Memory LCPL [m] Complement Data Memory LCPLA [m] Complement Data Memory with result in ACC Increment & Decrement LINCA [m] LINC [m] LDECA [m] LDEC [m] Rotate LRRA [m] LRR [m] LRRCA [m] LRRC [m] LRLA [m] LRL [m] LRLCA [m] LRLC [m] Data Move LMOV A,[m] LMOV [m],A Bit Operation LCLR [m].i LSET [m].i Rev. 1.20 237 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Mnemonic Description Cycles Flag Affected Branch LSZ [m] LSZA [m] LSNZ [m] LSZ [m].i LSNZ [m].i LSIZ [m] LSDZ [m] LSIZA [m] LSDZA [m] Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if Data Memory is not zero Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC 2Note 2Note 2Note 2Note 2Note 2Note 2Note 2Note 2Note None None None None None None None None None 3Note 3Note 3Note None None None 3Note None 2Note 2Note 2Note 2 None None None None Table Read LTABRD [m] Read table to TBLH and Data Memory LTABRDL [m] Read table (last page) to TBLH and Data Memory LITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory Increment table pointer TBLP first and Read table (last page) to TBLH and LITABRDL [m] Data Memory Miscellaneous LCLR [m] LSET [m] LSWAP [m] LSWAPA [m] Clear Data Memory Set Data Memory Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Note: 1. For these extended skip instructions, if the result of the comparison involves a skip then up to four cycles are required, if no skip takes place two cycles is required. 2. Any extended instruction which changes the contents of the PCL register will also require three cycles for execution. Rev. 1.20 238 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Instruction Definition ADC A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C, SC ADCM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C, SC Add Data Memory to ACC ADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C, SC ADD A,x Description Operation Affected flag(s) Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C, SC ADDM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C, SC AND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z AND A,x Description Operation Affected flag(s) Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z ANDM A,[m] Description Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z Rev. 1.20 239 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU CALL addr Description Operation Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Affected flag(s) Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CPL [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z CPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z DAA [m] Description Operation Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C Rev. 1.20 240 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z HALT Description Operation Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Operation Affected flag(s) Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z JMP addr Description Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None Rev. 1.20 241 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Operation Affected flag(s) Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z OR A,x Description Operation Affected flag(s) Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z ORM A,[m] Description Operation Affected flag(s) Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z RET Description Operation Affected flag(s) Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None RET A,x Description Operation Affected flag(s) Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None RETI Description Operation Affected flag(s) Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None RL [m] Description Operation Affected flag(s) Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None Rev. 1.20 242 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU RLA [m] Description Operation Affected flag(s) Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None RLC [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C RLCA [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C RR [m] Description Operation Affected flag(s) Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None RRA [m] Description Operation Affected flag(s) Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None RRC [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C Rev. 1.20 243 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU RRCA [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C SBC A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C, SC, CZ SBC A, x Description Operation Affected flag(s) Subtract immediate data from ACC with Carry The immediate data and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC - [m] - C OV, Z, AC, C, SC, CZ SBCM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C, SC, CZ SDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None SDZA [m] Description Operation Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None Rev. 1.20 244 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Operation Affected flag(s) Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None SIZA [m] Description Operation Affected flag(s) Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None SNZ [m].i Description Operation Affected flag(s) Skip if Data Memory is not 0 If the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None SNZ [m] Description Operation Affected flag(s) Skip if Data Memory is not 0 If the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m]≠ 0 None SUB A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C, SC, CZ Rev. 1.20 245 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C, SC, CZ SUB A,x Description Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C, SC, CZ SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Operation Affected flag(s) Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SZ [m] Description Operation Affected flag(s) Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None SZA [m] Description Operation Affected flag(s) Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None SZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None Rev. 1.20 246 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU TABRD [m] Description Operation Affected flag(s) Read table (specific page) to TBLH and Data Memory The low byte of the program code (specific page) addressed by the table pointer pair (TBLP and TBHP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDL [m] Description Operation Affected flag(s) Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None ITABRD [m] Description Operation Affected flag(s) Increment table pointer low byte first and read table to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None ITABRDL [m] Description Operation Affected flag(s) Increment table pointer low byte first and read table (last page) to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None XOR A,[m] Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z XORM A,[m] Description Operation Affected flag(s) Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z XOR A,x Description Operation Affected flag(s) Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z Rev. 1.20 247 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Extended Instruction Definition The extended instructions are used to directly access the data stored in any data memory sections. LADC A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C, SC LADCM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C, SC LADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C, SC LADDM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C, SC LAND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z LANDM A,[m] Description Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z LCLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None LCLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None Rev. 1.20 Add Data Memory to ACC 248 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU LCPL [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z LCPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z LDAA [m] Description Operation Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C LDEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z LDECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z LINC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z LINCA [m] Description Operation Affected flag(s) Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z Rev. 1.20 249 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU LMOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None LMOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None LOR A,[m] Description Operation Affected flag(s) Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z LORM A,[m] Description Operation Affected flag(s) Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z LRL [m] Description Operation Affected flag(s) Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None LRLA [m] Description Operation Affected flag(s) Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None LRLC [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C LRLCA [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C Rev. 1.20 250 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU LRR [m] Description Operation Affected flag(s) Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None LRRA [m] Description Operation Affected flag(s) Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None LRRC [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C LRRCA [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C LSBC A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C, SC, CZ LSBCM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C, SC, CZ Rev. 1.20 251 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU LSDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None LSDZA [m] Description Operation Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None LSET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None LSET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None LSIZ [m] Description Operation Affected flag(s) Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None LSIZA [m] Description Operation Affected flag(s) Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None LSNZ [m].i Description Operation Affected flag(s) Skip if Data Memory is not 0 If the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None Rev. 1.20 252 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU LSNZ [m] Description Operation Affected flag(s) Skip if Data Memory is not 0 If the content of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m] ≠ 0 None LSUB A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C, SC, CZ LSUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C, SC, CZ LSWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None LSWAPA [m] Description Operation Affected flag(s) Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None LSZ [m] Description Operation Affected flag(s) Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None LSZA [m] Description Operation Affected flag(s) Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None Rev. 1.20 253 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU LSZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None LTABRD [m] Description Operation Affected flag(s) Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None LTABRDL [m] Description Operation Affected flag(s) Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None LITABRD [m] Description Operation Increment table pointer low byte first and read table to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None LITABRDL [m] Description Operation Affected flag(s) Increment table pointer low byte first and read table (last page) to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None LXOR A,[m] Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z LXORM A,[m] Description Operation Affected flag(s) Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z Rev. 1.20 254 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.20 255 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU 20-pin SOP (300mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.406 BSC — B — 0.406 BSC — C 0.012 — 0.020 C’ — 0.504 BSC — D — — 0.104 E — 0.050 BSC — F 0.004 — 0.012 G 0.016 — 0.050 H 0.008 — 0.013 α 0° — 8° Symbol Rev. 1.20 Dimensions in mm Min. Nom. Max. A — 10.30 BSC — B — 7.5 BSC — C — 7.5 BSC — C’ — 12.8 BSC — D — 12.8 BSC — E — 1.27 BSC — F 0.10 — 0.30 G 0.40 — 1.27 H 0.40 — 1.27 α 0° — 8° 256 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU 24-pin SOP(300mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. A — 0.406 BSC — B — 0.295 BSC — Max. 0.020 C 0.012 — C’ — 0.606 BSC — D — — 0.104 E — 0.050 BSC — F 0.004 — 0.012 G 0.016 — 0.050 H 0.008 — 0.013 α 0° — 8° Symbol Rev. 1.20 Dimensions in mm Min. Nom. A — 10.30 BSC Max. — B — 7.5 BSC — 0.51 C 0.31 — C’ — 15.4 BSC — D — — 2.65 E — 1.27 BSC — F 0.10 — 0.30 G 0.40 — 1.27 H 0.20 — 0.33 α 0° — 8° 257 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU 28-pin SOP(300mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. A — 0.406 BSC — B — 0.295 BSC — Max. 0.020 C 0.012 — C’ — 0.705 BSC — D — — 0.104 E — 0.050 BSC — F 0.004 — 0.012 G 0.016 — 0.050 H 0.008 — 0.013 α 0° — 8° Symbol Rev. 1.20 Dimensions in mm Min. Nom. Max. A — 10.30 BSC — B — 7.5 BSC — 0.51 C 0.31 — C’ — 17.9 BSC — D — — 2.65 E — 1.27 BSC — F 0.10 — 0.30 G 0.40 — 1.27 H 0.20 — 0.33 α 0° — 8° 258 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU 44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.472 BSC — B — 0.394 BSC — C — 0.472 BSC — D — 0.394 BSC — E — 0.032 BSC — F 0.012 0.015 0.018 G 0.053 0.055 0.057 H — — 0.063 I 0.002 — 0.006 J 0.018 0.024 0.030 K 0.004 — 0.008 α 0° — 7° Symbol Rev. 1.20 Dimensions in mm Min. Nom. Max. A — 12.00 BSC — B — 10.00 BSC — C — 12.00 BSC — D — 10.00 BSC — E — 0.80 BSC — F 0.30 0.37 0.45 G 1.35 1.40 1.45 H — — 1.60 I 0.05 — 0.15 J 0.45 0.60 0.75 K 0.09 — 0.20 α 0° — 7° 259 July 21, 2015 HT66FV130/HT66FV140 HT66FV150/HT66FV160 Enhanced Voice 8-Bit Flash MCU Copyright© 2015 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.20 260 July 21, 2015