HT1380/HT1381 Serial Timekeeper Chip

HT1380/HT1381
Serial Timekeeper Chip
Features
· Operating voltage: 2.0V~5.5V
· Two data transmission modes: single-byte,
or burst mode
· Maximum input serial clock: 500kHz at VDD=2V,
· Serial I/O transmission
2MHz at VDD=5V
· All registers store BCD format
· Operating current: less than 1mA at 2V,
· HT1380: 8-pin DIP package
less than 1.2mA at 5V
· TTL compatible
- VIH: 2.0V~VDD+0.3V at VDD=5V
- VIL: -0.3V~+0.8V at VDD=5V
HT1381: 8-pin SOP package
Applications
· Microcomputer serial clock
· Clock and Calendar
General Description
The HT1380/HT1381 is a serial timekeeper IC which
provides seconds, minutes, hours, day, date, month and
year information. The number of days in each month
and leap years are automatically adjusted. The
HT1380/HT1381 is designed for low power consumption and can operate in two modes: one is the 12-hour
mode with an AM/PM indicator, the other is the 24-hour
mode.
The HT1380/HT1381 has several registers to store the
corresponding information with 8-bit data format. A
32768Hz crystal is required to provide the correct timing. In order to minimize the pin number, the
HT1380/HT1381 use a serial I/O transmission method
to interface with a microprocessor. Only three wires are
required: (1) REST, (2) SCLK and (3) I/O. Data can be
delivered 1 byte at a time or in a burst of up to 8 bytes.
Block Diagram
I/O
S C L K
D a ta S h ift
R e g is te r
R e a l T im e
C lo c k
R E S T
C o m m a n d
C o n tr o l L o g ic
O s c illa to r a n d
D iv id e r C ir c u it
X 1
X 2
Pin Assignment
N C
1
8
V D D
N C
1
8
V D D
X 1
2
7
X 1
2
7
X 2
3
6
S C L K
I/O
X 2
3
6
S C L K
I/O
V S S
4
5
R E S T
V S S
4
5
R E S T
H T 1 3 8 0
8 D IP -A
Rev. 1.30
H T 1 3 8 1
8 S O P -A
1
May 27, 2011
HT1380/HT1381
Pad Assignment
X 1
1
X 2
2
7
V D D
6
(0 ,0 )
S C L K
V S S
5
I/O
3
4
R E S T
Chip size: 2010 ´ 1920 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Pad Coordinates
Unit: mm
Pad No.
X
Y
1
-851.40
775.00
2
-851.40
494.60
3
-844.40
-203.90
4
845.90
-618.30
5
848.40
-4.30
6
845.90
332.60
7
844.40
572.60
Pad Description
Pad No.
Pad Name
I/O
Internal
Connection
1
X1
I
CMOS
32768Hz crystal input pad
2
X2
O
CMOS
Oscillator output pad
3
VSS
¾
CMOS
Negative power supply, ground
4
REST
I
CMOS
Reset pin with serial transmission
5
I/O
I/O
CMOS
Data input/output pin with serial transmission
6
SCLK
I
CMOS
Serial clock pulse pin with serial transmission
7
VDD
¾
CMOS
Positive power supply
Rev. 1.30
Description
2
May 27, 2011
HT1380/HT1381
Absolute Maximum Ratings
Supply Voltage .........................................-0.3V to 5.5V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...............................0°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Parameter
VDD
Operating Voltage
ISTB
Standby Current
IDD
Operating Current
IOH
Source Current
Ta=25°C
Test Conditions
VDD
¾
2V
5V
Conditions
¾
¾
2V
No load
5V
Min.
Typ.
Max.
Unit
2
¾
5.5
V
¾
¾
100
nA
¾
¾
100
nA
¾
0.7
1.0
mA
¾
0.7
1.2
mA
¾
mA
2V
VOH=1.8V
-0.2
-0.4
5V
VOH=4.5V
-0.5
-1.0
¾
mA
2V
VOL=0.2V
0.7
1.5
¾
mA
5V
VOL=0.5V
2.0
4.0
¾
mA
IOL
Sink Current
VIH
²H² Input Voltage
5V
¾
2
¾
¾
V
VIL
²L² Input Voltage
5V
¾
¾
¾
0.8
V
Note: * ISTB is specified with SCLK, I/O, REST open. The clock halt bit must be set to logic 1 (oscillator disabled).
A.C. Characteristics
Symbol
Parameter
tDC
Data to Clock Setup
tCDH
Clock to Data Hold
tCDD
Clock to Data Delay
tCL
Clock Low Time
tCH
Clock High Time
fSCLK
Clock Frequency
Rev. 1.30
Ta=25°C
Test Conditions
Min.
Typ.
Max.
¾
200
¾
¾
5V
¾
50
¾
¾
2V
¾
280
¾
¾
5V
¾
70
¾
¾
2V
¾
¾
¾
800
5V
¾
¾
¾
200
2V
¾
1000
¾
¾
5V
¾
250
¾
¾
2V
¾
1000
¾
¾
5V
¾
250
¾
¾
2V
¾
¾
¾
0.5
5V
¾
¾
¾
2.0
VDD
Conditions
2V
3
Unit
ns
ns
ns
ns
ns
MHz
May 27, 2011
HT1380/HT1381
Symbol
tr
Parameter
tf
Clock Rise and Fall
Time
tCC
Reset to Clock Setup
tCCH
Clock to Reset Hold
tCWH
Reset Inactive Time
tCDZ
Reset to I/O High Impedance
Test Conditions
Min.
Typ.
Max.
¾
¾
¾
2000
5V
¾
¾
¾
500
2V
¾
4
¾
¾
5V
¾
1
¾
¾
2V
¾
240
¾
¾
5V
¾
60
¾
¾
2V
¾
4
¾
¾
5V
¾
1
¾
¾
2V
¾
¾
¾
280
5V
¾
¾
¾
70
VDD
Conditions
2V
Unit
ns
us
ns
us
ns
Functional Description
These bits control the operation of the oscillator and so
data can be written to the register array. These two bits
should first be specified in order to read from and write
to the register array properly.
The HT1380/HT1381 mainly contains the following internal elements: a data shift register array to store the
clock/calendar data, command control logic, oscillator
circuit and read timer clock. The clock is contained in
eight read/write registers as shown below. Data contained in the clock register is in binary coded decimal
format.
Command Byte
For each data transfer, a Command Byte is initiated to
specify which register is accessed. This is to determine
whether a read, write, or test cycle is operated and
whether a single byte or burst mode transfer is to occur.
Refer to the table shown below and follow the steps to
write the data to the chip. First give a Command Byte of
HT1380/HT1381, and then write a data in the register.
Two modes are available for transferring the data between the microprocessor and the HT1380/HT1381.
One is in single-byte mode and the other is in multiple-byte mode.
The HT1380/HT1381 also contains two additional bits,
the clock halt bit (CH) and the write protect bit (WP).
This table illustrates the correlation between Command Byte and their bits:
Function Description
Command Byte
C7
C6
C5
C4
C3
C2
C1
A2
A1
A0
Select Read or Write Cycle
C0
R/W
Specify the Register to be Accessed
Clock Halt Flag
C
For IC Test Only
1
0
0
1
x
x
x
1
Select Single Byte or Burst Mode
1
0
1
1
1
1
1
x
Note: ²x² stands for don¢t care
Rev. 1.30
4
May 27, 2011
HT1380/HT1381
The following table shows the register address and its data format:
Register Definition
Register
Name
Range
Data
D7
Seconds
00~59
CH
10 SEC
Minutes
00~59
0
10 MIN
Hours
01~12
00~23
12\
24
0
0
AP
10
Date
01~31
0
0
Month
01~12
0
0
0
Day
01~07
0
0
0
Year
00~99
Write
Protect
00~80
D6
Address
A2~A0
Bit
R/W
Command
Byte
SEC
000
W
R
10000000
10000001
MIN
001
W
R
10000010
10000011
HR
HR
HOUR
010
W
R
10000100
10000101
10 DATE
DATE
011
W
R
10000110
10000111
10M
MONTH
100
W
R
10001000
10001001
0
DAY
101
W
R
10001010
10001011
YEAR
110
W
R
10001100
10001101
111
W
R
10001110
10001111
D5
D4
D3
D2
10 YEAR
WP
D1
D0
ALWAYS ZERO
CH: Clock Halt bit
CH=0 oscillator enabled
CH=1 oscillator disabled
WP: Write protect bit
WP=0 register data can be written in
WP=1 register data can not be written in
A0~A2
Bit 7 of Reg2:
Burst Mode
Bit 5 of Reg2:
A0 to A2 of the Command Byte is used to specify which
registers are to be accessed. There are eight registers
used to control the month data, etc., and each of these
registers have to be set as a write cycle in the initial time.
12/24 mode flag
bit 7=1, 12-hour mode
bit 7=0, 24-hour mode
AM/PM mode defined
AP=1 PM mode
AP=0 AM mode
When the Command Byte is 10111110 (or 10111111),
the HT1380/HT1381 is configured in burst mode. In this
mode the eight clock/calendar registers can be written
(or read) in series, starting with bit 0 of register address
0 (see the timing on the next page).
R/W Signal
Test Mode
The LSB of the Command Byte determines whether the
data in the register be read or be written to.
When the Command Byte is set as 1001xxx1,
HT1380/HT1381 is configured in test mode. The test
mode is used by Holtek only for testing purposes. If used
generally, unpredictable conditions may occur.
When it is set as ²0² means that a write cycle is to take
place otherwise this chip will be set into the read mode.
Rev. 1.30
5
May 27, 2011
HT1380/HT1381
Write Protect Register
This register is used to prevent a write operation to any
other register. Data can be written into the designated
register only if the Write Protect signal (WP) is set to
logic 0. The Write Protect Register should be set first before restarting the system or before writing the new data
to the system, and it should set as logic 1 in the read cycle. The Write Protect bit cannot be written to in the burst
mode.
The input signal of SCLK is a sequence of a falling edge
followed by a rising edge and it is used to synchronize
the register data whether read or write. For data input,
the data must be read after the rising edge of SCLK. The
data on the I/O pin becomes output mode after the falling edge of the SCLK. All data transfer terminates if the
REST pin is low and the I/O pin goes to a high impedance state. The data transfer is illustrated on the next
page.
Clock HALT Bit
Data Input and Data Out
D7 of the Seconds Register is defined as the Clock Halt
Flag (CH).
In writing a data byte with HT1380/HT1381, the
read/write should first set as R/W=0 in the Command
Byte and follow with the corresponding data register on
the rising edge of the next eight SCLK cycles. Additional
SCLK cycles are ignored. Data inputs are entered starting with bit 0.
When this bit is set to logic 1, the clock oscillator is
stopped and the chip goes into a low-power standby
mode. When this bit is written to logic 0, the clock will
start.
In reading a data on the register of HT1380/HT1381,
R/W=1 should first be entered as input. The data bit outputs on the falling edge of the next eight SCLK cycles.
Note that the first data bit to be transmitted on the first
falling edge after the last bit of the read command byte is
written. Additional SCLK cycles re-transmits the data
bytes as long as REST remains at high level. Data outputs are read starting with bit 0.
12-hour/24-hour Mode
The D7 of the hour register is defined as the 12-hour or
24-hour mode select bit.
When this bit is in high level, the 12-hour mode is selected otherwise it¢s the 24-hour mode.
AM-PM Mode
Crystal Selection
These are two functions for the D5 of the hour register
determined by the value D7 of the same register.
A 32768Hz crystal can be directly connected to the
HT1380/HT1381 on pins 2 and 3 which are the crystal
X1 and X2 pins. In order to ensure that the desired frequency is achieved, it is recommended to use a crystal
with a capacitance of 9.0pF. It is not recommended that
additional load capacitors are connected to the X1 and
X2 pins. Refer to the following page for the crystal specifications.
One is used in AM/PM selection on the 12-hour mode.
When D5 is logic 1, it is PM, otherwise it¢s AM. The other
is used to set the second 10-hour bit (20~23 hours) on
the 24-hour mode.
Reset and Serial Clock Control
The REST pin is used to allow access data to the shift
register like a toggle switch. When the REST pin is taken
high, the built-in control logic is turned on and the address/command sequence can access the corresponding shift register. The REST pin is also used to terminate
either single-byte or burst mode data format.
Rev. 1.30
3 2 7 6 8 H z
X 1
6
X 2
May 27, 2011
HT1380/HT1381
The following diagram shows the single and burst mode transfer:
· Single Byte Transfer
S C L K
R E S T
0
I/O
R /W
1
2
3
4
A 0
A 1
A 2
5
0
6
0
0
7
0
1
2
3
4
5
6
7
1
C o m m a n d B y te
D a ta I/O
· Burst Mode Transfer
S C L K
R E S T
0
I/O
R /W
1
2
1
3
1
4
1
1
5
1
6
0
7
0
7
0
7
1
C o m m a n d B y te
D a ta B y te 0
D a ta B y te 7
Crystal Specifications
Symbol
Parameter
Min.
Typ.
Max.
Unit
fO
Nominal Frequency
¾
32.768
¾
kHz
ESR
Series Resistance
¾
¾
50
kW
CL
Load Capacitance
¾
9.0
¾
pF
Note:
1. It is strongly recommended to use a crystal with a load capacitance of 9.0 pF. Never use a crystal with a load
capacitance of 12.5 pF.
2. The oscillator selection can be optimized using a high quality resonator with a small ESR value. Refer to the
crystal manufacturer for more details: www.microcrystal.com.
Operating Flowchart
To initiate any transfer of data, REST is taken high and an 8-bit command byte is first loaded into the control logic to provide the register address and command information. Following the command word, the clock/calendar data is serially
transferred to or from the corresponding register. The REST pin must be taken low again after the transfer operation is
completed. All data enter on the rising edge of SCLK and outputs on the falling edge of SCLK. In total, 16 clock pulses
are needed for a single byte mode and 72 for burst mode. Both input and output data starts with bit 0.
In using the HT1380/HT1381, set first the WP and CH to 0 and wait for about 3 seconds, the oscillator will generate the
clocks for internal use. Then, choose either single mode or burst mode to input the data. The read or write operating
flowcharts are shown on the next page.
Rev. 1.30
7
May 27, 2011
HT1380/HT1381
· To disable the write protect
· Single byte data transfer
· Burst mode data transfer
(WP=0) bit and enable the
oscillator (CH=0)
S T A R T
S T A R T
S e t R E S T p in
fr o m lo w to h ig h
D is a b le th e w r ite p r o te c t
b it a n d e n a b le th e o s c illa to r
In p u t th e w r ite
p ro te c t c o m m a n d
b y te 8 E H
S e t R E S T p in
fr o m lo w to h ig h
D is a b le th e
p r o te c t b it
b y s e ttin g th
o f r e g is te r 7
w r ite
(W P )
e M S B
to z e ro
R e s e t R E S T p in
fr o m h ig h to lo w
S e t R E S T p in
fr o m lo w to h ig h
In p u t th e w r ite
c o m m a n d b y te 8 0 H
E n a b le th e o s c illa to r
b y s e ttin g th e M S B o f
r e g is te r 0 to z e r o
S T A R T
D is a b le th e w r ite p r o te c t
b it a n d e n a b le th e o s c illa to r
S e t R E S T p in
fr o m lo w to h ig h
In p u t th e b u rs t m o d e
c o m m a n d b y te ($ B E o r
$ B F ) s ta r tin g w ith b it 0
*
In p u t th e c o m m a n d
b y te s ta r tin g w ith b it 0
R e a d o r w r ite th e
c o r r e s p o n d in g r e g is te r d a ta
b y te s ta r tin g w ith b it 0
*
R e s e t R E S T p in
fr o m h ig h to lo w
If a n o th e r r e g is te r
is a c c e s s e d
R e a d o
d a ta b y
th e H T
b it
r w r ite
te (6 4
1 3 8 1 s
0 o f re
a ll r e g is te r
d a ta b its ) in
ta r tin g w ith
g is te r 0
R e s e t R E S T p in
fr o m h ig h to lo w
Y e s
E N D
N o
E N D
R e s e t R E S T p in
fr o m h ig h to lo w
E N D
Note:
* In reading data byte from HT1380/HT1381 register, the first data bit to be transmitted at the first falling edge
after the last bit of the command byte is written.
Rev. 1.30
8
May 27, 2011
HT1380/HT1381
Timing Diagrams
Read Data Transfer
R E S T
tC C
S C L K
tC D H
tC D D
tD C
7
0
I/O
tC D Z
7
0
C o m m a n d B y te
O u tp u t D a ta B y te
Write Data Transfer
tC W H
R E S T
tr
tC H
tC C
tC C H
S C L K
tC D H
7
0
I/O
tf
tC L
tD C
7
0
C o m m a n d B y te
In p u t D a ta B y te
Application Circuits
V
D D
R 1 *
1 0 0 W
C 1 *
0 .1 m F
V D D
X 1
S C L K
M C U
In te r fa c e
3 2 7 6 8 H z *
I/O
X 2
R E S T
V S S
H T 1 3 8 0 /H T 1 3 8 1
Note:
* In order to obtain the correct frequency, it is recommended to use a crystal with a load capacitance of 9.0pF.
It is not recommended to connect load capacitors to the X1 and X2 pins.
If the power line is noisy, it is recommended to add R1 and C1 for filtering out noise.
Rev. 1.30
9
May 27, 2011
HT1380/HT1381
Package Information
8-pin DIP (300mil) Outline Dimensions
A
8
5
B
1
4
H
C
D
I
G
E
F
Symbol
Nom.
Max.
A
0.355
¾
0.375
B
0.240
¾
0.260
C
0.125
¾
0.135
D
0.125
¾
0.145
E
0.016
¾
0.020
F
0.050
¾
0.070
G
¾
0.100
¾
H
0.295
¾
0.315
I
¾
0.375
¾
Symbol
Rev. 1.30
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
9.02
¾
9.53
B
6.10
¾
6.60
C
3.18
¾
3.43
D
3.18
¾
3.68
E
0.41
¾
0.51
F
1.27
¾
1.78
G
¾
2.54
¾
H
7.49
¾
8.00
I
¾
9.53
¾
10
May 27, 2011
HT1380/HT1381
8-pin SOP (150mil) Outline Dimensions
A
5
8
1
B
4
C
C '
G
H
D
E
a
F
· MS-012
Symbol
Nom.
Max.
A
0.228
¾
0.244
B
0.150
¾
0.157
C
0.012
¾
0.020
C¢
0.188
¾
0.197
D
¾
¾
0.069
E
¾
0.050
¾
F
0.004
¾
0.010
G
0.016
¾
0.050
H
0.007
¾
0.010
a
0°
¾
8°
Symbol
A
Rev. 1.30
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
5.79
¾
6.20
B
3.81
¾
3.99
C
0.30
¾
0.51
C¢
4.78
¾
5.00
D
¾
¾
1.75
E
¾
1.27
¾
F
0.10
¾
0.25
G
0.41
¾
1.27
H
0.18
¾
0.25
a
0°
¾
8°
11
May 27, 2011
HT1380/HT1381
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 8N
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Rev. 1.30
13.0
+0.5/-0.2
2.0±0.5
12.8
+0.3/-0.2
18.2±0.2
12
May 27, 2011
HT1380/HT1381
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
B 0
C
D 1
P
K 0
A 0
R e e l H o le
IC
p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
SOP 8N
Symbol
Description
Dimensions in mm
12.0
+0.3/-0.1
W
Carrier Tape Width
P
Cavity Pitch
8.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
5.5±0.1
D
Perforation Diameter
D1
Cavity Hole Diameter
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.4±0.1
B0
Cavity Width
5.2±0.1
K0
Cavity Depth
2.1±0.1
t
Carrier Tape Thickness
C
Cover Tape Width
Rev. 1.30
1.55±0.1
1.50
+0.25/-0.00
0.30±0.05
9.3±0.1
13
May 27, 2011
HT1380/HT1381
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2011 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.30
14
May 27, 2011