HT1380A/HT1381A Serial Timekeeper Chip Features General Description • Operating voltage: 2.0V~5.5V The HT1380A/HT1381A is a serial timekeeper IC which provides seconds, minutes, hours, day, date, month and year information. The number of days in each month and leap years are automatically adjusted. The HT1380A/HT1381A is designed for low power consumption and can operate in two modes: one is the 12-hour mode with an AM/PM indicator, the other is the 24-hour mode. • Maximum input serial clock: 500kHz at VDD=2V, 2MHz at VDD=5V • Operating current: –– less than 0.5μA at 2V –– less than 0.7μA at 3V –– less than 1.0μA at 5V • TTL compatible –– VIH: 2.0V~VDD+0.3V at VDD=5V –– VIL: 0.3V~+0.8V at VDD=5V The HT1380A/HT1381A has several registers to store the corresponding information with 8-bit data format. A 32768Hz crystal is required to provide the correct timing. In order to minimize the pin number, the HT1380A/HT1381A use a serial I/O transmission method to interface with a microprocessor. Only three wires are required: (1) REST, (2) SCLK and (3) I/O. Data can be delivered 1 byte at a time or in a burst of up to 8 bytes. • Two data transmission modes: single-byte, or burst mode • Serial I/O transmission • All registers store BCD format • HT1380A: 8-pin DIP package HT1381A: 8-pin SOP package Applications • Microcomputer serial clock • Clock and Calendar Block Diagram Pin Assignment Rev. 1.00 1 June 15, 2012 HT1380A/HT1381A Pad Assignment N C 1 N C 3 2 N C 4 V S S (0 ,0 ) X 1 5 X 2 V S S 6 7 1 1 V D D 1 0 S C L K 9 I/O 8 R E S T Chip size: 1136 × 900 (μm)2 * The IC substrate should be connected to VSS in the PCB layout artwork. Pad Coordinates Unit: μm Pad No. X Y 1 -456.985 333.025 2 -456.985 264.025 3 -456.985 195.025 4 -455.590 109.935 5 -466.000 -154.955 6 -466.000 -249.955 7 -466.000 -344.955 8 465.966 -309.630 9 465.966 -214.630 10 465.966 -119.630 11 465.966 -24.630 Pad Description Pin Name I/O Internal Connection VSS � CMOS Negative power supply, ground X1 I CMOS 32768Hz crystal input pad X2 O CMOS Oscillator output pad REST I CMOS Reset pin with serial transmission I/O I/O CMOS Data Input/Output pin with serial transmission SCLK I CMOS Serial Clock pulse pin with serial transmission VDD � CMOS Positive power supply Rev. 1.00 Description 2 June 15, 2012 HT1380A/HT1381A Absolute Maximum Ratings Supply Voltage ........................................ -0.3V ~ 5.5V Storage Temperature .............................-50˚C ~ 125˚C Input Voltage.............................. VSS-0.3V ~ VDD+0.3V Operating Temperature............................-40˚C ~ 85˚C Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter Ta=25˚C Test Conditions Min. Typ. Max. — — 100 — — 100 5V — — 100 2V — 0.30 0.50 — 0.50 0.70 — 0.85 1.00 VDD Conditions 2V ISTB IDD Standby Current Operating Current 3V 3V — No load 5V IOH IOL Source Current Sink Current VIH "H" Input Voltage VIL "L" Input Voltage 2V VOH=1.8V -0.20 -0.40 — 3V VOH=2.7V -0.35 -0.70 — 5V VOH=4.5V -0.50 -1.00 — 2V VOL=0.2V 0.70 1.50 — 3V VOL=0.3V 1.20 2.50 — 5V VOL=0.5V 2.00 4.00 — 2.00 — — 2.00 — — — — 0.60 — — 0.80 3V 5V 3V 5V — — Unit nA μA mA mA V V Note: ISTB is specified with SCLK, I/O, REST open. The clock halt bit must be set to logic 1 (oscillator disabled). Rev. 1.00 3 June 15, 2012 HT1380A/HT1381A A.C. Characteristics Symbol tDC tCDH tCDD tCL tCH fSCLK tr/tf tCC tCCH tCWH tCDZ Rev. 1.00 Parameter Data to Clock Setup Clock to Data Hold Clock to Data Delay Clock Low Time Clock High Time Clock Frequency Clock Rise and Fall Time Reset to Clock Setup Clock to Reset Hold Reset Inactive Time Reset to I/O High Impedance Ta=25˚C Test Conditions Min. Typ. Max. — 200 — — — 100 — — 5V — 50 — — 2V — 280 — — 3V — 140 — — 5V — 70 — — 2V — — — 800 3V — — — 400 5V — — — 200 2V — 1000 — — 3V — 500 — — 5V — 250 — — 2V — 1000 — — 3V — 500 — — 5V — 250 — — 2V — — — 0.5 3V — — — 1.0 5V — — — 2.0 2V — — — 2000 3V — — — 1000 5V — — — 500 2V — 4 — — 3V — 2 — — 5V — 1 — — 2V — 240 — — 3V — 120 — — 5V — 60 — — 2V — 4 — — 3V — 2 — — 5V — 1 — — 2V — — — 280 3V — — — 140 5V — — — 70 VDD Conditions 2V 3V 4 Unit ns ns ns ns ns MHz ns μs ns μs ns June 15, 2012 HT1380A/HT1381A Functional Description data can be written to the register array. These two bits should first be specified in order to read from and write to the register array properly. The HT1380A/HT1381A mainly contains the following internal elements: a data shift register array to store the clock/calendar data, command control logic, oscillator circuit and read timer clock. The clock is contained in eight read/write registers as shown below. Data contained in the clock register is in binary coded decimal format. Command Byte For each data transfer, a Command Byte is initiated to specify which register is accessed. This is to determine whether a read, write, or test cycle is operated and whether a single byte or burst mode transfer is to occur. Refer to the table shown below and follow the steps to write the data to the chip. First give a Command Byte of HT1380A/HT1381A, and then write a data in the register. Two modes are available for transferring the data between the microprocessor and the HT1380A/ HT1381A. One is in single-byte mode and the other is in multiple-byte mode. This table illustrates the correlation between Command Byte and their bits: The HT1380A/HT1381A also contains two additional bits, the clock halt bit (CH) and the write protect bit (WP). These bits control the operation of the oscillator and so Command Byte Function Description C7 C6 C5 C4 C3 C2 C1 C0 Select Read or Write Cycle — — — — — — — R/W Specify the Register to be Accessed — — — — A2 A1 A0 — Clock Halt Flag C — — — — — — — For IC Test Only 1 0 0 1 x x x 1 Select Single Byte or Burst Mode 1 0 1 1 1 1 1 x Note: ″x″ stands for don′t care The following table shows the register address and its data format: Register Name Register Definition Range Data D7 Address A2~A0 Bit R/W Command Byte Seconds 00~59 CH 10 SEC SEC 000 W R 10000000 10000001 Minutes 00~59 0 10 MIN MIN 001 W R 10000010 10000011 Hours 01~12 00~23 12\ 24 0 0 AP 10 HR HR HOUR 010 W R 10000100 10000101 Date 01~31 0 0 10 DATE DATE 011 W R 10000110 10000111 Month 01~12 0 0 0 10M MONTH 100 W R 10001000 10001001 Day 01~07 0 0 0 0 DAY 101 W R 10001010 10001011 Year 00~99 YEAR 110 W R 10001100 10001101 Write Protect 00~80 111 W R 10001110 10001111 D6 D5 D4 D3 D2 10 YEAR WP ALWAYS ZERO D1 D0 CH: Clock Halt bit CH=0 oscillator enabled CH=1 oscillator disabled Bit 7 of Reg2: 12/24 mode flag bit 7=1, 12-hour mode bit 7=0, 24-hour mode WP: Write protect bit WP=0 register data can be written in WP=1 register data can not be written in Bit 5 of Reg2: AM/PM mode defined AP=1 PM mode AP=0 AM mode Rev. 1.00 5 June 15, 2012 HT1380A/HT1381A R/W Signal AM-PM Mode The LSB of the Command Byte determines whether the data in the register be read or be written to. These are two functions for the D5 of the hour register determined by the value D7 of the same register. When it is set as ″0″ means that a write cycle is to take place otherwise this chip will be set into the read mode. One is used in AM/PM selection on the 12-hour mode. When D5 is logic 1, it is PM, otherwise it′s AM. The other is used to set the second 10-hour bit (20~23 hours) on the 24-hour mode. A0~A2 A0 to A2 of the Command Byte is used to specify which registers are to be accessed. There are eight registers used to control the month data, etc., and each of these registers have to be set as a write cycle in the initial time. Reset and Serial Clock Control The REST pin is used to allow access data to the shift register like a toggle switch. When the REST pin is taken high, the built-in control logic is turned on and the address/command sequence can access the corresponding shift register. The REST pin is also used to terminate either single-byte or burst mode data format. Burst Mode When the Command Byte is 10111110 (or 10111111), the HT1380A/HT1381A is configured in burst mode. In this mode the eight clock/calendar registers can be written (or read) in series, starting with bit 0 of register address 0 (see the timing on the next page). The input signal of SCLK is a sequence of a falling edge followed by a rising edge and it is used to synchronize the register data whether read or write. For data input, the data must be read after the rising edge of SCLK. The data on the I/O pin becomes output mode after the falling edge of the SCLK. All data transfer terminates if the REST pin is low and the I/O pin goes to a high impedance state. The data transfer is illustrated on the next page. Test Mode When the Command Byte is set as 1001xxx1, HT1380A/HT1381A is configured in test mode. The test mode is used by Holtek only for testing purposes. If used generally, unpredictable conditions may occur. Data Input and Data Out Write Protect Register In writing a data byte with HT1380A/HT1381A, the read/write should first set as R/W=0 in the Command Byte and follow with the corresponding data register on the rising edge of the next eight SCLK cycles. Additional SCLK cycles are ignored. Data inputs are entered starting with bit 0. This register is used to prevent a write operation to any other register. Data can be written into the designated register only if the Write Protect signal (WP) is set to logic 0. The Write Protect Register should be set first before restarting the system or before writing the new data to the system, and it should set as logic 1 in the read cycle. The Write Protect bit cannot be written to in the burst mode. In reading a data on the register of HT1380A/ HT1381A, R/W=1 should first be entered as input. The data bit outputs on the falling edge of the next eight SCLK cycles. Note that the first data bit to be transmitted on the first falling edge after the last bit of the read command byte is written. Additional SCLK cycles re-transmits the data bytes as long as REST remains at high level. Data outputs are read starting with bit 0. Clock HALT Bit D7 of the Seconds Register is defined as the Clock Halt Flag (CH). When this bit is set to logic 1, the clock oscillator is stopped and the chip goes into a low-power standby mode. When this bit is written to logic 0, the clock will start. Crystal Selection A 32768Hz crystal can be directly connected to the HT1380A/HT1381A on pins 2 and 3 which are the crystal X1 and X2 pins. In order to ensure that the desired frequency is achieved, it is recommended to use a crystal with a capacitance of 9.0pF. It is not recommended that additional load capacitors are connected to the X1 and X2 pins. Refer to the following page for the crystal specifications. 12-hour/24-hour Mode The D7 of the hour register is defined as the 12-hour or 24-hour mode select bit. When this bit is in high level, the 12-hour mode is selected otherwise it′s the 24-hour mode. Rev. 1.00 6 June 15, 2012 HT1380A/HT1381A The following diagram shows the single and burst mode transfer: Single Byte Transfer S C L K R E S T 0 I/O R /W 1 2 3 A 0 A 1 A 2 4 5 0 6 0 7 0 0 1 2 3 4 5 6 7 1 C o m m a n d B y te D a ta I/O Burst Mode Transfer S C L K R E S T 0 I/O R /W 1 1 2 1 3 1 4 1 5 1 6 0 7 0 7 0 7 1 C o m m a n d B y te D a ta B y te 0 D a ta B y te 7 Crystal Specifications Symbol Parameter Min. Typ. Max. Unit fO Nominal Frequency — 32.768 — kHz ESR Series Resistance — — 50 kΩ CL Load Capacitance — 9.0 — pF Note: 1. It is strongly recommended to use a crystal with a load capacitance of 9.0pF. Never use a crystal with a load capacitance of 12.5pF. 2. The oscillator selection can be optimized using a high quality resonator with a small ESR value. Refer to the crystal manufacturer for more details: www.microcrystal.com. Operating Flowchart In using the HT1380A/HT1381A, set first the WP and CH to 0 and wait for about 3 seconds, the oscillator will generate the clocks for internal use. Then, choose either single mode or burst mode to input the data. The read or write operating flowcharts are shown on the next page. To initiate any transfer of data, REST is taken high and an 8-bit command byte is first loaded into the control logic to provide the register address and command information. Following the command word, the clock/ calendar data is serially transferred to or from the corresponding register. The REST pin must be taken low again after the transfer operation is completed. All data enter on the rising edge of SCLK and outputs on the falling edge of SCLK. In total, 16 clock pulses are needed for a single byte mode and 72 for burst mode. Both input and output data starts with bit 0. Rev. 1.00 7 June 15, 2012 HT1380A/HT1381A Note: * In reading data byte from HT1380A/HT1381A register, the first data bit to be transmitted at the first falling edge after the last bit of the command byte is written. Rev. 1.00 8 June 15, 2012 HT1380A/HT1381A Timing Diagrams Read Data Transfer R E S T tC C S C L K tC D H tC D D tD C 7 0 I/O tC D Z 7 0 C o m m a n d B y te O u tp u t D a ta B y te Write Data Transfer tC W H R E S T S C L K tC D H tD C tC C H tf tC L 7 0 I/O tr tC H tC C 7 0 C o m m a n d B y te In p u t D a ta B y te Application Circuit Note: * In order to obtain the correct frequency, it is recommended to use a crystal with a load capacitance of 9.0pF. It is not recommended to connect load capacitors to the X1 and X2 pins. If the power line is noisy, it is recommended to add R1 and C1 for filtering out noise. Rev. 1.00 9 June 15, 2012 HT1380A/HT1381A Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website (http://www.holtek.com.tw/english/ literature/package.pdf) for the latest version of the package information. 8-pin DIP (300mil) Outline Dimensions Symbol Min. Nom. Max. A 0.355 ― 0.375 B 0.240 ― 0.260 C 0.125 ― 0.135 D 0.125 ― 0.145 E 0.016 ― 0.020 F 0.050 ― 0.070 G ― 0.100 ― H 0.295 ― 0.315 I ― 0.375 ― Symbol Rev. 1.00 Dimensions in inch Dimensions in mm Min. Nom. Max. A 9.02 ― 9.53 B 6.10 ― 6.60 C 3.18 ― 3.43 D 3.18 ― 3.68 E 0.41 ― 0.51 F 1.27 ― 1.78 G ― 2.54 ― H 7.49 ― 8.00 I ― 9.53 ― 10 June 15, 2012 HT1380A/HT1381A 8-pin SOP (150mil) Outline Dimensions MS-012 Symbol Min. Nom. Max. A 0.228 ― 0.244 B 0.150 ― 0.157 C 0.012 ― 0.020 C' 0.188 ― 0.197 D ― ― 0.069 E ― 0.050 ― F 0.004 ― 0.010 G 0.016 ― 0.050 H 0.007 ― 0.010 α 0° ― 8° Symbol Rev. 1.00 Dimensions in inch Dimensions in mm Min. Nom. Max. A 5.79 ― 6.20 B 3.81 ― 3.99 C 0.30 ― 0.51 C' 4.78 ― 5.00 D ― ― 1.75 E ― 1.27 ― F 0.10 ― 0.25 G 0.41 ― 1.27 H 0.18 ― 0.25 α 0° ― 8° 11 June 15, 2012 HT1380A/HT1381A Reel Dimensions SOP 8N (150mil) Symbol Description Dimensions in mm A Reel Outer Diameter B Reel Inner Diameter 100.0±1.5 C Spindle Hole Diameter 13.0 +0.5/-0.2 D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 330.0±1.0 2.0±0.5 12.8 +0.3/-0.2 18.2±0.2 12 June 15, 2012 HT1380A/HT1381A Carrier Tape Dimensions SOP 8N (150mil) Symbol Description W Carrier Tape Width Dimensions in mm 12.0 +0.3/-0.1 P Cavity Pitch E Perforation Position 1.75±0.10 8.0±0.1 5.50±0.1 F Cavity to Perforation (Width Direction) D Perforation Diameter 1.55±0.1 D1 Cavity Hole Diameter 1.50 +0.25/-0.00 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 6.4±0.1 B0 Cavity Width 5.2±0.1 K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 2.1±0.1 0.30±0.05 9.3±0.1 13 June 15, 2012 HT1380A/HT1381A Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright© 2012 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 14 June 15, 2012