HT66F0187

A/D 8-Bit Flash MCU with EEPROM
HT66F0187
Revision: V1.00
Date: ��������������
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Table of Contents
Features................................................................................................................. 7
CPU Features...............................................................................................................................7
Peripheral Features.......................................................................................................................7
General Description.............................................................................................. 8
Block Diagram....................................................................................................... 8
Pin Assignment..................................................................................................... 9
Pin Description................................................................................................... 10
Absolute Maximum Ratings............................................................................... 13
D.C. Characteristics............................................................................................ 14
A.C. Characteristics............................................................................................ 17
HIRC Electrical Characteristics......................................................................... 18
A/D Converter Electrical Characteristics.......................................................... 19
Comparator Electrical Characteristics............................................................. 20
Power on Reset Characteristics........................................................................ 20
System Architecture........................................................................................... 21
Clocking and Pipelining...............................................................................................................21
Program Counter.........................................................................................................................22
Stack...........................................................................................................................................23
Arithmetic and Logic Unit – ALU.................................................................................................23
Flash Program Memory...................................................................................... 24
Structure......................................................................................................................................24
Special Vectors...........................................................................................................................24
Look-up Table..............................................................................................................................24
Table Program Example..............................................................................................................25
In Circuit Programming – ICP.....................................................................................................26
On-Chip Debug Support – OCDS...............................................................................................27
RAM Data Memory.............................................................................................. 27
Structure......................................................................................................................................27
Data Memory Addressing............................................................................................................28
General Purpose Data Memory..................................................................................................28
Special Purpose Data Memory...................................................................................................29
Special Function Register Description............................................................. 30
Indirect Addressing Register – IAR0, IAR1, IAR2.......................................................................30
Memory Pointers – MP0, MP1H/MP1L, MP2H/MP2L ................................................................30
Accumulator – ACC.....................................................................................................................32
Program Counter Low Register – PCL .......................................................................................32
Look-up Table Registers – TBLP, TBHP, TBLH ..........................................................................32
Status Register – STATUS .........................................................................................................33
Rev. 1.00
2
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
EEPROM Data memory...................................................................................... 35
EEPROM Data Memory Structure..............................................................................................35
EEPROM Registers....................................................................................................................35
Reading Data from the EEPROM...............................................................................................37
Writing Data to the EEPROM......................................................................................................37
Write Protection...........................................................................................................................37
EEPROM Interrupt......................................................................................................................37
Programming Considerations......................................................................................................38
Oscillator............................................................................................................. 39
Oscillator Overview ....................................................................................................................39
System Clock Configurations .....................................................................................................39
External Crystal/Ceramic Oscillator – HXT ................................................................................40
Internal RC Oscillator – HIRC ....................................................................................................41
External 32.768kHz Crystal Oscillator – LXT..............................................................................41
Internal 32kHz Oscillator – LIRC ................................................................................................42
Supplementary Oscillators .........................................................................................................42
Operating Modes and System Clocks ............................................................. 43
System Clocks ...........................................................................................................................43
System Operation Modes ...........................................................................................................44
Control Registers........................................................................................................................45
Fast Wake-up .............................................................................................................................47
Operating Mode Switching .........................................................................................................48
Standby Current Considerations ................................................................................................52
Wake-up .....................................................................................................................................52
Programming Considerations .....................................................................................................53
Watchdog Timer.................................................................................................. 53
Watchdog Timer Clock Source....................................................................................................53
Watchdog Timer Control Register...............................................................................................53
Watchdog Timer Operation.........................................................................................................55
Reset and Initialisation....................................................................................... 56
Reset Functions .........................................................................................................................56
Reset Initial Conditions ..............................................................................................................58
Input/Output Ports ............................................................................................. 61
Pull-high Resistors......................................................................................................................62
Port A Wake-up...........................................................................................................................62
I/O Port Control Registers...........................................................................................................62
I/O Port Source Current Control..................................................................................................62
Pin-remapping Functions............................................................................................................64
I/O Pin Structures........................................................................................................................65
Programming Considerations .....................................................................................................66
Rev. 1.00
3
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Timer Modules – TM........................................................................................... 67
Introduction.................................................................................................................................67
TM Operation..............................................................................................................................67
TM Clock Source.........................................................................................................................68
TM Interrupts...............................................................................................................................68
TM External Pins ........................................................................................................................68
TM Input/Output Pin Control Registers.......................................................................................69
Programming Considerations......................................................................................................72
Standard Type TM – STM................................................................................... 73
Standard TM Operation...............................................................................................................73
Standard Type TM Register Description ....................................................................................73
Standard Type TM Operating Modes .........................................................................................78
Periodic Type TM – PTM..................................................................................... 88
Periodic TM Operation................................................................................................................88
Periodic Type TM Register Description.......................................................................................88
Periodic Type TM Operating Modes............................................................................................93
Analog to Digital Converter – ADC.................................................................. 102
A/D Overview............................................................................................................................102
A/D Converter Register Description..........................................................................................103
A/D Converter Data Registers – SADOL, SADOH....................................................................103
A/D Converter Control Registers – SADC0, SADC1, SADC2, ACERL.....................................104
A/D Operation...........................................................................................................................108
A/D Reference Voltage..............................................................................................................109
A/D Converter Input Signal....................................................................................................... 110
Conversion Rate and Timing Diagram...................................................................................... 110
Summary of A/D Conversion Steps........................................................................................... 111
Programming Considerations.................................................................................................... 112
A/D Transfer Function............................................................................................................... 112
A/D Programming Examples..................................................................................................... 113
Serial Interface Module – SIM.......................................................................... 115
SPI Interface............................................................................................................................. 115
SPI Registers............................................................................................................................ 116
SPI Communication.................................................................................................................. 119
I2C Interface..............................................................................................................................122
I2C Registers.............................................................................................................................123
I2C Time-out Control..................................................................................................................130
Comparator....................................................................................................... 132
Comparator Operation..............................................................................................................132
Comparator Interrupt.................................................................................................................132
Programming Considerations....................................................................................................132
SCOM Function for LCD................................................................................... 134
LCD Operation..........................................................................................................................134
LCD Bias Control......................................................................................................................134
Rev. 1.00
4
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
UART Interface.................................................................................................. 136
UART External Pins..................................................................................................................137
UART Data Transfer Scheme...................................................................................................137
UART Status and Control Registers.........................................................................................137
Baud Rate Generator................................................................................................................143
UART Setup and Control..........................................................................................................145
UART Transmitter.....................................................................................................................146
UART Receiver.........................................................................................................................147
Managing Receiver Errors........................................................................................................149
UART Interrupt Structure..........................................................................................................150
Address Detect Mode................................................................................................................151
UART Wake-up.........................................................................................................................151
Low Voltage Detector – LVD............................................................................ 152
LVD Register.............................................................................................................................152
LVD Operation...........................................................................................................................153
Interrupts........................................................................................................... 154
Interrupt Registers.....................................................................................................................154
Interrupt Operation....................................................................................................................159
External Interrupt.......................................................................................................................160
Comparator Interrupt.................................................................................................................161
Multi-function Interrupt..............................................................................................................161
A/D Converter Interrupt.............................................................................................................161
Time Base Interrupt...................................................................................................................162
EEPROM Interrupt....................................................................................................................163
LVD Interrupt ............................................................................................................................163
TM Interrupts ............................................................................................................................163
SIM Interrupt.............................................................................................................................164
UART Transfer Interrupt............................................................................................................164
Interrupt Wake-up Function.......................................................................................................164
Programming Considerations....................................................................................................165
Configuration Option........................................................................................ 166
Application Circuits.......................................................................................... 166
Instruction Set................................................................................................... 167
Introduction...............................................................................................................................167
Instruction Timing......................................................................................................................167
Moving and Transferring Data...................................................................................................167
Arithmetic Operations................................................................................................................167
Logical and Rotate Operation...................................................................................................168
Branches and Control Transfer.................................................................................................168
Bit Operations...........................................................................................................................168
Table Read Operations.............................................................................................................168
Other Operations.......................................................................................................................168
Rev. 1.00
5
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Instruction Set Summary................................................................................. 169
Table Conventions.....................................................................................................................169
Extended Instruction Set...........................................................................................................171
Instruction Definition........................................................................................ 173
Extended Instruction Definition.................................................................................................182
Package Information........................................................................................ 189
44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions.................................................190
48-pin LQFP (7mm×7mm) Outline Dimensions........................................................................191
Rev. 1.00
6
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Features
CPU Features
• Operating Voltage
♦♦
fSYS=8MHz: 2.2V~5.5V
♦♦
fSYS=12MHz: 2.7V~5.5V
♦♦
fSYS=20MHz: 4.5V~5.5V
• Up to 0.2μs instruction cycle with 20MHz system clock at VDD=5V
• Power down and wake-up functions to reduce power consumption
• Oscillators
♦♦
External Crystal – HXT
♦♦
External 32.768kHz Crystal – LXT
♦♦
Internal High Speed RC – HIRC
♦♦
Internal 32kHz RC – LIRC
• Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP
• Fully integrated internal 8/12/16MHz oscillator requires no external components
• All instructions executed in one to three instruction cycles
• Table read instructions
• 115 powerful instructions
• 8-level subroutine nesting
• Bit manipulation instruction
Peripheral Features
• Flash Program Memory: 4K × 16
• RAM Data Memory: 256 × 8
• EEPROM Memory: 64 × 8
• Watchdog Timer function
• 46 bidirectional I/O lines
• Software controlled 4-SCOM lines LCD driver with 1/2 bias
• Programmable I/O port source current for LED applications
• Two pin-shared external interrupts
• Multiple Timer Module for time measure, input capture, compare match output, PWM output or
single pulse output functions
• Serial Interface Module with SPI and I2C interfaces
• Full-duplex Universal Asynchronous Receiver and Transmitter Interface – UART
• One comparator function
• Dual Time-Base functions for generation of fixed time interrupt signals
• 8-channel 12-bit resolution A/D converter
• Low Voltage Reset function
• Low Voltage Detect function
• Package type: 44/48-pin LQFP
Rev. 1.00
7
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
General Description
The device is a Flash Memory type 8-bit high performance RISC architecture microcontroller.
Offering users the convenience of Flash Memory multi-programming features, the device also
includes a wide range of functions and features. Other memory includes an area of RAM Data
Memory as well as an area of EEPROM memory for storage of non-volatile data such as serial
numbers, calibration data etc.
Analog features include a multi-channel 12-bit A/D converter and comparator functions. Multiple
and extremely flexible Timer Modules provide timing, pulse generation and PWM generation
functions. Communication with the outside world is catered for by including fully integrated SPI
or I2C interface functions, two popular interfaces which provide designers with a means of easy
communication with external peripheral hardware. Protective features such as an internal Watchdog
Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and
ESD protection ensure that reliable operation is maintained in hostile electrical environments.
A full choice of high and low speed, internal and external oscillator functions are provided including
a fully integrated system oscillator which requires no external components for its implementation.
The ability to operate and switch dynamically between a range of operating modes using different
clock sources gives users the ability to optimise microcontroller operation and minimise power
consumption.
The UART module can support applications such as data communication networks between
microcontrollers, low-cost data links between PCs and peripheral devices, portable and battery
operated device communication, etc.
The inclusion of flexible I/O programming features, Time-Base functions along with many other
features ensure that the device will find excellent use in applications such as electronic metering,
environmental monitoring, handheld instruments, household appliances, electronically controlled
tools, motor driving in addition to many others.
Block Diagram
Flash/EEPROM
Programming Circuitry
EEPROM
Data
Memory
Flash
Program
Memory
Watchdog
Timer
Internal
HIRC/LIRC
Oscillators
Low
Voltage
Detect
Low
Voltage
Reset
RAM Data
Memory
Time
Bases
Reset
Circuit
8-bit
RISC
MCU
Core
Interrupt
Controller
External
HXT/LXT
Oscillators
12-bit A/D
Converter
Comparator
I/O
Rev. 1.00
SCOM
Timer
Modules
SIM
(SPI/I2C)
8
UART
+
─
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Pin Assignment
PC4/SCOM0
PC�/SCOM1
PC6/SCOM�
PC�/SCOM3
VDD
PB0/XT1
PB1/XT�
VSS
PC0/OSC1
PC1/OSC�
P�0/OCDSD�/ICPD�
P��/OCDSCK/ICPCK
PC�/STP0
PE6/SCS
PF0/SCK/SCL
PB�/SDI/SD�
PB3/SDO
PB4/CLO/TX
PC3/PTCK/RX
PB�/STP1
PB6/PTPI
PE�/STCK1
44 43 4� 41 40 39 38 3� 36 3� 34
1
33
�
3�
3
31
4
30
�
HT66F0187/HT66V0187 �9
6
�8
44 LQFP-A
�
��
8
�6
9
��
10
�4
11
�3
1� 13 14 1� 16 1� 18 19 �0 �1 ��
PE�/[STCK1]/[TX]
PE4/[STCK0]/[RX]
PE3/[STP1]
PE�/PTP
PE1/C+
PE0/CPD�/CX
PD6/[STP0I]
PD�/[INT1]
PD4/[PTPI]
PD3/[STP0]/[SCOM3]
PD�/[PTCK]/[SCOM�]
PD1/[PTP]/[SCOM1]
PD0/INT1/[SCOM0]
P��/[STP1I]/�N0
P�6/STCK0/�N1
P��/STP0I/�N�
P�4/�N3
P�3/�N4/VREFI
P�1/�N�/VREF
PF1/INT0/�N6
PB�/STP1I/�N�
PE4/[STCK0]/[RX]
PE�/[STCK1]/[TX]
PC4/SCOM0
PC�/SCOM1
PC6/SCOM�
PC�/SCOM3
VDD
PB0/XT1
PB1/XT�
VSS
PC0/OSC1
PC1/OSC�
P�0/OCDSD�/ICPD�
P��/OCDSCK/ICPCK
PC�/STP0
PE6/SCS
PF0/SCK/SCL
PB�/SDI/SD�
PB3/SDO
PB4/CLO/TX
PC3/PTCK/RX
PB�/STP1
PB6/PTPI
PE�/STCK1
48 4� 46 4�44 43 4� 41 403938 3�
36
1
3�
�
34
3
33
4
�
3�
6
HT66F0187/HT66V0187 31
�
30
48 LQFP-A
�9
8
�8
9
��
10
�6
11
��
1�
13141�16 1�1819�0�1���3�4
PE3/[STP1]
PE�/PTP
PE1/C+
PE0/CPD�/CX
PD6/[STP0I]
PD�/[INT1]
PD4/[PTPI]
PD3/[STP0]/[SCOM3]
PD�/[PTCK]/[SCOM�]
PD1/[PTP]/[SCOM1]
PD0/INT1/[SCOM0]
PF�/[INT0]
PF3
PF4
PF�
P��/[STP1I]/�N0
P�6/STCK0/�N1
P��/STP0I/�N�
P�4/�N3
P�3/�N4/VREFI
P�1/�N�/VREF
PF1/INT0/�N6
PB�/STP1I/�N�
Note: 1. If the pin-shared pin functions have multiple outputs, then the function at the rightmost side
of the “/” sign will have higher priority.
2. The OCDSDA and OCDSCK pins are the OCDS dedicated pins and only available for the
HT66V0187 EV device.
Rev. 1.00
9
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Pin Description
With the exception of the power pins, all pins on the device can be referenced by its Port name,
e.g. PA0, PA1 etc., which refer to the digital I/O function of the pins. However these Port pins are
also shared with other function such as the Analog to Digital Converter, Timer Module pins etc.
The function of each pin is listed in the following table, however the details behind how each pin is
configured is contained in other sections of the datasheet.
Pin Name
PA0/OCDSDA/ICPDA
PA1/AN5/VREF
PA2/OCDSCK/ICPCK
PA3/AN4/VREFI
PA4/AN3
PA5/STP0I/AN2
PA6/STCK0/AN1
PA7/[STP1I]/AN0
PB0/XT1
PB1/XT2
PB2/SDI/SDA
PB3/SDO
Rev. 1.00
Function
OPT
PA0
PAPU
PAWU
I/T
O/T
ST
General purpose I/O. Register enabled pull-high
CMOS
and wake-up.
Description
OCDSDA
—
ST
CMOS OCDS Address/Data, for EV chip only
ICPDA
—
ST
CMOS ICP Address/Data
PA1
PAPU
PAWU
ST
CMOS
General purpose I/O. Register enabled pull-high
and wake-up.
AN5
ACERL
AN
—
A/D Converter input channel 5
VREF
SADC2
—
AN
A/D Converter reference voltage output
PA2
PAPU
PAWU
ST
CMOS
OCDSCK
—
ST
—
OCDS Clock pin, for EV chip only
ICPCK
—
ST
—
ICP Clock pin
PA3
PAPU
PAWU
ST
CMOS
General purpose I/O. Register enabled pull-high
and wake-up.
General purpose I/O. Register enabled pull-high
and wake-up.
AN4
ACERL
AN
—
A/D Converter input channel 4
VREFI
SADC2
AN
—
A/D Converter Reference Voltage Input
PA4
PAPU
PAWU
ST
CMOS
AN3
ACERL
AN
—
PA5
PAPU
PAWU
ST
CMOS
STP0I
PRM
STM0C1
ST
—
STM0 Capture input
AN2
ACERL
AN
—
A/D Converter input channel 2
PA6
PAPU
PAWU
ST
CMOS
STCK0
PRM
STM0C0
ST
—
STM0 clock input
AN1
ACERL
AN
—
A/D Converter input channel 1
PA7
PAPU
PAWU
ST
CMOS
STP1I
PRM
TMPC
STM1C1
ST
—
STM1 Capture input
AN0
ACERL
AN
—
A/D Converter input channel 0
PB0
PBPU
ST
XT1
CO
LXT
PB1
PBPU
ST
General purpose I/O. Register enabled pull-high
and wake-up.
A/D Converter input channel 3
General purpose I/O. Register enabled pull-high
and wake-up.
General purpose I/O. Register enabled pull-high
and wake-up.
General purpose I/O. Register enabled pull-high
and wake-up.
CMOS General purpose I/O. Register enabled pull-high.
—
LXT oscillator pin
CMOS General purpose I/O. Register enabled pull-high.
XT2
CO
—
PB2
PBPU
ST
LXT
LXT oscillator pin
SDI
SIMC0
ST
SDA
SIMC0
ST
CMOS I2C data line
PB3
PBPU
ST
CMOS General purpose I/O. Register enabled pull-high.
SDO
SIMC0
—
CMOS SPI serial data output
CMOS General purpose I/O. Register enabled pull-high.
—
10
SPI serial data input
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Pin Name
PB4/CLO/TX
PB5/STP1
PB6/PTPI
PB7/STP1I/AN7
PC0/OSC1
PC1/OSC2
PC2/STP0
PC3/PTCK/RX
PC4/SCOM0
PC5/SCOM1
PC6/SCOM2
PC7/SCOM3
PD0/INT1/[SCOM0]
PD1/[PTP]/[SCOM1]
Rev. 1.00
Function
OPT
I/T
PB4
PBPU
ST
CMOS General purpose I/O. Register enabled pull-high.
O/T
CLO
TMPC
—
CMOS System clock output
TX
PRM
UCR1
UCR2
—
CMOS UART transmit line
PB5
PBPU
ST
CMOS General purpose I/O. Register enabled pull-high.
STP1
PRM
TMPC
—
CMOS STM1 output
PB6
PBPU
ST
CMOS General purpose I/O. Register enabled pull-high.
PTPI
PRM
PTMC1
ST
PB7
PBPU
ST
STP1I
PRM
STM1C1
ST
AN7
ACERL
AN
PC0
PCPU
ST
OSC1
CO
HXT
PC1
PCPU
ST
—
Description
PTM Capture input
CMOS General purpose I/O. Register enabled pull-high.
—
STM1 Capture input
—
A/D Converter input channel 7
CMOS General purpose I/O. Register enabled pull-high.
—
HXT oscillator pin
CMOS General purpose I/O. Register enabled pull-high.
OSC2
CO
—
PC2
PCPU
ST
CMOS General purpose I/O. Register enabled pull-high.
HXT
HXT oscillator pin
STP0
PRM
TMPC
—
CMOS STM0 output
PC3
PCPU
ST
CMOS General purpose I/O. Register enabled pull-high.
PTCK
PRM
PTMC0
ST
—
PTM clock input
RX
PRM
UCR1
UCR2
ST
—
UART receive line
PC4
PCPU
ST
SCOM0
PRM
SCOMC
—
PC5
PCPU
ST
SCOM1
PRM
SCOMC
—
PC6
PCPU
ST
SCOM2
PRM
SCOMC
—
PC7
PCPU
ST
SCOM3
PRM
SCOMC
—
PD0
PDPU
ST
INT1
PRM
INTEG
ST
—
External interrupt 1 input
SCOM0
PRM
SCOMC
—
AN
Software controlled 1/2 bias LCD COM
PD1
PDPU
ST
CMOS General purpose I/O. Register enabled pull-high.
PTP
PRM
TMPC
—
CMOS PTM output
SCOM1
PRM
SCOMC
—
CMOS General purpose I/O. Register enabled pull-high.
AN
Software controlled 1/2 bias LCD COM
CMOS General purpose I/O. Register enabled pull-high.
AN
Software controlled 1/2 bias LCD COM
CMOS General purpose I/O. Register enabled pull-high.
AN
Software controlled 1/2 bias LCD COM
CMOS General purpose I/O. Register enabled pull-high.
AN
Software controlled 1/2 bias LCD COM
CMOS General purpose I/O. Register enabled pull-high.
AN
11
Software controlled 1/2 bias LCD COM
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Pin Name
PD2/[PTCK]/[SCOM2]
PD3/[STP0]/[SCOM3]
PD4/[PTPI]
PD5/[INT1]
PD6/[STP0I]
PD7/CX
PE0/CPE1/C+
PE2/PTP
PE3/[STP1]
PE4/[STCK0]/[RX]
PE5/[STCK1]/[TX]
PE6/SCS
PE7/STCK1
PF0/SCK/SCL
Rev. 1.00
Function
OPT
I/T
PD2
PDPU
ST
O/T
Description
PTCK
PRM
PTMC0
ST
—
PTM clock input
SCOM2
PRM
SCOMC
—
AN
Software controlled 1/2 bias LCD COM
PD3
PDPU
ST
CMOS General purpose I/O. Register enabled pull-high.
STP0
PRM
TMPC
—
CMOS STM0 output
SCOM3
PRM
SCOMC
—
PD4
PDPU
ST
PTPI
PRM
PTMC1
ST
PD5
PDPU
ST
INT1
PRM
INTEG
ST
PD6
PDPU
ST
STP0I
PRM
STM0C1
ST
PD7
PDPU
ST
CMOS General purpose I/O. Register enabled pull-high.
CX
CPC
—
CMOS Comparator output
PE0
PEPU
ST
CMOS General purpose I/O. Register enabled pull-high.
C-
CPC
AN
PE1
PEPU
ST
CMOS General purpose I/O. Register enabled pull-high.
AN
Software controlled 1/2 bias LCD COM
CMOS General purpose I/O. Register enabled pull-high.
—
PTM Capture input
CMOS General purpose I/O. Register enabled pull-high.
—
External interrupt 1 input
CMOS General purpose I/O. Register enabled pull-high.
—
—
STM0 Capture input
Comparator input
CMOS General purpose I/O. Register enabled pull-high.
C+
CPC
AN
PE2
PEPU
ST
CMOS General purpose I/O. Register enabled pull-high.
—
Comparator input
PTP
PRM
TMPC
—
CMOS PTM output
PE3
PEPU
ST
CMOS General purpose I/O. Register enabled pull-high.
STP1
PRM
TMPC
—
CMOS STM1 output
PE4
PEPU
ST
CMOS General purpose I/O. Register enabled pull-high.
STCK0
PRM
STM0C0
ST
—
STM0 clock input
RX
PRM
UCR1
UCR2
ST
—
UART receiver pin
PE5
PEPU
ST
STCK1
PRM
STM1C0
ST
TX
PRM
UCR1
UCR2
—
CMOS UART transmitter pin
CMOS General purpose I/O. Register enabled pull-high.
—
STM1 clock input
PE6
PEPU
ST
CMOS General purpose I/O. Register enabled pull-high.
SCS
SIMC0
ST
CMOS SPI slave select pin
PE7
PEPU
ST
CMOS General purpose I/O. Register enabled pull-high.
STCK1
PRM
STM1C0
ST
—
STM1 clock input
PF0
PFPU
ST
CMOS General purpose I/O. Register enabled pull-high.
SCK
SIMC0
ST
CMOS SPI serial clock
SCL
SIMC0
ST
CMOS I2C clock line
12
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Pin Name
PF1/INT0/AN6
PF2/[INT0]
PF3~PF5
Function
OPT
I/T
PF1
PFPU
ST
INT0
PRM
INTEG
ST
AN6
ACERL
AN
PF2
PFPU
ST
INT0
PRM
INTEG
ST
O/T
Description
CMOS General purpose I/O. Register enabled pull-high.
—
External interrupt input 0
—
A/D Converter input channel 6
CMOS General purpose I/O. Register enabled pull-high.
—
External interrupt input 0
PF3~PF5
PFPU
ST
VDD
VDD
—
PWR
CMOS General purpose I/O. Register enabled pull-high.
—
Power Supply
VSS
VSS
—
PWR
—
Ground
Note: I/T: Input type
O/T: Output type
OPT: Optional by configuration option (CO) or register option
PWR: Power
CO: Configuration option
ST: Schmitt Trigger input
CMOS: CMOS output
AN: Analog signal pin
HXT: High frequency crystal oscillator
LXT: Low frequency crystal oscillator
As the Pin Description Summary table applies to the package type with the most pins, not all of the above
listed pins may be present on package types with smaller numbers of pins.
Absolute Maximum Ratings
Supply Voltage..................................................................................................... VSS-0.3V to VSS+6.0V
Input Voltage....................................................................................................... VSS-0.3V to VDD+0.3V
Storage Temperature........................................................................................................-50°C to 125°C
Operating Temperature.....................................................................................................-40°C to 85°C
IOL Total......................................................................................................................................... 80mA
IOH Total........................................................................................................................................-80mA
Total Power Dissipation............................................................................................................. 500mW
Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute
Maximum Ratings” may cause substantial damage to the device. Functional operation of this
device at other conditions beyond those listed in the specification is not implied and prolonged
exposure to extreme conditions may affect device reliability.
Rev. 1.00
13
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
D.C. Characteristics
Ta=25°C
Symbol
Parameter
Operating Voltage (HXT)
Test Conditions
—
VDD
Operating Voltage (HIRC)
—
Typ.
Max.
Unit
fSYS=fHXT=8MHz
2.2
—
5.5
V
fSYS=fHXT=12MHz
2.7
—
5.5
V
fSYS=fHXT=16MHz
4.5
—
5.5
V
fSYS=fHXT=20MHz
4.5
—
5.5
V
fSYS=fHIRC=8MHz
2.2
—
5.5
V
fSYS=fHIRC=12MHz
2.7
—
5.5
V
fSYS=fHIRC=16MHz
4.5
—
5.5
V
V
Conditions
Operating Voltage (LXT)
—
fSYS=fLXT=32.768kHz
2.2
—
5.5
Operating Voltage (LIRC)
—
fSYS=fLIRC=32kHz
2.2
—
5.5
V
3V
No load, all peripherals off,
fSYS=fHXT=8MHz
—
1.0
1.5
mA
—
2.0
3.0
mA
No load, all peripherals off,
fSYS=fHXT=12MHz
—
1.5
2.75
mA
—
3.0
4.5
mA
5V
No load, all peripherals off,
fSYS=fHXT=16MHz
—
4.5
7.0
mA
5V
No load, all peripherals off,
fSYS=fHXT=20MHz
—
5.5
8.5
mA
No load, all peripherals off,
fSYS=fHIRC=8MHz
—
0.8
1.2
mA
—
1.6
2.4
mA
No load, all peripherals off,
fSYS=fHIRC=12MHz
—
1.2
1.8
mA
—
2.4
3.6
mA
—
4.5
7.0
mA
No load, all peripherals off,
fSYS=fLXT=32768Hz
—
10
20
μA
—
30
50
μA
No load, all peripherals off,
fSYS=fLIRC=32KHz
—
10
20
μA
—
30
50
μA
5V
3V
Operating Current (HXT)
5V
3V
IDD
5V
Operating Current (HIRC)
3V
5V
5V
Operating Current (LXT)
Operating Current (LIRC)
Rev. 1.00
Min.
VDD
3V
5V
3V
5V
No load, all peripherals off,
fSYS=fHIRC=16MHz
14
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
No load, all peripherals off,
WDT off
—
—
1
μA
—
—
2
μA
No load, all peripherals off,
WDT on
—
—
3
μA
—
—
5
μA
No load, all peripherals off,
fSUB on
—
3
5
μA
—
5
10
μA
No load, all peripherals off,
fSUB on, fSYS=fHIRC=8MHz
—
0.8
1.6
mA
—
1.0
2.0
mA
No load, all peripherals off,
fSUB on, fSYS=fHIRC=12MHz
—
1.2
2.4
mA
—
1.5
3.0
mA
—
2.0
4.0
mA
No load, all peripherals off,
fSUB on, fSYS=fHXT=8MHz
—
0.5
1.0
mA
—
1.0
2.0
mA
No load, all peripherals off,
fSUB on, fSYS=fHXT=12MHz
—
0.6
1.2
mA
—
1.2
2.4
mA
5V
No load, all peripherals off,
fSUB on, fSYS=fHXT=16MHz
—
2.0
4.0
mA
5V
No load, all peripherals off,
fSUB on, fSYS=fHXT=20MHz
—
2.5
5.0
mA
—
LVR enable,
voltage select 2.1V
-5%
2.1
+5%
—
LVR enable,
voltage select 2.55V
-5%
2.55
+5%
—
LVR enable,
voltage select 3.15V
-5%
3.15
+5%
—
LVR enable,
voltage select 3.8V
-5%
3.8
+5%
—
LVD enable,
voltage select 2.0V
-5%
2.0
+5%
—
LVD enable,
voltage select 2.2V
-5%
2.2
+5%
—
LVD enable,
voltage select 2.4V
-5%
2.4
+5%
—
LVD enable,
voltage select 2.7V
-5%
2.7
+5%
—
LVD enable,
voltage select 3.0V
-5%
3.0
+5%
—
LVD enable,
voltage select 3.3V
-5%
3.3
+5%
—
LVD enable,
voltage select 3.6V
-5%
3.6
+5%
—
LVD enable,
voltage select 4.0V
-5%
4.0
+5%
VDD
Conditions
Standby Current
(SLEEP0 Mode)
3V
Standby Current
(SLEEP1 Mode)
3V
Standby Current
(IDLE0 Mode)
3V
5V
5V
5V
3V
5V
ISTB
Standby Current
(IDLE1 Mode, HIRC)
3V
5V
5V
3V
5V
3V
Standby Current
(IDLE1 Mode, HXT)
VLVR
VLVD
5V
Low Voltage Reset Voltage
Low Voltage Detection Voltage
Rev. 1.00
No load, all peripherals off,
fSUB on, fSYS=fHIRC=16MHz
15
V
V
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Symbol
Parameter
Test Conditions
VDD
Conditions
Typ.
Max.
Unit
VBG
Bandgap Reference Voltage
—
-3%
1.04
+3%
V
ILVR
Additional current for LVR Enable
—
LVD disable, VBGEN=0
—
20
25
μA
ILVD
Additional current for LVD Enable
—
LVR disable, VBGEN=0
VIL
VIH
IOL
IOH
RPH
IBIAS
VSCOM
Rev. 1.00
Input Low Voltage for I/O Ports
Input High Voltage for I/O Ports
I/O Port Sink Current
—
20
25
μA
5V
—
0
—
1.5
V
—
—
0
—
0.2VDD
V
5V
—
3.5
—
5
V
—
0.8VDD
—
VDD
V
3V
—
VOL=0.1VDD
16
31
—
mA
5V
VOL=0.1VDD
32
62
—
mA
3V
VOH=0.9VDD
Source current=Level 0
-0.67
-1.33
—
mA
5V
VOH=0.9VDD
Source current=Level 0
-1.5
-3.0
—
mA
3V
VOH=0.9VDD
Source current=Level 1
-1.0
-2.0
—
mA
5V
VOH=0.9VDD
Source current=Level 1
-2.0
-4.0
—
mA
3V
VOH=0.9VDD
Source current=Level 2
-1.34
-2.67
—
mA
5V
VOH=0.9VDD
Source current=Level 2
-3.5
-7.0
—
mA
3V
VOH=0.9VDD
Source current=Level 3
-4.0
-7.0
—
mA
5V
VOH=0.9VDD
Source current=Level 3
-7.0
-14.0
—
mA
I/O Port, Source Current
Pull-high Resistance for I/O Ports
VDD/2 Bias Current for LCD
—
Min.
3V
—
20
60
100
kΩ
5V
—
10
30
50
kΩ
5V
ISEL[1:0]=00B
17.5
25
32.5
μA
5V
ISEL[1:0]=01B
35
50
65
μA
5V
ISEL[1:0]=10B
70
100
130
μA
5V
ISEL[1:0]=11B
140
200
260
μA
2.2V~
VDD/2 Voltage for LCD COM Port
No load
5.5V
16
0.475VDD 0.5VDD 0.525VDD
V
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
A.C. Characteristics
Ta=25°C
Symbol
Parameter
Test Conditions
Min.
Typ.
2.2V~
fSYS=fHXT=8MHz
5.5V
—
8
—
MHz
2.7V~
fSYS=fHXT=12MHz
5.5V
—
12
—
MHz
4.5V~
fSYS=fHXT=20MHz
5.5V
—
20
—
MHz
2.2V~
fSYS=fHIRC=8MHz
5.5V
—
8
—
MHz
2.7V~
fSYS=fHIRC=12MHz
5.5V
—
12
—
MHz
4.5V~
fSYS=fHXT=16MHz
5.5V
—
16
—
MHz
System Clock (LXT)
2.2V~
fSYS=fLXT=32.768kHz
5.5V
—
32768
—
Hz
System Clock (LIRC)
2.2V~
fSYS=fLIRC=32kHz
5.5V
—
32
—
kHz
System Clock (HXT)
fSYS
System Clock (HIRC)
VDD
3V
fLIRC
Low Speed Internal RC Oscillator (LIRC)
Conditions
Max. Unit
Ta=25°C
-10%
32
+10% kHz
3V
Ta=-40°C~85°C
±0.3V
-40%
32
+40% kHz
2.2V~
Ta=-40°C~85°C
5.5V
-50%
32
+60% kHz
5V
Ta=25°C
-10%
32
+10% kHz
5V
Ta=-40°C~85°C
± 0.5V
-40%
32
+40% kHz
2.2V~
Ta=-40°C~85°C
5.5V
-50%
32
+60% kHz
tTC
xTCKn Input Pin Minimum Pulse Width
—
—
0.3
—
—
μs
tINT
External Interrupt Minimum Pulse Width
—
—
10
—
—
μs
—
—
25
50
100
ms
tRSTD
System Reset Delay Time
(POR Reset, LVR Hardware Reset, LVR
Software Reset, WDT Software Reset)
System Reset Delay Time
(WDT Time-out Hardware Cold Reset)
—
—
8.3
16.7
33.3
ms
System Start-up Timer Period
(wake-up from HALT, fSYS off at HALT)
tSST
tBGS
tLVDS
—
fSYS=fSUB=fLXT
128
—
—
tLXT
—
fSYS=fH~fH/64, fH=fHXT
128
—
—
tHXT
—
fSYS=fH~fH/64, fH=fHIRC
16
—
—
tHIRC
—
fSYS=fSUB=fLIRC
2
—
—
tLIRC
—
fSYS=fH~fH/64, fSYS=fHXT or fHIRC
2
—
—
tSYS
—
fSYS=fLXT or fLIRC
2
—
—
tSYS
System Start-up Timer Period
(WDT Time-out Hardware Cold Reset)
—
—
0
—
—
tH
VBG Turn On Stable Time
—
No load
—
—
150
us
—
For LVR enable,
VBGEN=0, LVD off → on
—
—
15
μs
—
For LVR disable,
VBGEN=0, LVD off → on
—
—
150
μs
System Start-up Timer Period
(wake-up from HALT, fSYS on at HALT State)
LVDO Stable Time
tLVR
Minimum Low Voltage Width to Reset
—
—
120
240
480
μs
tLVD
Minimum Low Voltage Width to Interrupt
—
—
60
120
240
μs
Rev. 1.00
17
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
HIRC Electrical Characteristics
Ta=25°C
Frequency Accuracy Trimmed 8MHz at VDD=3V
Symbol
Parameter
Test Conditions
VDD
3V
Conditions
Ta=25°C
Typ.
Max.
Unit
-2%
8
+2%
MHz
3V±0.3V
Ta=0°C~70°C
-5%
8
+5%
MHz
3V±0.3V
Ta=-40°C~85°C
-15%
8
+15%
MHz
-7%
8
+7%
MHz
-10%
8
+10%
MHz
High Speed Internal RC Oscillator
2.2V~5.5V Ta=0°C~70°C
(HIRC)
2.2V~5.5V Ta=-40°C~85°C
fHIRC
Min.
3V
Ta=25°C
-20%
12
+20%
MHz
3V
Ta=25°C
-20%
16
+20%
MHz
Min.
Typ.
Max.
Unit
- 2%
8
+2%
MHz
Frequency Accuracy Trimmed 8MHz at VDD=5V
Symbol
Parameter
Test Conditions
VDD
5V
Conditions
Ta=25°C
5V±0.5V
Ta=0°C~70°C
-5%
8
+5%
MHz
5V±0.5V
Ta=-40°C~85°C
-15%
8
+15%
MHz
-7%
8
+7%
MHz
-10%
8
+10%
MHz
High Speed Internal RC Oscillator
2.2V~5.5V Ta=0°C~70°C
(HIRC)
2.2V~5.5V Ta=-40°C~85°C
fHIRC
5V
Ta=25°C
-20%
12
+20%
MHz
5V
Ta=25°C
-20%
16
+20%
MHz
Min.
Typ.
Max.
Unit
-2%
12
+2%
MHz
Frequency Accuracy Trimmed 12MHz at VDD=3V
Symbol
Parameter
Test Conditions
VDD
3V
High Speed Internal RC Oscillator
(HIRC)
fHIRC
Conditions
Ta=25°C
3V±0.3V
Ta=0°C~70°C
-5%
12
+5%
MHz
3V±0.3V
Ta=-40°C~85°C
-15%
12
+15%
MHz
2.2V~5.5V Ta=0°C~70°C
-7%
12
+7%
MHz
2.2V~5.5V Ta=-40°C~85°C
-10%
12
+10%
MHz
3V
Ta=25°C
-20%
8
+20%
MHz
3V
Ta=25°C
-20%
16
+20%
MHz
Min.
Typ.
Max.
Unit
-2%
12
+2%
MHz
Frequency Accuracy Trimmed 12MHz at VDD=5V
Symbol
Parameter
Test Conditions
VDD
5V
fHIRC
Rev. 1.00
Conditions
Ta=25°C
5V±0.5V
Ta=0°C~70°C
-5%
12
+5%
MHz
5V±0.5V
Ta=-40°C~85°C
-15%
12
+15%
MHz
-7%
12
+7%
MHz
-10%
12
+10%
MHz
High Speed Internal RC Oscillator
2.2V~5.5V Ta=0°C~70°C
(HIRC)
2.2V~5.5V Ta=-40°C~85°C
5V
Ta=25°C
-20%
8
+20%
MHz
5V
Ta=25°C
-20%
16
+20%
MHz
18
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Frequency Accuracy Trimmed 16MHz at VDD=5V
Symbol
Test Conditions
Parameter
Min.
Typ.
Max.
Unit
Ta=25°C
-2%
16
+2%
MHz
Ta=0°C~70°C
-5%
16
+5%
MHz
-15%
16
+15%
MHz
-7%
16
+7%
MHz
-10%
16
+10%
MHz
VDD
5V
5V±0.5V
Conditions
5V ± 0.5V Ta=-40°C~85°C
fHIRC
High Speed Internal RC Oscillator
2.2V~5.5V Ta=0°C~70°C
(HIRC)
2.2V~5.5V Ta=-40°C~85°C
5V
Ta=25°C
-20%
8
+20%
MHz
5V
Ta=25°C
-20%
12
+20%
MHz
Note: 1. tSYS=1/fSYS
2.To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor should
be connected between VDD and VSS and located as close to the device as possible.
A/D Converter Electrical Characteristics
Ta=25°C
Symbol
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
VDD
Operating Voltage
—
—
2.7
—
5.5
V
VADI
Input Voltage
—
—
0
—
VREF
V
VREF
Reference Voltage
—
—
2
—
VDD
V
-3
—
+3
LSB
-4
—
+4
LSB
DNL
INL
Differential Nonlinearity
Integral Nonlinearity
3V
VREF=VDD, tADCK=0.5μs
5V
VREF=VDD, tADCK=0.5μs
3V
VREF=VDD, tADCK=10μs
5V
VREF=VDD, tADCK=10μs
3V
VREF=VDD, tADCK=0.5μs
5V
VREF=VDD, tADCK=0.5μs
3V
VREF=VDD, tADCK=10μs
5V
VREF=VDD, tADCK=10μs
3V
No load (tADCK=0.5μs)
—
1.0
2.0
mA
5V
No load (tADCK=0.5μs)
—
1.5
3.0
mA
IADC
Additional Current for ADC Enable
tADCK
Clock Period
—
—
0.5
—
10
μs
tON2ST
ADC on to ADC Start
—
—
4
—
—
μs
tADC
Conversion Time
(Include ADC Sample and Hold Time)
—
—
—
16
—
tADCK
Note: ADC conversion time (tADC)=n (bits ADC) + 4 (sampling time), the conversion for each bit needs one ADC
clock (tADCK).
Rev. 1.00
19
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Comparator Electrical Characteristics
Ta=25°C
Symbol
VDD
Test Conditions
Parameter
VDD
Conditions
Operating Voltage
Min.
Typ.
Max.
Unit
—
—
2.2
—
5.5
V
3V
—
—
37
56
μA
5V
—
—
130
200
μA
5V
—
-10
—
10
mV
ICMP
Additional Current for Comparator Enable
VOS
Input Offset Voltage
VCM
Common Mode Voltage Range
—
—
VSS
—
VDD-1.4
V
AOL
Open Loop Gain
5V
—
60
80
—
dB
VHYS
Hysteresis
5V
CHYEN =0
0
0
5
mV
CHYEN =1
tRP
Response Time
20
40
60
mV
3V With 100mV overdrive
—
370
560
ns
5V With 100mV overdrive
—
370
560
ns
Note: Measured with comparator one input pin at VCM=(VDD-1.4)/2 while the other pin input transition from VSS to
(VCM+100mV) or from VDD to (VCM-100mV).
Power on Reset Characteristics
Ta=25°C
Symbol
Test Conditions
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
VPOR
VDD Start Voltage to Ensure Power-on Reset
—
—
—
—
100
mV
RRPOR
VDD Raising Rate to Ensure Power-on Reset
—
—
0.035
—
—
V/ms
tPOR
Minimum Time for VDD Stays at VPOR to
Ensure Power-on Reset
—
—
1
—
—
ms
Rev. 1.00
20
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed
to their internal system architecture. The range of the device take advantage of the usual features
found within RISC microcontrollers providing increased speed of operation and enhanced
performance. The pipelining scheme is implemented in such a way that instruction fetching and
instruction execution are overlapped, hence instructions are effectively executed in one cycle, with
the exception of branch or call instructions or extended instructions. An 8-bit wide ALU is used in
practically all instruction set operations, which carries out arithmetic operations, logic operations,
rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving
data through the Accumulator and the ALU. Certain internal registers are implemented in the
Data Memory and can be directly or indirectly addressed. The simple addressing methods of these
registers along with additional architectural features ensure that a minimum of external components
is required to provide a functional I/O and A/D control system with maximum reliability and
flexibility. This makes the device suitable for low-cost, high-volume production for controller
applications.
Clocking and Pipelining
The main system clock, derived from either a HXT, LXT, HIRC or LIRC oscillator is subdivided
into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented
at the beginning of the T1 clock during which time a new instruction is fetched. The remaining
T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock
cycle forms one instruction cycle. Although the fetching and execution of instructions takes place
in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that
instructions are effectively executed in one instruction cycle except extended instructions. The
exception to this are instructions where the contents of the Program Counter are changed, such
as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to
execute.


   
   
System Clocking and Pipelining
Rev. 1.00
21
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
For instructions involving branches, such as jump or call instructions, two machine cycles are
required to complete instruction execution. An extra cycle is required as the program takes one
cycle to first obtain the actual jump or call address and then another cycle to actually execute the
branch. The requirement for this extra cycle should be taken into account by programmers in timing
sensitive applications.
  
    
 Instruction Fetching
Program Counter
During program execution, the Program Counter is used to keep track of the address of the
next instruction to be executed. It is automatically incremented by one each time an instruction
is executed except for instructions, such as “JMP” or “CALL” that demands a jump to a nonconsecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low
Register, are directly addressable by the application program.
When executing instructions requiring jumps to non-consecutive addresses such as a jump
instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control
by loading the required address into the Program Counter. For conditional skip instructions, once
the condition has been met, the next instruction, which has already been fetched during the present
instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is
obtained.
Program Counter
Program Counter High Byte
PCL Register
PC11~PC8
PCL7~PCL0
Program Counter
The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is
available for program control and is a readable and writeable register. By transferring data directly
into this register, a short program jump can be executed directly. However, as only this low byte
is available for manipulation, the jumps are limited to the present page of memory, that is 256
locations. When such program jumps are executed it should also be noted that a dummy cycle
will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is
needed to pre-fetch.
Rev. 1.00
22
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Stack
This is a special part of the memory which is used to save the contents of the Program Counter
only. The stack is organized into 8 levels and neither part of the data nor part of the program space,
and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is
neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of
the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value
from the stack. After a device reset, the Stack Pointer will point to the top of the stack.
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but
the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI,
the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use
the structure more easily. However, when the stack is full, a CALL subroutine instruction can still
be executed which will result in a stack overflow. Precautions should be taken to avoid such cases
which might cause unpredictable program branching.
If the stack is overflow, the first Program Counter save in the stack will be lost.
P�og�am Counte�
To� of Stack
Stack Leve� 1
Stack Leve� �
Stack
Pointe�
Stack Leve� 3
Bottom of Stack
Stack Leve� 8
:
:
:
P�og�am Memo�y
Arithmetic and Logic Unit – ALU
The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic
and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU
receives related instruction codes and performs the required arithmetic or logical operations after
which the result will be placed in the specified register. As these ALU calculation or operations may
result in carry, borrow or other status changes, the status register will be correspondingly updated to
reflect these changes. The ALU supports the following functions:
• Arithmetic operations:
ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA
LADD, LADDM, LADC, LADCM, LSUB, LSUBM, LSBC, LSBCM, LDAA
• Logic operations:
AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA
LAND, LOR, LXOR, LANDM, LORM, LXORM, LCPL, LCPLA
• Rotation:
RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC
LRRA, LRR, LRRCA, LRRC, LRLA, LRL, LRLCA, LRLC
• Increment and Decrement:
INCA, INC, DECA, DEC
LINCA, LINC, LDECA, LDEC
• Branch decision:
JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI
LSZ, LSZA, LSNZ, LSIZ, LSDZ, LSIZA, LSDZA
Rev. 1.00
23
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Flash Program Memory
The Program Memory is the location where the user code or program is stored. For this device the
Program Memory is Flash type, which means it can be programmed and re-programmed a large
number of times, allowing the user the convenience of code modification on the same device. By
using the appropriate programming tools, the Flash device offer users the flexibility to conveniently
debug and develop their applications while also offering a means of field programming and
updating.
Structure
The Program Memory has a capacity of 4K×16 bits. The Program Memory is addressed by the
Program Counter and also contains data, table information and interrupt entries. Table data, which
can be setup in any location within the Program Memory, is addressed by a separate table pointer
register.
000H
Initia�isation Vecto�
004H
Inte��u�t Vecto�s
0�CH
030H
n00H
Look-u� Tab�e
nFFH
FFFH
16 bits
Program Memory Structure
Special Vectors
Within the Program Memory, certain locations are reserved for the reset and interrupts. The location
0000H is reserved for use by the device reset for program initialisation. After a device reset is
initiated, the program will jump to this location and begin execution.
Look-up Table
Any location within the Program Memory can be defined as a look-up table where programmers can
store fixed data. To use the look-up table, the table pointer must first be setup by placing the address
of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers
define the total address of the look-up table.
After setting up the table pointer, the table data can be retrieved from the Program Memory using
the “TABRD [m]” or “TABRDL [m]” instructions, respectively when the memory [m] is located in
sector 0. If the memory [m] is located in other sectors, the data can be retrieved from the program
memory using the corresponding extended table read instruction such as “LTABRD [m]” or
“LTABRDL [m]” respectively. When the instruction is executed, the lower order table byte from the
Program Memory will be transferred to the user defined Data Memory register [m] as specified in
the instruction. The higher order table data byte from the Program Memory will be transferred to the
TBLH special register. Any unused bits in this transferred higher order byte will be read as 0.
The accompanying diagram illustrates the addressing data flow of the look-up table.
Rev. 1.00
24
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
A d d re s s
L a s t p a g e o r
T B H P R e g is te r
T B L P R e g is te r
D a ta
1 6 b its
R e g is te r T B L H
U s e r S e le c te d
R e g is te r
H ig h B y te
L o w B y te
Table Program Example
The following example shows how the table pointer and table data is defined and retrieved from
the microcontroller. This example uses raw table data located in the Program Memory which is
stored there using the ORG statement. The value at this ORG statement is “0F00H” which refers to
the start address of the last page within the 4K Program Memory of the microcontroller. The table
pointer low byte register is setup here to have an initial value of “06H”. This will ensure that the first
data read from the data table will be at the Program Memory address “0F06H” or 6 locations after
the start of the last page. Note that the value for the table pointer is referenced to the first address of
the page that TBHP pointed if the “TABRD [m]” instruction is being used. The high byte of the table
data which in this case is equal to zero will be transferred to the TBLH register automatically when
the “TABRD [m]” instruction is executed.
Because the TBLH register is a read/write register and cannot be restored, care should be taken
to ensure its protection if both the main routine and Interrupt Service Routine use table read
instructions. If using the table read instructions, the Interrupt Service Routines may change the
value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read instructions should be avoided. However, in
situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the
execution of any main routine table-read instructions. Note that all table related instructions require
two instruction cycles to complete their operation.
Table Read Program Example
tempreg1 db
?; temporary register #1
tempreg2 db
?; temporary register #2
:
mov a, 06h ; initialise low table pointer - note that this address is
; referenced
mov tblp, a ; to the last page or the page that tbhp pointed
mov a, 0Fh; initialise high table pointer
mov tbhp, a
:
tabrd tempreg1 ; transfers value in table referenced by table pointer data at
; program memory address 0F06H transferred to tempreg1 and TBLH
dec tblp ; reduce value of table pointer by one
tabrd tempreg2 ; transfers value in table referenced by table pointer data at
; program memory address 0F05H transferred to tempreg2 and TBLH
; in this example the data 1AH is transferred to tempreg1 and
; data 0FH to register tempreg2
:
org 0F00h; sets initial address of program memory
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
Rev. 1.00
25
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
In Circuit Programming – ICP
The provision of Flash type Program Memory provides the user with a means of convenient and easy
upgrades and modifications to their programs on the same device. As an additional convenience,
Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface.
This provides manufacturers with the possibility of manufacturing their circuit boards complete with
a programmed or un-programmed microcontroller, and then programming or upgrading the program
at a later stage. This enables product manufacturers to easily keep their manufactured products
supplied with the latest program releases without removal and re-insertion of the device.
The Holtek Flash MCU to Writer Programming Pin correspondence table is as follows:
Holtek Writer Pins
MCU Programming Pins
Pin Description
ICPDA
PA0
Programming Serial Data/Address
ICPCK
PA2
Programming Clock
VDD
VDD
Power Supply
VSS
VSS
Ground
The Program Memory and EEPROM data Memory can both be programmed serially in-circuit using
this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional
line for the clock. Two additional lines are required for the power supply. The technical details
regarding the in-circuit programming of the device are beyond the scope of this document and will
be supplied in supplementary literature.
During the programming process, taking control of the ICPDA and ICPCK pins for data and clock
programming purposes. The user must there take care to ensure that no other outputs are connected
to these two pins.
W r ite r C o n n e c to r
S ig n a ls
M C U
P r o g r a m m in g
P in s
V D D
W r ite r _ V D D
IC P D A
P A 0
IC P C K
P A 2
W r ite r _ V S S
V S S
*
*
T o o th e r C ir c u it
Note: * may be resistor or capacitor. The resistance of * must be greater than 1kΩ or the capacitance
of * must be less than 1nF.
Rev. 1.00
26
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
On-Chip Debug Support – OCDS
There is an EV chip named HT66v0187 which is used to emulate the real MCU device named
HT66F0187. This EV chip device also provides an “On-Chip Debug” function to debug the device
during the development process. The EV chip and the actual MCU device are almost functionally
compatible except for the “On-Chip Debug” function. Users can use the EV chip device to emulate
the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the Holtek HTIDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the
OCDSCK pin is the OCDS clock input pin. When users use the EV chip for debugging, other
functions which are shared with the OCDSDA and OCDSCK pins in the actual MCU device will
have no effect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP
programming pins are still used as the Flash Memory programming pins for ICP. For a more detailed
OCDS description, refer to the corresponding document named “Holtek e-Link for 8-bit MCU
OCDS User’s Guide”.
Holtek e-Link Pins
EV Chip Pins
Pin Description
OCDSDA
OCDSDA
On-chip Debug Support Data/Address input/output
OCDSCK
OCDSCK
On-chip Debug Support Clock input
VDD
VDD
Power Supply
VSS
VSS
Ground
RAM Data Memory
The Data Memory is an 8-bit wide RAM internal memory and is the location where temporary
information is stored.
Divided into two types, the first of Data Memory is an area of RAM where special function registers
are located. These registers have fixed locations and are necessary for correct operation of the
device. Many of these registers can be read from and written to directly under program control,
however, some remain protected from user manipulation. The second area of Data Memory is
reserved for general purpose use. All locations within this area are read and write accessible under
program control.
Switching between the different Data Memory sectors is achieved by properly setting the Memory
Pointers to correct value.
Structure
The Data Memory is subdivided into two sectors, all of which are implemented in 8-bit wide
Memory. Each of the Data Memory sectors is categorized into two types, the Special Purpose Data
Memory and the General Purpose Data Memory.
The address range of the Special Purpose Data Memory for the device is from 00H to 7FH while the
address range of the General Purpose Data Memory is from 80H to FFH.
Special Purpose Data Memory
General Purpose Data Memory
Available Sectors
Capacity
Sectors
0, 1
256 × 8
0: 80H~FFH
1: 80H~FFH
Data Memory Summary
Rev. 1.00
27
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
00H
S�ecia� Pu��ose
Data Memo�y
40H
�FH
80H
Gene�a� Pu��ose
Data Memo�y
Secto� 0
Secto� 1
FFH
Data Memory Structure
Data Memory Addressing
For this device that supports the extended instructions, there is no Bank Pointer for Data Memory.
or Data Memory the desired Sector is pointed by the MP1H or MP2H register and the certain Data
Memory address in the selected sector is specified by the MP1L or MP2L register when using
indirect addressing access.
Direct Addressing can be used in all sectors using the corresponding instruction which can address
all available data memory space. For the accessed data memory which is located in any data
memory sectors except sector 0, the extended instructions can be used to access the data memory
instead of using the indirect addressing access. The main difference between standard instructions
and extended instructions is that the data memory address “m” in the extended instructions can be 9
bits, the high byte indicates a sector and the low byte indicates a specific address.
General Purpose Data Memory
All microcontroller programs require an area of read/write memory where temporary data can be
stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose
Data Memory. This area of Data Memory is fully accessible by the user programing for both reading
and writing operations. By using the bit operation instructions individual bits can be set or reset
under program control giving the user a large range of flexibility for bit manipulation in the Data
Memory.
Rev. 1.00
28
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Special Purpose Data Memory
This area of Data Memory is where registers, necessary for the correct operation of the
microcontroller, are stored. Most of the registers are both readable and writeable but some are
protected and are readable only, the details of which are located under the relevant Special Function
Register section. Note that for locations that are unused, any read instruction to these addresses will
return the value “00H”.
00H
01H
0�H
03H
04H
0�H
06H
0�H
08H
09H
0�H
0BH
0CH
0DH
0EH
0FH
10H
11H
1�H
13H
14H
1�H
16H
1�H
18H
19H
1�H
1BH
1CH
1DH
1EH
1FH
�0H
�1H
��H
�3H
�4H
��H
�6H
��H
�8H
�9H
��H
�BH
�CH
�DH
�EH
�FH
30H
31H
3�H
33H
34H
3�H
36H
Secto� 0� 1
I�R0
MP0
I�R1
MP1L
MP1H
�CC
PCL
TBLP
TBLH
TBHP
ST�TUS
I�R�
MP�L
MP�H
INTC1
INTC�
MFI0
MFI1
MFI�
P�
P�C
P�PU
P�WU
PRM
TMPC
WDTC
TBC
CTRL
LVRC
EE�
EED
S�DOL
S�DOH
S�DC0
S�DC1
S�DC�
PB
PBC
PBPU
STM1C0
STM1C1
STM1DL
STM1DH
STM1�L
STM1�H
STM1RP
STM0C0
STM0C1
STM0DL
STM0DH
STM0�L
STM0�H
STM0RP
PTMC0
3�H
38H
39H
3�H
3BH
3CH
3DH
3EH
3FH
40H
41H
4�H
43H
44H
4�H
46H
4�H
48H
49H
4�H
4BH
4CH
4DH
4EH
4FH
�0H
�1H
��H
�3H
�4H
��H
�6H
��H
�8H
�9H
��H
�BH
�CH
�DH
�EH
Secto� 0 Secto� 1
PTMC1
PTMDL
PTMDH
PTM�L
PTM�H
PTMRPL
PTMRPH
CPC
�CERL
EEC
PC
PCC
PCPU
PD
PDC
PDPU
PE
PEC
PEPU
PF
PFC
PFPU
SMOD
LVDC
INTEG
INTC0
SCOMC
SIMC0
SIMC1
SIMD
SIMC�/SIM�
SIMTOC
SLEDC0
SLEDC1
SLEDC�
USR
UCR1
UCR�
BRG
TXR_RXR
�FH
: Unused� �ead as 00H
Special Purpose Data Memory
Rev. 1.00
29
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Special Function Register Description
Most of the Special Function Register details will be described in the relevant functional sections;
however several registers require a separate description in this section.
Indirect Addressing Register – IAR0, IAR1, IAR2
The Indirect Addressing Registers, IAR0, IAR1 and IAR2, although having their locations in normal
RAM register space, do not actually physically exist as normal registers. The method of indirect
addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory
Pointers, in contrast to direct memory addressing, where the actual memory address is specified.
Actions on the IAR0, IAR1 and IAR2 registers will result in no actual read or write operation to
these registers but rather to the memory location specified by their corresponding Memory Pointers,
MP0, MP1L/MP1H or MP2L/MP2H. Acting as a pair, IAR0 and MP0 can together access data
only from Sector 0 while the IAR1 register together with MP1L/MP1H register pair and IAR2
register together with MP2L/MP2H register pair can access data from any Data Memory sector. As
the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing
Registers indirectly will return a result of “00H” and writing to the registers indirectly will result in
no operation.
Memory Pointers – MP0, MP1H/MP1L, MP2H/MP2L
Five Memory Pointers, known as MP0, MP1L, MP1H, MP2L and MP2H, are provided. These
Memory Pointers are physically implemented in the Data Memory and can be manipulated in the
same way as normal registers providing a convenient way with which to address and track data.
When any operation to the relevant Indirect Addressing Registers is carried out, the actual address
that the microcontroller is directed to is the address specified by the related Memory Pointer. MP0,
together with Indirect Addressing Register, IAR0, are used to access data from Sector 0, while
MP1L/MP1H together with IAR1 and MP2L/MP2H together with IAR2 are used to access data
from all data sectors according to the corresponding MP1H or MP2H register. Direct Addressing can
be used in all data sectors using the corresponding instruction which can address all available data
memory space.
The following example shows how to clear a section of four Data Memory locations already defined
as locations adres1 to adres4.
Rev. 1.00
30
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Indirect Addressing Program Example
Example 1
data.section ‘data’
adres1 db?
adres2 db?
adres3 db?
adres4 db?
block db?
code.section at 0 ‘code’
org 00h
start:
mov a, 04h;
mov block, a
mov a, offset adres1 ;
mov mp0, a ;
loop:
clr IAR0 ;
inc mp0;
sdz block ;
jmp loop
continue:
setup size of block
Accumulator loaded with first RAM address
setup memory pointer with first RAM address
clear the data at address defined by MP0
increment memory pointer
check if last memory location has been cleared
The important point to note here is that in the example shown above, no reference is made to specific
Data Memory addresses.
Example 2
data .section ‘data’
adres1 db?
adres2 db?
adres3 db?
adres4 db?
block db?
code .section at 0 ‘code’
org 00h
start:
mov a,04h ; setup size of block
mov block,a
mov a,01h ; setup the memory sector
mov mp1h,a
mov a,offset adres1 ; Accumulator loaded with first RAM address
mov mp1l,a ; setup memory pointer with first RAM address
loop:
clr IAR1 ; clear the data at address defined by MP1
inc mp1l ; increment memory pointer MP1L
sdz block ; check if last memory location has been cleared
jmp loop
continue:
:
The important point to note here is that in the example shown above, no reference is made to specific
RAM addresses.
Rev. 1.00
31
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Direct Addressing Program Example using extended instructions
data .section ‘data’
temp db ?
code .section at 0 ‘code ‘
org 00h
start:
lmov
a,[m]; move [m] data to acc
lsuba, [m+1] ; compare [m] and [m+1] data
snz
c; [m]>[m+1]?
jmp continue; no
lmova,[m] ; yes, exchange [m] and [m+1] data
movtemp,a
lmova,[m+1]
lmov[m],a
mova,temp
lmov[m+1],a
continue:
:
Note: Here “m” is a data memory address located in any data memory sectors. For example,
m=1F0H, it indicates address 0F0H in Sector 1.
Accumulator – ACC
The Accumulator is central to the operation of any microcontroller and is closely related with
operations carried out by the ALU. The Accumulator is the place where all intermediate results
from the ALU are stored. Without the Accumulator it would be necessary to write the result of
each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads. Data transfer operations usually involve
the temporary storage function of the Accumulator; for example, when transferring data between
one user defined register and another, it is necessary to do this by passing the data through the
Accumulator as no direct transfer between two registers is permitted.
Program Counter Low Register – PCL
To provide additional program control functions, the low byte of the Program Counter is made
accessible to programmers by locating it within the Special Purpose area of the Data Memory. By
manipulating this register, direct jumps to other program locations are easily implemented. Loading
a value directly into this PCL register will cause a jump to the specified Program Memory location,
however, as the register is only 8-bit wide, only jumps within the current Program Memory page are
permitted. When such operations are used, note that a dummy cycle will be inserted.
Look-up Table Registers – TBLP, TBHP, TBLH
These three special function registers are used to control operation of the look-up table which is
stored in the Program Memory. TBLP and TBHP are the table pointers and indicate the location
where the table data is located. Their value must be setup before any table read commands are
executed. Their value can be changed, for example using the “INC” or “DEC” instructions, allowing
for easy table data pointing and reading. TBLH is the location where the high order byte of the table
data is stored after a table read data instruction has been executed. Note that the lower order table
data byte is transferred to a user defined location.
Rev. 1.00
32
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Status Register – STATUS
This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), SC flag, CZ flag, power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/
logical operation and system management flags are used to record the status and operation of the
microcontroller.
With the exception of the TO and PDF flags, bits in the status register can be altered by instructions
like most other registers. Any data written into the status register will not change the TO or PDF flag.
In addition, operations related to the status register may give different results due to the different
instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or
by executing the “CLR WDT” or “HALT” instruction. The PDF flag is affected only by executing
the “HALT” or “CLR WDT” instruction or during a system power-up.
The Z, OV, AC, C, SC and CZ flags generally reflect the status of the latest operations.
• C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through
carry instruction.
• AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
• Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
• OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
• PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by
executing the “HALT” instruction.
• TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is
set by a WDT time-out.
• SC is the result of the “XOR” operation which is performed by the OV flag and the MSB of the
current instruction operation result.
• CZ is the operational result of different flags for different instuctions. Refer to register definitions
for more details.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will
not be pushed onto the stack automatically. If the contents of the status registers are important and if
the subroutine can corrupt the status register, precautions must be taken to correctly save it.
Rev. 1.00
33
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
STATUS Register
Bit
7
6
5
4
3
2
1
0
Name
SC
CZ
TO
PDF
OV
Z
AC
C
R/W
R
R
R
R
R/W
R/W
R/W
R/W
POR
x
x
0
0
x
x
x
x
“x”: unknown
Rev. 1.00
Bit 7
SC: The result of the “XOR” operation which is performed by the OV flag and the
MSB of the instruction operation result.
Bit 6
CZ: The the operational result of different flags for different instuctions.
For SUB/SUBM/LSUB/LSUBM instructions, the CZ flag is equal to the Z flag.
For SBC/SBCM/LSBC/LSBCM instructions, the CZ flag is the “AND” operation
result which is performed by the previous operation CZ flag and current operation zero
flag. For other instructions, the CZ flag willl not be affected.
Bit 5
TO: Watchdog Time-out flag
0: After power up or executing the “CLR WDT” or “HALT” instruction
1: A watchdog time-out occurred
Bit 4
PDF: Power down flag
0: After power up or executing the “CLR WDT” instruction
1: By executing the “HALT” instructin
Bit 3
OV: Overflow flag
0: No overflow
1: An operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa
Bit 2
Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
Bit 1
AC: Auxiliary flag
0: No auxiliary carry
1: An operation results in a carry out of the low nibbles, in addition, or no borrow
from the high nibble into the low nibble in substraction
Bit 0
C: Carry flag
0: No carry-out
1: An operation results in a carry during an addition operation or if a borrow does
not take place during a subtraction operation
The “C” flag is also affected by a rotate through carry instruction.
34
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
EEPROM Data memory
This device contains an area of internal EEPROM Data Memory. EEPROM, which stands for
Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form
of re-programmable memory, with data retention even when its power supply is removed. By
incorporating this kind of data memory, a whole new host of application possibilities are made
available to the designer. The availability of EEPROM storage allows information such as product
identification numbers, calibration values, specific user data, system setup data or other product
information to be stored directly within the product microcontroller. The process of reading and
writing data to the EEPROM memory has been reduced to a very trivial affair.
EEPROM Data Memory Structure
The EEPROM Data Memory capacity is 64×8 bits for the device. Unlike the Program Memory
and RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space
and is therefore not directly addressable in the same way as the other types of memory. Read and
Write operations to the EEPROM are carried out in single byte operations using an address and data
register in Sector 0 and a single control register in Sector 1.
Capacity
Address
64×8
00H~3FH
EEPROM Registers
Three registers control the overall operation of the internal EEPROM Data Memory. These are the
address register, EEA, the data register, EED and a single control register, EEC. As both the EEA
and EED registers are located in Sector 0, they can be directly accessed in the same was as any other
Special Function Register. The EEC register, however, being located in Sector 1, can be read from
or written to indirectly using the MP1H/MP1L or MP2H/MP12L Memory Pointer pair and Indirect
Addressing Register, IAR1 or IAR2. Because the EEC control register is located at address 40H
in Sector 1, the Memory Pointer low byte register, MP1L or MP2L, must first be set to the value
40H and the Memory Pointer high byte register, MP1H or MP2H, set to the value, 01H, before any
operations on the EEC register are executed.
Register
Name
Bit
7
6
5
4
3
2
1
0
D0
EEA
—
—
D5
D4
D3
D2
D1
EED
D7
D6
D5
D4
D3
D2
D1
D0
EEC
—
—
—
—
WREN
WR
RDEN
RD
2
1
0
EEPROM Registers List
EEA Register
Rev. 1.00
Bit
7
6
5
4
Name
—
—
D5
D4
D3
D2
D1
D0
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7~6
Unimplemented, read as “0”
Bit 5~0
D5~D0: Data EEPROM address
Data EEPROM address bit 5~bit 0
35
3
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
EED Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
D7~D0: Data EEPROM data
Data EEPROM data bit 7~bit 0
EEC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
WREN
WR
RDEN
RD
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 7~4
Unimplemented, read as “0”
Bit 3
WREN: Data EEPROM Write Enable
0: Disable
1: Enable
This is the Data EEPROM Write Enable Bit which must be set high before Data
EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM write operations.
Bit 2
WR: EEPROM Write Control
0: Write cycle has finished
1: Activate a write cycle
This is the Data EEPROM Write Control Bit and when set high by the application
program will activate a write cycle. This bit will be automatically reset to zero by the
hardware after the write cycle has finished. Setting this bit high will have no effect if
the WREN has not first been set high.
Bit 1
RDEN: Data EEPROM Read Enable
0: Disable
1: Enable
This is the Data EEPROM Read Enable Bit which must be set high before Data
EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM read operations.
Bit 0
RD: EEPROM Read Control
0: Read cycle has finished
1: Activate a read cycle
This is the Data EEPROM Read Control Bit and when set high by the application
program will activate a read cycle. This bit will be automatically reset to zero by the
hardware after the read cycle has finished. Setting this bit high will have no effect if
the RDEN has not first been set high.
Note: The WREN, WR, RDEN and RD cannot be set to “1” at the same time in one instruction. The
WR and RD cannot be set to “1” at the same time.
Rev. 1.00
36
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Reading Data from the EEPROM
To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set
high to enable the read function. The EEPROM address of the data to be read must then be placed
in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated.
Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When
the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can
be read from the EED register. The data will remain in the EED register until another read or write
operation is executed. The application program can poll the RD bit to determine when the data is
valid for reading.
Writing Data to the EEPROM
To write data to the EEPROM, the EEPROM address of the data to be written must first be placed
in the EEA register and the data placed in the EED register. Then the write enable bit, WREN,
in the EEC register must first be set high to enable the write function. After this, the WR bit in
the EEC register must be immediately set high to initiate a write cycle. These two instructions
must be executed consecutively. The global interrupt bit EMI should also first be cleared before
implementing any write operations, and then set again after the write cycle has started. Note that
setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the
EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to
microcontroller system clock, a certain time will elapse before the data will have been written into
the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the
WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates,
the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the
data has been written to the EEPROM. The application program can therefore poll the WR bit to
determine when the write cycle has ended.
Write Protection
Protection against inadvertent write operation is provided in several ways. After the device is
powered on, the Write Enable bit in the control register will be cleared preventing any write
operations. Also at power-on the Memory Pointer high byte registers, MP1H and MP2H, will be
reset to zero, which means that Data Memory Sector 0 will be selected. As the EEPROM control
register is located in Sector 1, this adds a further measure of protection against spurious write
operations. During normal program operation, ensuring that the Write Enable bit in the control
register is cleared will safeguard against incorrect write operations.
EEPROM Interrupt
The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM
interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. However, as
the EEPROM is contained within a Multi-function Interrupt, the associated multi-function interrupt
enable bit must also be set. When an EEPROM write cycle ends, the DEF request flag and its
associated multi-function interrupt request flag will both be set. If the global, EEPROM and Multifunction interrupts are enabled and the stack is not full, a jump to the associated Multi-function
Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag
will be automatically reset, the EEPROM interrupt flag must be manually reset by the application
program.
Rev. 1.00
37
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Programming Considerations
Care must be taken that data is not inadvertently written to the EEPROM. Protection can be
enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the
Memory Pointer high byte register could be normally cleared to zero as this would inhibit access to
Sector 1 where the EEPROM control register exist. Although certainly not necessary, consideration
might be given in the application program to the checking of the validity of new write data by a
simple read back process. When writing data the WR bit must be set high immediately after the
WREN bit has been set high, to ensure the write cycle executes correctly. The global interrupt bit
EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle
starts. Note that the device should not enter the IDLE or SLEEP mode until the EEPROM read or
write operation is totally complete. Otherwise, the EEPROM read or write operation will fail.
Programming Examples
Reading data from the EEPROM - polling method
MOV A, EEPROM_ADRES MOV EEA, A
MOV A, 040H MOV MP1L, A MOV A, 01H MOV MP1H, A
SET IAR1.1 SET IAR1.0
BACK:
SZ IAR1.0 JMP BACK
CLR IAR1 CLR MP1H
MOV A, EED
MOV READ_DATA, A
; user defined address
; setup memory pointer MP1L
; MP1L points to EEC register
; setup Memory Pointer high byte MP1H
; set RDEN bit, enable read operations
; start Read Cycle - set RD bit
; check for read cycle end
; disable EEPROM read/write
; move read data to register
Writing Data to the EEPROM - polling method
MOV A, EEPROM_ADRES
MOV EEA, A
MOV A, EEPROM_DATA MOV EED, A
MOV A, 040H MOV MP1L, A MOV A, 01H MOV MP1H, A
CLR EMI
SET IAR1.3
SET IAR1.2
SET EMI
BACK:
SZ IAR1.2 JMP BACK
CLR IAR1 CLR MP1H
Rev. 1.00
; user defined address
; user defined data
; setup memory pointer MP1L
; MP1L points to EEC register
; setup Memory Pointer high byte MP1H
; set WREN bit, enable write operations
; start Write Cycle - set WR bit
; check for write cycle end
; disable EEPROM read/write
38
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Oscillator
Various oscillator options offer the user a wide range of functions according to their various
application requirements. The flexible features of the oscillator functions ensure that the best
optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation
are selected through a combination of configuration options and relevant control registers.
Oscillator Overview
In addition to being the source of the main system clock the oscillators also provide clock sources
for the Watchdog Timer and Time Base Interrupts. External oscillators requiring some external
components as well as fully integrated internal oscillators, requiring no external components,
are provided to form a wide range of both fast and slow system oscillators. All oscillator options
are selected through the configuration options. The higher frequency oscillators provide higher
performance but carry with it the disadvantage of higher power requirements, while the opposite
is of course true for the lower frequency oscillators. With the capability of dynamically switching
between fast and slow system clock, the device has the flexibility to optimize the performance/
power ratio, a feature especially important in power sensitive portable applications.
Name
Freq.
Pins
External Crystal
Type
HXT
400kHz~20MHz
OSC1/OSC2
Internal High Speed RC
HIRC
8MHz/12MHz/16MHz
—
External Low Speed Crystal
LXT
32.768kHz
XT1/XT2
Internal Low Speed RC
LIRC
32kHz
—
Oscillator Types
System Clock Configurations
There are four methods of generating the system clock, two high speed oscillators and two low
speed oscillators. The high speed oscillators are the external crystal/ceramic oscillator - HXT and
the internal 8MHz, 12MHz, 16MHz, RC oscillator - HIRC. The two low speed oscillators are the
internal 32kHz RC oscillator - LIRC and the external 32.768kHz crystal oscillator - LXT. Selecting
whether the low or high speed oscillator is used as the system oscillator is implemented using the
HLCLK bit and CKS2~CKS0 bits in the SMOD register and as the system clock can be dynamically
selected.
The actual source clock used for each of the high speed and low speed oscillators is chosen via
configuration options. Note that two oscillator selections must be made namely one high speed and
one low speed system oscillators. It is not possible to choose a no-oscillator selection for either the
high or low speed oscillator. The OSC1 and OSC2 pins are used to connect the external components
for the external crystal.
Rev. 1.00
39
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
fH
High S�eed
Osci��ato�
fH/�
fH/4
HXT
fH/8
P�esca�e�
HIRC
fH
Low S�eed
Osci��ato�
High S�eed Osci��ato�
Configu�ation O�tion
fH/16
fSYS
fH/3�
fH/64
LXT
HLCLK�
CKS�~CKS0
fSUB
Fast Wake-u� f�om IDLE
o� SLEEP Mode Cont�o�
(fo� HXT on�y )
fSUB
LIRC
Low S�eed Osci��ato�
Configu�ation O�tion
System Clock Configurations
External Crystal/Ceramic Oscillator – HXT
The External Crystal/Ceramic System Oscillator is one of the high frequency oscillator choices,
which is selected via configuration option. For most crystal oscillator configurations, the simple
connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for
oscillation, without requiring external capacitors. However, for some crystal types and frequencies,
to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a
ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as
shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the
crystal or resonator manufacturer’s specification.
For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure
that the crystal and any associated resistors and capacitors along with interconnecting lines are all
located as close to the MCU as possible.
     Crystal/Resonator Oscillator – HXT
Rev. 1.00
40
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
HXT Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
12MHz
0pF
0pF
8MHz
0pF
0pF
4MHz
0pF
0pF
1MHz
100pF
100pF
Note: C1 and C2 values are for guidance only.
Crystal Recommended Capacitor Values
Internal RC Oscillator – HIRC
The internal RC oscillator is a fully integrated system oscillator requiring no external components.
The internal RC oscillator has three fixed frequencies of 8MHz, 12MHz, 16MHz. Device trimming
during the manufacturing process and the inclusion of internal frequency compensation circuits are
used to ensure that the influence of the power supply voltage, temperature and process variations on
the oscillation frequency are minimised. As a result, at a power supply of either 3V or 5V and at a
temperature of 25°C degrees, the fixed oscillation frequency of 8MHz, 12MHz or 16MHz. will have
a tolerance within 2%. Note that if this internal system clock option is selected, as it requires no
external pins for its operation, I/O pins are free for use as normal I/O pins.
External 32.768kHz Crystal Oscillator – LXT
The External 32.768kHz Crystal System Oscillator is one of the low frequency oscillator choices,
which is selected via configuration option. This clock source has a fixed frequency of 32.768kHz
and requires a 32.768kHz crystal to be connected between pins XT1 and XT2. The external resistor
and capacitor components connected to the 32.768kHz crystal are necessary to provide oscillation.
For applications where precise frequencies are essential, these components may be required to
provide frequency compensation due to different crystal manufacturing tolerances. During power-up
there is a time delay associated with the LXT oscillator waiting for it to start-up.
When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched off to stop
microcontroller activity and to conserve power. However, in many microcontroller applications
it may be necessary to keep the internal timers operational even when the microcontroller is in
the SLEEP or IDLE Mode. To do this, another clock, independent of the system clock, must be
provided.
However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary
to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should
be selected in consultation with the crystal or resonator manufacturer specification. The external
parallel feedback resistor, RP, is required.
Some configuration options determine if the XT1/XT2 pins are used for the LXT oscillator or as
normal I/O or other pin-shared functional pins.
• If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/
O or other pin-shared functional pins.
• If the LXT oscillator is used for any clock source, the 32.768kHz crystal should be connected to
the XT1/XT2 pins.
For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure
that the crystal and any associated resistors and capacitors along with interconnecting lines are all
located as close to the MCU as possible.
Rev. 1.00
41
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
‚   
­ €
  ‚  External LXT Oscillator
LXT Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
32.768kHz
10pF
10pF
Note: 1. C1 and C2 values are for guidance only.
2. RP=5MΩ~10MΩ is recommended.
32.768kHz Crystal Recommended Capacitor Values
LXT Oscillator Low Power Function
The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power
Mode. The mode selection is executed using the LXTLP bit in the TBC register.
LXTLP Bit
LXT Mode
0
1
Quick Start
Low-power
After power on, the LXTLP bit will be automatically cleared to zero ensuring that the LXT oscillator
is in the Quick Start operating mode. In the Quick Start Mode the LXT oscillator will power up
and stabilise quickly. However, after the LXT oscillator has fully powered up it can be placed
into the Low-power mode by setting the LXTLP bit high. The oscillator will continue to run but
with reduced current consumption, as the higher current consumption is only required during the
LXT oscillator start-up. In power sensitive applications, such as battery applications, where power
consumption must be kept to a minimum, it is therefore recommended that the application program
sets the LXTLP bit high about 2 seconds after power-on.
It should be noted that, no matter what condition the LXTLP bit is set to, the LXT oscillator will
always function normally, the only difference is that it will take more time to start up if in the Lowpower mode.
Internal 32kHz Oscillator – LIRC
The Internal 32kHz System Oscillator is one of the low frequency oscillator choices, which is
selected via configuration option. It is a fully integrated RC oscillator with a typical frequency of
32kHz at 5V, requiring no external components for its implementation. Device trimming during
the manufacturing process and the inclusion of internal frequency compensation circuits are used
to ensure that the influence of the power supply voltage, temperature and process variations on the
oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of
25°C degrees, the fixed oscillation frequency of 32kHz will have a tolerance within 10%.
Supplementary Oscillators
The low speed oscillators, in addition to providing a system clock source are also used to provide
a clock source to two other device functions. These are the Watchdog Timer and the Time Base
Interrupts.
Rev. 1.00
42
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Operating Modes and System Clocks
Present day applications require that their microcontrollers have high performance but often still
demand that they consume as little power as possible, conflicting requirements that are especially
true in battery powered portable applications. The fast clocks required for high performance will
by their nature increase current consumption and of course vice-versa, lower speed clocks reduce
current consumption. As Holtek has provided the device with both high and low speed clock sources
and the means to switch between them dynamically, the user can optimise the operation of their
microcontroller to achieve the best performance/power ratio.
System Clocks
The device has many different clock sources for both the CPU and peripheral function operation.
By providing the user with a wide range of clock options using configuration options and register
programming, a clock system can be configured to obtain maximum application performance.
The main system clock, can come from either a high frequency fH or low frequency fSUB source, and
is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system
clock can be sourced from either an HXT or HIRC oscillator, selected via a configuration option.
The low speed system clock source can be sourced from internal clock fSUB. If fSUB is selected then it
can be sourced by either the LXT or LIRC oscillator, selected via a configuration option. The other
choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64.
There are two additional internal clocks for the peripheral circuits, the substitute clock, fSUB, and
the Time Base clock, fTBC. Each of these internal clocks is sourced by either the LXT or LIRC
oscillators, selected via configuration options. The fSUB clock is used to provide a substitute clock for
the microcontroller just after a wake-up has occurred to enable faster wake-up times.
fH
High S�eed
Osci��ation
fH/�
fH/4
HXT
HIRC
fH/8
P�esca�e�
fH
fH/16
fSYS
fH/3�
fH/64
Low S�eed
Osci��ation
LXT
High S�eed Osci��ato�
Configu�ation O�tion
Fast Wake-u� f�om IDLE
o� SLEEP Mode Cont�o�
(fo� HXT on�y )
HLCLK�
CKS�~CKS0
fSUB
fSUB
LIRC
fSUB
Low S�eed Osci��ato�
Configu�ation O�tion
fSUB
IDLEN
WDT
fTBC
fTBC
fTB
fSYS/4
Time Base
TBCK
Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillation will
stop to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use.
Rev. 1.00
43
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
System Operation Modes
There are six different modes of operation for the microcontroller, each one with its own
special characteristics and which can be chosen according to the specific performance and
power requirements of the application. There are two modes allowing normal operation of the
microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0,
SLEEP1, IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to
conserve power.
Operating Mode
Description
CPU
fSYS
fSUB
fTBC
NORMAL Mode
on
fH~fH/64
on
on
SLOW Mode
on
fSUB
on
on
IDLE0 Mode
off
off
on
on
IDLE1 Mode
off
on
on
on
SLEEP0 Mode
off
off
off
off
SLEEP1 Mode
off
off
on
off
NORMAL Mode
As the name suggests this is one of the main operating modes where the microcontroller has all of
its functions operational and where the system clock is provided by one of the high speed oscillators.
This mode operates allowing the microcontroller to operate normally with a clock source will come
from one of the high speed oscillators, either the HXT or HIRC oscillators. The high speed oscillator
will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the
CKS2~CKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is used,
running the microcontroller at a divided clock ratio reduces the operating current.
SLOW Mode
This is also a mode where the microcontroller operates normally although now with a slower speed
clock source. The clock source used will be from one of the low speed oscillators, either the LXT
or the LIRC. Running the microcontroller in this mode allows it to run with much lower operating
currents. In the SLOW Mode, the fH is off.
SLEEP0 Mode
The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the
SMOD register is low. In the SLEEP0 mode the CPU will be stopped, and the fSUB clock will be
stopped too, and the Watchdog Timer function is disabled. In this mode, the LVDEN is must set to “0”.
If the LVDEN is set to “1”, it won’t enter the SLEEP0 Mode.
SLEEP1 Mode
The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the
SMOD register is low. In the SLEEP1 mode the CPU will be stopped. However the fSUB clock will
continue to operate if the Watchdog Timer function is enabled with its clock source coming from the
fSUB.
IDLE0 Mode
The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the
SMOD register is high and the FSYSON bit in the CTRL register is low. In the IDLE0 Mode the
system oscillator will be inhibited from driving the CPU but some peripheral functions will remain
operational such as the Watchdog Timer, TMs and SIM. In the IDLE0 Mode, the system oscillator
will be stopped.
Rev. 1.00
44
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
IDLE1 Mode
The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in
the SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode
the system oscillator will be inhibited from driving the CPU but may continue to provide a clock
source to keep some peripheral functions operational such as the Watchdog Timer, TMs and SIM. In
the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high
speed or low speed system oscillator.
Control Registers
A single register, SMOD, is used for overall control of the internal clocks within the device.
SMOD Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
CKS2
CKS1
CKS0
FSTEN
LTO
HTO
IDLEN
HLCLK
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
POR
0
0
0
0
0
0
1
1
Bit 7~5
CKS2~CKS0: The system clock selection when HLCLK is “0”
000: fSUB (fLXT or fLIRC)
001: fSUB (fLXT or fLIRC)
010: fH/64
011: fH/32
100: fH/16
101: fH/8
110: fH/4
111: fH/2
These three bits are used to select which clock is used as the system clock source. In
addition to the system clock source, which can be either the LXT or LIRC, a divided
version of the high speed system oscillator can also be chosen as the system clock
source.
Bit 4
FSTEN: Fast Wake-up Control (only for HXT)
0: Disable
1: Enable
This is the Fast Wake-up Control bit which determines if the fSUB clock source is
initially used after the device wakes up. When the bit is high, the fSUB clock source can
be used as a temporary system clock to provide a faster wake up time as the fSUB clock
is available.
Bit 3
LTO: Low speed system oscillator ready flag
0: Not ready
1: Ready
This is the low speed system oscillator ready flag which indicates when the low speed
system oscillator is stable after power on reset or a wake-up has occurred. The flag
will be low when in the SLEEP0 Mode but after a wake-up has occurred, the flag will
change to a high level after 128 clock cycles if the LXT oscillator is used and 1~2
clock cycles if the LIRC oscillator is used.
Bit 2
HTO: High speed system oscillator ready flag
0: Not ready
1: Ready
This is the high speed system oscillator ready flag which indicates when the high speed
system oscillator is stable. This flag is cleared to “0” by hardware when the device is
powered on and then changes to a high level after the high speed system oscillator is
stable.
45
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Therefore this flag will always be read as “1” by the application program after device
power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a wakeup has occurred, the flag will change to a high level after 512 clock cycles if the HXT
oscillator is used and after 15~16 clock cycles if the HIRC oscillator is used.
Bit 1
IDLEN: IDLE Mode control
0: Disable
1: Enable
This is the IDLE Mode Control bit and determines what happens when the HALT
instruction is executed. If this bit is high, when a HALT instruction is executed the
device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running
but the system clock will continue to keep the peripheral functions operational, if
FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop
in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT
instruction is executed.
Bit 0
HLCLK: system clock selection
0: fH/2~fH/64 or fSUB
1: fH
This bit is used to select if the fH clock or the fH/2~fH/64 or fSUB clock is used as
the system clock. When the bit is high the fH clock will be selected and if low the
fH/2~fH/64 or fSUB clock will be selected. When system clock switches from the fH
clock to the fSUB clock and the fH clock will be automatically switched off to conserve
power.
CTRL Register
Bit
7
6
5
4
3
2
1
0
Name
FSYSON
—
—
—
—
R/W
R/W
—
—
—
—
LVRF
LRF
WRF
R/W
R/W
POR
0
—
—
—
—
R/W
x
0
0
“x”: unknown
Bit 7
Rev. 1.00
FSYSON: fSYS Control in IDLE Mode
0: Disable
1: Enable
This bit is used to control whether the system clock is switched on or not in the IDLE
Mode. If this bit is set to “0”, the system clock will be switched off in the IDLE Mode.
However, the system clock will be switched on in the IDLE Mode when the FSYSON
bit is set to “1”.
Bit 6~3
Unimplemented, read as “0”
Bit 2
LVRF: LVR function reset flag
Described elsewhere.
Bit 1
LRF: LVR control register software reset flag
Described elsewhere.
Bit 0
WRF: WDT control register software reset flag
Described elsewhere.
46
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Fast Wake-up
To minimise power consumption the device can enter the SLEEP or IDLE0 Mode, where the system
clock source to the device will be stopped. However when the device is woken up again, it can take
a considerable time for the original system oscillator to restart, stabilise and allow normal operation
to resume. To ensure the device is up and running as fast as possible a Fast Wake-up function is
provided, which allows fSUB, namely either the LXT or LIRC oscillator, to act as a temporary clock
to first drive the system until the original system oscillator has stabilised. As the clock source for
the Fast Wake-up function is fSUB, the Fast Wake-up function is only available in the SLEEP1 and
IDLE0 modes. When the device is woken up from the SLEEP0 mode, the Fast Wake-up function has
no effect because the fSUB clock is stopped. The Fast Wake-up enable/disable function is controlled
using the FSTEN bit in the SMOD register.
If the HXT oscillator is selected as the NORMAL Mode system clock, and if the Fast Wake-up
function is enabled, then it will take one to two tSUB clock cycles of the LIRC or LXT oscillator for
the system to wake-up. The system will then initially run under the fSUB clock source until 512 HXT
clock cycles have elapsed, at which point the HTO flag will switch high and the system will switch
over to operating from the HXT oscillator.
If the HIRC oscillator or LIRC oscillator is used as the system oscillator then it will take 15~16
clock cycles of the HIRC or 1~2 cycles of the LIRC to wake up the system from the SLEEP or
IDLE0 Mode. The Fast Wake-up bit, FSTEN will have no effect in these cases.
System
Oscillator
FSTEN
Bit
0
Wake-up Time
(SLEEP0 Mode)
Wake-up Time
(SLEEP1 Mode)
Wake-up Time
(IDLE0 Mode)
Wake-up Time
(IDLE1 Mode)
128
128 HXT cycles
1~2 HXT cycles
1
128 HXT cycles
1~2 fSUB cycles
(System runs with fSUB first for 512 HXT cycles and
then switches over to run with the HXT clock)
1~2 HXT cycles
HIRC
x
15~16 HIRC cycles 15~16 HIRC cycles
1~2 HIRC cycles
LIRC
x
1~2 LIRC cycles
1~2 LIRC cycles
1~2 LIRC cycles
LXT
x
128 LXT cycles
128 LXT cycles
1~2 LXT cycles
HXT
“x”: don’t care
Wake-Up Times
Note that if the Watchdog Timer is disabled, which means that the LXT and LIRC are all both off,
then there will be no Fast Wake-up function available when the device wake-up from the SLEEP0
Mode.
Rev. 1.00
47
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Operating Mode Switching
The device can switch between operating modes dynamically allowing the user to select the best
performance/power ratio for the present task in hand. In this way microcontroller operations that
do not require high performance can be executed using slower clocks thus requiring less operating
current and prolonging battery life in portable applications.
In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed
using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the
NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When
a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is
determined by the condition of the IDLEN bit in the SMOD register and FSYSON bit in the CTRL
register.
When the HLCLK bit switches to a low level, which implies that clock source is switched from the
high speed clock source, fH, to the clock source, fH/2~fH/64 or fSUB. If the clock is from the fSUB, the
high speed clock source will stop running to conserve power. When this happens it must be noted
that the fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation
of other internal functions such as the TMs and SIM. The accompanying flowchart shows what
happens when the device moves between the various operating modes.
NORMAL
fSYS=fH~fH/64
fH on
CPU �un
fSYS on
fSUB on
fTBC on
SLOW
fSYS=fSUB
fSUB on
CPU �un
fSYS on
fH off
fTBC on
SLEEP0
H�LT inst�uction executed
CPU sto�
IDLEN=0
fSYS off
fSUB off
fTBC off
WDT & LVD off
IDLE0
H�LT inst�uction executed
CPU sto�
IDLEN=1
FSYSON=0
fSYS off
fSUB on
fTBC on
SLEEP1
H�LT inst�uction executed
CPU sto�
IDLEN=0
fSYS off
fSUB on
fTBC off
WDT on
Rev. 1.00
48
IDLE1
H�LT inst�uction executed
CPU sto�
IDLEN=1
FSYSON=1
fSYS on
fSUB on
fTBC on
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
NORMAL Mode to SLOW Mode Switching
When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore
consumes more power, the system clock can switch to run in the SLOW Mode by set the HLCLK bit
to “0” and set the CKS2~CKS0 bits to “000” or “001” in the SMOD register. This will then use the
low speed system oscillator which will consume less power. Users may decide to do this for certain
operations which do not require high performance and can subsequently reduce power consumption.
The SLOW Mode is sourced from the LXT or the LIRC oscillators and therefore requires these
oscillators to be stable before full mode switching occurs. This is monitored using the LTO bit in the
SMOD register.
NORMAL Mode
CKS�~CKS0 = 00xB &
HLCLK = 0
SLOW Mode
WDT and LVD a�e a�� off
IDLEN=0
H�LT inst�uction is executed
SLEEP0 Mode
WDT is on
IDLEN=0
H�LT inst�uction is executed
SLEEP1 Mode
IDLEN=1� FSYSON=0
H�LT inst�uction is executed
IDLE0 Mode
IDLEN=1� FSYSON=1
H�LT inst�uction is executed
IDLE1 Mode
Rev. 1.00
49
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
SLOW Mode to NORMAL Mode Switching
In SLOW Mode the system uses either the LXT or LIRC low speed system oscillator. To switch
back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should
be set to “1” or HLCLK bit is “0”, but CKS2~CKS0 is set to “010”, “011”, “100”, “101”, “110”
or “111”. As a certain amount of time will be required for the high frequency clock to stabilise,
the status of the HTO bit is checked. The amount of time required for high speed system oscillator
stabilization depends upon which high speed system oscillator type is used.
SLOW Mode
CKS2~CKS0 ≠ 000B or 001B
as HLCLK = 0 or HLCLK = 1
NORMAL Mode
WDT and LVD are all off
IDLEN=0
HALT instruction is executed
SLEEP0 Mode
WDT is on
IDLEN=0
HALT instruction is executed
SLEEP1 Mode
IDLEN=1, FSYSON=0
HALT instruction is executed
IDLE0 Mode
IDLEN=1, FSYSON=1
HALT instruction is executed
IDLE1 Mode
Entering the SLEEP0 Mode
There is only one way for the device to enter the SLEEP0 Mode and that is to execute the “HALT”
instruction in the application program with the IDLEN bit in SMOD register equal to “0” and the
WDT and LVD both off. When this instruction is executed under the conditions described above, the
following will occur:
• The system clock, WDT clock and Time Base clock will be stopped and the application program
will stop at the “HALT” instruction.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and stopped no matter if the WDT clock source orginates from the
LXT or LIRC oscillator.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Rev. 1.00
50
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Entering the SLEEP1 Mode
There is only one way for the device to enter the SLEEP1 Mode and that is to execute the “HALT”
instruction in the application program with the IDLEN bit in SMOD register equal to “0” and the
WDT on. When this instruction is executed under the conditions described above, the following will
occur:
• The system clock and Time Base clock will be stopped and the application program will stop at
the “HALT” instruction, but the WDT will remain with the clock source coming from the fSUB
clock.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT function is enabled.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the IDLE0 Mode
There is only one way for the device to enter the IDLE0 Mode and that is to execute the “HALT”
instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the
FSYSON bit in CTRL register equal to “0”. When this instruction is executed under the conditions
described above, the following will occur:
• The system clock will be stopped and the application program will stop at the “HALT”
instruction, but the Time Base clock and fSUB clock will be on.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT function is enabled.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the IDLE1 Mode
There is only one way for the device to enter the IDLE1 Mode and that is to execute the “HALT”
instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the
FSYSON bit in CTRL register equal to “1”. When this instruction is executed under the conditions
described above, the following will occur:
• The system clock, Time Base clock and fSUB clock will be on and the application program will
stop at the “HALT” instruction.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT function is enabled.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Rev. 1.00
51
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Standby Current Considerations
As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the
device to as low a value as possible, perhaps only in the order of several micro-amps except in the
IDLE1 Mode, there are other considerations which must also be taken into account by the circuit
designer if the power consumption is to be minimised. Special attention must be made to the I/O pins
on the device. All high-impedance input pins must be connected to either a fixed high or low level as
any floating input pins could create internal oscillations and result in increased current consumption.
This also applies to the device which has different package types, as there may be unbonded pins.
These must either be setup as outputs or if setup as inputs must have pull-high resistors connected.
Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs.
These should be placed in a condition in which minimum current is drawn or connected only to
external circuits that do not draw current, such as other CMOS inputs. Also note that additional
standby current will also be required if the configuration options have enabled the LXT or LIRC
oscillator.
In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system
oscillator, the additional standby current will also be perhaps in the order of several hundred microamps.
Wake-up
After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources
listed as follows:
• An external falling edge on Port A
• A system interrupt
• A WDT overflow
When the device executes the “HALT” instruction, the PDF flag will be set to 1. The PDF flag will
be cleared to 0 if the device experiences a system power-up or executes the clear Watchdog Timer
instruction. If the system is woken up by a WDT overflow, a Watchdog Timer reset will be initiated
and the TO flag will be set to 1. The TO flag is set if a WDT time-out occurs and causes a wake-up
that only resets the Program Counter and Stack Pointer, other flags remain in their original status.
Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin
to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at
the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then
two possible situations may occur. The first is where the related interrupt is disabled or the interrupt
is enabled but the stack is full, in which case the program will resume execution at the instruction
following the "HALT" instruction. In this situation, the interrupt which woke-up the device will not
be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled
or when a stack level becomes free. The other situation is where the related interrupt is enabled and
the stack is not full, in which case the regular interrupt response takes place. If an interrupt request
flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related
interrupt will be disabled.
Rev. 1.00
52
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Programming Considerations
The high speed and low speed oscillators both use the same SST counter. For example, if the system
is woken up from the SLEEP0 Mode and both the HIRC and LXT oscillators need to start-up from
an off state. The LXT oscillator uses the SST counter after HIRC oscillator has finished its SST
period.
• If the device is woken up from the SLEEP0 Mode to the NORMAL Mode, the high speed system
oscillator needs an SST period. The device will execute first instruction after HTO is “1”. At this
time, the LXT oscillator may not be stability if fSUB is from LXT oscillator. The same situation occurs
in the power-on state. The LXT oscillator is not ready yet when the first instruction is executed.
• If the device is woken up from the SLEEP1 Mode to NORMAL Mode, and the system clock
source is from HXT oscillator and FSTEN is “1”, the system clock can be switched to the LIRC
oscillator after wake up.
• There are peripheral functions, such as WDT, TMs and SIM, for which the fSYS is used. If the system
clock source is switched from fH to fSUB, the clock source to the peripheral functions mentioned
above will change accordingly.
• The on/off condition of fSUB depends upon whether the WDT is enabled or disabled as the WDT
clock source is selected from fSUB.
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to
unknown locations, due to certain uncontrollable external events such as electrical noise.
Watchdog Timer Clock Source
The Watchdog Timer clock source is provided by the internal clock, fSUB, which is in turn supplied
by the LIRC or LXT oscillator. The LXT oscillator is supplied by an external 32.768kHz crystal. The
LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it
should be noted that this specified internal clock period can vary with VDD, temperature and process
variations. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 218 to give longer
timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register.
Watchdog Timer Control Register
A single register, WDTC, controls the required timeout period as well as the enable/disable
operation. This register controls the overall operation of the Watchdog Timer.
Rev. 1.00
53
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
WDTC Register
Bit
7
6
5
4
3
2
1
0
Name
WE4
WE3
WE2
WE1
WE0
WS2
WS1
WS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
0
1
1
Bit 7~3
WE4~WE0: WDT function software control
10101: Disable
01010: Enable
Other: Reset MCU
When these bits are changed by the environmental noise or software setting to reset
the microcontroller, the reset operation will be activated after 2~3 LIRC clock cycles
and the WRF bit in the CTRL register will be set to 1.
Bit 2~0
WS2~WS0: WDT time-out period selection
000: 28/fSUB
001: 210/fSUB
010: 212/fSUB
011: 214/fSUB
100: 215/fSUB
101: 216/fSUB
110: 217/fSUB
111: 218/fSUB
CTRL Register
Bit
7
6
5
4
3
2
1
0
Name
FSYSON
—
—
—
—
R/W
R/W
—
—
—
—
LVRF
LRF
WRF
R/W
R/W
POR
0
—
—
—
—
R/W
x
0
0
“x”: unknown
Rev. 1.00
Bit 7
FSYSON: fSYS Control in IDLE Mode
Described elsewhere
Bit 6~3
Unimplemented, read as “0”
Bit 2
LVRF: LVR function reset flag
Described elsewhere
Bit 1
LRF: LVR Control register software reset flag
Described elsewhere
Bit 0
WRF: WDT Control register software reset flag
0: Not occur
1: Occurred
This bit is set to 1 by the WDT Control register software reset and cleared by the
application program. Note that this bit can only be cleared to 0 by the application
program.
54
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Watchdog Timer Operation
The Watchdog Timer operates by providing a device reset when its timer overflows. This means
that in the application program and during normal operation the user has to strategically clear the
Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is
done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps
to an unknown location, or enters an endless loop, these clear instructions will not be executed in the
correct manner, in which case the Watchdog Timer will overflow and reset the device. With regard to
the Watchdog Timer enable/disable function, there are five bits, WE4~WE0, in the WDTC register
to offer additional enable/disable and reset control of the Watchdog Timer. The WDT function
will be disabled when the WE4~WE0 bits are set to a value of 10101B. The WDT function will be
enabled if the WE4~WE0 bits value is equal to 01010B. If the WE4~WE0 bits are set to any other
values by the environmental noise or software setting, except 01010B and 10101B, it will reset the
device after 2~3 LIRC clock cycles. After power on these bits will have the value of 01010B.
WE4~WE0 Bits
WDT Function
10101B
Disable
01010B
Enable
Any other value
Reset MCU
Watchdog Timer Enable/Disable Control
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set
the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer
time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer.
The first is a WDT reset, which means a certain value except 01010B and 10101B written into the
WE4~WE0 bit filed, the second is using the Watchdog Timer software clear instructions and the
third is via a HALT instruction.
There is only one method of using software instruction to clear the Watchdog Timer. That is to use
the single “CLR WDT” instruction to clear the WDT.
The maximum time out period is when the 218 division ratio is selected. As an example, with a
32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8
seconds for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration.
WDTC Registe�
WE4~WE0 bits
Reset MCU
CLR
“H�LT”Inst�uction
“CLR WDT”Inst�uction
LXT
LIRC
M
U
X
fSUB
Low S�eed Osci��ato�
Configu�ation o�tion
8-stage Divide�
fSUB/�8
WS�~WS0
WDT P�esca�e�
8-to-1 MUX
WDT Time-out
(�8/fSUB ~ �18/fSUB)
Watchdog Timer
Rev. 1.00
55
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set
to some predetermined condition irrespective of outside parameters. The most important reset
condition is after power is first applied to the microcontroller. In this case, internal circuitry will
ensure that the microcontroller, after a short delay, will be in a well-defined state and ready to
execute the first program instruction. After this power-on reset, certain important internal registers
will be set to defined states before the program commences. One of these registers is the Program
Counter, which will be reset to zero forcing the microcontroller to begin program execution from the
lowest Program Memory address.
Another type of reset is when the Watchdog Timer overflows and resets. All types of reset operations
result in different register conditions being setup. Another reset exists in the form of a Low Voltage
Reset, LVR, where a full reset, is implemented in situations where the power supply voltage falls
below a certain threshold.
Reset Functions
There are several ways in which a reset can occur, each of which will be described as follows.
Power-on Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied to
the microcontroller. As well as ensuring that the Program Memory begins execution from the first
memory address, a power-on reset also ensures that certain other registers are preset to known
conditions. All the I/O port and port control registers will power up in a high condition ensuring that
all I/O ports will be first set to inputs.
VDD
Powe�-on Reset
tRSTD
SST Time-out
Note: tRSTD is power-on delay with typical time=50 ms
Power-On Reset Timing Chart
Low Voltage Reset — LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of
the device. The LVR function is always enabled with a specific LVR voltage VLVR. If the supply
voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing
the battery, the LVR will automatically reset the device internally and the LVRF bit in the CTRL
register will also be set to 1. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range
between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. Electrical
Characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the
low supply voltage and will not perform a reset function. The actual VLVR value can be selected by
the LVS bits in the LVRC register. If the LVS7~LVS0 bits are changed to some certain values by the
environmental noise or software setting, the LVR will reset the device after 2~3 LIRC clock cycles.
When this happens, the LRF bit in the CTRL register will be set to 1. After power on the register
will have the value of 01010101B. Note that the LVR function will be automatically disabled when
the device enters the power down mode.
Rev. 1.00
56
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
LVR
tRSTD + tSST
Inte�na� Reset
Note: tRSTD is power-on delay with typical time=50 ms
Low Voltage Reset Timing Chart
• LVRC Register
Bit
7
6
5
4
3
2
1
0
Name
LVS7
LVS6
LVS5
LVS4
LVS3
LVS2
LVS1
LVS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
1
0
1
Bit 7~0
LVS7~LVS0: LVR voltage select
01010101: 2.1V(Default)
00110011: 2.55V
10011001: 3.15V
10101010: 3.8V
Other values: Generates a MCU reset – register is reset to POR value
When an actual low voltage condition occurs, as specified by one of the four defined
LVR voltage values above, an MCU reset will be generated. In this situation the
register contents will remain the same after such a reset occurs.
Any register value, other than the four defined LVR values above, will also result in
the generation of an MCU reset. The reset operation will be activated after 2~3 LIRC
clock cycles. However in this situation the register contents will be reset to the POR
value.
• CTRL Register
Bit
7
6
5
4
3
2
1
0
Name
FSYSON
—
—
—
—
LVRF
LRF
WRF
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
x
0
0
“x”: unknown
Bit 7
Rev. 1.00
FSYSON: fSYS Control in IDLE Mode
Described elsewhere
Bit 6~3
Unimplemented, read as "0"
Bit 2
LVRF: LVR function reset flag
0: Not occur
1: Occurred
This bit is set to 1 when a specific Low Voltage Reset situation condition occurs. This
bit can only be cleared to 0 by the application program.
Bit 1
LRF: LVR Control register software reset flag
0: Not occur
1: Occurred
This bit is set to 1 if the LVRC register contains any non-defined LVR voltage register
values. This in effect acts like a software-reset function. This bit can only be cleared to
0 by the application program.
Bit 0
WRF: WDT Control register software reset flag
Described elsewhere
57
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as the hardware LVR reset except
that the Watchdog time-out flag TO will be set to "1".
WDT Time-out
tRSTD + tSST
Inte�na� Reset
Note: tRSTD is power-on delay with typical time=16.7 ms
WDT Time-out Reset during Normal Operation Timing Chart
Watchdog Time-out Reset during SLEEP or IDLE Mode
The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds
of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack
Pointer will be cleared to “0” and the TO flag will be set to “1”. Refer to the A.C. Characteristics for
tSST details.
WDT Time-out
tSST
Inte�na� Reset
WDT Time-out Reset during SLEEP or IDLE Timing Chart
Reset Initial Conditions
The different types of reset described affect the reset flags in different ways. These flags, known
as PDF and TO are located in the status register and are controlled by various microcontroller
operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are
shown in the table:
TO
PDF
0
0
Power-on reset
Reset Conditions
u
u
LVR reset during Normal or SLOW Mode operation
1
u
WDT time-out reset during Normal or SLOW Mode operation
1
1
WDT time-out reset during IDLE or SLEEP Mode operation
“u” stands for unchanged
The following table indicates the way in which the various components of the microcontroller are
affected after a power-on reset occurs.
Item
Condition after Reset
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT, Time Base
Clear after reset, WDT begins counting
Timer Modules
Timer Modules will be turned off
Input/Output Ports
I/O ports will be setup as inputs
Stack Pointer
Stack Pointer will point to the top of the stack
The different kinds of resets all affect the internal registers of the microcontroller in different ways.
To ensure reliable continuation of normal program execution after a reset occurs, it is important to
know what condition the microcontroller is in after a particular reset occurs. The following table
describes how each type of reset affects each of the microcontroller internal registers. Note that
where more than one package type exists the table will reflect the situation for the larger package
type.
Rev. 1.00
58
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Register
IAR0
MP0
IAR1
MP1L
MP1H
ACC
PCL
TBLP
TBLH
TBHP
STATUS
IAR2
MP2L
MP2H
INTC1
INTC2
MFI0
MFI1
MFI2
PA
PAC
PAPU
PAWU
PRM
TMPC
WDTC
TBC
CTRL
LVRC
EEA
EED
SADOL (ADRFS=0)
SADOL (ADRFS=1)
SADOH (ADRFS=0)
SADOH (ADRFS=1)
SADC0
SADC1
SADC2
PB
PBC
PBPU
STM1C0
STM1C1
STM1DL
STM1DH
STM1AL
STM1AH
STM1RP
STM0C0
STM0C1
Rev. 1.00
Reset
LVR Reset
WDT Time-out
(Power On) (Normal Operation) (Normal Operation)
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xx00 xxxx
xxuu uuuu
xx1u uuuu
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
--00 --00
--00 --00
--00 --00
0000 0000
0000 0000
0000 0000
--00 --00
--00 --00
--00 --00
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
-000 0000
-000 0000
-000 0000
0--- -000
0--- -000
0--- -000
0 1 0 1 0 0 11
0 1 0 1 0 0 11
0 1 0 1 0 0 11
0 0 11 0 111
0 0 11 0 111
0 0 11 0 111
0--- -x00
0--- -000
0--- -000
0101 0101
0101 0101
0101 0101
--00 0000
--00 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx ---xxxx ---xxxx ---xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- xxxx
---- xxxx
---- xxxx
0000 -000
0000 -000
0000 -000
000- -000
000- -000
000- -000
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
0000 0000
0000 0000
0000 0000
0000 0--0000 0--0000 0--0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0--0000 0--0000 0--0000 0000
0000 0000
0000 0000
59
WDT Time-out
(HALT)*
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
u u 11 u u u u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu --uu
uuuu uuuu
--uu --uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
u--- -uuu
uuuu uuuu
uuuu uuuu
u--- -uuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu ---uuuu uuuu
uuuu uuuu
---- uuuu
uuuu -uuu
uuu- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u--uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u--uuuu uuuu
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Register
STM0DL
STM0DH
STM0AL
STM0AH
STM0RP
PTMC0
PTMC1
PTMDL
PTMDH
PTMAL
PTMAH
PTMRPL
PTMRPH
CPC
ACERL
PC
PCC
PCPU
PD
PDC
PDPU
PE
PEC
PEPU
PF
PFC
PFPU
SMOD
LVDC
INTEG
INTC0
SCOMC
SIMC0
SIMC1
SIMD
SIMA
SIMC2
SIMTOC
SLEDC0
SLEDC1
SLEDC2
USR
UCR1
UCR2
BRG
TXR_RXR
EEC
Reset
LVR Reset
WDT Time-out
(Power On) (Normal Operation) (Normal Operation)
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0--0000 0--0000 0--0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
---- --00
---- --00
---- --00
0000 0000
0000 0000
0000 0000
---- --00
---- --00
---- --00
0000 0000
0000 0000
0000 0000
---- --00
---- --00
---- --00
1000 0001
1000 0001
1000 0001
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
0000 0000
0000 0000
0000 0000
- - 11 1111
- - 11 1111
- - 11 1111
- - 11 1111
- - 11 1111
- - 11 1111
--00 0000
--00 0000
--00 0000
0 0 0 0 0 0 11
0 0 0 0 0 0 11
0 0 0 0 0 0 11
--00 -000
--00 -000
--00 -000
---- 0000
---- 0000
---- 0000
-000 0000
-000 0000
-000 0000
-000 0000
-000 0000
-000 0000
111 - 0 0 0 0
111 - 0 0 0 0
111 - 0 0 0 0
1000 0001
1000 0001
1000 0001
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000000 0000000 0000000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0101 0101
0101 0101
0101 0101
0101 0101
0101 0101
0101 0101
0101 0101
0101 0101
0101 0101
0 0 0 0 1 0 11
0 0 0 0 1 0 11
0 0 0 0 1 0 11
0000 00x0
0000 00x0
0000 00x0
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- 0000
---- 0000
---- 0000
WDT Time-out
(HALT)*
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u--uuuu uuuu
uuuu uuuu
---- --uu
uuuu uuuu
---- --uu
uuuu uuuu
---- --uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
uuuu uuuu
--uu -uuu
---- uuuu
-uuu uuuu
-uuu uuuu
uuu- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuuuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- uuuu
Note: “u” stands for unchanged
“x” stands for unknown
“-” stands for unimplemented
Rev. 1.00
60
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output
designation of every pin fully under user program control, pull-high selections for all ports and
wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a
wide range of application possibilities.
The device provides bidirectional input/output lines labeled with port names PA~PF. These I/O ports
are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose
Data Memory table. All of these I/O ports can be used for input and output operations. For input
operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge
of instruction “MOV A, [m]”, where m denotes the port address. For output operation, all the data is
latched and remains unchanged until the output latch is rewritten.
Bit
Register
Name
7
6
5
4
3
2
1
0
PA
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PAC
PAC7
PAC6
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
PAPU
PAPU7
PAPU6
PAPU5
PAPU4
PAPU3
PAPU2
PAPU1
PAPU0
PAWU
PAWU7
PAWU6
PAWU5
PAWU4
PAWU3
PAWU2
PAWU1
PAWU0
PB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PBC
PBC7
PBC6
PBC5
PBC4
PBC3
PBC2
PBC1
PBC0
PBPU
PBPU7
PBPU6
PBPU5
PBPU4
PBPU3
PBPU2
PBPU1
PBPU0
PC
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PCC
PCC7
PCC6
PCC5
PCC4
PCC3
PCC2
PCC1
PCC0
PCPU
PCPU
PCPU6
PCPU5
PCPU4
PCPU3
PCPU2
PCPU1
PCPU0
PD
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PDC
PDC7
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
PDPU
PDPU7
PDPU6
PDPU5
PDPU4
PDPU3
PDPU2
PDPU1
PDPU0
PE
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PEC
PEC7
PEC6
PEC5
PEC4
PEC3
PEC2
PEC1
PEC0
PEPU
PEPU7
PEPU6
PEPU5
PEPU4
PEPU3
PEPU2
PEPU1
PEPU0
PF
—
—
PF5
PF4
PF3
PF2
PF1
PF0
PFC
—
—
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
PFPU
—
—
PFPU5
PFPU4
PFPU3
PFPU2
PFPU1
PFPU0
I/O Registers List
“—”: Unimplemented, read as “0”
PAWUn: Port A Pin wake-up function control
0: Disable
1: Enable
PAPUn/PBPUn/PCPUn/PDPUn/PEPUn/PFPUn: I/O Pin pull-high function control
0: Disable
1: Enable
PAn/PBn/PCn/PDn/PEn/PFn: I/O Port Data bit
0: Data 0
1: Data 1
PACn/PBCn/PCCn/PDCn/PECn/PFCn: I/O Pin type selection
0: Output
1: Input
Rev. 1.00
61
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Pull-high Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the
use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when
configured as an input have the capability of being connected to an internal pull-high resistor. These
pull-high resistors are selected using registers PAPU~PFPU, and are implemented using weak
PMOS transistors.
Port A Wake-up
The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves
power, a feature that is important for battery and other low-power applications. Various methods
exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port
A pins from high to low. This function is especially suitable for applications that can be woken up
via external switches. Each pin on Port A can be selected individually to have this wake-up feature
using the PAWU register.
I/O Port Control Registers
Each I/O port has its own control register known as PAC~PFC, to control the input/output
configuration. With this control register, each CMOS output or input can be reconfigured
dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its
associated port control register. For the I/O pin to function as an input, the corresponding bit of the
control register must be written as a “1”. This will then allow the logic state of the input pin to be
directly read by instructions. When the corresponding bit of the control register is written as a “0”,
the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions
can still be used to read the output register. However, it should be noted that the program will in fact
only read the status of the output data latch and not the actual logic status of the output pin.
I/O Port Source Current Control
The device supports different source current driving capability for each I/O port. With the
corresponding selection register, SLEDC0, SLEDC1 and SLEDC2, each I/O port can support four
levels of the source current driving capability. Users should refer to the D.C. characteristics section
to select the desired source current for different applications.
Bit
Register
Name
7
6
5
4
3
2
1
0
SLEDC0
PBPS3
PBPS2
PBPS1
PBPS0
PAPS3
PAPS2
PAPS1
PAPS0
SLEDC1
PDPS3
PDPS2
PDPS1
PDPS0
PCPS3
PCPS2
PCPS1
PCPS0
SLEDC2
PFPS3
PFPS2
PFPS1
PFPS0
PEPS3
PEPS2
PEPS1
PEPS0
I/O Port Source Current Control Registers List
Rev. 1.00
62
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
SLEDC0 Register
Bit
7
6
5
4
3
2
1
0
Name
PBPS3
PBPS2
PBPS1
PBPS0
PAPS3
PAPS2
PAPS1
PAPS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
1
0
1
Bit 7~6
PBPS3~PBPS2: PB7~PB4 source current selection
00: Source current=Level 0 (min.)
01: Source current=Level 1
10: Source current=Level 2
11: Source current=Level 3 (max.)
Bit 5~4
PBPS1~PBPS0: PB3~PB0 source current selection
00: Source current=Level 0 (min.)
01: Source current=Level 1
10: Source current=Level 2
11: Source current=Level 3 (max.)
Bit 3~2
PAPS3~PAPS2: PA7~PA4 source current selection
00: Source current=Level 0 (min.)
01: Source current=Level 1
10: Source current=Level 2
11: Source current=Level 3 (max.)
Bit 1~0
PAPS1~PAPS0: PA3~PA0 source current selection
00: Source current=Level 0 (min.)
01: Source current=Level 1
10: Source current=Level 2
11: Source current=Level 3 (max.)
SLEDC1 Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
PDPS3
PDPS2
PDPS1
PDPS0
PCPS3
PCPS2
PCPS1
PCPS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
1
0
1
Bit 7~6
PDPS3~PDPS2: PD7~PD4 source current selection
00: Source current=Level 0 (min.)
01: Source current=Level 1
10: Source current=Level 2
11: Source current=Level 3 (max.)
Bit 5~4
PDPS1~PDPS0: PD3~PD0 source current selection
00: Source current=Level 0 (min.)
01: Source current=Level 1
10: Source current=Level 2
11: Source current=Level 3 (max.)
Bit 3~2
PCPS3~PCPS2: PC7~PC4 source current selection
00: Source current=Level 0 (min.)
01: Source current=Level 1
10: Source current=Level 2
11: Source current=Level 3 (max.)
Bit 1~0
PCPS1~PCPS0: PC3~PC0 source current selection
00: Source current=Level 0 (min.)
01: Source current=Level 1
10: Source current=Level 2
11: Source current=Level 3 (max.)
63
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
SLEDC2 Register
Bit
7
6
5
4
3
2
1
0
Name
PFPS3
PFPS2
PFPS1
PFPS0
PEPS3
PEPS2
PEPS1
PEPS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
1
0
1
Bit 7~6
PFPS3~PFPS2: PF5~PF4 source current selection
00: Source current=Level 0 (min.)
01: Source current=Level 1
10: Source current=Level 2
11: Source current=Level 3 (max.)
Bit 5~4
PFPS1~PFPS0: PF3~PF0 source current selection
00: Source current=Level 0 (min.)
01: Source current=Level 1
10: Source current=Level 2
11: Source current=Level 3 (max.)
Bit 3~2
PEPS3~PEPS2: PE7~PE4 source current selection
00: Source current=Level 0 (min.)
01: Source current=Level 1
10: Source current=Level 2
11: Source current=Level 3 (max.)
Bit 1~0
PEPS1~PEPS0: PE3~PE0 source current selection
00: Source current=Level 0 (min.)
01: Source current=Level 1
10: Source current=Level 2
11: Source current=Level 3 (max.)
Pin-remapping Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more
than one function. Limited numbers of pins can force serious design constraints on designers but
by supplying pins with multi-functions, many of these difficulties can be overcome. The way in
which the pin function of each pin is selected is different for each function and a priority order is
established where more than one pin function is selected simultaneously. Additionally there is a
register, PRM, to establish certain pin functions.
The limited number of supplied pins in a package can impose restrictions on the amount of functions
a certain device can contain. However by allowing the same pins to share several different functions
and providing a means of function selection, a wide range of different functions can be incorporated
into even relatively small package sizes. If the pin-shared pin function have multiple outputs
simultaneously, its pin names at the right side of the “/” sign can be used for higher priority.
Rev. 1.00
64
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
PRM Register
Bit
7
6
5
4
3
2
1
0
Name
—
PRMS6
PRMS5
PRMS4
PRMS3
PRMS2
PRMS1
PRMS0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7
Unimplemented, read as “0”
Bit 6
PRMS6: UART pin-remapping selection
0: TX on PB4, RX on PC3(default)
1: TX on PE5, RX on PE4
Bit 5
PRMS5: INT1 pin-remapping selection
0: INT1 on PD0(default)
1: INT1 on PD5
Bit 4
PRMS4: INT0 pin-remapping selection
0: INT0 on PF1 (default)
1: INT0 on PF2
Bit 3
PRMS3: STM1 pin-remapping selection
0: STP1 on PB5, STP1I on PB7, STCK1 on PE7(default)
1: STP1 on PE3, STP1I on PA7, STCK1 on PE5
Bit 2
PRMS2: PTM pin-remapping selection
0: PTP on PE2, PTPI on PB6, PTCK on PC3(default)
1: PTP on PD1, PTPI on PD4, PTCK on PD2
Bit 1
PRMS1: STM0 pin-remapping selection
0: STP0 on PC2, STP0I on PA5, STCK0 on PA6(default)
1: STP0 on PD3, STP0I on PD6, STCK0 on PE4
Bit 0
PRMS0: SCOM pin-remapping selection
0: SCOM3 on PC7, SCOM2 on PC6, SCOM1 on PC5, SCOM0 on PC4(default)
1: SCOM3 on PD3, SCOM2 on PD2, SCOM1 on PD1, SCOM0 on PD0
I/O Pin Structures
The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As
the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a
guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared
structures does not permit all types to be shown.
   
   Generic Input/Output Structure
Rev. 1.00
65
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
ƒ ­ €

€
‚
€
‚
€
­    
  
A/D Input/Output Structure
Programming Considerations
Within the user program, one of the first things to consider is port initialisation. After a reset, all of
the I/O data and port control registers will be set high. This means that all I/O pins will default to
an input state, the level of which depends on the other connected circuitry and whether pull-high
selections have been chosen. If the port control registers, PAC~PFC, are then programmed to setup
some pins as outputs, these output pins will have an initial high output value unless the associated
port data registers, PA~PF, are first programmed. Selecting which pins are inputs and which are
outputs can be achieved byte-wide by loading the correct values into the appropriate port control
register or by programming individual bits in the port control register using the “SET [m].i” and
“CLR [m].i” instructions. Note that when using these bit control instructions, a read-modify-write
operation takes place. The microcontroller must first read in the data on the entire port, modify it to
the required new bit values and then rewrite this data back to the output ports.
The power-on reset condition of the A/D converter control registers ensures that any A/D input
pins, which are always shared with other I/O functions, will be setup as analog inputs after a reset.
Although these pins will be configured as A/D inputs after a reset, the A/D converter will not be
switched on. It is therefore important to note that if it is required to use these pins as I/O digital
input pins or as other functions, the A/D converter control registers must be correctly programmed
to remove the A/D function. Note also that as the A/D channel is enabled, any internal pull-high
resistor connections will be removed.
Port A has the additional capability of providing wake-up functions. When the device is in the
SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high
to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this
function.
Rev. 1.00
66
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Timer Modules – TM
One of the most fundamental functions in any microcontroller device is the ability to control and
measure time. To implement time related functions each device includes several Timer Modules,
abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide
operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output
as well as being the functional unit for the generation of PWM signals. Each of the TMs has two
individual interrupts. The addition of input and output pins for each TM ensures that users are
provided with timing units with a wide and flexible range of features.
The common features of the different TM types are described here with more detailed information
provided in the individual Standard and Periodic TM sections.
Introduction
The device contains three TMs and each individual TM can be categorised as a certain type, namely
Standard Type TM or Periodic Type TM. Although similar in nature, the different TM types vary in
their feature complexity. The common features to the Standard and Periodic TMs will be described
in this section and the detailed operation regarding each of the TM types will be described in
separate sections. The main features and differences between the two types of TMs are summarised
in the accompanying table.
STM
PTM
Timer/Counter
Function
√
√
I/P Capture
√
√
Compare Match Output
√
√
PWM Channels
1
1
Single Pulse Output
1
1
Edge
Edge
Duty or Period
Duty or Period
PWM Alignment
PWM Adjustment Period & Duty
STM
PTM
16-bit STM0
16-bit STM1
10-bit PTM
TM Name/Type Reference
TM Operation
The two different types of TM offer a diverse range of functions, from simple timing operations
to PWM signal generation. The key to understanding how the TM operates is to see it in terms of
a free running counter whose value is then compared with the value of pre-programmed internal
comparators. When the free running counter has the same value as the pre-programmed comparator,
known as a compare match situation, a TM interrupt signal will be generated which can clear the
counter and perhaps also change the condition of the TM output pin. The internal TM counter is
driven by a user selectable clock source, which can be an internal clock or an external pin.
Rev. 1.00
67
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
TM Clock Source
The clock source which drives the main counter in each TM can originate from various sources. The
selection of the required clock source is implemented using the xTnCK2~xTnCK0 bits in the TM
control registers. The clock source can be a ratio of the system clock fSYS or the internal high clock
fH, the fSUB clock source or the external xTCKn pin. Note that setting these bits to the value 101 will
select a reserved clock input, in effect disconnecting the TM clock source. The xTCKn pin clock
source is used to allow an external signal to drive the TM as an external clock source or for event
counting.
TM Interrupts
The Standard Type and Periodic Type TMs each have two internal interrupts, one for each of the
internal comparator A or comparator P, which generate a TM interrupt when a compare match
condition occurs. When a TM interrupt is generated it can be used to clear the counter and also to
change the state of the TM output pin.
TM External Pins
Each of the TMs, irrespective of what type, has one TM input pin, with the label xTCKn. The
xTMn, xTCKn input pin is essentially a clock source for the xTMn and is selected using the
xTnCK2~xTnCK0 bits in the xTMnC0 register. This external TM input pin allows an external clock
source to drive the internal TM. The xTCKn input pin can be chosen to have either a rising or falling
active edge. The STCKn and PTCK pins are also used as the external trigger input pin in single
pulse output mode for the STMn and PTM respectively.
The other xTMn input pin, xTPnI, is the capture input whose active edge can be a rising edge, a
falling edge or both rising and falling edges and the active edge transition type is selected using the
xTnIO1~xTnIO0 bits in the xTMnC1 register respectively. There is another capture input, PTCK,
for PTM capture input mode, which can be used as the external trigger input source except the PTPI
pin.
The TMs each have one output pin with the label xTPn. When the TM is in the Compare Match
Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle
when a compare match situation occurs. The external xTPn output pin is also the pin where the
TM generates the PWM output waveform. The xTPn pin acts as an input when the TM is setup to
operate in the Capture Input Mode. As the xTPn pins are pin-shared with other functions, the xTPn
pin function is enabled or disabled according to the internal TM on/off control, operation mode and
output control settings. When the corresponding TM configuration selects the xTPn pin to be used as
an output pin, the associated pin will be setup as an external TM output pin. If the TM configuration
selects the xTPn pin to be setup as an input pin, the input signal supplied on the associated pin can
be derived from an external signal and other pin-shared output function. If the TM configuration
determines that the xTPn pin function is not used, the associated pin will be controlled by other
pin-shared functions. The details of the xTPn pin for each TM type and device are provided in the
accompanying table.
STM0
STM1
PTM
Register
STCK0
STP0I
STP0
STCK1
STP1I
STP1
PTCK
PTPI
PTP
TMPC
TM External Pins
Rev. 1.00
68
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
TM Input/Output Pin Control Registers
Selecting to have a TM input/output or whether to retain its other shared function is implemented
using the relevant pin-shared function selection registers, with the corresponding selection bits in
each pin-shared function register corresponding to a TM input/output pin. Configuring the selection
bits correctly will setup the corresponding pin as a TM input/output. The details of the pin-shared
function selection are described in the pin-shared function section.
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TMPC
CLOP
—
—
—
—
ST1CP
PT0CP
ST0CP
TM Pin Control Register
STM0 Pin Control
PC� Out�ut Function
0
1
PC�/STP0
0
Out�ut
STM0
1
ST0CP
PC�
Ca�tu�e In�ut
1
P��/STP0I
0
TCK In�ut
P�6/STCK0
STM0 Function Pin Control Block Diagram (PRMS1=0)
PD3 Out�ut Function
0
1
PD3/STP0
0
Out�ut
STM0
1
ST0CP
PD3
Ca�tu�e In�ut
1
PD6/STP0I
0
TCK In�ut
PE4/STCK0
STM0 Function Pin Control Block Diagram (PRMS1=1)
Rev. 1.00
69
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
STM1 Pin Control
PB� Out�ut Function
0
1
PB�/STP1
0
Out�ut
STM1
1
ST1CP
PB�
Ca�tu�e In�ut
1
PB�/STP1I
0
TCK In�ut
PE�/STCK1
STM1 Function Pin Control Block Diagram (PRMS3=0)
PE3 Out�ut Function
0
1
PE3/STP1
0
Out�ut
STM1
1
ST1CP
PE3
Ca�tu�e In�ut
1
P��/STP1I
0
TCK In�ut
PE�/STCK1
STM1 Function Pin Control Block Diagram (PRMS3=1)
Rev. 1.00
70
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
PTM0 Pin Control
PE� Out�ut Function
0
PE�/PTP0
1
0
Out�ut
1
PT0CP
PE�
PTM0
1
0
Ca�tu�e In�ut
PB6/PTP0I
0
1
PT0C�PTS
TCK In�ut
PC3/PTCK0
PTM0 Function Pin Control Block Diagram (PRMS2=0)
PD1 Out�ut Function
0
PD1/PTP0
1
0
Out�ut
1
PT0CP
PD1
PTM0
1
0
Ca�tu�e In�ut
PD4/PTP0I
0
1
PT0C�PTS
TCK In�ut
PD�/PTCK0
PTM0 Function Pin Control Block Diagram (PRMS2=1)
TMPC Register
Bit
7
6
5
4
3
2
1
0
Name
CLOP
—
—
—
—
ST1CP
PTCP
ST0CP
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
0
0
0
Bit 7
Rev. 1.00
CLOP: CLO pin control
0: Disable
1: Enable
Bit 6~3
Unimplemented, read as “0”
Bit 2
ST1CP: STP1 pin control
0: Disable
1: Enable
Bit 1
PTCP: PTP pin control
0: Disable
1: Enable
Bit 0
ST0CP: STP0 pin control
0: Disable
1: Enable
71
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Programming Considerations
The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, being either 10-bit
or 16-bit, all have a low and high byte structure. The high bytes can be directly accessed, but as
the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register
pairs must be carried out in a specific way. The important point to note is that data transfer to and
from the 8-bit buffer and its related low byte only takes place when a write or read operation to its
corresponding high byte is executed.
As the CCRA register and PTM CCRP registers are implemented in the way shown in the
following diagram and accessing the register is carried out in a specific way described above, it is
recommended to use the “MOV” instruction to access the CCRA or PTM CCRP low byte register,
named xTMnAL or PTMRPL, using the following access procedures. Accessing the CCRA or
PTM CCRP low byte register without following these access procedures will result in unpredictable
values.
TM Counte� Registe� (Read on�y)
xTMnDL
xTMnDH
8-bit Buffe�
xTMn�L
xTMn�H
TM CCR� Registe� (Read/W�ite)
PTMRPL
PTMRPH
PTM CCRP Registe� (Read/W�ite)
Data
Bus
The following steps show the read and write procedures:
• Writing Data to CCRA or PTM CCRP
♦♦
Step 1. Write data to Low Byte xTMnAL or PTMRPL
––Note that here data is only written to the 8-bit buffer.
♦♦
Step 2. Write data to High Byte xTMnAH or PTMRPH
––Here data is written directly to the high byte registers and simultaneously data is latched
from the 8-bit buffer to the Low Byte registers.
• Reading Data from the Counter Registers and CCRA or PTM CCRP
Rev. 1.00
♦♦
Step 1. Read data from the High Byte xTMnDH, xTMnAH or PTMRPH
––Here data is read directly from the High Byte registers and simultaneously data is latched
from the Low Byte register into the 8-bit buffer.
♦♦
Step 2. Read data from the Low Byte xTMnDL, xTMnAL or PTMRPL
––This step reads data from the 8-bit buffer.
72
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Standard Type TM – STM
The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/
Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can
also be controlled with two external input pin and can drive one external output pin.
STM core
STM Input Pin
STM Output Pin
16-bit STM (STM0, STM1)
STCK0,STP0I
STCK1,STP1I
STP0, STP1
Standard TM Operation
There is a 16-bit wide STM. At the core is a 16-bit count-up counter which is driven by a user
selectable internal or external clock source. There are also two internal comparators with the names,
Comparator A and Comparator P. These comparators will compare the value in the counter with
CCRP and CCRA registers. The CCRP comparator is 8-bit wide whose value is compared with the
highest 8 bits in the counter while the CCRA is the 16 bits and therefore compares all counter bits.
The only way of changing the value of the 16-bit counter using the application program, is to
clear the counter by changing the STnON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a STM interrupt signal will also usually be generated. The Standard
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control an output pin. All operating setup conditions are
selected using relevant internal registers.
CCRP
fSYS/4
fSYS
fH/16
fH/64
fSUB
fH/8
STCKn
000
001
010
011
100
101 STnON
110 STnP�U
111
STnCK�~STnCK0
8-bit Com�a�ato� P
Com�a�ato� P Match
b8~b1�
16-bit Count-u� Counte�
Counte� C�ea� 0
1
STnCCLR
b0~b1�
16-bit Com�a�ato� �
STMnPF Inte��u�t
STnOC
Com�a�ato� � Match
Out�ut
Cont�o�
Po�a�ity
Cont�o�
Pin
Cont�o�
STnM1� STnM0
STnIO1� STnIO0
STnPOL
STnCP
STPn
STMn�F Inte��u�t
STnIO1� STnIO0
Edge
Detecto�
CCR�
STPnI
Standard Type TM Block Digram (n=0 or 1)
Standard Type TM Register Description
Overall operation of the Standard TM is controlled using a series of registers. A read only register
pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store
the internal 16-bit CCRA value. There is also a read/write register used to store the internal 8-bit
CCRP value. The remaining two registers are control registers which setup the different operating
and control modes.
Rev. 1.00
73
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Bit
Register
Name
7
6
5
4
3
STMnC0
STnPAU
STnCK2
STnCK1
STnCK0
STnON
STMnC1
STnM1
STnM0
STnIO1
STnIO0
STnOC
2
1
0
—
—
—
STnPOL STnDPX STnCCLR
STMnDL
D7
D6
D5
D4
D3
D2
D1
D0
STMnDH
D15
D14
D13
D12
D11
D10
D9
D8
STMnAL
D7
D6
D5
D4
D3
D2
D1
D0
STMnAH
D15
D14
D13
D12
D11
D10
D9
D8
STMnRP
D7
D6
D5
D4
D3
D2
D1
D0
16-bit Standard TM Registers List (n=0 or 1)
STMnC0 Register (n=0 or 1)
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
STnPAU
STnCK2
STnCK1
STnCK0
STnON
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
POR
0
0
0
0
0
—
—
—
Bit 7
STnPAU: STMn Counter Pause Control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the STMn will remain powered
up and continue to consume power. The counter will retain its residual value when
this bit changes from low to high and resume counting from this value when the bit
changes to a low value again.
Bit 6~4
STnCK2~STnCK0: Select STMn Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fSUB
101: fH/8
110: STCKn rising edge clock
111: STCKn falling edge clock
These three bits are used to select the clock source for the STM. The external pin clock
source can be chosen to be active on the rising or falling edge. The clock source fSYS is
the system clock, while fH and fSUB are other internal clocks, the details of which can
be found in the oscillator section.
Bit 3
STnON: STMn Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the STM. Setting the bit high enables
the counter to run, clearing the bit disables the STM. Clearing this bit to zero will
stop the counter from counting and turn off the STM which will reduce its power
consumption. When the bit changes state from low to high the internal counter value
will be reset to zero, however when the bit changes from high to low, the internal
counter will retain its residual value. If the STM is in the Compare Match Output
Mode then the STM output pin will be reset to its initial condition, as specified by the
STnOC bit, when the STnON bit changes from low to high.
Bit 2~0
Unimplemented, read as “0”
74
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
STMnC1 Register (n=0 or 1)
Rev. 1.00
Bit
7
6
5
4
3
Name
STnM1
STnM0
STnIO1
STnIO0
STnOC
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
STnPOL STnDPX STnCCLR
Bit 7~6
STnM1~STnM0: Select STMn Operating Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the STM. To ensure reliable operation
the STM should be switched off before any changes are made to the STnM1 and
STnM0 bits. In the Timer/Counter Mode, the STM output pin control will be disabled.
Bit 5~4
STnIO1~STnIO0: Select STM external pin (STPn or STPnI) function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Mode/Single Pulse Output Mode
00: PWM Output inactive state
01: PWM Output active state
10: PWM output
11: Single pulse output
Capture Input Mode
00: Input capture at rising edge of STPnI
01: Input capture at falling edge of STPnI
10: Input capture at falling/rising edge of STPnI
11: Input capture disabled
Timer/Counter Mode
Unused
These two bits are used to determine how the STM output pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the STM is running.
In the Compare Match Output Mode, the STnIO1 and STnIO0 bits determine how the
STM output pin changes state when a compare match occurs from the Comparator A.
The STM output pin can be setup to switch high, switch low or to toggle its present
state when a compare match occurs from the Comparator A. When the bits are both
zero, then no change will take place on the output. The initial value of the STM output
pin should be setup using the STnOC bit in the STMnC1 register. Note that the output
level requested by the STnIO1 and STnIO0 bits must be different from the initial value
setup using the STnOC bit otherwise no change will occur on the STM output pin
when a compare match occurs. After the STM output pin changes state, it can be reset
to its initial level by changing the level of the STnON bit from low to high.
In the PWM Mode, the STnIO1 and STnIO0 bits determine how the STM output
pin changes state when a certain compare match condition occurs. The PWM output
function is modified by changing these two bits. It is necessary to only change the
values of the STnIO1 and STnIO0 bits only after the STM has been switched off.
Unpredictable PWM outputs will occur if the STnIO1 and STnIO0 bits are changed
when the STM is running.
75
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Rev. 1.00
Bit 3
STnOC: STPn Output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode/Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the STM output pin. Its operation depends upon
whether STM is being used in the Compare Match Output Mode or in the PWM
Mode/Single Pulse Output Mode. It has no effect if the STM is in the Timer/Counter
Mode. In the Compare Match Output Mode it determines the logic level of the STM
output pin before a compare match occurs. In the PWM Mode/Single Pulse Output
Mode it determines if the PWM signal is active high or active low.
Bit 2
STnPOL: STPn Output polarity Control
0: Non-invert
1: Invert
This bit controls the polarity of the STPn output pin. When the bit is set high the STM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the
STM is in the Timer/Counter Mode.
Bit 1
STnDPX: STMn PWM period/duty Control
0: CCRP - period; CCRA - duty
1: CCRP - duty; CCRA - period
This bit, determines which of the CCRA and CCRP registers are used for period and
duty control of the PWM waveform.
Bit 0
STnCCLR: Select STMn Counter clear condition
0: STMn Comparatror P match
1: STMn Comparatror A match
This bit is used to select the method which clears the counter. Remember that the
Standard TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the STnCCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The STnCCLR bit is not
used in the PWM Output, Single Pulse Output or Capture Input Mode.
76
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
STMnDL Register (n=0 or 1)
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
D7~D0: STMn Counter Low Byte Register bit 7~bit 0
STMn 16-bit Counter bit 7~bit 0
STMnDH Register (n=0 or 1)
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
D15~D8: STMn Counter High Byte Register bit 7~bit 0
STMn 16-bit Counter bit 15~bit 8
STMnAL Register (n=0 or 1)
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
D7~D0: STMn CCRA Low Byte Register bit 7~bit 0
STMn 16-bit CCRA bit 7~bit 0
STMnAH Register (n=0 or 1)
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
2
1
0
Bit 7~0
D15~D8: STMn CCRA High Byte Register bit 7~bit 0
STMn 16-bit CCRA bit 15~bit 8
STMnRP Register (n=0 or 1)
Bit
6
5
4
3
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
7
D7~D0: STMn CCRP 8-bit Register, compared with the STMn Counter bit 15~bit 8.
Comparator P Match Period
0: 65536 STMn clocks
1~255: 256×(1~255) STMn clocks
These eight bits are used to setup the value on the internal CCRP 8-bit register, which
are then compared with the internal counter’s highest eight bits. The result of this
comparison can be selected to clear the internal counter if the STnCCLR bit is set to
zero. Setting the STnCCLR bit to zero ensures that a compare match with the CCRP
values will reset the internal counter. As the CCRP bits are only compared with the
highest eight counter bits, the compare values exist in 256 clock cycle multiples.
Clearing all eight bits to zero is in effect allowing the counter to overflow at its
maximum value.
77
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Standard Type TM Operating Modes
The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the STnM1 and STnM0 bits in the STMnC1 register.
Compare Match Output Mode
To select this mode, bits STnM1 and STnM0 in the STMnC1 register, should be set to 00
respectively. In this mode once the counter is enabled and running it can be cleared by three
methods. These are a counter overflow, a compare match from Comparator A and a compare match
from Comparator P. When the STnCCLR bit is low, there are two ways in which the counter can be
cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all
zero which allows the counter to overflow. Here both STMnAF and STMnPF interrupt request flags
for Comparator A and Comparator P respectively, will both be generated.
If the STnCCLR bit in the STMnC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the STMnAF interrupt request flag will
be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore
when STnCCLR is high no STMnPF interrupt request flag will be generated. In the Compare Match
Output Mode, the CCRA cannot be set to “0”.
As the name of the mode suggests, after a comparison is made, the STM output pin, will change
state. The STM output pin condition however only changes state when a STMnAF interrupt request
flag is generated after a compare match occurs from Comparator A. The STMnPF interrupt request
flag, generated from a compare match occurs from Comparator P, will have no effect on the STM
output pin. The way in which the STM output pin changes state are determined by the condition of
the STnIO1 and STnIO0 bits in the STMnC1 register. The STM output pin can be selected using
the STnIO1 and STnIO0 bits to go high, to go low or to toggle from its present condition when a
compare match occurs from Comparator A. The initial condition of the STM output pin, which is
setup after the STnON bit changes from low to high, is setup using the STnOC bit. Note that if the
STnIO1 and STnIO0 bits are zero then no pin change will take place.
Rev. 1.00
78
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Counter Value
Counter overflow
CCRP=0
0xFFFF
STnCCLR = 0; STnM [1:0] = 00
CCRP > 0
Counter cleared by CCRP value
CCRP > 0
Counter
Restart
Resume
CCRP
Pause
CCRA
Stop
Time
STnON
STnPAU
STnPOL
CCRP Int.
flag STMnPF
CCRA Int.
flag STMnAF
STMn
O/P Pin
Output pin set to
initial Level Low
if STnOC=0
Output not affected by STMnAF
flag. Remains High until reset by
STnON bit
Output Toggle with
STMnAF flag
Here STnIO [1:0] = 11
Toggle Output select
Note STnIO [1:0] = 10
Active High Output select
Output Inverts
when STnPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode – STnCCLR=0
Note: 1. With STnCCLR=0 a Comparator P match will clear the counter
2. The STM output pin is controlled only by the STMnAF flag
3. The output pin is reset to its initial state by a STnON bit rising edge
4. n=0 or 1
Rev. 1.00
79
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Counter Value
STnCCLR = 1; STnM [1:0] = 00
CCRA = 0
Counter overflow
CCRA > 0 Counter cleared by CCRA value
0xFFFF
CCRA=0
Resume
CCRA
Pause
Stop
Counter Restart
CCRP
Time
STnON
STnPAU
STnPOL
No STMnAF flag
generated on
CCRA overflow
CCRA Int.
flag STMnAF
CCRP Int.
flag STMnPF
STMn
O/P Pin
STMnPF not
generated
Output pin set to
initial Level Low
if STnOC=0
Output does
not change
Output Toggle with
STMnAF flag
Here STnIO [1:0] = 11
Toggle Output select
Output not affected by
STMnAF flag. Remains High
until reset by STnON bit
Note STnIO [1:0] = 10
Active High Output select
Output Inverts
when STnPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode – STnCCLR=1
Note: 1. With STnCCLR=1 a Comparator A match will clear the counter
2. The STM output pin is controlled only by the STMnAF flag
3. The output pin is reset to its initial state by a STnON bit rising edge
4. A STMnPF flag is not generated when STnCCLR=1
5. n=0 or 1
Rev. 1.00
80
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Timer/Counter Mode
To select this mode, bits STnM1 and STnM0 in the STMnC1 register should be set to 11
respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output
Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the
STM output pin is not used. Therefore the above description and Timing Diagrams for the Compare
Match Output Mode can be used to understand its function. As the STM output pin is not used in
this mode, the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits STnM1 and STnM0 in the STMnC1 register should be set to 10 respectively
and also the STnIO1 and STnIO0 bits should be set to 10 respectively. The PWM function within
the STM is useful for applications which require functions such as motor control, heating control,
illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the
STM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS
values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the STnCCLR bit has no effect as the PWM
period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register
is used to clear the internal counter and thus control the PWM waveform frequency, while the other
one is used to control the duty cycle. Which register is used to control either frequency or duty cycle
is determined using the STnDPX bit in the STMnC1 register. The PWM waveform frequency and
duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The STnOC bit in the STMnC1 register is used
to select the required polarity of the PWM waveform while the two STnIO1 and STnIO0 bits are
used to enable the PWM output or to force the STM output pin to a fixed high or low level. The
STnPOL bit is used to reverse the polarity of the PWM output waveform.
• 16-bit STM, PWM Mode, Edge-aligned Mode, STnDPX=0
CCRP
1~255
0
Period
CCRP×256
65536
Duty
CCRA
If fSYS=16MHz, STM clock source select fSYS/4, CCRP=2 and CCRA=128,
The STM PWM output frequency=(fSYS/4)/(2×256)=fSYS/2048=7.8125kHz, duty=128/(2×256)=25%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
• 16-bit STM, PWM Mode, Edge-aligned Mode, STnDPX=1
CCRP
1~255
Period
0
CCRA
Duty
CCRP×256
65536
The PWM output period is determined by the CCRA register value together with the STM clock
while the PWM duty cycle is defined by the (CCRP×256) except when the CCRP value is equal to
000b.
Rev. 1.00
81
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Counter Value
STnDPX = 0; STnM [1:0] = 10
Counter cleared
by CCRP
Counter Reset when
STnON returns high
CCRP
Pause Resume
CCRA
Counter Stop if
STnON bit low
Time
STnON
STnPAU
STnPOL
CCRA Int.
flag STMnAF
CCRP Int.
flag STMnPF
STMn O/P Pin
(STnOC=1)
STMn O/P Pin
(STnOC=0)
PWM Duty Cycle
set by CCRA
PWM Period
set by CCRP
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
when STnPOL = 1
PWM Mode – STnDPX=0
Note: 1. Here STnDPX=0 – Counter cleared by CCRP
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when STnIO [1:0]=00 or 01
4. The STnCCLR bit has no influence on PWM operation
5. n=0 or 1
Rev. 1.00
82
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Counter Value
STnDPX = 1; STnM [1:0] = 10
Counter cleared
by CCRA
Counter Reset when
STnON returns high
CCRA
Pause Resume
CCRP
Counter Stop if
STnON bit low
Time
STnON
STnPAU
STnPOL
CCRP Int.
flag STMnPF
CCRA Int.
flag STMnAF
STMn O/P
Pin (STnOC=1)
STMn O/P
Pin (STnOC=0)
PWM resumes
operation
PWM Duty Cycle
set by CCRP
PWM Period
set by CCRA
Output controlled by
other pin-shared function
Output Inverts
when STnPOL = 1
PWM Mode – STnDPX=1
Note: 1. Here STnDPX=1 – Counter cleared by CCRA
2. A counter clear sets the PWM Period
3. The internal PWM function continues even when STnIO [1:0]=00 or 01
4. The STnCCLR bit has no influence on PWM operation
5. n=0 or 1
Rev. 1.00
83
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Single Pulse Output Mode
To select this mode, bits STnM1 and STnM0 in the STMnC1 register should be set to 10
respectively and also the STnIO1 and STnIO0 bits should be set to 11 respectively. The Single Pulse
Output Mode, as the name suggests, will generate a single shot pulse on the STM output pin.
The trigger for the pulse output leading edge is a low to high transition of the STnON bit, which
can be implemented using the application program. However in the Single Pulse Mode, the STnON
bit can also be made to automatically change from low to high using the external STCKn pin,
which will in turn initiate the Single Pulse output. When the STnON bit transitions to a high level,
the counter will start running and the pulse leading edge will be generated. The STnON bit should
remain high when the pulse is in its active state. The generated pulse trailing edge will be generated
when the STnON bit is cleared to zero, which can be implemented using the application program or
when a compare match occurs from Comparator A.
S/W Command
SET“STnON”
o�
STCKn Pin
T�ansition
CCR�
Leading Edge
CCR�
T�ai�ing Edge
STnON bit
0
1
STnON bit
1
0
S/W Command
CLR“STnON”
o�
CCR� Com�a�e
Match
STPn Out�ut Pin
Pu�se Width = CCR� Va�ue
Single Pulse Generation (n=0 or 1)
However a compare match from Comparator A will also automatically clear the STnON bit and thus
generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the
pulse width. A compare match from Comparator A will also generate a STM interrupt. The counter
can only be reset back to zero when the STnON bit changes from low to high when the counter
restarts. In the Single Pulse Mode CCRP is not used. The STnCCLR and STnDPX bits are not used
in this Mode.
Rev. 1.00
84
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Counter Value
STnM [1:0] = 10 ; STnIO [1:0] = 11
Counter stopped
by CCRA
Counter Reset when
STnON returns high
CCRA
Pause
Counter Stops
by software
Resume
CCRP
Time
STnON
Software
Trigger
Auto. set by
STCKn pin
Cleared by
CCRA match
STCKn pin
Software
Trigger
Software
Trigger
Software
Clear
Software
Trigger
STCKn pin
Trigger
STnPAU
STnPOL
No CCRP Interrupts
generated
CCRP Int. Flag
STMnPF
CCRA Int. Flag
STMnAF
STMn O/P Pin
(STnOC=1)
STMn O/P Pin
(STnOC=0)
Output Inverts
when STnPOL = 1
Pulse Width
set by CCRA
Single Pulse Mode
Note: 1. Counter stopped by CCRA
2. CCRP is not used
3. The pulse is triggered by the STCKn pin or by setting the STnON bit high
4. A STCKn pin active edge will automatically set the STnON bit high
5. In the Single Pulse Mode, STnIO [1:0] must be set to “11” and cannot be changed.
6. n=0 or 1
Rev. 1.00
85
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Capture Input Mode
To select this mode bits STnM1 and STnM0 in the STMnC1 register should be set to 01 respectively.
This mode enables external signals to capture and store the present value of the internal counter
and can therefore be used for applications such as pulse width measurements. The external signal
is supplied on the STPnI pin, whose active edge can be a rising edge, a falling edge or both rising
and falling edges; the active edge transition type is selected using the STnIO1 and STnIO0 bits in
the STMnC1 register. The counter is started when the STnON bit changes from low to high which is
initiated using the application program.
When the required edge transition appears on the STPnI pin the present value in the counter will be
latched into the CCRA registers and a STM interrupt generated. Irrespective of what events occur
on the STPnI pin the counter will continue to free run until the STnON bit changes from high to
low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP
value can be used to control the maximum counter value. When a CCRP compare match occurs from
Comparator P, a STM interrupt will also be generated. Counting the number of overflow interrupt
signals from the CCRP can be a useful method in measuring long pulse widths. The STnIO1 and
STnIO0 bits can select the active trigger edge on the STPnI pin to be a rising edge, falling edge or
both edge types. If the STnIO1 and STnIO0 bits are both set high, then no capture operation will
take place irrespective of what happens on the STPnI pin, however it must be noted that the counter
will continue to run.
As the STPnI pin is pin shared with other functions, care must be taken if the STM is in the Input
Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may
cause an input capture operation to be executed. The STnCCLR and STnDPX bits are not used in
this Mode.
Rev. 1.00
86
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Counter Value
STnM [1:0] = 01
Counter cleared
by CCRP
Counter Counter
Stop
Reset
CCRP
YY
Pause
Resume
XX
Time
STnON
STnPAU
Active
edge
Active
edge
Active edge
STMn capture
pin STPnI
CCRA Int. Flag
STMnAF
CCRP Int. Flag
STMnPF
CCRA
Value
STnIO [1:0]
Value
XX
00 – Rising edge
YY
01 – Falling edge
XX
10 – Both edges
YY
11 – Disable Capture
Capture Input Mode
Note: 1. STnM [1:0]=01 and active edge set by the STnIO [1:0] bits
2. A STM Capture input pin active edge transfers the counter value to CCRA
3. STnCCLR bit not used
4. No output function – STnOC and STnPOL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to
zero.
6. n= 0 or 1
Rev. 1.00
87
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Periodic Type TM – PTM
The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/
Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can
also be controlled with two external input pin and can drive one external output pin.
PTM core
PTM Input Pin
PTM Output Pin
10-bit PTM
PTCK, PTPI
PTP
Periodic TM Operation
At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock
source. There are two internal comparators with the names, Comparator A and Comparator P. These
comparators will compare the value in the counter with the CCRA and CCRP registers.
The only way of changing the value of the 10-bit counter using the application program, is to
clear the counter by changing the PTON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a PTM interrupt signal will also usually be generated. The Periodic
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control the output pin. All operating setup conditions are
selected using relevant internal registers.
CCRP
fSYS/4
fSYS
fH/16
fH/64
fSUB
fH
PTCK
000
001
010
011
100
101 PTON
110 PTP�U
111
PTCK�~PTCK0
10-bit Com�a�ato� P
Com�a�ato� P Match
PTMPF Inte��u�t
PTOC
b0~b9
10-bit Count-u� Counte�
PTCCLR
b0~b9
10-bit Com�a�ato� �
Out�ut
Cont�o�
Po�a�ity
Cont�o�
Pin
Cont�o�
PTM1� PTM0
PTIO1� PTIO0
PTPOL
PTCP
Counte� C�ea� 0
1
Com�a�ato� � Match
PTM�F Inte��u�t
PTIO1� PTIO0
PTC�PTS
Edge
Detecto�
0
1
CCR�
PTP
PTPI
Periodic Type TM Block Diagram
Periodic Type TM Register Description
Overall operation of the Periodic TM is controlled using a series of registers. A read only register
pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store
the internal 10-bit CCRA and CCRP value. The remaining two registers are control registers which
setup the different operating and control modes.
Rev. 1.00
88
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Bit
Register
Name
7
6
5
4
3
PTMC0
PTPAU
PTCK2
PTCK1
PTCK0
PTON
—
—
—
PTMC1
PTM1
PTM0
PTIO1
PTIO0
PTOC
PTPOL
PTCAPTS
PTCCLR
2
1
0
PTMDL
D7
D6
D5
D4
D3
D2
D1
D0
PTMDH
—
—
—
—
—
—
D9
D8
PTMAL
D7
D6
D5
D4
D3
D2
D1
D0
PTMAH
—
—
—
—
—
—
D9
D8
PTMRPL
D7
D6
D5
D4
D3
D2
D1
D0
PTMRPH
—
—
—
—
—
—
D9
D8
10-bit Periodic TM Registers List
PTMC0 Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
PTPAU
PTCK2
PTCK1
PTCK0
PTON
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
POR
0
0
0
0
0
—
—
—
Bit 7
PTPAU: PTM Counter Pause Control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the PTM will remain powered
up and continue to consume power. The counter will retain its residual value when
this bit changes from low to high and resume counting from this value when the bit
changes to a low value again.
Bit 6~4
PTCK2~PTCK0: Select PTM Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fSUB
101: fH
110: PTCK rising edge clock
111: PTCK falling edge clock
These three bits are used to select the clock source for the PTM. The external pin clock
source can be chosen to be active on the rising or falling edge. The clock source fSYS is
the system clock, while fH and fSUB are other internal clocks, the details of which can
be found in the oscillator section.
Bit 3
PTON: PTM Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the PTM. Setting the bit high enables
the counter to run, clearing the bit disables the PTM. Clearing this bit to zero will
stop the counter from counting and turn off the PTM which will reduce its power
consumption. When the bit changes state from low to high the internal counter value
will be reset to zero, however when the bit changes from high to low, the internal
counter will retain its residual value until the bit returns high again.
If the PTM is in the Compare Match Output Mode then the PTM output pin will
be reset to its initial condition, as specified by the PTOC bit, , when the PTON bit
changes from low to high.
Bit 2~0
Unimplemented, read as “0”
89
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
PTMC1 Register
Rev. 1.00
Bit
7
6
5
4
3
2
Name
PTM1
PTM0
PTIO1
PTIO0
PTOC
PTPOL
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
PTCAPTS PTCCLR
Bit 7~6
PTM1~PTM0: Select PTM Operation Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the PTM. To ensure reliable operation
the PTM should be switched off before any changes are made to the PTM1 and PTM0
bits. In the Timer/Counter Mode, the PTM output pin control must be disabled.
Bit 5~4
PTIO1~PTIO0: Select PTM external pin PTP, PTCK or PTPI function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Mode/Single Pulse Output Mode
00: PWM Output inactive state
01: PWM Output active state
10: PWM output
11: Single pulse output
Capture Input Mode
00: Input capture at rising edge of PTCK or PTPI
01: Input capture at falling edge of PTCK or PTPI
10: Input capture at falling/rising edge of PTCK or PTPI
11: Input capture disabled
Timer/counter Mode
Unused
These two bits are used to determine how the PTM output pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the PTM is running.
In the Compare Match Output Mode, the PTIO1 and PTIO0 bits determine how the
PTM output pin changes state when a compare match occurs from the Comparator A.
The PTM output pin can be setup to switch high, switch low or to toggle its present
state when a compare match occurs from the Comparator A. When these bits are both
zero, then no change will take place on the output. The initial value of the PTM output
pin should be setup using the PTOC bit. Note that the output level requested by the
PTIO1 and PTIO0 bits must be different from the initial value setup using the PTOC
bit otherwise no change will occur on the PTM output pin when a compare match
occurs. After the PTM output pin changes state, it can be reset to its initial level by
changing the level of the PTON bit from low to high.
In the PWM Mode, the PTIO1 and PTIO0 bits determine how the PTM output pin
changes state when a certain compare match condition occurs. The PWM output
function is modified by changing these two bits. It is necessary to change the values of
the PTIO1 and PTIO0 bits only after the PTM has been switched off. Unpredictable
PWM outputs will occur if the PTIO1 and PTIO0 bits are changed when the PTM is
running.
90
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Bit 3
PTOC: PTP Output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode/Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the PTM output pin. Its operation depends upon
whether PTM is being used in the Compare Match Output Mode or in the PWM
Mode/Single Pulse Output Mode. It has no effect if the PTM is in the Timer/Counter
Mode. In the Compare Match Output Mode it determines the logic level of the PTM
output pin before a compare match occurs. In the PWM Mode it determines if the
PWM signal is active high or active low.
Bit 2
PTPOL: PTP Output polarity Control
0: Non-invert
1: Invert
This bit controls the polarity of the PTP output pin. When the bit is set high the PTM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the
PTM is in the Timer/Counter Mode.
Bit 1
PTCAPTS: PTM capture trigger source select
0: From PTPI pin
1: From PTCK pin
Bit 0
PTCCLR: Select PTM Counter clear condition
0: PTM Comparatror P match
1: PTM Comparatror A match
This bit is used to select the method which clears the counter. Remember that the
Periodic TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the PTCCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The PTCCLR bit is not
used in the PWM Output, Single Pulse Output or Capture Input Mode.
PTMDL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
PTMDL: PTM Counter Low Byte Register bit 7~bit 0
PTM 10-bit Counter bit 7~bit 0
PTMDH Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R
R
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as “0”
Bit 1~0
PTMDH: PTM Counter High Byte Register bit 1~bit 0
PTM 10-bit Counter bit 9~bit 8
91
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
PTMAL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
PTMAL: PTM CCRA Low Byte Register bit 7~bit 0
PTM 10-bit CCRA bit 7~bit 0
PTMAH Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
2
1
0
Bit 7~2
Unimplemented, read as “0”
Bit 1~0
PTMAH: PTM CCRA High Byte Register bit 1~bit 0
PTM 10-bit CCRA bit 9~bit 8
PTMRPL Register
Bit
7
6
5
4
3
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
PTMRPL: PTM CCRP Low Byte Register bit 7~bit 0
PTM 10-bit CCRP bit 7~bit 0
PTMRPH Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as “0”
Bit 1~0
PTMRPH: PTM CCRP High Byte Register bit 1~bit 0
PTM 10-bit CCRP bit 9~bit 8
92
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Periodic Type TM Operating Modes
The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the PTM1 and PTM0 bits in the PTMC1 register.
Compare Match Output Mode
To select this mode, bits PTM1 and PTM0 in the PTMC1 register, should be all cleared to 00
respectively. In this mode once the counter is enabled and running it can be cleared by three
methods. These are a counter overflow, a compare match from Comparator A and a compare match
from Comparator P. When the PTCCLR bit is low, there are two ways in which the counter can
be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP
bits are all zero which allows the counter to overflow. Here both the PTMAF and PTMPF interrupt
request flags for Comparator A and Comparator P respectively, will both be generated.
If the PTCCLR bit in the PTMC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the PTMAF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
PTCCLR is high no PTMPF interrupt request flag will be generated. In the Compare Match Output
Mode, the CCRA cannot be set to “0”.
As the name of the mode suggests, after a comparison is made, the PTM output pin, will change
state. The PTM output pin condition however only changes state when a PTMAF interrupt request
flag is generated after a compare match occurs from Comparator A. The PTMPF interrupt request
flag, generated from a compare match from Comparator P, will have no effect on the PTM output
pin. The way in which the PTM output pin changes state are determined by the condition of the
PTIO1 and PTIO0 bits in the PTMC1 register. The PTM output pin can be selected using the PTIO1
and PTIO0 bits to go high, to go low or to toggle from its present condition when a compare match
occurs from Comparator A. The initial condition of the PTM output pin, which is setup after the
PTON bit changes from low to high, is setup using the PTOC bit. Note that if the PTIO1, PTIO0 bits
are zero then no pin change will take place.
Rev. 1.00
93
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Counter Value
Counter overflow
CCRP=0
0x3FF
PTCCLR = 0; PTM [1:0] = 00
CCRP > 0
Counter cleared by CCRP value
CCRP > 0
Counter
Restart
Resume
CCRP
Pause
CCRA
Stop
Time
PTON
PTPAU
PTPOL
CCRP Int. Flag
PTMPF
CCRA Int. Flag
PTMAF
PTM
O/P Pin
Output pin set to
initial Level Low
if PTOC=0
Output not affected by
PTMAF flag. Remains High
until reset by PTON bit
Output Toggle with
PTMAF flag
Here PTIO [1:0] = 11
Toggle Output select
Note PTIO [1:0] = 10
Active High Output select
Output Inverts
when PTPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode – PTCCLR=0
Note: 1. With PTCCLR=0 – a Comparator P match will clear the counter
2. The PTM output pin is controlled only by the PTMAF flag
3. The output pin is reset to initial state by a PTON bit rising edge
Rev. 1.00
94
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Counter Value
PTCCLR = 1; PTM [1:0] = 00
CCRA = 0
Counter overflow
CCRA > 0 Counter cleared by CCRA value
0x3FF
CCRA=0
Resume
CCRA
Pause
Stop
Counter Restart
CCRP
Time
PTON
PTPAU
PTPOL
No PTMAF flag
generated on
CCRA overflow
CCRA Int. Flag
PTMAF
CCRP Int. Flag
PTMPF
PTM
O/P Pin
PTMPF not
generated
Output pin set to
initial Level Low
if PTOC=0
Output does
not change
Output Toggle with
PTMAF flag
Here PTIO [1:0] = 11
Toggle Output select
Output not affected by PTMAF
flag. Remains High until reset
by PTON bit
Note PTIO [1:0] = 10
Active High Output select
Output Inverts
when PTPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode – PTCCLR=1
Note: 1. With PTCCLR=1 – a Comparator A match will clear the counter
2. The PTM output pin is controlled only by the PTMAF flag
3. The output pin is reset to initial state by a PTON rising edge
4. The PTMPF flag is not generated when PTCCLR=1
Rev. 1.00
95
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Timer/Counter Mode
To select this mode, bits PTM1 and PTM0 in the PTMC1 register should all be set to 11
respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output
Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the
PTM output pin is not used. Therefore the above description and Timing Diagrams for the Compare
Match Output Mode can be used to understand its function. As the PTM output pin is not used in
this mode, the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 10 respectively
and also the PTIO1 and PTIO0 bits should be set to 10 respectively. The PWM function within
the PTM is useful for applications which require functions such as motor control, heating control,
illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the
PTM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS
values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the PTCCLR bit has no effect as the PWM
period. Both of the CCRP and CCRA registers are used to generate the PWM waveform, one register
is used to clear the internal counter and thus control the PWM waveform frequency, while the other
one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore
be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The PTOC bit in the PTMC1 register is used to
select the required polarity of the PWM waveform while the two PTIO1 and PTIO0 bits are used to
enable the PWM output or to force the PTM output pin to a fixed high or low level. The PTPOL bit
is used to reverse the polarity of the PWM output waveform.
• 10-bit PTM, PWM Mode
CCRP
1~1023
0
Period
1~1023
1024
Duty
CCRA
If fSYS=16MHz, PTM clock source select fSYS/4, CCRP=512 and CCRA=128,
The PTM PWM output frequency=(fSYS/4)/(2×256)=fSYS/2048=7.8125kHz, duty=128/512=25%,
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
Rev. 1.00
96
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Counter Value
PTM [1:0] = 10
Counter cleared
by CCRP
Counter Reset when
PTON returns high
CCRP
Pause Resume
CCRA
Counter Stop if
PTON bit low
Time
PTON
PTPAU
PTPOL
CCRA Int. Flag
PTMAF
CCRP Int. Flag
PTMPF
PTM O/P Pin
(PTOC=1)
PTM O/P Pin
(PTOC=0)
PWM Duty Cycle
set by CCRA
PWM Period
set by CCRP
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
When PTPOL = 1
PWM Mode
Note: 1. Here Counter cleared by CCRP
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when PTIO[1:0]=00 or 01
4. The PTCCLR bit has no influence on PWM operation
Rev. 1.00
97
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Single Pulse Output Mode
To select this mode, the required bit pairs, PTM1 and PTM0 should be set to 10 respectively and
also the corresponding PTIO1 and PTIO0 bits should be set to 11 respectively. The Single Pulse
Output Mode, as the name suggests, will generate a single shot pulse on the PTM output pin.
The trigger for the pulse output leading edge is a low to high transition of the PTON bit, which can
be implemented using the application program. However in the Single Pulse Mode, the PTON bit
can also be made to automatically change from low to high using the external PTCK pin, which will
in turn initiate the Single Pulse output. When the PTON bit transitions to a high level, the counter
will start running and the pulse leading edge will be generated. The PTON bit should remain high
when the pulse is in its active state. The generated pulse trailing edge will be generated when the
PTON bit is cleared to zero, which can be implemented using the application program or when a
compare match occurs from Comparator A.
However a compare match from Comparator A will also automatically clear the PTON bit and thus
generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the
pulse width. A compare match from Comparator A will also generate PTM interrupts. The counter
can only be reset back to zero when the PTON bit changes from low to high when the counter
restarts. In the Single Pulse Mode CCRP is not used. The PTCCLR bit is also not used.
S/W Command
SET“PTON”
o�
PTCK Pin
T�ansition
CCR�
Leading Edge
CCR�
T�ai�ing Edge
PTON bit
1
0
PTON bit
0
1
S/W Command
CLR“PTON”
o�
CCR� Com�a�e
Match
PTP Out�ut Pin
Pu�se Width = CCR� Va�ue
Single Pulse Generation
Rev. 1.00
98
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Counter Value
PTM [1:0] = 10 ; PTIO [1:0] = 11
Counter stopped
by CCRA
Counter Reset when
PTON returns high
CCRA
Pause
Counter Stops
by software
Resume
CCRP
Time
PTON
Software
Trigger
Auto. set by
PTCK pin
Cleared by
CCRA match
PTCK pin
Software
Trigger
Software
Clear
Software
Trigger
Software
Trigger
PTCK pin
Trigger
PTPAU
PTPOL
No CCRP Interrupts
generated
CCRP Int. Flag
PTMPF
CCRA Int. Flag
PTMAF
PTM O/P Pin
(PTOC=1)
PTM O/P Pin
(PTOC=0)
Pulse Width
set by CCRA
Output Inverts
when PTPOL = 1
Single Pulse Mode
Note: 1. Counter stopped by CCRA
2. CCRP is not used
3. The pulse is triggered by the PTCK pin or by setting the PTON bit high
4. A PTCK pin active edge will automatically set the PTON bit high
5. In the Single Pulse Mode, PTIO [1:0] must be set to “11” and cannot be changed.
Rev. 1.00
99
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Capture Input Mode
To select this mode bits PTM1 and PTM0 in the PTMC1 register should be set to 01 respectively.
This mode enables external signals to capture and store the present value of the internal counter
and can therefore be used for applications such as pulse width measurements. The external signal is
supplied on the PTPI or PTCK pin, selected by the PTCAPTS bit in the PTMC0 register. The input
pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active
edge transition type is selected using the PTIO1 and PTIO0 bits in the PTMC1 register. The counter
is started when the PTON bit changes from low to high which is initiated using the application
program.
When the required edge transition appears on the PTPI or PTCK pin the present value in the counter
will be latched into the CCRA register and a PTM interrupt generated. Irrespective of what events
occur on the PTPI or PTCK pin the counter will continue to free run until the PTON bit changes
from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this
way the CCRP value can be used to control the maximum counter value. When a CCRP compare
match occurs from Comparator P, a PTM interrupt will also be generated. Counting the number of
overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths.
The PTIO1 and PTIO0 bits can select the active trigger edge on the PTPI or PTCK pin to be a rising
edge, falling edge or both edge types. If the PTIO1 and PTIO0 bits are both set high, then no capture
operation will take place irrespective of what happens on the PTPI or PTCK pin, however it must be
noted that the counter will continue to run.
As the PTPI or PTCK pin is pin shared with other functions, care must be taken if the PTM is in the
Capture Input Mode. This is because if the pin is setup as an output, then any transitions on this pin
may cause an input capture operation to be executed. The PTCCLR, PTOC and PTPOL bits are not
used in this Mode.
Rev. 1.00
100
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Counter Value
PTM [1:0] = 01
Counter cleared
by CCRP
Counter Counter
Stop
Reset
CCRP
YY
Pause
Resume
XX
Time
PTON
PTPAU
Active
edge
Active
edge
Active edge
PTM capture pin
PTPI or PTCK
CCRA Int. Flag
PTMAF
CCRP Int. Flag
PTMPF
CCRA
Value
PTIO [1:0]
Value
XX
00 – Rising edge
YY
01 – Falling edge
XX
10 – Both edges
YY
11 – Disable Capture
Capture Input Mode
Note: 1. PTM [1:0]=01 and active edge set by the PTIO[1:0] bits
2. A PTM Capture input pin active edge transfers counter value to CCRA
3. The PTCCLR bit is not used
4. No output function – PTOC and PTPOL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to
zero
Rev. 1.00
101
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Analog to Digital Converter – ADC
The need to interface to real world analog signals is a common requirement for many electronic
systems. However, to properly process these signals by a microcontroller, they must first be
converted into digital signals by A/D converters. By integrating the A/D conversion electronic
circuitry into the microcontroller, the need for external components is reduced significantly with the
corresponding follow-on benefits of lower costs and reduced component space requirements.
A/D Overview
The device contains a multi-channel analog to digital converter which can directly interface
to external analog signals, such as that from sensors or other control signals and convert these
signals directly into a 12-bit digital value. The external or internal analog signal to be converted is
determined by the SAINS2~SAINS0 bits together with the SACS2~SACS0 bits. Note that when the
external and internal analog signals are simultaneously selected to be converted, the internal analog
signal will have the priority. In the meantime the external analog signal will temporarily be switched
off until the internal analog signal is deselected. More detailed information about the A/D input
signal is described in the “A/D Converter Control Registers” and “A/D Converter Input Signal”
sections respectively.
External Input Channel
Internal Analog Signals
A/D Signal Select Bits
AN0~AN7
VDD, VDD/2, VDD/4, VR, VR/2, VR/4
SAINS2~SAINS0; SACS2~SACS0
The accompanying block diagram shows the overall internal structure of the A/D converter, together
with its associated registers.
VDD
fSYS
�CE�~�CE0
S�CS�~S�CS0
÷ �N
(N=0~�)
S�CKS�~
S�CKS0
�N0
EN�DC
VSS
�/D C�ock
�N1
�DRFS
S�DOL
�/D Conve�te�
S�DOH
�N�
�/D Data
Registe�s
�/D Refe�ence Vo�tage
ST�RT
�DBZ EN�DC
S�INS�~S�INS0
VREF
S�VRS3~S�VRS0
VDD
VREFPS
VDD/�
VDD/4
VR
VR/�
VBG (1.04V)
VRI OP�
(Gain=1~4)
VREFI
VDD
VR
VR/4
VREFIPS
ENOP�
A/D Converter Structure
Rev. 1.00
102
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
A/D Converter Register Description
Overall operation of the A/D converter is controlled using six registers. A read only register pair
exists to store the ADC data 12-bit value. One register, ACERL, is used to configure the external
analog input pin function.The remaining three registers are control registers which setup the
operating and control function of the A/D converter.
Register Name
SADOL(ADRFS=0)
Bit
7
6
5
4
3
2
1
0
D3
D2
D1
D0
—
—
—
—
SADOL(ADRFS=1)
D7
D6
D5
D4
D3
D2
D1
D0
SADOH(ADRFS=0)
D11
D10
D9
D8
D7
D6
D5
D4
SADOH(ADRFS=1)
—
—
—
—
D11
D10
D9
D8
SADC0
START
ADBZ
ENADC
ADRFS
—
SACS2
SACS1
SACS0
SADC1
SAINS2
SAINS1
SAINS0
—
—
SACKS2
SACKS1
SACKS0
SADC2
ENOPA
VBGEN
VREFIPS
VREFPS
SAVRS3
SAVRS2
SAVRS1
SAVRS0
ACERL
ACE7
ACE6
ACE5
ACE4
ACE3
ACE2
ACE1
ACE0
A/D Converter Register List
A/D Converter Data Registers – SADOL, SADOH
As the device contains an internal 12-bit A/D converter, it requires two data registers to store the
converted value. These are a high byte register, known as SADOH, and a low byte register, known
as SADOL. After the conversion process takes place, these registers can be directly read by the
microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space
is utilised, the format in which the data is stored is controlled by the ADRFS bit in the SADC0
register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits.
Any unused bits will be read as zero. Note that the A/D converter data register contents will keep
unchanged if the A/D converter is disabled.
ADRFS
0
1
SADOH
7
6
5
D11 D10 D9
0
0
0
SADOL
4
3
2
1
0
7
6
5
4
3
2
1
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
A/D Data Registers
Rev. 1.00
103
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
A/D Converter Control Registers – SADC0, SADC1, SADC2, ACERL
To control the function and operation of the A/D converter, several control registers known as
SADC0, SADC1, SADC2 and ACERL are provided. These 8-bit registers define functions such
as the selection of which analog channel is connected to the internal A/D converter, the digitised
data format, the A/D clock source as well as controlling the start function and monitoring the A/D
converter busy status. As the device contains only one actual analog to digital converter hardware
circuit, each of the external and internal analog signals must be routed to the converter. The
SACS2~SACS0 bits in the SADC0 register are used to determine which external channel input is
selected to be converted. The SAINS2~SAINS0 bits in the SADC1 register are used to determine
that the analog signal to be converted comes from the internal analog signal or external analog
channel input. If the SAINS2~SAINS0 bits are set to “000” or “100”, the external analog channel
input is selected to be converted and the SACS2~SACS0 bits can determine which external channel
is selected to be converted. If the SAINS2~SAINS0 bits are set to any other values except “000”
and “100”, one of the internal analog signals is selected to be converted. The internal analog signals
can be derived from the A/D converter supply power, VDD, or internal reference voltage, VR, with a
specific ratio of 1, 1/2 or 1/4. If the internal analog signal is selected to be converted, the external
channel signal input will automatically be switched off to avoid the signal contention.
The ACERL control register contains the ACE7~ACE0 bits which determine which pins on I/O Port
are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D
converter input. Setting the corresponding bit high will select the A/D input function, clearing the
bit to zero will select either the I/O or other pin-shared function. When the pin is selected to be an
A/D input, its original function whether it is an I/O or other pin-shared function will be removed. In
addition, any internal pull-high resistors connected to these pins will be automatically removed if the
pin is selected to be an A/D input.
SAINS [2:0]
SACS [2:0]
Input Signals
000, 100
000~111
AN0~AN7
Description
001
xxx
VDD
010
xxx
VDD/2
A/D converter power supply voltage/2
011
xxx
VDD/4
A/D converter power supply voltage/4
101
xxx
VR
110
xxx
VR/2
Internal reference voltage/2
111
xxx
VR/4
Internal reference voltage/4
External channel analog input
A/D converter power supply voltage
Internal reference voltage
A/D Converter Input Signal Selection
Rev. 1.00
104
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
SADC0 Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
START
ADBZ
ENADC
ADRFS
—
SACS2
SACS1
SACS0
R/W
R/W
R
R/W
R/W
—
R/W
R/W
R/W
POR
0
0
0
0
—
0
0
0
Bit 7
START: Start the A/D conversion
0→1→0: Start A/D conversion
0→1: Reset the A/D converter and set ADBZ to 0
1→0: Start A/D conversion and set ADBZ to 1
This bit is used to initiate an A/D conversion process. The bit is normally low but if set
high and then cleared low again, the A/D converter will initiate a conversion process.
Bit 6
ADBZ: A/D Converter busy flag
0: No A/D conversion is in progress
1: A/D conversion is in progress
This read only flag is used to indicate whether the A/D conversion is in progress or
not. When the START bit is set from low to high and then to low again, the ADBZ flag
will be set high to indicate that the A/D conversion is initiated. The ADBZ flag will be
cleared to zero after the A/D conversion is complete.
Bit 5
ENADC: A/D Converter function enable control
0: Disable
1: Enable
This bit controls the A/D internal function. This bit should be set high to enable the A/D
converter. If the bit is set low, then the A/D converter will be switched off reducing the
device power consumption. When the A/D converter function is disabled, the contents
of the A/D data register pair, SADOH and SADOL, will keep unchanged.
Bit 4
ADRFS: A/D Converter data format control
0: ADC output data format → SADOH=D[11:4]; SADOL=D[3:0]
1: ADC output data format → SADOH=D[11:8]; SADOL=D[7:0]
This bit controls the format of the 12-bit converted A/D value in the two A/D data
registers. Details are provided in the A/D converter data register section.
Bit 3
Unimplemented, read as “0”
Bit 2~0
SACS2~SACS0: A/D converter external analog input channel selection
000: AN0
001: AN1
010: AN2
011: AN3
100: AN4
101: AN5
110: AN6
111: AN7
105
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
SADC1 Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
SAINS2
SAINS1
SAINS0
—
—
SACKS2
SACKS1
SACKS0
R/W
R/W
R/W
R/W
—
—
R/W
R/W
R/W
POR
0
0
0
—
—
0
0
0
Bit 7~5
SAINS2~SAINS0: A/D converter input signal selection
000, 100: External signal – External analog channel input
001: Internal signal – Internal A/D converter power supply voltage VDD
010: Internal signal – Internal A/D converter power supply voltage VDD/2
011: Internal signal – Internal A/D converter power supply voltage VDD/4
101: Internal signal – Internal A/D converter power supply voltage VR
110: Internal signal – Internal A/D converter power supply voltage VR/2
111: Internal signal – Internal A/D converter power supply voltage VR/4
When the internal analog signal is selected to be converted, the external channel input
signal will automatically be switched off regardless of the SACS2~SACS0 bit field
value. The internal reference voltage can be derived from various sources selected
using the SAVRS3~SAVRS0 bits in the SADC2 register.
Bit 4~3
Unimplemented, read as “0”
Bit 2~0
SACKS2~SACKS0: A/D conversion clock source selection
000: fSYS
001: fSYS/2
010: fSYS/4
011: fSYS/8
100: fSYS/16
101: fSYS/32
110: fSYS/64
111: fSYS/128
These bits are used to select the clock source for the A/D converter.
106
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
SADC2 Register
Rev. 1.00
Bit
7
6
5
4
Name
ENOPA
VBGEN
VREFIPS
VREFPS
3
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
2
1
0
SAVRS1
SAVRS0
R/W
R/W
R/W
0
0
0
SAVRS3 SAVRS2
Bit 7
ENOPA: A/D converter OPA enable/disable control
0: Disable
1: Enable
This bit controls the internal OPA function to provide various reference voltage for
the A/D converter. When the bit is set high, the internal reference voltage, VR, can be
used as the internal converter signal or reference voltage by the A/D converter. If the
internal reference voltage is not used by the A/D converter, then the OPA function
should be properly configured to conserve power.
Bit 6
VBGEN: Internal Bandgap reference voltage enable control
0: Disable
1: Enable
This controls the internal Bandgap circuit on/off function to the A/D converter. When
the bit is set high, the Bandgap reference voltage can be used by the A/D converter. If
the Bandgap reference voltage is not used by the A/D converter and the LVD or LVR
function is disabled, then the bandgap reference circuit will be automatically switched
off to conserve power. When the Bandgap reference voltage is switched on for use by
the A/D converter, a time, tBGS, should be allowed for the Bandgap circuit to stabilise
before implementing an A/D conversion.
Bit 5
VREFIPS: VREFI input control
0: Disable – VREFI pin is not selected
1: Enable – VREFI pin is selected
Bit 4
VREFPS: VREF output control
0: Disable
1: Enable
Bit 3~0
SAVRS3~SAVRS0: A/D converter reference voltage selection
0000: VDD
0001: VREFI
0010: VREFI × 2
0011: VREFI × 3
0100: VREFI × 4
1001: Reserved, can not be used
1010: VBG × 2
1011: VBG × 3
1100: VBG × 4
Others: VDD
When the A/D converter reference voltage source is selected to derive from the
internal VBG voltage, the reference voltage which comes from the VDD or VREFI pin
will be automatically switched off.
107
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
ACERL Register
Bit
7
6
5
4
3
2
1
0
Name
ACE7
ACE6
ACE5
ACE4
ACE3
ACE2
ACE1
ACE0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
1
1
1
1
1
Bit 7
ACE7: Define PB7 is A/D input or not
0: Not A/D input
1: A/D input, AN7
Bit 6
ACE6: Define PF1 is A/D input or not
0: Not A/D input
1: A/D input, AN6
Bit 5
ACE5: Define PA1 is A/D input or not
0: Not A/D input
1: A/D input, AN5
Bit 4
ACE4: Define PA3 is A/D input or not
0: Not A/D input
1: A/D input, AN4
Bit 3
ACE3: Define PA4 is A/D input or not
0: Not A/D input
1: A/D input, AN3
Bit 2
ACE2: Define PA5 is A/D input or not
0: Not A/D input
1: A/D input, AN2
Bit 1
ACE1: Define PA6 is A/D input or not
0: Not A/D input
1: A/D input, AN1
Bit 0
ACE0: Define PA7 is A/D input or not
0: Not A/D input
1: A/D input, AN0
A/D Operation
The START bit in the SADC0 register is used to start and reset the A/D converter. When the
microcontroller sets this bit from low to high and then low again, an analog to digital conversion
cycle will be initiated. When the START bit is brought from low to high but not low again, the
ADBZ bit in the SADC0 register will be cleared to zero and the analog to digital converter will be
reset. It is the START bit that is used to control the overall start operation of the internal analog to
digital converter.
The ADBZ bit in the SADC0 register is used to indicate whether the analog to digital conversion
process is in process or not. When the A/D converter is reset by setting the START bit from low
to high, the ADBZ flag will be cleared to “0”. This bit will be automatically set to “1” by the
microcontroller after an A/D conversion is successfully initiated. When the A/D conversion is
complete, the ADBZ will be cleared to “0”. In addition, the corresponding A/D interrupt request flag
will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal
interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to
the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled,
the microcontroller can be used to poll the ADBZ bit in the SADC0 register to check whether it has
been cleared as an alternative method of detecting the end of an A/D conversion cycle.
Rev. 1.00
108
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen
to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the
SACKS2~SACKS0 bits in the SADC1 register. Although the A/D clock source is determined by
the system clock fSYS, and by bits SACKS2~SACKS0, there are some limitations on the maximum
A/D clock source speed that can be selected. As the recommended value of permissible A/D clock
period, tADCK, is from 0.5μs to 10μs, care must be taken for system clock frequencies. For example,
if the system clock operates at a frequency of 8MHz, the SACKS2~SACKS0 bits should not be set
to “000”, “001” or “111”. Doing so will give A/D clock periods that are less than the minimum A/D
clock period or greater than the maximum A/D clock period which may result in inaccurate A/D
conversion values. Refer to the following table for examples, where values marked with an asterisk
* show where, depending upon the device, special care must be taken, as the values may be less than
the specified minimum A/D Clock Period.
A/D Clock Period (tADCK)
SACKS2,
SACKS1,
SACKS0
=000
(fSYS)
SACKS2,
SACKS1,
SACKS0
=001
(fSYS/2)
SACKS2,
SACKS1,
SACKS0
=010
(fSYS/4)
SACKS2,
SACKS1,
SACKS0
=011
(fSYS/8)
SACKS2,
SACKS1,
SACKS0
=100
(fSYS/16)
SACKS2,
SACKS1,
SACKS0
=101
(fSYS/32)
SACKS2,
SACKS1,
SACKS0
=110
(fSYS/64)
SACKS2,
SACKS1,
SACKS0
=111
(fSYS/128)
1MHz
1μs
2μs
4μs
8μs
16μs*
32μs*
64μs*
128μs*
2MHz
500ns
1μs
2μs
4μs
8μs
16μs*
32μs*
64μs*
4MHz
250ns*
500ns
1μs
2μs
4μs
8μs
16μs*
32μs*
8MHz
125ns*
250ns*
500ns
1μs
2μs
4μs
8μs
16μs*
12MHz
83ns*
167ns*
333ns*
667ns
1.33μs
2.67μs
5.33μs
10.67μs*
16MHz
62.5ns*
125ns*
250ns*
500ns
1μs
2μs
4μs
8μs
20MHz
50ns*
100ns*
200ns*
400ns*
800ns
1.6μs
3.2μs
6.4μs
fSYS
A/D Clock Period Examples
Controlling the power on/off function of the A/D converter circuitry is implemented using the
ENADC bit in the SADC0 register. This bit must be set high to power on the A/D converter. When
the ENADC bit is set high to power on the A/D converter internal circuitry a certain delay, as
indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if
no pins are selected for use as A/D inputs by configuring the corresponding pin control bits, if the
ENADC bit is high then some power will still be consumed. In power conscious applications it is
therefore recommended that the ENADC is set low to reduce power consumption when the A/D
converter function is not being used.
A/D Reference Voltage
The reference voltage supply to the A/D Converter can be supplied from the positive power supply
pin, VDD, an external reference source supplied on pin VREFI or an internal reference source
derived from the Bandgap circuit. Then the selected reference voltage source can be amplified
through an operational amplifier except the one sourced from VDD. The OPA gain can be equal to
1, 2, 3 or 4. The desired selection is made using the SAVRS3~SAVRS0 bits in the SADC2 register
and relevant pin function control bits. Note that the desired selected reference voltage will be output
on the VREF pin which is pin-shared with other functions. As the VREFI and VREF pins both are
pin-shared with other functions, when the VREFI or VREF pin is selected as the reference voltage
supply pin, the pin function control bit VREFIPS or VREFPS should be set high to disable other pinshared functions. When VREFI or VBG is selected by ADC input or ADC reference voltage, the OPA
needs to be enabled by setting the ENOPA bit to “1”. In addition, if the programs select external
reference voltage VREFI and the internal reference voltage VBG as ADC reference voltage, then the
hardware will only choose the internal reference voltage VBG as an ADC reference voltage input.
Rev. 1.00
109
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
SAVRS[3:0]
Reference
0000/others
VDD
ADC Reference Voltage comes from VDD
Description
0001
VREFI
ADC Reference Voltage comes from External VREFI
0010
VREFI×2
ADC Reference Voltage comes from External VREFI×2
0011
VREFI×3
ADC Reference Voltage comes from External VREFI×3
0100
VREFI×4
ADC Reference Voltage comes from External VREFI×4
1010
VBG×2
ADC Reference Voltage comes from VBG×2
1011
VBG×3
ADC Reference Voltage comes from VBG×3
1100
VBG×4
ADC Reference Voltage comes from VBG×4
A/D Converter Reference Voltage Selection
A/D Converter Input Signal
All of the A/D analog input pins are pin-shared with the I/O pins on Port A, Port B and Port F as
well as other functions. The corresponding selection bit in the ACERL register, determines whether
the input pin is setup as A/D converter analog input or whether it has other functions. If the control
bit configures its corresponding pin as an A/D analog channel input, the pin will be setup to be an
A/D converter external channel input and the original pin functions disabled. In this way, pins can
be changed under program control to change their function between A/D inputs and other functions.
All pull-high resistors, which are setup through register programming, will be automatically
disconnected if the pins are setup as A/D inputs. Note that it is not necessary to first setup the A/D
pin as an input in the PAC, PBC and PFC port control register to enable the A/D input as when the
control bits enable an A/D input, the status of the port control register will be overridden.
The A/D converter has its own reference voltage pin, VREFI. However the reference voltage can
also be supplied from the power supply pin or an internal Bandgap circuit, a choice which is made
through the SAVRS3~SAVRS0 bits in the SADC2 register. The selected A/D reference voltage
can be output on the VREF pin. The analog input values must not be allowed to exceed the value
of VREF. Note that the VREFI or VREF pin function selection bit in the SADC2 register must be
properly configured before the reference voltage pin function is used.
Conversion Rate and Timing Diagram
A complete A/D conversion contains two parts, data sampling and data conversion. The data
sampling which is defined as tADS takes 4 A/D clock cycles and the data conversion takes 12 A/D
clock cycles. Therefore a total of 16 A/D clock cycles for an A/D conversion which is defined as tADC
are necessary.
Maximum single A/D conversion rate=A/D clock period/16
The accompanying diagram shows graphically the various stages involved in an analog to digital
conversion process and its associated timing. After an A/D conversion process has been initiated
by the application program, the microcontroller internal hardware will begin to carry out the
conversion, during which time the program can continue with other functions. The time taken for the
A/D conversion is 16tADCK clock cycles where tADCK is equal to the A/D clock period.
Rev. 1.00
110
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
tON�ST
EN�DC
off
on
off
�/D sam��ing time
t�DS
�/D sam��ing time
t�DS
Sta�t of �/D conve�sion
Sta�t of �/D conve�sion
End of �/D
conve�sion
End of �/D
conve�sion
on
ST�RT
�DBZ
S�CS[�:0]
S�INS[�:0]=000B
011B
�/D channe�
switch
010B
000B
t�DC
�/D conve�sion time
t�DC
�/D conve�sion time
Sta�t of �/D conve�sion
001B
t�DC
�/D conve�sion time
A/D Conversion Timing
Summary of A/D Conversion Steps
The following summarises the individual steps that should be executed in order to implement an A/D
conversion process.
• Step 1
Select the required A/D conversion clock by properly programming the SACKS2~SACKS0 bits
in the SADC1 register.
• Step 2
Enable the A/D converter by setting the ENADC bit in the SADC0 register to “1”.
• Step 3
Select which signal is to be connected to the internal A/D converter by correctly configuring the
SAINS2~SAINS0 bits.
Select the external channel input to be converted, go to Step 4.
Select the internal analog signal to be converted, go to Step 5.
• Step 4
If the A/D input signal comes from the external channel input selecting by configuring the SAINS
bit field, the corresponding pin should first be configured as A/D input function by configuring
the relevant pin control bit in the ACERL register. The desired analog channel then should be
selected by configuring the SACS bit field. After this step, go to Step 6.
• Step 5
If the A/D input signal is selected to come from the internal analog signal, the SAINS bit
field should be properly configured and then the external channel input will automatically be
disconnected regardless of the SACS bit field value. After this step, go to Step 6.
• Step 6
Select the reference voltage source by configuring the SAVRS3~SAVRS0 bits.
Note: If select VREFI pin as the reference voltage, the VREFIPS bit must be set high.
• Step 7
Select A/D converter output data format by configuring the ADRFS bit.
• Step 8
If A/D conversion interrupt is used, the interrupt control registers must be correctly configured
to ensure the A/D interrupt function is active. The master interrupt control bit, EMI, and the A/D
converter interrupt bits, ADE, must both set high in advance.
Rev. 1.00
111
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
• Step 9
The A/D conversion procedure can now be initialised by setting the START bit from low to high
and then low again.
• Step 10
If A/D conversion is in progress, the ADBZ flag will be set high. After the A/D conversion
process is completed, the ADBZ flag will go low and then output data can be read from the
SADOH and SADOL registers. If the ADC interrupt is enabled and the stack is not full, data can
be acquired by interrupt service program.
Note: When checking for the end of the conversion process, if the method of polling the ADBZ bit
in the SADC0 register is used, the interrupt enable step above can be omitted.
Programming Considerations
During microcontroller operations where the A/D converter is not being used, the A/D internal
circuitry can be switched off to reduce power consumption, by clearing the ENADC bit in the
SADC0 register. When this happens, the internal A/D converter circuits will not consume power
irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are
used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then
this may lead to some increase in power consumption.
A/D Transfer Function
As the device contains a 12-bit A/D converter, its full-scale converted digitised value is equal to
FFFH. Since the full-scale analog input value is equal to the VREF voltage, this gives a single bit
analog input value of VREF divided by 4096.
1 LSB= VREF/4096
The A/D Converter input voltage value can be calculated using the following equation:
A/D input voltage=A/D output digital value × VREF/4096
The diagram shows the ideal transfer function between the analog input value and the digitised
output value for the A/D converter. Except for the digitised zero value, the subsequent digitised
values will change at a point 0.5 LSB below where they would change without the offset, and the
last full scale digitised value will change at a point 1.5 LSB below the VDD level.
    
 
      Ideal A/D Transfer Function
Rev. 1.00
112
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
A/D Programming Examples
The following two programming examples illustrate how to setup and implement an A/D conversion.
In the first example, the method of polling the ADBZ bit in the SADC0 register is used to detect
when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to
determine when the conversion is complete.
Example: using an ADBZ polling method to detect the end of conversion
clr
ADE; disable ADC interrupt
mova,03H
mov SADC1,a ; select fSYS/8 as A/D clock
set ENADC
mov a,01h ; setup ACERL to configure pin AN0
mov ACERL,a
mova,20h
mov SADC0,a ; enable and connect AN0 channel to A/D converter
:
start_conversion:
clr START ; high pulse on start bit to initiate conversion
set START ; reset A/D
clr START ; start A/D
polling_EOC:
sz ADBZ ; poll the SADC0 register ADBZ bit to detect end of A/D conversion
jmp polling_EOC ; continue polling
mov a,SADOL ; read low byte conversion result value
mov SADOL_buffer,a ; save result to user defined register
mov a,SADOH ; read high byte conversion result value
mov SADOH_buffer,a ; save result to user defined register
:
jmp start_conversion ; start next A/D conversion
Rev. 1.00
113
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Example: using the interrupt method to detect the end of conversion
clr
ADE ; disable ADC interrupt
mova,0BH
mov SADC1,a ; select fSYS/8 as A/D clock and switch off the bandgap reference
; voltage
set ENADC
mov a,01h ; setup ACERL to configure pin AN0
mov ACERL,a
mova,20h
mov SADC0,a ; enable and connect AN0 channel to A/D converter
Start_conversion:
clr START ; high pulse on START bit to initiate conversion
set START ; reset A/D
clr START ; start A/D
clr ADF ; clear ADC interrupt request flag
set
ADE; enable ADC interrupt
set EMI ; enable global interrupt
:
:
; ADC interrupt service routine
ADC_ISR:
mov acc_stack,a ; save ACC to user defined memory
mov a,STATUS
mov status_stack,a ; save STATUS to user defined memory
:
:
mov a,SADOL ; read low byte conversion result value
mov SADOL_buffer,a ; save result to user defined register
mov a,SADOH ; read high byte conversion result value
mov SADOH_buffer,a ; save result to user defined register
:
:
EXIT_INT_ISR:
mov a,status_stack
mov STATUS,a ; restore STATUS from user defined memory
mov a,acc_stack ; restore ACC from user defined memory
reti
Rev. 1.00
114
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Serial Interface Module – SIM
The device contains a Serial Interface Module, which includes both the four-line SPI interface or
two-line I2C interface types, to allow an easy method of communication with external peripheral
hardware. Having relatively simple communication protocols, these serial interface types allow
the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or
EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins and therefore the
SIM interface functional pins must first be selected using the corresponding pin-shared function
selection bits. As both interface types share the same pins and registers, the choice of whether the
SPI or I2C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in
the SIMC0 register. These pull-high resistors of the SIM pin-shared I/O pins are selected using pullhigh control registers when the SIM function is enabled and the corresponding pins are used as SIM
input pins.
SPI Interface
The SPI interface is often used to communicate with external peripheral devices such as sensors,
Flash or EEPROM memory devices, etc. Originally developed by Motorola, the four line SPI
interface is a synchronous serial data interface that has a relatively simple communication protocol
simplifying the programming requirements when communicating with external hardware devices.
The communication is full duplex and operates as a slave/master type, where the devices can be
either master or slave. Although the SPI interface specification can control multiple slave devices
from a single master, these devices provided only one SCS pin. If the master needs to control
multiple slave devices from a single master, the master can use I/O pin to select the slave devices.
SPI Interface Operation
The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin
names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data
Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins
are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface pins must first
be selected by configuring the pin-shared function selection bits and setting the correct bits in the
SIMC0 and SIMC2 registers. After the desired SPI configuration has been set it can be disabled or
enabled using the SIMEN bit in the SIMC0 register. Communication between devices connected
to the SPI interface is carried out in a slave/master mode with all data transfer initiations being
implemented by the master. The Master also controls the clock signal. As the device only contains
a single SCS pin only one slave device can be utilized. The SCS pin is controlled by software, set
CSEN bit to 1 to enable SCS pin function, set CSEN bit to 0 the SCS pin will be floating state.
The SPI function in this device offers the following features:
• Full duplex synchronous data transfer
• Both Master and Slave modes
• LSB first or MSB first data transmission modes
• Transmission complete flag
• Rising or falling active clock edge
The status of the SPI interface pins is determined by a number of factors such as whether the device
is in the master or slave mode and upon the condition of certain control bits such as CSEN and
SIMEN.
Rev. 1.00
115
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
SPI Master/Slave Connection

  €  ‚ ƒ € ƒ €  
  ­
 ‚ ƒ SPI Block Diagram
SPI Registers
There are three internal registers which control the overall operation of the SPI interface. These are
the SIMD data register and two registers SIMC0 and SIMC2. Note that the SIMC1 register is only
used by the I2C interface.
Bit
Register
Name
7
6
5
4
SIMC0
SIM2
SIM1
SIM0
—
SIMC2
D7
D6
CKPOLB
CKEG
MLS
SIMD
D7
D6
D5
D4
D3
3
2
1
0
SIMEN
SIMICF
CSEN
WCOL
TRF
D2
D1
D0
SIMDBNC1 SIMDBNC0
SPI Registers List
SIMD Register
The SIMD register is used to store the data being transmitted and received. The same register is used
by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to
be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the
device can read it from the SIMD register. Any transmission or reception of data from the SPI bus
must be made via the SIMD register.
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
“x”: unknown
Rev. 1.00
116
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2
register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used
by the SPI function, only by the I2C function. Register SIMC0 is used to control the enable/disable
function and to set the data transmission clock frequency. Register SIMC2 is used for other control
functions such as LSB/MSB selection, write collision flag, etc.
SIMC0 Register
Bit
7
6
5
4
Name
SIM2
SIM1
SIM0
—
R/W
R/W
R/W
R/W
—
R/W
POR
1
1
1
—
0
Bit 7~5
Rev. 1.00
3
2
1
0
SIMEN
SIMICF
R/W
R/W
R/W
0
0
0
SIMDBNC1 SIMDBNC0
SIM2~SIM0: SIM Operating Mode Control
000: SPI master mode; SPI clock is fSYS/4
001: SPI master mode; SPI clock is fSYS/16
010: SPI master mode; SPI clock is fSYS/64
011: SPI master mode; SPI clock is fSUB
100: SPI master mode; SPI clock is PTM CCRP match frequency/2
101: SPI slave mode
110: I2C slave mode
111: Non SIM function
These bits setup the overall operating mode of the SIM function. As well as selecting
if the I2C or SPI function, they are used to control the SPI Master/Slave selection and
the SPI Master clock frequency. The SPI clock is a function of the system clock or
fSUB but can also be chosen to be sourced from PTM. If the SPI Slave Mode is selected
then the clock will be supplied by an external Master device.
Bit 4
Unimplemented, read as “0”
Bit 3~2
SIMDBNC1~SIMDBNC0: I2C Debounce Time Selection
00: No debounce
01: 2 system clock debounce
1x: 4 system clock debounce
Bit 1
SIMEN: SIM Enable Control
0: Disable
1: Enable
The bit is the overall on/off control for the SIM interface. When the SIMEN bit is
cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and
SCL lines will lose their SPI or I2C function and the SIM operating current will be
reduced to a minimum value. When the bit is high the SIM interface is enabled. The
SIM configuration option must have first enabled the SIM interface for this bit to be
effective.If the SIM is configured to operate as an SPI interface via the SIM2~SIM0
bits, the contents of the SPI control registers will remain at the previous settings when
the SIMEN bit changes from low to high and should therefore be first initialised by
the application program. If the SIM is configured to operate as an I2C interface via the
SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C
control bits such as HTX and TXAK will remain at the previous settings and should
therefore be first initialised by the application program while the relevant I2C flags
such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states.
117
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Bit 0
SIMICF: SIM Incomplete Flag
0: SIM incomplete condition not occurred
1: SIM incomplete condition occured
This bit is only available when the SIM is configured to operate in an SPI slave mode.
If the SPI operates in the slave mode with the SIMEN and CSEN bits both being set
to 1 but the SCS line is pulled high by the external master device before the SPI data
transfer is completely finished, the SIMICF bit will be set to 1 together with the TRF
bit. When this condition occurs, the corresponding interrupt will occur if the interrupt
function is enabled. However, the TRF bit will not be set to 1 if the SIMICF bit is set
to 1 by software application program.
SIMC2 Register
Bit
Rev. 1.00
7
6
5
4
3
2
1
0
Name
D7
D6
CKPOLB
CKEG
MLS
CSEN
WCOL
TRF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
Undefined bits
These bits can be read or written by the application program.
Bit 5
CKPOLB: SPI clock line base condition selection
0: The SCK line will be high when the clock is inactive.
1: The SCK line will be low when the clock is inactive.
The CKPOLB bit determines the base condition of the clock line, if the bit is high,
then the SCK line will be low when the clock is inactive. When the CKPOLB bit is
low, then the SCK line will be high when the clock is inactive.
Bit 4
CKEG: SPI SCK clock active edge type selection
CKPOLB=0
0: SCK is high base level and data capture at SCK rising edge
1: SCK is high base level and data capture at SCK falling edge
CKPOLB=1
0: SCK is low base level and data capture at SCK falling edge
1: SCK is low base level and data capture at SCK rising edge
The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs
and inputs data on the SPI bus. These two bits must be configured before data transfer
is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit
determines the base condition of the clock line, if the bit is high, then the SCK line
will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK
line will be high when the clock is inactive. The CKEG bit determines active clock
edge type which depends upon the condition of CKPOLB bit.
Bit 3
MLS: SPI data shift order
0: LSB first
1: MSB first
This is the data shift select bit and is used to select how the data is transferred, either
MSB or LSB first. Setting the bit high will select MSB first and low for LSB first.
Bit 2
CSEN: SPI SCS pin control
0: Disable
1: Enable
The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the
SCS pin will be disabled and placed into I/O pin or other pin-shared functions. If the
bit is high, the SCS pin will be enabled and used as a select pin.
118
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Bit 1
WCOL: SPI write collision flag
0: No collision
1: Collision
The WCOL flag is used to detect whether a data collision has occurred or not. If this
bit is high, it means that data has been attempted to be written to the SIMD register
duting a data transfer operation. This writing operation will be ignored if data is being
transferred. This bit can be cleared by the application program.
Bit 0
TRF: SPI Transmit/Receive complete flag
0: SPI data is being transferred
1: SPI data transfer is completed
The TRF bit is the Transmit/Receive Complete flag and is set to 1 automatically when
an SPI data transfer is completed, but must cleared to 0 by the application program. It
can be used to generate an interrupt.
SPI Communication
After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when
data is written to the SIMD register, transmission/reception will begin simultaneously. When the
data transfer is complete, the TRF flag will be set automatically, but must be cleared using the
application program. In the Slave Mode, when the clock signal from the master has been received,
any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into
the SIMD register. The master should output a SCS signal to enable the slave devices before a
clock signal is provided. The slave data to be transferred should be well prepared at the appropriate
moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG
bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal
for various configurations of the CKPOLB and CKEG bits.
The SPI master mode will continue to function even in the IDLE Mode if the selected SPI clock
source is running.
          ­
 €  ‚
 ‚  €
 ­    
  
         ­
 €  ‚
 ‚  €
 ­    
  
   ƒ „ 
SPI Master Mode Timing
Rev. 1.00
119
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
        ­€   SPI Slave Mode Timing – CKEG=0
               ­  €‚   € ƒ „ …  ‚ † ‡ ˆ ‰€  Š ƒ  ˆ Š ƒ ‰  ‚ ‹   Œ ‚ ˆ
 ˆ     ‚ † ‚Ž
SPI Slave Mode Timing – CKEG=1
Rev. 1.00
120
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM

  †‡ ˆ‰ Š ‰ ‰ ‰ „
‰ ‰ „‰ ‰ „‰ ‰ ‰  †‡ ˆ‰ Š ‰ ­ € ‚ ƒ „
‚ … „  
 

   SPI Transfer Control Flow Chart
Rev. 1.00
121
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
I2C Interface
The I 2C interface is used to communicate with external peripheral devices such as sensors,
EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface
for synchronous serial data transfer. The advantage of only two lines for communication, relatively
simple communication protocol and the ability to accommodate multiple devices on the same bus
has made it an extremely popular interface type for many applications.
I2C Master/Slave Bus Connection
I2C interface Operation
The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As
many devices may be connected together on the same bus, their outputs are both open drain types.
For this reason it is necessary that external pull-high resistors are connected to these outputs. Note
that no chip select line exists, as each device on the I2C bus is identified by a unique address which
will be transmitted and received on the I2C bus.
When two devices communicate with each other on the bidirectional I2C bus, one is known as the
master device and one as the slave device. Both master and slave can transmit and receive data,
however, it is the master device that has overall control of the bus. For these devices, which only
operate in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit
mode and the slave receive mode.
  Ž ‰
    „
ˆ  † ‡ ‡ ­ …
‰ Š
‹
‰ Œ
Rev. 1.00
      „ ­ ‚ ƒ  €
   122
 ­   
„ April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
S T A R T s ig n a l
fro m M a s te r
S e n d s la v e a d d r e s s
a n d R /W b it fr o m M a s te r
A c k n o w le d g e
fr o m s la v e
S e n d d a ta b y te
fro m M a s te r
A c k n o w le d g e
fr o m s la v e
S T O P s ig n a l
fro m M a s te r
The SIMDBNC1 and SIMDBNC0 bits determine the debounce time of the I2C interface. This uses
the system clock to in effect add a debounce time to the external clock to reduce the possibility
of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be
chosen to be either 2 or 4 system clocks. To achieve the required I2C data transfer speed, there
exists a relationship between the system clock, fSYS, and the I2C debounce time. For either the I2C
Standard or Fast mode operation, users must take care of the selected system clock frequency and
the configured debounce time to match the criterion shown in the following table.
I2C Debounce Time Selection
I2C Standard Mode (100kHz)
I2C Fast Mode (400kHz)
No Devounce
fSYS > 2 MHz
fSYS > 5 MHz
2 system clock debounce
fSYS > 4 MHz
fSYS > 10 MHz
fSYS > 8 MHz
fSYS > 20 MHz
4 system clock debounce
I C Minimum fSYS Frequency
2
I2C Registers
There are three control registers associated with the I2C bus, SIMC0, SIMC1 and SIMTOC, one
slave address register, SIMA, and one data register, SIMD. The SIMD register, which is shown in
the above SPI section, is used to store the data being transmitted and received on the I2C bus. Before
the microcontroller writes data to the I2C bus, the actual data to be transmitted must be placed in the
SIMD register. After the data is received from the I2C bus, the microcontroller can read it from the
SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD
register.
Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN
and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface.
Bit
Register
Name
7
SIMC0
SIMC1
6
5
4
SIM2
SIM1
SIM0
—
HCF
HAAS
HBB
HTX
TXAK
SRW
SIMA
A6
A5
A4
A3
A2
A1
A0
—
SIMD
D7
D6
D5
D4
D3
D2
D1
D0
SIMTOC SIMTOEN SIMTOF SIMTOS5 SIMTOS4
3
2
SIMDBNC1 SIMDBNC0
SIMTOS3
1
0
SIMEN
SIMICF
IAMWU
RXAK
SIMTOS2 SIMTOS1 SIMTOS0
I2C Registers List
Rev. 1.00
123
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
SIMD Register
The SIMD register is used to store the data being transmitted and received. The same register is used
by both the SPI and I2C functions. Before the device writes data to the I2C bus, the actual data to
be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the
device can read it from the SIMD register. Any transmission or reception of data from the I2C bus
must be made via the SIMD register.
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
“x”: unknown
SIMA Register
The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is
the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register
define the device slave address. Bit 0 is not defined.
When a master device, which is connected to the I2C bus, sends out an address, which matches the
slave address in the SIMA register, the slave device will be selected. Note that the SIMA register is
the same register address as SIMC2 which is used by the SPI interface.
Bit
7
6
5
4
3
2
1
0
Name
A6
A5
A4
A3
A2
A1
A0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
POR
0
0
0
0
0
0
0
—
Bit 7~1
A6~A0: I C slave address
A6~A0 is the I2C slave address bit 6~bit 0
Bit 0
Unimplemented, read as “0”
2
There are also three control registers for the I2C interface, SIMC0, SIMC1 and SIMTOC. The
register SIMC0 is used to control the enable/disable function and to set the data transmission
clock frequency.The SIMC1 register contains the relevant flags which are used to indicate the I2C
communication status. The SIMTOC register is used to control the I2C bus time-out function which
is described in the I2C Time-out Control section.
Rev. 1.00
124
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
SIMC0 Register
Bit
7
6
5
4
Name
SIM2
SIM1
SIM0
—
R/W
R/W
R/W
R/W
—
R/W
POR
1
1
1
—
0
Bit 7~5
Rev. 1.00
3
2
1
0
SIMEN
SIMICF
R/W
R/W
R/W
0
0
0
SIMDBNC1 SIMDBNC0
SIM2~SIM0: SIM Operating Mode Control
000: SPI master mode; SPI clock is fSYS/4
001: SPI master mode; SPI clock is fSYS/16
010: SPI master mode; SPI clock is fSYS/64
011: SPI master mode; SPI clock is fSUB
100: SPI master mode; SPI clock is PTM CCRP match frequency/2
101: SPI slave mode
110: I2C slave mode
111: Non SIM function
These bits setup the overall operating mode of the SIM function. As well as selecting
if the I2C or SPI function, they are used to control the SPI Master/Slave selection and
the SPI Master clock frequency. The SPI clock is a function of the system clock or
fSUB but can also be chosen to be sourced from PTM. If the SPI Slave Mode is selected
then the clock will be supplied by an external Master device.
Bit 4
Unimplemented, read as “0”
Bit 3~2
SIMDBNC1~SIMDBNC0: I2C Debounce Time Selection
00: No debounce
01: 2 system clock debounce
1x: 4 system clock debounce
Bit 1
SIMEN: SIM Enable Control
0: Disable
1: Enable
The bit is the overall on/off control for the SIM interface. When the SIMEN bit is
cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and
SCL lines will lose their SPI or I2C function and the SIM operating current will be
reduced to a minimum value. When the bit is high the SIM interface is enabled. The
SIM configuration option must have first enabled the SIM interface for this bit to be
effective.If the SIM is configured to operate as an SPI interface via the SIM2~SIM0
bits, the contents of the SPI control registers will remain at the previous settings when
the SIMEN bit changes from low to high and should therefore be first initialised by
the application program. If the SIM is configured to operate as an I2C interface via the
SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C
control bits such as HTX and TXAK will remain at the previous settings and should
therefore be first initialised by the application program while the relevant I2C flags
such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states.
Bit 0
SIMICF: SIM Incomplete Flag
0: SIM incomplete condition not occurred
1: SIM incomplete condition occured
This bit is only available when the SIM is configured to operate in an SPI slave mode.
If the SPI operates in the slave mode with the SIMEN and CSEN bits both being set
to 1 but the SCS line is pulled high by the external master device before the SPI data
transfer is completely finished, the SIMICF bit will be set to 1 together with the TRF
bit. When this condition occurs, the corresponding interrupt will occur if the interrupt
function is enabled. However, the TRF bit will not be set to 1 if the SIMICF bit is set
to 1 by software application program.
125
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
SIMC1 Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
HCF
HAAS
HBB
HTX
TXAK
SRW
IAMWU
RXAK
R/W
R
R
R
R/W
R/W
R/W
R/W
R
POR
1
0
0
0
0
0
0
1
Bit 7
HCF: I C Bus data transfer completion flag
0: Data is being transferred
1: Completion of an 8-bit data transfer
The HCF flag is the data transfer flag. This flag will be zero when data is being
transferred. Upon completion of an 8-bit data transfer the flag will go high and an
interrupt will be generated.
Bit 6
HAAS: I2C Bus data transfer completion flag
0: Not address match
1: Address match
The HAAS flag is the address match flag. This flag is used to determine if the slave
device address is the same as the master transmit address. If the addresses match then
this bit will be high, if there is no match then the flag will be low.
Bit 5
HBB: I2C Bus busy flag
0: I2C Bus is not busy
1: I2C Bus is busy
The HBB flag is the I2C busy flag. This flag will be “1” when the I2C bus is busy
which will occur when a START signal is detected. The flag will be set to “0” when
the bus is free which will occur when a STOP signal is detected.
Bit 4
HTX: I2C slave device transmitter/receiver selection
0: Slave device is the receiver
1: Slave device is the transmitter
Bit 3
TXAK: I2C bus transmit acknowledge flag
0: Slave send acknowledge flag
1: Slave does not send acknowledge flag
The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits
of data, this bit will be transmitted to the bus on the 9th clock from the slave device.
The slave device must always set TXAK bit to “0” before further data is received.
Bit 2
SRW: I2C slave read/write flag
0: Slave device should be in receive mode
1: Slave device should be in transmit mode
The SRW flag is the I 2C Slave Read/Write flag. This flag determines whether
the master device wishes to transmit or receive data from the I2C bus. When the
transmitted address and slave address is match, that is when the HAAS flag is set high,
the slave device will check the SRW flag to determine whether it should be in transmit
mode or receive mode. If the SRW flag is high, the master is requesting to read data
from the bus, so the slave device should be in transmit mode. When the SRW flag
is zero, the master will write data to the bus, therefore the slave device should be in
receive mode to read this data.
Bit 1
IAMWU: I2C Address Match Wake-Up control
0: Disable
1: Enable – must be cleared by the application program after wake-up
This bit should be set to 1 to enable the I2C address match wake up from the SLEEP
or IDLE Mode. If the IAMWU bit has been set before entering either the SLEEP or
IDLE mode to enable the I2C address match wake up, then this bit must be cleared by
the application program after wake-up to ensure correction device operation.
2
126
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Bit 0
RXAK: I2C bus receive acknowledge flag
0: Slave receives acknowledge flag
1: Slave does not receive acknowledge flag
The RXAK flag is the receiver acknowledge flag. When the RXAK flag is “0”, it
means that a acknowledge signal has been received at the 9th clock, after 8 bits of data
have been transmitted. When the slave device in the transmit mode, the slave device
checks the RXAK flag to determine if the master receiver wishes to receive the next
byte. The slave transmitter will therefore continue sending out data until the RXAK
flag is “1”. When this occurs, the slave transmitter will release the SDA line to allow
the master to send a STOP signal to release the I2C Bus.
I2C Bus Communication
Communication on the I2C bus requires four separate steps, a START signal, a slave device address
transmission, a data transmission and finally a STOP signal. When a START signal is placed on
the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of
data on the bus. The first seven bits of the data will be the slave address with the first bit being the
MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the
SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service
routine, the slave device must first check the condition of the HAAS and SIMTOF bits to determine
whether the interrupt source originates from an address match, 8-bit data transfer completion or
I2C bus time-out occurrence. During a data transfer, note that after the 7-bit slave address has been
transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in
the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or
receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise
the bus, the following are steps to achieve this:
• Step 1
Set the SIM2~SIM0 bits to “110” and SIMEN bit to “1” in the SIMC0 register to enable the I2C
bus.
• Step 2
Write the slave address of the device to the I2C bus address register SIMA.
• Step 3
Set the SIME interrupt enable bit of the interrupt control register to enable the SIM interrupt.
Rev. 1.00
127
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Sta�t
Set SIM[�:0]=110
Set SIMEN
W�ite S�ave
�dd�ess to SIM�
No
Yes
I�C Bus
Inte��u�t=?
CLR SIME
Po�� SIMF to decide when
to go to I�C Bus ISR
SET SIME and
Wait fo� Inte��u�t
Goto Main P�og�am
Goto Main P�og�am
I2C Bus Initialisation Flow Chart
I2C Bus Start Signal
The START signal can only be generated by the master device connected to the I2C bus and not by
the slave device. This START signal will be detected by all devices connected to the I2C bus. When
detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START
condition occurs when a high to low transition on the SDA line takes place when the SCL line
remains high.
I2C Slave Address
The transmission of a START signal by the master will be detected by all devices on the I2C bus.
To determine which slave device the master wishes to communicate with, the address of the slave
device will be sent out immediately following the START signal. All slave devices, after receiving
this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by
the master matches the internal address of the microcontroller slave device, then an internal I2C bus
interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines
the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will
then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set
the status flag HAAS when the addresses match.
As an I2C bus interrupt can come from three sources, when the program enters the interrupt
subroutine, the HAAS and SIMTOF bits should be examined to see whether the interrupt source has
come from a matching slave address, the completion of a data byte transfer or the I2C bus time-out
occurrence. When a slave address is matched, the devices must be placed in either the transmit mode
and then write data to the SIMD register, or in the receive mode where it must implement a dummy
read from the SIMD register to release the SCL line.
I2C Bus Read/Write Signal
The SRW bit in the SIMC1 register defines whether the master device wishes to read data from the
I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to
be a transmitter or a receiver. If the SRW flag is “1” then this indicates that the master device wishes
to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as
a transmitter. If the SRW flag is “0” then this indicates that the master wishes to send data to the I2C
bus, therefore the slave device must be setup to read data from the I2C bus as a receiver.
Rev. 1.00
128
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
I2C Bus Slave Address Acknowledge Signal
After the master has transmitted a calling address, any slave device on the I 2C bus, whose
own internal address matches the calling address, must generate an acknowledge signal. The
acknowledge signal will inform the master that a slave device has accepted its calling address. If no
acknowledge signal is received by the master then a STOP signal must be transmitted by the master
to end the communication. When the HAAS flag is high, the addresses have matched and the slave
device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag
is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register
should be set to “1”. If the SRW flag is low, then the microcontroller slave device should be setup as
a receiver and the HTX bit in the SIMC1 register should be set to “0”.
I2C Bus Data and Acknowledge Signal
The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged
receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last.
After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level “0”, before
it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal
from the master receiver, then the slave transmitter will release the SDA line to allow the master
to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the SIMD
register. If setup as a transmitter, the slave device must first write the data to be transmitted into the
SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD
register.
When the slave receiver receives the data byte, it must generate an acknowledge bit, known as
TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit
in the SIMC1 register to determine if it is to send another data byte, if not then it will release the
SDA line and await the receipt of a STOP signal from the master.
€

€

­
         ­ Note: *When a slave address is matched, the devices must be placed in either the transmit mode
and then write data to the SIMD register, or in the receive mode where it must implement a
dummy read from the SIMD register to release the SCL line.
I2C Communication Timing Diagram
Rev. 1.00
129
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
     
            I2C Bus ISR Flow Chart
I2C Time-out Control
In order to reduce the I2C lockup problem due to reception of erroneous clock sources, a time-out
function is provided. If the clock source connected to the I2C bus is not received for a while, then the
I2C circuitry and registers will be reset after a certain time-out period. The time-out counter starts to
count on an I2C bus “START” & “address match”condition, and is cleared by an SCL falling edge.
Before the next SCL falling edge arrives, if the time elapsed is greater than the time-out period
specified by the SIMTOC register, then a time-out condition will occur. The time-out function will
stop when an I2C “STOP” condition occurs.
Rev. 1.00
130
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
S ta rt
S C L
S R W
S la v e A d d r e s s
0
1
S D A
1
1
0
1
0
A C K
1
0
I2 C t i m e - o u t
c o u n te r s ta rt
S to p
S C L
1
0
0
1
0
1
0
0
S D A
I2 C t im e - o u t c o u n t e r r e s e t
o n S C L n e g a tiv e tr a n s itio n
I2C Time-out
When an I2C time-out counter overflow occurs, the counter will stop and the SIMTOEN bit will
be cleared to zero and the SIMTOF bit will be set high to indicate that a time-out condition has
occurred. The time-out condition will also generate an interrupt which uses the I2C interrrupt vector.
When an I2C time-out occurs, the I2C internal circuitry will be reset and the registers will be reset
into the following condition:
Register
After I2C Time-out
SIMD, SIMA, SIMC0
No change
SIMC1
Reset to POR condition
I2C Register after Time-out
The SIMTOF flag can be cleared by the application program. There are 64 time-out period selections
which can be selected using the SIMTOS bits in the SIMTOC register. The time-out duration is
calculated by the formula: ((1~64) × (32/fSUB)). This gives a time-out period which ranges from
about 1ms to 64ms.
SIMTOC Register
Rev. 1.00
Bit
7
Name
SIMTOEN
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0
Bit 7
SIMTOEN: SIM I C Time-out function control
0: Disable
1: Enable
Bit 6
SIMTOF: SIM I2C Time-out flag
0: No time-out occurred
1: Time-out occurred
Bit 5~0
SIMTOS5~SIMTOS0: SIM I2C Time-out period selection
I2C Time-out clock source is fSUB/32
I2C Time-out period is equal to (SIMTOS[5:0] + 1) × (32/fSUB)
2
131
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Comparator
An analog comparator is contained within the device. The comparator function offers flexibility
via their register controlled features such as power-down, polarity select, hysteresis etc. In sharing
their pins with normal I/O pins the comparators do not waste precious I/O pins if there functions are
otherwise unused.
Comparator
Comparator Operation
The device contains a comparator function which is used to compare two analog voltages and
provide an output based on their difference. Full control over the internal comparators is provided
via the control register CPC assigned to the comparator. The comparator output is recorded via a bit
in the control register, but can also be transferred out onto a shared I/O pin. Additional comparator
functions include, output polarity, hysteresis functions and power down control.
Any pull-high resistors connected to the shared comparator input pins will be automatically
disconnected when the comparator is enabled. As the comparator inputs approach their switching
level, some spurious output signals may be generated on the comparator output due to the slow
rising or falling nature of the input signals. This can be minimised by selecting the hysteresis
function will apply a small amount of positive feedback to the comparator. Ideally the comparator
should switch at the point where the positive and negative inputs signals are at the same voltage
level, however, unavoidable input offsets introduce some uncertainties here. The hysteresis function,
if enabled, also increases the switching offset value.
Comparator Interrupt
The comparator possesses its own interrupt function. When the comparator output bit changes state,
its relevant interrupt flag will be set, and if the corresponding interrupt enable bit is set, then a jump
to its relevant interrupt vector will be executed. A choice of either rising or falling or both edge types
can be chosen to trigger a comparator interrupt. Note that it is the changing state of the COUT bit
and not the output pin which generates an interrupt. If the microcontroller is in the SLEEP or IDLE
Mode and the Comparator is enabled, then if the external input lines cause the Comparator output to
change state, the resulting generated interrupt flag will also generate a wake-up. If it is required to
disable a wake-up from occurring, then the interrupt flag should be first set high before entering the
SLEEP or IDLE Mode.
Programming Considerations
If the comparator is enabled, it will remain active when the microcontroller enters the SLEEP or
IDLE Mode, however as it will consume a certain amount of power, the user may wish to consider
disabling it before the SLEEP or IDLE Mode is entered. As comparator pins are shared with normal
I/O pins the I/O registers for these pins will be read as zero (port control register is “1”) or read as
port data register value (port control register is “0”) if the comparator function is enabled.
Rev. 1.00
132
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
CPC Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
CSEL
CEN
CPOL
COUT
COS
CINTE1
CINTE0
CHYEN
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
POR
1
0
0
0
0
0
0
1
Bit 7
CSEL: Select Comparator pins or I/O pins
0: I/O pin selected
1: Comparator input pin C+ and C- selected
This is the Comparator input pin or I/O pin select bit. If the bit is high the comparator
input pins will be enabled. As a result, these two pins will lose their I/O pin functions.
Any pull-high configuration options associated with the comparator shared pins will
also be automatically disconnected.
Bit 6
CEN: Comparator On/Off control
0: Off
1: On
This is the Comparator on/off control bit. If the bit is zero the comparator will be
switched off and no power consumed even if analog voltages are applied to its inputs.
For power sensitive applications this bit should be cleared to zero if the comparator is
not used or before the device enters the SLEEP or IDLE mode.
Bit 5
CPOL: Comparator output polarity
0: output not inverted
1: output inverted
This is the comparator polarity bit. If the bit is zero then the COUT bit will reflect
the non-inverted output condition of the comparator. If the bit is high the comparator
COUT bit will be inverted.
Bit 4
COUT: Comparator output bit
CPOL=0
0: C+ < C1: C+ > CCPOL=1
0: C+ > C1: C+ < CThis bit stores the comparator output bit. The polarity of the bit is determined by the
voltages on the comparator inputs and by the condition of the CPOL bit.
Bit 3
COS: Output path select
0: CX pin (compare output can output to CX pin)
1: I/O pin select (compare output only internal use)
Bit 2~1
CINTE1~CINTE0: Interrupt edge control
00: Rising edge → comparator interrupt trigger signal generated if COUT changed
state from 0 to 1
01: Falling edge → comparator interrupt trigger signal generated if COUT changed
state from 1 to 0
1x: Rising edge and falling edge → comparator interrupt trigger signal generated if
COUT changed state from 0 to 1 or 1 to 0
Bit 0
CHYEN: Hysteresis Control
0: Off
1: On
This is the hysteresis control bit and if set high will apply a limited amount of
hysteresis to the comparator, as specified in the Comparator Electrical Characteristics
table. The positive feedback induced by hysteresis reduces the effect of spurious
switching near the comparator threshold.
133
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
SCOM Function for LCD
The device has the capability of driving external LCD panels. The common pins for LCD driving,
SCOM0~SCOM3, are pin shared with the I/O pins. The LCD signals (COM and SEG) are generated
using the application program.
LCD Operation
An external LCD panel can be driven using this device by configuring the I/O pins as common pins
and using other output ports lines as segment pins. The LCD driver function is controlled using the
SCOMC register which in addition to controlling the overall on/off function also controls the bias
voltage setup function. This enables the LCD COM driver to generate the necessary VDD/2 voltage
levels for LCD 1/2 bias operation.
LCD COM Bias
The SCOMEN bit in the SCOMC register is the overall master control for the LCD driver; however
this bit is used in conjunction with the COMnEN bits to select which I/O pins are used for LCD
driving. Note that the Port Control register does not need to first setup the pins as outputs to enable
the LCD driver operation.
SCOMEN
COMnEN
Pin Function
O/P Level
0
x
I/O
0 or 1
1
0
I/O
0 or 1
1
1
SCOMn
VDD/2
Output Control
LCD Bias Control
The LCD COM driver enables a range of selections to be provided to suit the requirement of the
LCD panel which is being used. The bias resistor choice is implemented using the ISEL1 and ISEL0
bits in the SCOMC register.
Rev. 1.00
134
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
SCOMC Register
Rev. 1.00
Bit
7
6
5
Name
—
ISEL1
ISEL0
4
3
2
1
0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
SCOMEN COM3EN COM2EN COM1EN COM0EN
Bit 7
Unimplemented, read as “0”
Bit 6~5
ISEL1~ISEL0: Select R type LCD typical bias current (VDD=5V)
00: 25μA
01: 50μA
10: 100μA
11: 200μA
Bit 4
SCOMEN: LCD control bit
0: Disable
1: Enable
When SCOMEN is set, it will turn on the DC path of resistor to generate 1/2 VDD bias
voltage.
Bit 3
COM3EN: SCOM3 or other pin function selection
0: Other pin-shared functions
1: SCOM3
Bit 2
COM2EN: SCOM2 or other pin function selection
0: Other pin-shared functions
1: SCOM2
Bit 1
COM1EN: SCOM1 or other pin function selection
0: Other pin-shared functions
1: SCOM1
Bit 0
COM0EN: SCOM0 or other pin function selection
0: Other pin-shared functions
1: SCOM0
135
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
UART Interface
The device contains an integrated full-duplex asynchronous serial communications UART interface
that enables communication with external devices that contain a serial interface. The UART function
has many features and can transmit and receive data serially by transferring a frame of data with
eight or nine data bits per transmission as well as being able to detect errors when the data is
overwritten or incorrectly framed. The UART function possesses its own internal interrupt which
can be used to indicate when a reception occurs or when a transmission terminates.
The integrated UART function contains the following features:
• Full-duplex, asynchronous communication
• 8 or 9 bits character length
• Even, odd or no parity options
• One or two stop bits
• Baud rate generator with 8-bit prescaler
• Parity, framing, noise and overrun error detection
• Support for interrupt on address detect (last character bit=1)
• Separately enabled transmitter and receiver
• 2-byte Deep FIFO Receive Data Buffer
• Transmit and receive interrupts
• Interrupts can be initialized by the following conditions:
♦♦
Transmitter Empty
♦♦
Transmitter Idle
♦♦
Receiver Full
♦♦
Receiver Overrun
♦♦
Address Mode Detect
♦♦
RX enable, RX falling edge
T�ansmitte� Shift Registe� (TSR)
MSB
…………………………
Receive� Shift Registe� (RSR)
LSB
TX Pin
TX Registe� (TXR)
fSYS
RX Pin
MSB
LSB
RX Registe� (RXR)
Baud Rate
Gene�ato�
Data to be t�ansmitted
…………………………
Buffe�
Data �eceived
MCU Data Bus
UART Data Transfer Block Diagram
Rev. 1.00
136
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
UART External Pins
To communicate with an external serial interface, the internal UART has two external pins known
as TX and RX. The TX pin is the UART transmitter pin, which can be used as a general purpose I/O
or other pin-shared functions if the pin is not configured as a UART transmitter pin, which occurs
when the TXEN bit in the UCR2 control register is equal to zero. Similarly, the RX pin is the UART
receiver pin, which can also be used as a general purpose I/O pin, if the pin is not configured as a
receiver pin, which occurs if the RXEN bit in the UCR2 register is equal to zero. Along with the
UARTEN bit, the TXEN and RXEN bits, if set, will automatically setup these I/O pins or other pinshared functional to their respective TX output and RX input conditions and disable any pull-high
resistor option which may exist on the TX and RX pins. When the TX or RX pin function is disabled
by clearing the UARTEN, TXEN or RXEN bit, the TX or RX pin will be used as I/O or other pinshared functional pin depending upon the pin-shared function priority.
UART Data Transfer Scheme
The block diagram shows the overall data transfer structure arrangement for the UART interface.
The actual data to be transmitted from the MCU is first transferred to the TXR register by the
application program. The data will then be transferred to the Transmit Shift Register from where it
will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only
the TXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped
and is therefore inaccessible to the application program.
Data to be received by the UART is accepted on the external RX pin, from where it is shifted in,
LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When
the shift register is full, the data will then be transferred from the shift register to the internal RXR
register, where it is buffered and can be manipulated by the application program. Only the RXR
register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is
therefore inaccessible to the application program.
It should be noted that the actual register for data transmission and reception, although referred to
in the text, and in application programs, as separate TXR and RXR registers, only exists as a single
shared register in the Data Memory. This shared register known as the TXR_RXR register is used
for both data transmission and data reception.
UART Status and Control Registers
There are five control registers associated with the UART function. The USR, UCR1 and UCR2
registers control the overall function of the UART, while the BRG register controls the Baud rate.
The actual data to be transmitted and received on the serial interface is managed through the TXR_
RXR data register.
Bit
Register
Name
7
6
5
4
3
2
1
0
USR
PERR
NF
FERR
OERR
RIDLE
RXIF
TIDLE
TXIF
UCR1
UARTEN
BNO
PREN
PRT
STOPS
TXBRK
RX8
TX8
UCR2
TXEN
RXEN
BRGH
ADDEN
WAKE
RIE
TIIE
TEIE
TXR_RXR
TXRX7
TXRX6
TXRX5
TXRX4
TXRX3
TXRX2
TXRX1
TXRX0
BRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
UART Registers List
Rev. 1.00
137
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
TXR_RXR Register
The TXR_RXR register is the data register which is used to store the data to be transmitted on the
TX pin or being received from the RX pin.
Bit
7
6
5
4
3
2
1
0
Name
TXRX7
TXRX6
TXRX5
TXRX4
TXRX3
TXRX2
TXRX1
TXRX0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
“x”: unknown
Bit 7~0
TXRX7~TXRX0: UART Transmit/Receive Data bits
USR Register
The USR register is the status register for the UART, which can be read by the program to
determine the present status of the UART. All flags within the USR register are read only and further
explanations are given below:
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
PERR
NF
FERR
OERR
RIDLE
RXIF
TIDLE
TXIF
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
1
0
1
1
Bit 7
PERR: Parity error flag
0: No parity error is detected
1: Parity error is detected
The PERR flag is the parity error flag. When this read only flag is “0”, it indicates a
parity error has not been detected. When the flag is “1”, it indicates that the parity of
the received word is incorrect. This error flag is applicable only if Parity mode (odd or
even) is selected. The flag can also be cleared by a software sequence which involves
a read to the status register USR followed by an access to the RXR data register.
Bit 6
NF: Noise flag
0: No noise is detected
1: Noise is detected
The NF flag is the noise flag. When this read only flag is “0”, it indicates no noise
condition. When the flag is “1”, it indicates that the UART has detected noise on the
receiver input. The NF flag is set during the same cycle as the RXIF flag but will not
be set in the case of as overrun. The NF flag can be cleared by a software sequence
which will involve a read to the status register USR followed by an access to the RXR
data register.
Bit 5
FERR: Framing error flag
0: No framing error is detected
1: Framing error is detected
The FERR flag is the framing error flag. When this read only flag is “0”, it indicates
that there is no framing error. When the flag is “1”, it indicates that a framing error
has been detected for the current character. The flag can also be cleared by a software
sequence which will involve a read to the status register USR followed by an access to
the RXR data register.
Bit 4
OERR: Overrun error flag
0: No overrun error is detected
1: Overrun error is detected
The OERR flag is the overrun error flag which indicates when the receiver buffer has
overflowed. When this read only flag is “0”, it indicates that there is no overrun error.
When the flag is “1”, it indicates that an overrun error occurs which will inhibit further
transfers to the RXR receive data register. The flag is cleared by a software sequence,
which is a read to the status register USR followed by an access to the RXR data
register.
138
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Rev. 1.00
Bit 3
RIDLE: Receiver status
0: Data reception is in progress (data being received)
1: No data reception is in progress (receiver is idle)
The RIDLE flag is the receiver status flag. When this read only flag is “0”, it indicates
that the receiver is between the initial detection of the start bit and the completion of
the stop bit. When the flag is “1”, it indicates that the receiver is idle. Between the
completion of the stop bit and the detection of the next start bit, the RIDLE bit is “1”
indicating that the UART receiver is idle and the RX pin stays in logic high condition.
Bit 2
RXIF: Receive RXR data register status
0: RXR data register is empty
1: RXR data register has available data
The RXIF flag is the receive data register status flag. When this read only flag is “0”,
it indicates that the RXR read data register is empty. When the flag is “1”, it indicates
that the RXR read data register contains new data. When the contents of the shift
register are transferred to the RXR register, an interrupt is generated if RIE=1 in the
UCR2 register. If one or more errors are detected in the received word, the appropriate
receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The
RXIF flag is cleared when the USR register is read with RXIF set, followed by a read
from the RXR register, and if the RXR register has no data available.
Bit 1
TIDLE: Transmission status
0: Data transmission is in progress (data being transmitted)
1: No data transmission is in progress (transmitter is idle)
The TIDLE flag is known as the transmission complete flag. When this read only
flag is “0”, it indicates that a transmission is in progress. This flag will be set to “1”
when the TXIF flag is “1” and when there is no transmit data or break character being
transmitted. When TIDLE is equal to 1, the TX pin becomes idle with the pin state
in logic high condition. The TIDLE flag is cleared by reading the USR register with
TIDLE set and then writing to the TXR register. The flag is not generated when a data
character or a break is queued and ready to be sent.
Bit 0
TXIF: Transmit TXR data register status
0: Character is not transferred to the transmit shift register
1: Character has transferred to the transmit shift register (TXR data register is empty)
The TXIF flag is the transmit data register empty flag. When this read only flag is “0”,
it indicates that the character is not transferred to the transmitter shift register. When
the flag is “1”, it indicates that the transmitter shift register has received a character
from the TXR data register. The TXIF flag is cleared by reading the UART status
register (USR) with TXIF set and then writing to the TXR data register. Note that
when the TXEN bit is set, the TXIF flag bit will also be set since the transmit data
register is not yet full.
139
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
UCR1 Register
The UCR1 register together with the UCR2 register are the two UART control registers that are used
to set the various options for the UART function such as overall on/off control, parity control, data
transfer bit length, etc. Further explanation on each of the bits is given below:
Bit
7
6
5
4
3
2
1
0
Name
UARTEN
BNO
PREN
PRT
STOPS
TXBRK
RX8
TX8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
W
POR
0
0
0
0
0
0
x
0
“x”: unknown
Rev. 1.00
Bit 7
UARTEN: UART function enable control
0: Disable UART. TX and RX pins are used as I/O or other pin-shared functional pins
1: Enable UART. TX and RX pins function as UART pins
The UARTEN bit is the UART enable bit. When this bit is equal to “0”, the UART
will be disabled and the RX pin as well as the TX pin will be set as I/O or other pinshared functional pins. When the bit is equal to “1”, the UART will be enabled and
the TX and RX pins will function as defined by the TXEN and RXEN enable control
bits. When the UART is disabled, it will empty the buffer so any character remaining
in the buffer will be discarded. In addition, the value of the baud rate counter will be
reset. If the UART is disabled, all error and status flags will be reset. Also the TXEN,
RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF bits will be cleared, while the
TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2 and
BRG registers will remain unaffected. If the UART is active and the UARTEN bit is
cleared, all pending transmissions and receptions will be terminated and the module
will be reset as defined above. When the UART is re-enabled, it will restart in the
same configuration.
Bit 6
BNO: Number of data transfer bits selection
0: 8-bit data transfer
1: 9-bit data transfer
This bit is used to select the data length format, which can have a choice of either
8-bit or 9-bit format. When this bit is equal to “1”, a 9-bit data length format will be
selected. If the bit is equal to “0”, then an 8-bit data length format will be selected. If
9-bit data length format is selected, then bits RX8 and TX8 will be used to store the
9th bit of the received and transmitted data respectively.
Note: 1. If BNO=1(9-bit data transfer format) and when the parity function is enabled,
the 9th data is a parity bit since it will not be transferred to RX8.
2. If BNO=0(8-bit data transfer format) and when the parity function is enabled,
the 8th data is a parity bit since it will not be transferred to RX7.
Bit 5
PREN: Parity function enable control
0: Parity function is disabled
1: Parity function is enabled
This bit is the parity function enable bit. When this bit is equal to 1, the parity function
will be enabled. If the bit is equal to 0, then the parity function will be disabled.
Bit 4
PRT: Parity type selection bit
0: Even parity for parity generator
1: Odd parity for parity generator
This bit is the parity type selection bit. When this bit is equal to 1, odd parity type will
be selected. If the bit is equal to 0, then even parity type will be selected.
140
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Bit 3
STOPS: Number of stop bits selection
0: One stop bit format is used
1: Two stop bits format is used
This bit determines if one or two stop bits are to be used for TX. When this bit is equal
to “1”, two stop bits format are used. If the bit is equal to “0”, then only one stop bit
format is used.
Bit 2
TXBRK: Transmit break character
0: No break character is transmitted
1: Break characters transmit
The TXBRK bit is the Transmit Break Character bit. When this bit is equal to “0”,
there are no break characters and the TX pin operates normally. When the bit is
equal to “1”, there are transmit break characters and the transmitter will send logic
zeros. When this bit is equal to “1”, after the buffered data has been transmitted, the
transmitter output is held low for a minimum of a 13-bit length and until the TXBRK
bit is reset.
Bit 1
RX8: Receive data bit 8 for 9-bit data transfer format (read only)
This bit is only used if 9-bit data transfers are used, in which case this bit location will
store the 9th bit of the received data known as RX8. The BNO bit is used to determine
whether data transfers are in 8-bit or 9-bit format.
Bit 0
TX8: Transmit data bit 8 for 9-bit data transfer format (write only)
This bit is only used if 9-bit data transfers are used, in which case this bit location
will store the 9th bit of the transmitted data known as TX8. The BNO bit is used to
determine whether data transfers are in 8-bit or 9-bit format.
UCR2 Register
The UCR2 register is the second of the UART control registers and serves several purposes. One
of its main functions is to control the basic enable/disable operation if the UART Transmitter and
Receiver as well as enabling the various UART interrupt sources. The register also serves to control
the baud rate speed, receiver wake-up function enable and the address detect function enable.
Further explanation on each of the bits is given below:
Bit
7
6
5
4
3
2
1
0
Name
TXEN
RXEN
BRGH
ADDEN
WAKE
RIE
TIIE
TEIE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
Rev. 1.00
TXEN: UART Transmitter enable control
0: UART Transmitter is disabled
1: UART Transmitter is enabled
The bit named TXEN is the Transmitter Enable Bit. When this bit is equal to “0”, the
transmitter will be disabled with any pending data transmissions being aborted. In
addition the buffers will be reset. In this situation the TX pin will be used as an I/O or
other pin-shared functional pin. If the TXEN bit is equal to “1” and the UARTEN bit is
also equal to 1, the transmitter will be enabled and the TX pin will be controlled by the
UART. Clearing the TXEN bit during a transmission will cause the data transmission
to be aborted and will reset the transmitter. If this situation occurs, the TX pin will be
used as an I/O or other pin-shared functional pin.
141
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Rev. 1.00
Bit 6
RXEN: UART Receiver enable control
0: UART Receiver is disabled
1: UART Receiver is enabled
The bit named RXEN is the Receiver Enable Bit. When this bit is equal to “0”, the
receiver will be disabled with any pending data receptions being aborted. In addition
the receiver buffers will be reset. In this situation the RX pin will be used as an I/O or
other pin-shared functional pin. If the RXEN bit is equal to “1” and the UARTEN bit
is also equal to 1, the receiver will be enabled and the RX pin will be controlled by the
UART. Clearing the RXEN bit during a reception will cause the data reception to be
aborted and will reset the receiver. If this situation occurs, the RX pin will be used as
an I/O or other pin-shared functional pin.
Bit 5
BRGH: Baud Rate speed selection
0: Low speed baud rate
1: High speed baud rate
The bit named BRGH selects the high or low speed mode of the Baud Rate Generator.
This bit, together with the value placed in the baud rate register, BRG, controls the
baud rate of the UART. If the bit is equal to 0, the low speed mode is selected.
Bit 4
ADDEN: Address detect function enable control
0: Address detection function is disabled
1: Address detection function is enabled
The bit named ADDEN is the address detection function enable control bit. When this
bit is equal to 1, the address detection function is enabled. When it occurs, if the 8th
bit, which corresponds to RX7 if BNO=0, or the 9th bit, which corresponds to RX8
if BNO=1, has a value of “1”, then the received word will be identified as an address,
rather than data. If the corresponding interrupt is enabled, an interrupt request will be
generated each time the received word has the address bit set, which is the 8th or 9th
bit depending on the value of the BNO bit. If the address bit known as the 8th or 9th
bit of the received word is “0” with the address detection function being enabled, an
interrupt will not be generated and the received data will be discarded.
Bit 3
WAKE: RX pin falling edge wake-up function enable control
0: RX pin wake-up function is disabled
1: RX pin wake-up function is enabled
The bit enables or disables the receiver wake-up function. If this bit is equal to 1 and
the device is in IDLE0 or SLEEP mode, a falling edge on the RX pin will wake up the
device. If this bit is equal to 0 and the device is in the IDLE or SLEEP mode, any edge
transitions on the RX pin will not wake up the device.
Bit 2
RIE: Receiver interrupt enable control
0: Receiver related interrupt is disabled
1: Receiver related interrupt is enabled
The bit enables or disables the receiver interrupt. If this bit is equal to 1 and when the
receiver overrun flag OERR or received data available flag RXIF is set, the UART
interrupt request flag will be set. If this bit is equal to 0, the UART interrupt request
flag will not be influenced by the condition of the OERR or RXIF flags.
Bit 1
TIIE: Transmitter Idle interrupt enable control
0: Transmitter idle interrupt is disabled
1: Transmitter idle interrupt is enabled
The bit enables or disables the transmitter idle interrupt. If this bit is equal to 1 and
when the transmitter idle flag TIDLE is set, due to a transmitter idle condition, the
UART interrupt request flag will be set. If this bit is equal to 0, the UART interrupt
request flag will not be influenced by the condition of the TIDLE flag.
142
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Bit 0
TEIE: Transmitter Empty interrupt enable control
0: Transmitter empty interrupt is disabled
1: Transmitter empty interrupt is enabled
The bit enables or disables the transmitter empty interrupt. If this bit is equal to 1 and
when the transmitter empty flag TXIF is set, due to a transmitter empty condition, the
UART interrupt request flag will be set. If this bit is equal to 0, the UART interrupt
request flag will not be influenced by the condition of the TXIF flag.
Baud Rate Generator
To setup the speed of the serial data communication, the UART function contains its own dedicated
baud rate generator. The baud rate is controlled by its own internal free running 8-bit counter, the
period of which is determined by two factors. The first of these is the value placed in the BRG
register and the second is the value of the BRGH bit within the UCR2 control register. The BRGH
bit decides, if the baud rate generator is to be used in a high speed mode or low speed mode, which
in turn determines the formula that is used to calculate the baud rate. The value in the BRG register,
N, which is used in the following baud rate calculation formula determines the division factor. Note
that N is the decimal value placed in the BRG register and has a range of between 0 and 255.
UCR2 BRGH Bit
0
1
fSYS
fSYS
Baud Rate (BR)
[16(N+1)]
[64(N+1)]
By programming the BRGH bit which allows selection of the related formula and programming the
required value in the BRG register, the required baud rate can be setup. Note that because the actual
baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error
associated between the actual and requested value. The following example shows how the BRG
register value N and the error value can be calculated.
BRG Register
Bit
7
6
5
4
3
2
1
0
Name
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
“x”: unknown
Bit 7~0
Rev. 1.00
BRG7~BRG0: Baud Rate values
By programming the BRGH bit in the UCR2 register which allows selection of the
related formula described above and programming the required value in the BRG
register, the required baud rate can be setup.
143
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Calculating the Baud Rate and Error Values
For a clock frequency of 4MHz, and with BRGH set to 0 determine the BRG register value N, the
actual baud rate and the error value for a desired baud rate of 4800.
fSYS
From the above table the desired baud rate BR=
[64(N+1)]
fSYS
Re-arranging this equation gives N=
-1
(BR×64)
4000000
Giving a value for N=
-1=12.0208
(4800×64)
To obtain the closest value, a decimal value of 12 should be placed into the BRG register. This gives
4000000
an actual or calculated baud rate value of BR=
=4808
[64(12+1)]
4808-4800
Therefore the error is equal to
=0.16%
4800
The following tables show the actual values of baud rate and error values for the two value of
BRGH.
Baud
Rate
K/BPS
Baud Rates for BRGH=0
fSYS=4MHz
fSYS=3.579545MHz
fSYS=7.159MHz
BRG
Kbaud
Error(%)
BRG
Kbaud
Error(%)
BRG
Kbaud
Error(%)
0.3
207
0.300
0.16
185
0.300
0.00
—
—
—
1.2
51
1.202
0.16
46
1.190
-0.83
92
1.203
0.23
2.4
25
2.404
0.16
22
2.432
1.32
46
2.380
-0.83
4.8
12
4.808
0.16
11
4.661
-2.90
22
4.863
1.32
9.6
6
8.929
-6.99
5
9.321
-2.90
11
9.322
-2.90
19.2
2
20.833
8.51
2
18.643
-2.90
5
18.643
-2.90
38.4
—
—
—
—
—
—
2
32.286
-2.90
57.6
0
62.500
8.51
0
55.930
-2.90
1
55.930
-2.90
115.2
—
—
—
—
—
—
0
111.859
-2.90
Baud Rates and Error Values for BRGH=0
Baud
Rate
K/BPS
Baud Rates for BRGH=1
fSYS=4MHz
fSYS=3.579545MHz
fSYS=7.159MHz
BRG
Kbaud
Error(%)
BRG
Kbaud
Error(%)
BRG
Kbaud
Error(%)
0.3
—
—
—
—
—
—
—
—
—
1.2
207
1.202
0.16
185
1.203
0.23
—
—
—
2.4
103
2.404
0.16
92
2.406
0.23
185
2.406
0.23
4.8
51
4.808
0.16
46
4.76
-0.83
92
4.811
0.23
9.6
25
9.615
0.16
22
9.727
1.32
46
9.520
-0.83
19.2
12
19.231
0.166
11
18.643
-2.90
22
19.454
1.32
38.4
6
35.714
-6.99
5
37.286
-2.90
11
37.286
-2.90
57.6
3
62.5
8.51
3
55.930
-2.90
7
55.930
-2.90
115.2
1
125
8.51
1
111.86
-2.90
3
111.86
-2.90
250
0
250
0
—
—
—
—
—
—
Baud Rates and Error Values for BRGH=1
Rev. 1.00
144
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
UART Setup and Control
For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ,
format. This is composed of one start bit, eight or nine data bits and one or two stop bits. Parity
is supported by the UART hardware and can be setup to be even, odd or no parity. For the most
common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used
as the default setting, which is the setting at power-on. The number of data bits and stop bits, along
with the parity, are setup by programming the corresponding BNO, PRT, PREN and STOPS bits in
the UCR1 register. The baud rate used to transmit and receive data is setup using the internal 8-bit
baud rate generator, while the data is transmitted and received LSB first. Although the transmitter
and receiver of the UART are functionally independent, they both use the same data format and baud
rate. In all cases stop bits will be used for data transmission.
Enabling/Disabling the UART Interface
The basic on/off function of the internal UART function is controlled using the UARTEN bit in the
UCR1 register. If the UARTEN, TXEN and RXEN bits are set, then these two UART pins will act
as normal TX output pin and RX input pin respectively. If no data is being transmitted on the TX
pin, then it will default to a logic high value.
Clearing the UARTEN bit will disable the TX and RX pins and these two pins will be used as an
I/O or other pin-shared functional pin. When the UART function is disabled, the buffer will be
reset to an empty condition, at the same time discarding any remaining residual data. Disabling the
UART will also reset the enable control, the error and status flags with bits TXEN, RXEN, TXBRK,
RXIF, OERR, FERR, PERR and NF being cleared while bits TIDLE, TXIF and RIDLE will be
set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaffected.
If the UARTEN bit in the UCR1 register is cleared while the UART is active, then all pending
transmissions and receptions will be immediately suspended and the UART will be reset to a
condition as defined above. If the UART is then subsequently re-enabled, it will restart again in the
same configuration.
Data, Parity and Stop Bit Selection
The format of the data to be transferred is composed of various factors such as data bit length,
parity on/off, parity type, address bits and the number of stop bits. These factors are determined by
the setup of various bits within the UCR1 register. The BNO bit controls the number of data bits
which can be set to either 8 or 9. The PRT bit controls the choice if odd or even parity. The PREN
bit controls the parity on/off function. The STOPS bit decides whether one or two stop bits are to
be used. The following table shows various formats for data transmission. The address detect mode
control bit identifies the frame as an address character. The number of stop bits, which can be either
one or two, is independent of the data length.
Start Bit
Data Bits
Address Bits
Parity Bit
Stop Bit
1
Example of 8-bit Data Formats
1
8
0
0
1
7
0
1
1
1
7
1
0
1
1
Example of 9-bit Data Formats
1
9
0
0
1
8
0
1
1
1
8
1
0
1
Transmitter Receiver Data Format
The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data
formats.
Rev. 1.00
145
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
UART Transmitter
Data word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1
register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which
is the MSB, needs to be stored in the TX8 bit in the UCR1 register. At the transmitter core lies the
Transmitter Shift Register, more commonly known as the TSR, whose data is obtained from the
transmit data register, which is known as the TXR register. The data to be transmitted is loaded
into this TXR register by the application program. The TSR register is not written to with new data
until the stop bit from the previous transmission has been sent out. As soon as this stop bit has been
transmitted, the TSR can then be loaded with new data from the TXR register, if it is available. It
should be noted that the TSR register, unlike many other registers, is not directly mapped into the
Data Memory area and as such is not available to the application program for direct read/write
operations. An actual transmission of data will normally be enabled when the TXEN bit is set, but
the data will not be transmitted until the TXR register has been loaded with data and the baud rate
generator has defined a shift clock source. However, the transmission can also be initiated by first
loading data into the TXR register, after which the TXEN bit can be set. When a transmission of
data begins, the TSR is normally empty, in which case a transfer to the TXR register will result in
an immediate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission
will immediately cease and the transmitter will be reset. The TX output pin will then return to the I/O
or other pin-shared function.
Transmitting Data
When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with
the least significant bit LSB first. In the transmit mode, the TXR register forms a buffer between the
internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been
selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a
data transfer can be summarized as follows:
• Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word
length, parity type and number of stop bits.
• Setup the BRG register to select the desired baud rate.
• Set the TXEN bit to ensure that the UART transmitter is enabled and the TX pin is used as a
UART transmitter pin.
• Access the USR register and write the data that is to be transmitted into the TXR register. Note
that this step will clear the TXIF bit.
This sequence of events can now be repeated to send additional data. It should be noted that when
TXIF=0, data will be inhibited from being written to the TXR register. Clearing the TXIF flag is
always achieved using the following software sequence:
1. A USR register access
2. A TXR register write execution
Rev. 1.00
146
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is
empty and that other data can now be written into the TXR register without overwriting the previous
data. If the TEIE bit is set, then the TXIF flag will generate an interrupt. During a data transmission,
a write instruction to the TXR register will place the data into the TXR register, which will be
copied to the shift register at the end of the present transmission. When there is no data transmission
in progress, a write instruction to the TXR register will place the data directly into the shift register,
resulting in the commencement of data transmission, and the TXIF bit being immediately set. When
a frame transmission is complete, which happens after stop bits are sent or after the break frame, the
TIDLE bit will be set. To clear the TIDLE bit the following software sequence is used:
1. A USR register access
2. A TXR register write execution
Note that both the TXIF and TIDLE bits are cleared by the same software sequence.
Transmitting Break
If the TXBRK bit is set, then the break characters will be sent on the next transmission. Break
character transmission consists of a start bit, followed by 13xN “0” bits, where N=1, 2, etc. if a
break character is to be transmitted, then the TXBRK bit must be first set by the application program
and then cleared to generate the stop bits. Transmitting a break character will not generate a transmit
interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually
kept at a logic high level, then the transmitter circuitry will transmit continuous break characters.
After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the
last break character and subsequently send out one or two stop bits. The automatic logic high at the
end of the last break character will ensure that the start bit of the next frame is recognized.
UART Receiver
The UART is capable of receiving word lengths of either 8 or 9 bits can be selected by programming
the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In
this case the 9th bit, which is the MSB, will be stored in the RX8 bit in the UCR1 register. At the
receiver core lies the Receiver Shift Register more commonly known as the RSR. The data which
is received on the RX external input pin is sent to the data recovery block. The data recovery block
operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the
baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the
receive data register, if the register is empty. The data which is received on the external RX input pin
is sampled three times by a majority detect circuit to determine the logic level that has been placed
onto the RX pin. It should be noted that the RSR register, unlike many other registers, is not directly
mapped into the Data Memory area and as such is not available to the application program for direct
read/write operations.
Receiving Data
When the UART receiver is receiving data, the data is serially shifted in on the external RX input
pin to the shift register, with the least significant bit LSB first. The RXR register is a two byte deep
FIFO data buffer, where two bytes can be held in the FIFO while the third byte can continue to be
received. Note that the application program must ensure that the data is read from RXR before the
third byte has been completely shifted in, otherwise the third byte will be discarded and an overrun
error OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized
as follows:
Rev. 1.00
147
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
• Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word
length, parity type and number of stop bits.
• Setup the BRG register to select the desired baud rate.
• Set the RXEN bit to ensure that the UART receiver is enabled and the RX pin is used as a UART
receiver pin.
At this point the receiver will be enabled which will begin to look for a start bit.
When a character is received, the following sequence of events will occur:
• The RXIF bit in the USR register will be set then RXR register has data available, at least one
more character can be read.
• When the contents of the shift register have been transferred to the RXR register and if the RIE
bit is set, then an interrupt will be generated.
• If during reception, a frame error, noise error, parity error or an overrun error has been detected,
then the error flags can be set.
The RXIF bit can be cleared using the following software sequence:
1. A USR register access
2. A RXR register read execution
Receiving Break
Any break character received by the UART will be managed as a framing error. The receiver will
count and expect a certain number of bit times as specified by the values programmed into the BNO
and STOPS bits. If the break is much longer than 13 bit times, the reception will be considered as
complete after the number of bit times specified by BNO and STOPS. The RXIF bit is set, FERR
is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the
RIDLE bit is set. If a long break signal has been detected and the receiver has received a start bit,
the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a valid
stop bit before looking for the next start bit. The receiver will not make the assumption that the
break condition on the line is the next start bit. A break is regarded as a character that contains only
zeros with the FERR flag set. The break character will be loaded into the buffer and no further data
will be received until stop bits are received. It should be noted that the RIDLE read only flag will go
high when the stop bits have not yet been received. The reception of a break character on the UART
registers will result in the following:
• The framing error flag, FERR, will be set.
• The receive data register, RXR, will be cleared.
• The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set.
Idle Status
When the receiver is reading data, which means it will be in between the detection of a start bit and
the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE
flag, will have a zero value. In between the reception of a stop bit and the detection of the next start
bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition.
Receiver Interrupt
The read only receive interrupt flag RXIF in the USR register is set by an edge generated by the
receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift
Register, RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if
RIE=1.
Rev. 1.00
148
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Managing Receiver Errors
Several types of reception errors can occur within the UART module, the following section describes
the various types and how they are managed by the UART.
Overrun Error – OERR
The RXR register is composed of a two byte deep FIFO data buffer, where two bytes can be held
in the FIFO register, while a third byte can continue to be received. Before the third byte has been
entirely shifted in, the data should be read from the RXR register. If this is not done, the overrun
error flag OERR will be consequently indicated.
In the event of an overrun error occurring, the following will happen:
• The OERR flag in the USR register will be set.
• The RXR contents will not be lost.
• The shift register will be overwritten.
• An interrupt will be generated if the RIE bit is set.
The OERR flag can be cleared by an access to the USR register followed by a read to the RXR
register.
Noise Error – NF
Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is
detected within a frame, the following will occur:
• The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit.
• Data will be transferred from the shift register to the RXR register.
• No interrupt will be generated. However this bit rises at the same time as the RXIF bit which
itself generates an interrupt.
Note that the NF flag is reset by a USR register read operation followed by an RXR register read
operation.
Framing Error – FERR
The read only framing error flag, FERR, in the USR register, is set if a zero is detected instead of
stop bits. If two stop bits are selected, only first stop bit is detected, it must be high. If first stop bit is
low, the FERR flag will be set. The FERR flag is buffered along with the received data and is cleared
in any reset.
Parity Error – PERR
The read only parity error flag, PERR, in the USR register, is set if the parity of the received word
is incorrect. This error flag is only applicable if the parity function is enabled, PREN=1, and if the
parity type, odd or even, is selected. The read only PERR flag is buffered along with the received
data bytes. It is cleared on any reset, it should be noted that the FERR and PERR flags are buffered
along with the corresponding word and should be read before reading the data word.
Rev. 1.00
149
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
UART Interrupt Structure
Several individual UART conditions can generate a UART interrupt. When these conditions exist,
a low pulse will be generated to get the attention of the microcontroller. These conditions are a
transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address
detect and an RX pin wake-up. When any of these conditions are created, if its corresponding
interrupt control is enabled and the stack is not full, the program will jump to its corresponding
interrupt vector where it can be serviced before returning to the main program. Four of these
conditions have the corresponding USR register flags which will generate a UART interrupt if its
associated interrupt enable control bit in the UCR2 register is set. The two transmitter interrupt
conditions have their own corresponding enable control bits, while the two receiver interrupt
conditions have a shared enable control bit. These enable bits can be used to mask out individual
UART interrupt sources.
The address detect condition, which is also a UART interrupt source, does not have an associated
flag, but will generate a UART interrupt when an address detect condition occurs if its function
is enabled by setting the ADDEN bit in the UCR2 register. An RX pin wake-up, which is also a
UART interrupt source, does not have an associated flag, but will generate a UART interrupt if the
microcontroller is woken up from IDLE0 or SLEEP mode by a falling edge on the RX pin, if the
WAKE and RIE bits in the UCR2 register are set. Note that in the event of an RX wake-up interrupt
occurring, there will be a certain period of delay, commonly known as the System Start-up Time, for
the oscillator to restart and stabilize before the system resumes normal operation.
Note that the USR register flags are read only and cannot be cleared or set by the application
program, neither will they be cleared when the program jumps to the corresponding interrupt
servicing routine, as is the case for some of the other interrupts. The flags will be cleared
automatically when certain actions are taken by the UART, the details of which are given in the
UART register section. The overall UART interrupt can be disabled or enabled by the related
interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether
the interrupt requested by the UART module is masked out or allowed.
USR Registe�
UCR� Registe�
T�ansmitte� Em�ty
F�ag TXIF
TEIE
0
1
INTC�
T�ansmitte� Id�e
F�ag TIDLE
Receive� Ove��un
F�ag OERR
OR
Receive� Data
�vai�ab�e RXIF
RX Pin
Wake-u�
�DDEN
W�KE
0
1
UCR� Registe�
TIIE
0
1
RIE
0
1
U�RT Inte��u�t
Request F�ag
U�RTF
INTC�
U�RTE
INTC0
EMI
To MCU
inte��u�t Ci�cuit�y
0
1
0
1
RX� if BNO=0
RX8 if BNO=1
UART Interrupt Structure
Rev. 1.00
150
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Address Detect Mode
Setting the Address Detect function enable control bit, ADDEN, in the UCR2 register, enables this
special function. If this bit is set to 1, then an additional qualifier will be placed on the generation
of a Receiver Data Available interrupt, which is requested by the RXIF flag. If the ADDEN bit
is equal to 1, then when the data is available, an interrupt will only be generated, if the highest
received bit has a high value. Note that the related interrupt enable control bit and the EMI bit of the
microcontroller must also be enabled for correct interrupt generation. The highest address bit is the
9th bit if the bit BNO=1 or the 8th bit if the bit BNO=0. If the highest bit is high, then the received
word will be defined as an address rather than data. A Data Available interrupt will be generated
every time the last bit of the received word is set. If the ADDEN bit is equal to 0, then a Receive
Data Available interrupt will be generated each time the RXIF flag is set, irrespective of the data last
but status. The address detection and parity functions are mutually exclusive functions. Therefore, if
the address detect function is enabled, then to ensure correct operation, the parity function should be
disabled by resetting the parity function enable bit PREN to zero.
ADDEN
0
1
Bit 9 if BNO=1
Bit 8 if BNO=0
UART Interrupt Generated
0
√
1
√
0
X
1
√
ADDEN Bit Function
UART Wake-up
When the fSYS is off, the UART will cease to function, all clock sources to the module are shutdown.
If the fSYS is off while a transmission is still in progress, then the transmission will be paused until
the UART clock source derived from the microcontroller is activated. In a similar way, if the
MCU enters the Power Down Mode while receiving data, then the reception of data will likewise
be paused. When the MCU enters the IDLE or SLEEP Mode, note that the USR, UCR1, UCR2,
transmit and receive registers, as well as the BRG register will not be affected. It is recommended
to make sure first that the UART data transmission or reception has been finished before the
microcontroller enters the Power Down mode.
The UART function contains a receiver RX pin wake-up function, which is enabled or disabled
by the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit, UARTEN, the
receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set before the MCU enters the
IDLE0 or SLEEP Mode, then a falling edge on the RX pin will wake up the MCU from the IDLE0
or SLEEP Mode. Note that as it takes certain system clock cycles after a wake-up, before normal
microcontroller operation resumes, any data received during this time on the RX pin will be ignored.
For a UART wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global
interrupt enable bit, EMI, and the UART interrupt enable bit, UARTE, must also be set. If these two
bits are not set then only a wake up event will occur and no interrupt will be generated. Note also
that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes,
the UART interrupt will not be generated until after this time has elapsed.
Below two tables illustrate the UART RX wake-up functions in different operating mode.
If the main system clock can come from both high frequency fH and low frequency fSUB:
Rev. 1.00
151
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Description
Operation
Mode
IDLE0 Mode
CPU
fH
fSUB
Off
(HALT)
Off
On
RX wake-up function
When the UCR2.2(RIE)=1, UCR2.3(WAKE)=1 and the CPU is entered in
IDLE0 mode, a falling edge on the RX pin will turn on fSYS and wake-up CPU.
IDLE1 Mode
Off
(HALT)
On
When the UCR2.2(RIE)=1, UCR2.3(WAKE)=1 and the CPU is entered in
IDLE1 mode:
1. If the UART is not transfer and a falling edge occurred on the RX pin, the
fSYS is kept on running and CPU is still off. If the UART transmission is on
On
going, CPU will wake up in the end of transfer.
2. If the UART transmission is on going, the CPU will wake up in the end of
transfer.
Note: If RIE=0, WAKE=1 and the UART transmission is on going, the CPU will
not wake up in the end of receive.
SLEEP Mode
Off
(HALT)
Off
Off
When the UCR2.2(RIE)=1, UCR2.3(WAKE)=1 and the CPU is entered in
SLEEP mode, a falling edge on the RX pin will turn on fSYS and wake-up CPU.
Low Voltage Detector – LVD
Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to
monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain
level. This function may be especially useful in battery applications where the supply voltage will
gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated.
The Low Voltage Detector also has the capability of generating an interrupt signal.
LVD Register
The Low Voltage Detector function is controlled using a single register with the name LVDC. Three
bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which
a low voltage condition will be determined. A low voltage condition is indicated when the LVDO
bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage
value. The LVDEN bit is used to control the overall on/off function of the low voltage detector.
Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the
internal low voltage detector circuits. As the low voltage detector will consume a certain amount of
power, it may be desirable to switch off the circuit when not in use, an important consideration in
power sensitive battery powered applications.
LVDC Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
—
—
LVDO
LVDEN
—
VLVD2
VLVD1
VLVD0
R/W
—
—
R
R/W
—
R/W
R/W
R/W
POR
—
—
0
0
—
0
0
0
Bit 7~6
Unimplemented, read as “0”
Bit 5
LVDO: LVD Output Flag
0: No Low Voltage Detect
1: Low Voltage Detect
Bit 4
LVDEN: Low Voltage Detector Control
0: Disable
1: Enable
152
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Bit 3
Unimplemented, read as “0”
Bit 2~0
VLVD2~VLVD0: Select LVD Voltage
000: 2.0V
001: 2.2V
010: 2.4V
011: 2.7V
100: 3.0V
101: 3.3V
110: 3.6V
111: 4.0V
LVD Operation
The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a
pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V.
When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be
set high indicating a low power supply voltage condition. The Low Voltage Detector function is
supplied by a reference voltage which will be automatically enabled. When the device is SLEEP0
the Low Voltage Detector will disable, even if the LVDEN bit is high. After enabling the Low
Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the
LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that
of VLVD, there may be multiple bit LVDO transitions.
LVD Operation
The Low Voltage Detector also has its own interrupt which is contained within one of the Multifunction interrupts, providing an alternative means of low voltage detection, in addition to polling
the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been
set high by a low voltage condition. When the device is powered down the Low Voltage Detector
will remain active if the LVDEN bit is high. In this case, the LVF interrupt request flag will be set,
causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the
device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up
function is not required then the LVF flag should be first set high before the device enters the SLEEP
or IDLE Mode.
When LVD function is enabled, it is recommenced to clear LVD flag first, and then enables interrupt
function to avoid mistake action.
Rev. 1.00
153
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an
internal function such as a Timer Module or an A/D converter requires microcontroller attention,
their corresponding interrupt will enforce a temporary suspension of the main program allowing the
microcontroller to direct attention to their respective needs. The device contains several external
interrupt and internal interrupts functions. The external interrupt is generated by the action of the
external INTn pin, while the internal interrupts are generated by various internal functions such as
TMs, Comparator, Time Bases, LVD, EEPROM, SIM, UART and the A/D converter.
Interrupt Registers
Overall interrupt control, which basically means the setting of request flags when certain
microcontroller conditions occur and the setting of interrupt enable bits by the application program,
is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the
accompanying table. The first is the INTC0~INTC2 registers which setup the primary interrupts, the
second is the MFI0~MFI2 registers which setup the Multi-function interrupts.
Each register contains a number of enable bits to enable or disable individual registers as well as
interrupt flags to indicate the presence of an interrupt request. The naming convention of these
follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of
that interrupt followed by either an “E” for enable/disable bit or “F” for request flag.
Function
Enable Bit
Request Flag
Notes
EMI
—
—
INTnE
INTnF
n=0 or 1
CPE
CPF
—
MFnE
MFnF
n=0~2
Global
INTn Pin
Comparator
Multi-function
A/D Converter
ADE
ADF
—
Time Base
TBnE
TBnF
n=0 or 1
LVD
LVE
LVF
—
EEPROM
DEE
DEF
—
STMnPE
STMnPF
STMnAE
STMnAF
PTMPE
PTMPF
PTMAE
PTMAF
STM
PTM
SIM
UART
n=0 or 1
—
SIME
SIMF
—
UARTE
UARTF
—
Interrupt Register Bit Naming Conventions
Bit
Register
Name
7
INTEG
—
—
INTC0
—
MF0F
INTC1
TB0F
ADF
INTC2
UARTF
SIMF
MFI0
—
—
MFI1
MFI2
6
STM1AF STM1PF
—
—
5
4
3
2
1
0
—
—
INT1S1
INT1S0
INT0S1
INT0S0
CPF
INT0F
MF0E
CPE
INT0E
EMI
MF2F
MF1F
TB0E
ADE
MF2E
MF1E
INT1F
TB1F
UARTE
SIME
INT1E
TB1E
—
—
STM0AF STM0PF
PTMAF
PTMPF
DEF
LVF
STM1AE STM1PE
—
—
STM0AE STM0PE
PTMAE
PTMPE
DEE
LVE
Interrupt Registers List
Rev. 1.00
154
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
INTEG Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
INT1S1
INT1S0
INT0S1
INT0S0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
0
Bit 7~4
Unimplemented, read as “0”
Bit 3~2
INT1S1~INT1S0: interrupt edge control for INT1 pin
00: Disable
01: Rising edge
10: Falling edge
11: Both rising and falling edges
Bit 1~0
INT0S1~INT0S0: interrupt edge control for INT0 pin
00: Disable
01: Rising edge
10: Falling edge
11: Both rising and falling edges
INTC0 Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
Name
—
MF0F
CPF
INT0F
MF0E
CPE
INT0E
EMI
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7
Unimplemented, read as “0”
Bit 6
MF0F: Multi-function Interrupt 0 Request Flag
0: No request
1: Interrupt request
Bit 5
CPF: Comparator interrupt request flag
0: No request
1: Interrupt request
Bit 4
INT0F: INT0 Interrupt Request Flag
0: No request
1: Interrupt request
Bit 3
MF0E: Multi-function 0 Interrupt Control
0: Disable
1: Enable
Bit 2
CPE: Comparator interrupt control
0: Disable
1: Enable
Bit 1
INT0E: INT0 Interrupt Control
0: Disable
1: Enable
Bit 0
EMI: Global Interrupt Control
0: Disable
1: Enable
155
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
INTC1 Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
TB0F
ADF
MF2F
MF1F
TB0E
ADE
MF2E
MF1E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
TB0F: Time Base 0 Interrupt Request Flag
0: No request
1: Interrupt request
Bit 6
ADF: A/D Converter Interrupt Request Flag
0: No request
1: Interrupt request
Bit 5
MF2F: Multi-function Interrupt 2 Request Flag
0: No request
1: Interrupt request
Bit 4
MF1F: Multi-function Interrupt 1 Request Flag
0: No request
1: Interrupt request
Bit 3
TB0E: Time Base 0 Interrupt Control
0: Disable
1: Enable
Bit 2
ADE: A/D Converter Interrupt Control
0: Disable
1: Enable
Bit 1
MF2E: Multi-function 2 Interrupt Control
0: Disable
1: Enable
Bit 0
MF1E: Multi-function 1 Interrupt Control
0: Disable
1: Enable
156
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
INTC2 Register
Bit
7
6
5
4
3
2
1
0
Name
UARTF
SIMF
INT1F
TB1F
UARTE
SIME
INT1E
TB1E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
UARTF: UART Interrupt Request Flag
0: No request
1: Interrupt request
Bit 6
SIMF: SIM Interrupt Request Flag
0: No request
1: Interrupt request
Bit 5
INT1F: INT1 pin interrupt request flag
0: No request
1: Interrupt request
Bit 4
TB1F: Time Base 1 Interrupt Request Flag
0: No request
1: Interrupt request
Bit 3
UARTE: UART Interrupt Request Flag
0: No request
1: Interrupt request
Bit 2
SIME: SIM Interrupt Request Flag
0: No request
1: Interrupt request
Bit 1
INT1E: INT1 pin interrupt control
0: Disable
1: Enable
Bit 0
TB1E: Time Base 1 Interrupt Control
0: Disable
1: Enable
MFI0 Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
—
—
STM0AF
STM0PF
—
—
STM0AE
STM0PE
R/W
—
—
R/W
R/W
—
—
R/W
R/W
POR
—
—
0
0
—
—
0
0
Bit 7~6
Unimplemented, read as “0”
Bit 5
STM0AF: STM0 Comparator A match interrupt request flag
0: No request
1: Interrupt request
Bit 4
STM0PF: STM0 Comparator P match interrupt request flag
0: No request
1: Interrupt request
Bit 3~2
Unimplemented, read as “0”
Bit 1
STM0AE: STM0 Comparator A match interrupt control
0: Disable
1: Enable
Bit 0
STM0PE: STM0 Comparator P match interrupt control
0: Disable
1: Enable
157
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
MFI1 Register
Bit
7
6
5
4
3
2
1
0
Name
STM1AF
STM1PF
PTMAF
PTMPF
STM1AE
STM1PE
PTMAE
PTMPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
STM1AF: STM1 Comparator A match interrupt request flag
0: No request
1: Interrupt request
Bit 6
STM1PF: STM1 Comparator P match interrupt request flag
0: No request
1: Interrupt request
Bit 5
PTMAF: PTM Comparator A match interrupt request flag
0: No request
1: Interrupt request
Bit 4
PTMPF: PTM Comparator P match interrupt request flag
0: No request
1: Interrupt request
Bit 3
STM1AE: STM1 Comparator A match interrupt control
0: Disable
1: Enable
Bit 2
STM1PE: STM1 Comparator P match interrupt control
0: Disable
1: Enable
Bit 1
PTMAE: PTM Comparator A match interrupt control
0: Disable
1: Enable
Bit 0
PTMPE: PTM Comparator P match interrupt control
0: Disable
1: Enable
MFI2 Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
—
—
DEF
LVF
—
—
DEE
LVE
R/W
—
—
R/W
R/W
—
—
R/W
R/W
POR
—
—
0
0
—
—
0
0
Bit 7~6
Unimplemented, read as “0”
Bit 5
DEF: Data EEPROM interrupt request flag
0: No request
1: Interrupt request
Bit 4
LVF: LVD interrupt request flag
0: No request
1: Interrupt request
Bit 3~2
Unimplemented, read as “0”
Bit 1
DEE: Data EEPROM Interrupt Control
0: Disable
1: Enable
Bit 0
LVE: LVD Interrupt Control
0: Disable
1: Enable
158
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Interrupt Operation
When the conditions for an interrupt event occur, such as a TM Comparator P, Comparator A
match or A/D conversion completion etc., the relevant interrupt request flag will be set. Whether
the request flag actually generates a program jump to the relevant interrupt vector is determined by
the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to
its relevant vector, if the enable bit is zero then although the interrupt request flag is set an actual
interrupt will not be generated and the program will not jump to the relevant interrupt vector. The
global interrupt enable bit, if cleared to zero, will disable all interrupts.
When an interrupt is generated, the Program Counter, which stores the address of the next instruction
to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a
new address which will be the value of the corresponding interrupt vector. The microcontroller will
then fetch its next instruction from this interrupt vector. The instruction at this vector will usually
be a “JMP” which will jump to another section of program which is known as the interrupt service
routine. Here is located the code to control the appropriate interrupt. The interrupt service routine
must be terminated with a “RETI”, which retrieves the original Program Counter address from
the stack and allows the microcontroller to continue with normal execution at the point where the
interrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in the
Accompanying diagrams with their order of priority. Some interrupt sources have their own
individual vector while others share the same multi-function interrupt vector. Once an interrupt
subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit,
EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring.
However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded.
If an interrupt requires immediate servicing while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack
is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until
the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from
becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that
is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or
IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set
before the device is in SLEEP or IDLE Mode.
Rev. 1.00
159
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Legend
xxF
Request F�ag� no auto �eset in ISR
xxF
Request F�ag� auto �eset in ISR
xxE
Enab�e Bits
EMI auto disab�ed
in ISR
Inte��u�t
Name
INT0 Pin
Request
F�ags
INT0F
Enab�e
Bits
INT0E
Maste�
Enab�e
EMI
Vecto�
Com�a�ato�
CPF
CPE
EMI
08H
M. Funct. 0
MF0F
MF0E
EMI
0CH
M. Funct. 1
MF1F
MF1E
EMI
10H
04H
STM0P
STM0PF
STM0PE
STM0�
STM0�F
STM0�E
PTMP
PTMPF
PTMPE
PTM�
PTM�F
PTM�E
STM1P
STM1PF
STM1PE
STM1�
STM1�F
STM1�E
M. Funct. �
MF�F
MF�E
EMI
14H
LVD
LVF
LVE
�/D
�DF
�DE
EMI
18H
EEPROM
DEF
DEE
Time Base 0
TB0F
TB0E
EMI
1CH
Time Base 1
TB1F
TB1E
EMI
�0H
INT1 Pin
INT1F
INT1E
EMI
�4H
SIM
SIMF
SIME
EMI
�8H
U�RT
U�RTF
U�RTE
EMI
�CH
Inte��u�ts contained within
Mu�ti-Function Inte��u�ts
P�io�ity
High
Low
Interrupt Structure
External Interrupt
The external interrupt is controlled by signal transitions on the INTn pins. An external interrupt
request will take place when the external interrupt request flag, INTnF, is set, which will occur
when a transition, whose type is chosen by the edge select bits, appears on the external interrupt
pin. To allow the program to branch to its respective interrupt vector address, the global interrupt
enable bit, EMI, and respective external interrupt enable bit, INTnE, must first be set. Additionally
the correct interrupt edge type must be selected using the related register to enable the external
interrupt function and to choose the trigger edge type. As the external interrupt pin is pin-shared
with I/O pin, it can only be configured as external interrupt pin if the external interrupt enable bit in
the corresponding interrupt register has been set. The pin must also be setup as an input by setting
the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full
and the correct transition type appears on the external interrupt pin, a subroutine call to the external
interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flag,
INTnF, will be automatically reset and the EMI bit will be automatically cleared to disable other
interrupts. Note that any pull-high resistor selections on the external interrupt pin will remain valid
even if the pin is used as an external interrupt input.
The INTEG register is used to select the type of active edge that will trigger the external interrupt.
A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt.
Note that the INTEG register can also be used to disable the external interrupt function.
Rev. 1.00
160
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Comparator Interrupt
The comparator interrupt is controlled by the internal comparator. A comparator interrupt request
will take place when the comparator interrupt request flag, CPF, is set, a situation that will occur
when the comparator output bit changes state. To allow the program to branch to its respective
interrupt vector address, the global interrupt enable bit, EMI, and comparator interrupt enable bit,
CPE, must first be set. When the interrupt is enabled, the stack is not full and the comparator inputs
generate a comparator output transition, a subroutine call to the comparator interrupt vector, will
take place. When the interrupt is serviced, the comparator interrupt request flag will be automatically
reset and the EMI bit will be automatically cleared to disable other interrupts.
Multi-function Interrupt
Within the device there are up to three Multi-function interrupts. Unlike the other independent
interrupts, these interrupts have no independent source, but rather are formed from other existing
interrupt sources, namely the TM Interrupts, LVD interrupt and EEPROM interrupt.
A Multi-function interrupt request will take place the Multi-function interrupt request flag, MFnF
is set. The Multi-function interrupt flag will be set when any of its included functions generate an
interrupt request flag. To allow the program to branch to its respective interrupt vector address,
when the Multi-function interrupt is enabled and the stack is not full and either one of the interrupts
contained within each of Multi-function interrupt occurs, a subroutine call to the Multi-function
interrupt vector will take place. When the interrupt is serviced, the related Multi-Function request
flag will be automatically reset and the EMI bit will be automatically cleared to disable other
interrupts.
However, it must be noted that, although the Multi-function Interrupt flags will be automatically
reset when the interrupt is serviced, the request flags from the original source of the Multifunction interrupts, namely the TM Interrupts, LVD interrupt and EEPROM interrupt, will not be
automatically reset and must be manually reset by the application program.
A/D Converter Interrupt
The device contains an A/D converter which has its own independent interrupt. The A/D Converter
Interrupt is controlled by the termination of an A/D conversion process. An A/D Converter Interrupt
request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs
when the A/D conversion process finishes. To allow the program to branch to its respective interrupt
vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, must first be
set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a
subroutine call to the A/D Converter Interrupt vector, will take place. When the interrupt is serviced,
the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI bit will also be
automatically cleared to disable other interrupts.
Rev. 1.00
161
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Time Base Interrupt
The function of the Time Base Interrupts is to provide regular time signal in the form of an internal
interrupt. They are controlled by the overflow signals from their respective timer functions. When
these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the
program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI
and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack
is not full and the Time Base overflows, a subroutine call to their respective vector locations will
take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will
be automatically reset and the EMI bit will be cleared to disable other interrupts.
The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their
clock sources originate from the internal clock source fTB. This fTB input clock passes through a
divider, the division ratio of which is selected by programming the appropriate bits in the TBC
register to obtain longer interrupt periods whose value ranges. The clock source that generates fTB,
which in turn controls the Time Base interrupt period, can originate from several different sources,
as shown in the System Operating Mode section.
TBC Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
TBON
TBCK
TB11
TB10
LXTLP
TB02
TB01
TB00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
1
1
0
1
1
1
Bit 7
TBON: TB0 and TB1 function enable Control
0: Disable
1: Enable
Bit 6
TBCK: Select fTB Clock
0: fTBC
1: fSYS/4
Bit 5~4
TB11~TB10: Select Time Base 1 Time-out Period
00: 212/fTB
01: 213/fTB
10: 214/fTB
11: 215/fTB
Bit 3
LXTLP: LXT Low Power Control
0: Disable (LXT quick start-up)
1: Enable (LXT slow start-up)
Bit 2~0
TB02~TB00: Select Time Base 0 Time-out Period
000: 28/fTB
001: 29/fTB
010: 210/fTB
011: 211/fTB
100: 212/fTB
101: 213/fTB
110: 214/fTB
111: 215/fTB
162
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
      Time Base Interrupt
EEPROM Interrupt
The EEPROM interrupt is contained within the Multi-function Interrupt. An EEPROM Interrupt
request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs
when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt
vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit, DEE, and
associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the
stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective EEPROM
Interrupt vector, will take place. When the EEPROM Interrupt is serviced, the EMI bit will be
automatically cleared to disable other interrupts, however only the Multi-function interrupt request
flag will be also automatically cleared. As the DEF flag will not be automatically cleared, it has to be
cleared by the application program.
LVD Interrupt
The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. A LVD
Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs
when the Low Voltage Detector function detects a low power supply voltage. To allow the program
to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage
Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When
the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to
the Multi-function Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the
EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function
interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically
cleared, it has to be cleared by the application program.
TM Interrupts
The Standard and Periodic Type TMs have two interrupts each. All of the TM interrupts are
contained within the Multi-function Interrupts. For the Standard and Periodic there are two interrupt
request flags xTMnPF and xTMnAF, and two enable bits xTMnPE and xTMnAE. A TM interrupt
request will take place when any of the TM request flags are set, a situation which occurs when a
TM comparator P or A match situation happens.
To allow the program to branch to its respective interrupt vector address, the global interrupt enable
bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE,
must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match
situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take
place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other
interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt
request flags will not be automatically cleared, they have to be cleared by the application program.
Rev. 1.00
163
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
SIM Interrupt
The Serial Interface Module Interrupt, also known as the SIM interrupt, is controlled by the SPI or
I2C data transfer. A SIM Interrupt request will take place when the SIM Interrupt request flag, SIMF,
is set, which occurs when a byte of data has been received or transmitted by the SIM interface,
an I2C slave address match or I2C bus time-out occurrence. To allow the program to branch to its
respective interrupt vector address, the global interrupt enable bit, EMI and the Serial Interface
Interrupt enable bit, SIME, must first be set. When the interrupt is enabled, the stack is not full and
any of the above described situations occurs, a subroutine call to the respective SIM Interrupt vector,
will take place. When the Serial Interface Interrupt is serviced, the EMI bit will be automatically
cleared to disable other interrupts. The SIMF flag will also be automatically cleared.
UART Transfer Interrupt
The UART Transfer Interrupt is controlled by several UART transfer conditions. When one of these
conditions occurs, an interrupt pulse will be generated to get the attention of the microcontroller.
These conditions are a transmitter data register empty, transmitter idle, receiver data available,
receiver overrun, address detect and an RX pin wake-up. To allow the program to branch to its
respective interrupt vector address, the global interrupt enable bit, EMI, and UART Interrupt enable
bit, UARTE, must first be set. When the interrupt is enabled, the stack is not full and any of the
conditions described above occurs, a subroutine call to the UART Interrupt vector, will take place.
When the interrupt is serviced, the UART Interrupt flag, UARTF, will be automatically cleared. The
EMI bit will also be automatically cleared to disable other interrupts.
Interrupt Wake-up Function
Each of the interrupt functions has the capability of waking up the microcontroller when in the
SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to
high and is independent of whether the interrupt is enabled or not. Therefore, even though the device
is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge
transitions on the external interrupt pins, a low power supply voltage or comparator input change
may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care
must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up
function is to be disabled then the corresponding interrupt request flag should be set high before the
device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt
wake-up function.
Rev. 1.00
164
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Programming Considerations
By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being
serviced, however, once an interrupt request flag is set, it will remain in this condition in the
interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by
the application program.
Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt
service routine is executed, as only the Multi-function interrupt request flags, MFnF, will be
automatically cleared, the individual request flag for the function needs to be cleared by the
application program.
It is recommended that programs do not use the “CALL” instruction within the interrupt service
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately.
If only one stack is left and the interrupt is not well controlled, the original control sequence will be
damaged once a CALL subroutine is executed in the interrupt subroutine.
Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE
Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is
required to prevent a certain interrupt from waking up the microcontroller then its respective request
flag should be first set high before enter SLEEP or IDLE Mode.
As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the
contents of the accumulator, status register or other registers are altered by the interrupt service
program, their contents should be saved to the memory at the beginning of the interrupt service
routine.
To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI
instruction in addition to executing a return to the main program also automatically sets the EMI
bit high to allow further interrupts. The RET instruction however only executes a return to the main
program leaving the EMI bit in its present zero state and therefore disabling the execution of further
interrupts.
Rev. 1.00
165
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Configuration Option
Configuration options refer to certain options within the MCU that are programmed into the device
during the programming process. During the development process, these options are selected using
the HT-IDE software development tools. As these options are programmed into the device using
the hardware programming tools, once they are selected they cannot be changed later using the
application program. All options must be defined for proper system function, the details of which are
shown in the table.
No.
Options
Oscillator Options
1
High Speed System Oscillator Selection – fH:
1. HXT
2. HIRC
2
Low Speed System Oscillator Selection – fSUB:
1. LXT
2. LIRC
3
HIRC Frequency Selection:
1. 8MHz
2. 12MHz
3. 16MHz
Application Circuits
VDD
VDD
SCOM0~SCOM3
0.1µF
�N0~�N�
VSS
P�0~P��
PB0~PB�
PC0~PC�
See Osci��ato�
Section
OSC
Ci�cuit
OSC
Ci�cuit
PC0/OSC1
PC1/OSC�
PD0~PD�
PE0~PE�
PF0~PF�
PB0/XT1
TX
PB1/XT�
RX
See Osci��ato�
Section
Rev. 1.00
166
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Instruction Set
Introduction
Central to the successful operation of any microcontroller is its instruction set, which is a set of
program instruction codes that directs the microcontroller to perform certain operations. In the case
of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to
enable programmers to implement their application with the minimum of programming overheads.
For easier understanding of the various instruction codes, they have been subdivided into several
functional groupings.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch,
call, or table read instructions where two instruction cycles are required. One instruction cycle is
equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions
would be implemented within 0.5μs and branch or call instructions would be implemented within
1μs. Although instructions which require one more cycle to implement are generally limited to
the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other
instructions which involve manipulation of the Program Counter Low register or PCL will also take
one more cycle to implement. As instructions which change the contents of the PCL will imply a
direct jump to that new address, one more cycle will be required. Examples of such instructions
would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if
the result of the comparison involves a skip operation then this will also take one more cycle, if no
skip is involved then only one cycle is required.
Moving and Transferring Data
The transfer of data within the microcontroller program is one of the most frequently used
operations. Making use of three kinds of MOV instructions, data can be transferred from registers to
the Accumulator and vice-versa as well as being able to move specific immediate data directly into
the Accumulator. One of the most important data transfer applications is to receive data from the
input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and data manipulation is a necessary feature of
most microcontroller applications. Within the Holtek microcontroller instruction set are a range of
add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care
must be taken to ensure correct handling of carry and borrow data when results exceed 255 for
addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC
and DECA provide a simple means of increasing or decreasing by a value of one of the values in the
destination specified.
Rev. 1.00
167
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Logical and Rotate Operation
The standard logical operations such as AND, OR, XOR and CPL all have their own instruction
within the Holtek microcontroller instruction set. As with the case of most instructions involving
data manipulation, data must pass through the Accumulator which may involve additional
programming steps. In all logical data operations, the zero flag may be set if the result of the
operation is zero. Another form of logical data manipulation comes from the rotate instructions such
as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different
rotate instructions exist depending on program requirements. Rotate instructions are useful for serial
port programming applications where data can be rotated from an internal register into the Carry
bit from where it can be examined and the necessary serial bit set high or low. Another application
which rotate data operations are used is to implement multiplication and division calculations.
Branches and Control Transfer
Program branching takes the form of either jumps to specified locations using the JMP instruction
or to a subroutine using the CALL instruction. They differ in the sense that in the case of a
subroutine call, the program must return to the instruction immediately when the subroutine has
been carried out. This is done by placing a return instruction "RET" in the subroutine which will
cause the program to jump back to the address right after the CALL instruction. In the case of a JMP
instruction, the program simply jumps to the desired location. There is no requirement to jump back
to the original jumping off point as in the case of the CALL instruction. One special and extremely
useful set of branch instructions are the conditional branches. Here a decision is first made regarding
the condition of a certain data memory or individual bits. Depending upon the conditions, the
program will continue with the next instruction or skip over it and jump to the following instruction.
These instructions are the key to decision making and branching within the program perhaps
determined by the condition of certain input switches or by the condition of internal data bits.
Bit Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all
Holtek microcontrollers. This feature is especially useful for output port bit programming where
individual bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m].
i" instructions respectively. The feature removes the need for programmers to first read the 8-bit
output port, manipulate the input data to ensure that other bits are not changed and then output the
port with the correct new data. This read-modify-write process is taken care of automatically when
these bit operation instructions are used.
Table Read Operations
Data storage is normally implemented by using registers. However, when working with large
amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in
the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program
Memory to be set as a table where data can be directly stored. A set of easy to use instructions
provides the means by which this fixed data can be referenced and retrieved from the Program
Memory.
Other Operations
In addition to the above functional instructions, a range of other instructions also exist such as
the "HALT" instruction for Power-down operations and instructions to control the operation of
the Watchdog Timer for reliable program operations under extreme electric or electromagnetic
environments. For their relevant operations, refer to the functional related sections.
Rev. 1.00
168
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Instruction Set Summary
The instructions related to the data memory access in the following table can be used when the
desired data memory is located in Data Memory sector 0.
Table Conventions
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Description
Cycles
Flag Affected
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract immediate data from ACC with Carry
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
1
1Note
1
1
1Note
1
1
1Note
1
1
1Note
1Note
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
1
1Note
Z
Z
Z
Z
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,x
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Rev. 1.00
169
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Mnemonic
Description
Cycles Flag Affected
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
2
1Note
1Note
1Note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
None
2Note
2Note
2Note
None
None
None
2Note
None
1
1Note
1Note
1
1Note
1
1
None
None
None
TO, PDF
None
None
TO, PDF
Bit Operation
CLR [m].i
SET [m].i
Branch Operation
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m]
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if Data Memory is not zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
Table Read Operation
TABRD [m] Read table (specific page) to TBLH and Data Memory
TABRDL [m] Read table (last page) to TBLH and Data Memory
ITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory
Increment table pointer TBLP first and Read table (last page) to TBLH and
ITABRDL [m]
Data Memory
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
SWAP [m]
SWAPA [m]
HALT
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
Note: 1. For skip instructions, if the result of the comparison involves a skip then up to three cycles are required, if
no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the “CLR WDT” instruction the TO and PDF flags may be affected by the execution status. The TO
and PDF flags are cleared after the “CLR WDT” instructions is executed. Otherwise the TO and PDF
flags remain unchanged.
Rev. 1.00
170
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Extended Instruction Set
The extended instructions are used to support the full range address access for the data memory.
When the accessed data memory is located in any data memory sections except sector 0, the
extended instruction can be used to access the data memory instead of using the indirect addressing
access to improve the CPU firmware performance.
Mnemonic
Description
Cycles
Flag Affected
Add Data Memory to ACC
Add ACC to Data Memory
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
2
2Note
2
2Note
2
2Note
2
2Note
2Note
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
Z, C, AC, OV, SC, CZ
C
2
2
2
2Note
2Note
2Note
2Note
2
Z
Z
Z
Z
Z
Z
Z
Z
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
2
2Note
2
2Note
Z
Z
Z
Z
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
2
2Note
2
2Note
2
2Note
2
2Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
2
2Note
None
None
Clear bit of Data Memory
Set bit of Data Memory
2Note
2Note
None
None
Arithmetic
LADD A,[m]
LADDM A,[m]
LADC A,[m]
LADCM A,[m]
LSUB A,[m]
LSUBM A,[m]
LSBC A,[m]
LSBCM A,[m]
LDAA [m]
Logic Operation
LAND A,[m]
LOR A,[m]
LXOR A,[m]
LANDM A,[m]
LORM A,[m]
LXORM A,[m]
LCPL [m]
LCPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
LINCA [m]
LINC [m]
LDECA [m]
LDEC [m]
Rotate
LRRA [m]
LRR [m]
LRRCA [m]
LRRC [m]
LRLA [m]
LRL [m]
LRLCA [m]
LRLC [m]
Data Move
LMOV A,[m]
LMOV [m],A
Bit Operation
LCLR [m].i
LSET [m].i
Rev. 1.00
171
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Mnemonic
Description
Cycles Flag Affected
Branch
LSZ [m]
LSZA [m]
LSNZ [m]
LSZ [m].i
LSNZ [m].i
LSIZ [m]
LSDZ [m]
LSIZA [m]
LSDZA [m]
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if Data Memory is not zero
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
2Note
2Note
2Note
2Note
2Note
2Note
2Note
2Note
2Note
None
None
None
None
None
None
None
None
None
3Note
3Note
3Note
None
None
None
3Note
None
2Note
2Note
2Note
2
None
None
None
None
Table Read
LTABRD [m] Read table to TBLH and Data Memory
LTABRDL [m] Read table (last page) to TBLH and Data Memory
LITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory
Increment table pointer TBLP first and Read table (last page) to TBLH and
LITABRDL [m]
Data Memory
Miscellaneous
LCLR [m]
LSET [m]
LSWAP [m]
LSWAPA [m]
Clear Data Memory
Set Data Memory
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Note: 1. For these extended skip instructions, if the result of the comparison involves a skip then up to four cycles
are required, if no skip takes place two cycles is required.
2. Any extended instruction which changes the contents of the PCL register will also require three cycles for
execution.
Rev. 1.00
172
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Instruction Definition
ADC A,[m]
Description
Operation
Affected flag(s)
Add Data Memory to ACC with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
ACC ← ACC + [m] + C
OV, Z, AC, C, SC
ADCM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m] + C
OV, Z, AC, C, SC
Add Data Memory to ACC
ADD A,[m]
Description
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the Accumulator.
Operation
Affected flag(s)
ACC ← ACC + [m]
OV, Z, AC, C, SC
ADD A,x
Description
Operation
Affected flag(s)
Add immediate data to ACC
The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator.
ACC ← ACC + x
OV, Z, AC, C, SC
ADDM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory
The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m]
OV, Z, AC, C, SC
AND A,[m]
Description
Operation
Affected flag(s)
Logical AND Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ [m]
Z
AND A,x
Description
Operation
Affected flag(s)
Logical AND immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ x
Z
ANDM A,[m]
Description
Operation
Affected flag(s)
Logical AND ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
[m] ← ACC ″AND″ [m]
Z
Rev. 1.00
173
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
CALL addr
Description
Operation
Affected flag(s)
Subroutine call
Unconditionally calls a subroutine at the specified address. The Program Counter then
increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Stack ← Program Counter + 1
Program Counter ← addr
None
CLR [m]
Description
Operation
Affected flag(s)
Clear Data Memory
Each bit of the specified Data Memory is cleared to 0.
[m] ← 00H
None
CLR [m].i
Description
Operation
Affected flag(s)
Clear bit of Data Memory
Bit i of the specified Data Memory is cleared to 0.
[m].i ← 0
None
CLR WDT
Description
Operation
Affected flag(s)
Clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CPL [m]
Description
Operation
Affected flag(s)
Complement Data Memory
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa.
[m] ← [m]
Z
CPLA [m]
Description
Operation
Affected flag(s)
Complement Data Memory with result in ACC
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
ACC ← [m]
Z
DAA [m]
Description
Operation
Affected flag(s)
Decimal-Adjust ACC for addition with result in Data Memory
Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater than 9
or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6
will be added to the high nibble. Essentially, the decimal conversion is performed by adding
00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag
may be affected by this instruction which indicates that if the original BCD sum is greater than
100, it allows multiple precision decimal addition.
[m] ← ACC + 00H or
[m] ← ACC + 06H or [m] ← ACC + 60H or
[m] ← ACC + 66H
C
Rev. 1.00
174
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
DEC [m]
Description
Operation
Affected flag(s)
Decrement Data Memory
Data in the specified Data Memory is decremented by 1.
[m] ← [m] − 1
Z
DECA [m]
Description
Operation
Affected flag(s)
Decrement Data Memory with result in ACC
Data in the specified Data Memory is decremented by 1. The result is stored in the
Accumulator. The contents of the Data Memory remain unchanged.
ACC ← [m] − 1
Z
HALT
Description
Operation
Affected flag(s)
Enter power down mode
This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power
down flag PDF is set and the WDT time-out flag TO is cleared.
TO ← 0
PDF ← 1
TO, PDF
INC [m]
Description
Operation
Affected flag(s)
Increment Data Memory
Data in the specified Data Memory is incremented by 1.
[m] ← [m] + 1
Z
INCA [m]
Description
Operation
Affected flag(s)
Increment Data Memory with result in ACC
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator.
The contents of the Data Memory remain unchanged.
ACC ← [m] + 1
Z
JMP addr
Description
Operation
Affected flag(s)
Jump unconditionally
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Program Counter ← addr
None
MOV A,[m]
Description
Operation
Affected flag(s)
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ← [m]
None
MOV A,x
Description
Operation
Affected flag(s)
Move immediate data to ACC
The immediate data specified is loaded into the Accumulator.
ACC ← x
None
MOV [m],A
Description
Operation
Affected flag(s)
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ← ACC
None
Rev. 1.00
175
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
NOP
Description
Operation
Affected flag(s)
No operation
No operation is performed. Execution continues with the next instruction.
No operation
None
OR A,[m]
Description
Operation
Affected flag(s)
Logical OR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise
logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ [m]
Z
OR A,x
Description
Operation
Affected flag(s)
Logical OR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ x
Z
ORM A,[m]
Description
Operation
Affected flag(s)
Logical OR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
[m] ← ACC ″OR″ [m]
Z
RET
Description
Operation
Affected flag(s)
Return from subroutine
The Program Counter is restored from the stack. Program execution continues at the restored
address.
Program Counter ← Stack
None
RET A,x
Description
Operation
Affected flag(s)
Return from subroutine and load immediate data to ACC
The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address.
Program Counter ← Stack
ACC ← x
None
RETI
Description
Operation
Affected flag(s)
Return from interrupt
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the
EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Program Counter ← Stack
EMI ← 1
None
RL [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← [m].7
None
Rev. 1.00
176
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
RLA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left with result in ACC
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain
unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← [m].7
None
RLC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← C
C ← [m].7
C
RLCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the
Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← C
C ← [m].7
C
RR [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← [m].0
None
RRA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0
rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the
Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← [m].0
None
RRC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← C
C ← [m].0
C
Rev. 1.00
177
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
RRCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← C
C ← [m].0
C
SBC A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
ACC ← ACC − [m] − C
OV, Z, AC, C, SC, CZ
SBC A, x
Description
Operation
Affected flag(s)
Subtract immediate data from ACC with Carry
The immediate data and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC - [m] - C
OV, Z, AC, C, SC, CZ
SBCM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry and result in Data Memory
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m] − C
OV, Z, AC, C, SC, CZ
SDZ [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is 0
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
[m] ← [m] − 1
Skip if [m]=0
None
SDZA [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is zero with result in ACC
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0,
the program proceeds with the following instruction.
ACC ← [m] − 1
Skip if ACC=0
None
Rev. 1.00
178
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
SET [m]
Description
Operation
Affected flag(s)
Set Data Memory
Each bit of the specified Data Memory is set to 1.
[m] ← FFH
None
SET [m].i
Description
Operation
Affected flag(s)
Set bit of Data Memory
Bit i of the specified Data Memory is set to 1.
[m].i ← 1
None
SIZ [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is 0
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] + 1
Skip if [m]=0
None
SIZA [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is zero with result in ACC
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
ACC ← [m] + 1
Skip if ACC=0
None
SNZ [m].i
Description
Operation
Affected flag(s)
Skip if Data Memory is not 0
If the specified Data Memory is not 0, the following instruction is skipped. As this requires the
insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m].i ≠ 0
None
SNZ [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is not 0
If the specified Data Memory is not 0, the following instruction is skipped. As this requires the
insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m]≠ 0
None
SUB A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − [m]
OV, Z, AC, C, SC, CZ
Rev. 1.00
179
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
SUBM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with result in Data Memory
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m]
OV, Z, AC, C, SC, CZ
SUB A,x
Description
Operation
Affected flag(s)
Subtract immediate data from ACC
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − x
OV, Z, AC, C, SC, CZ
SWAP [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 ↔ [m].7~[m].4
None
SWAPA [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory with result in ACC
The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
ACC.3~ACC.0 ← [m].7~[m].4
ACC.7~ACC.4 ← [m].3~[m].0
None
SZ [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0
If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Skip if [m]=0
None
SZA [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0 with data movement to ACC
The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
ACC ← [m]
Skip if [m]=0
None
SZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is 0
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires
the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is not 0, the program proceeds with the following instruction.
Skip if [m].i=0
None
Rev. 1.00
180
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
TABRD [m]
Description
Operation
Affected flag(s)
Read table (specific page) to TBLH and Data Memory
The low byte of the program code (specific page) addressed by the table pointer pair (TBLP and TBHP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
TABRDL [m]
Description
Operation
Affected flag(s)
Read table (last page) to TBLH and Data Memory
The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
ITABRD [m]
Description
Operation
Affected flag(s)
Increment table pointer low byte first and read table to TBLH and Data Memory
Increment table pointer low byte, TBLP, first and then the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
ITABRDL [m]
Description
Operation
Affected flag(s)
Increment table pointer low byte first and read table (last page) to TBLH and Data Memory
Increment table pointer low byte, TBLP, first and then the low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
XOR A,[m]
Description
Operation
Affected flag(s)
Logical XOR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ [m]
Z
XORM A,[m]
Description
Operation
Affected flag(s)
Logical XOR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
[m] ← ACC ″XOR″ [m]
Z
XOR A,x
Description
Operation
Affected flag(s)
Logical XOR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ x
Z
Rev. 1.00
181
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Extended Instruction Definition
The extended instructions are used to directly access the data stored in any data memory sections.
LADC A,[m]
Description
Operation
Affected flag(s)
Add Data Memory to ACC with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
ACC ← ACC + [m] + C
OV, Z, AC, C, SC
LADCM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m] + C
OV, Z, AC, C, SC
LADD A,[m]
Description
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the Accumulator.
Operation
Affected flag(s)
ACC ← ACC + [m]
OV, Z, AC, C, SC
LADDM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory
The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m]
OV, Z, AC, C, SC
LAND A,[m]
Description
Operation
Affected flag(s)
Logical AND Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ [m]
Z
LANDM A,[m]
Description
Operation
Affected flag(s)
Logical AND ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
[m] ← ACC ″AND″ [m]
Z
LCLR [m]
Description
Operation
Affected flag(s)
Clear Data Memory
Each bit of the specified Data Memory is cleared to 0.
[m] ← 00H
None
LCLR [m].i
Description
Operation
Affected flag(s)
Clear bit of Data Memory
Bit i of the specified Data Memory is cleared to 0.
[m].i ← 0
None
Rev. 1.00
Add Data Memory to ACC
182
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
LCPL [m]
Description
Operation
Affected flag(s)
Complement Data Memory
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa.
[m] ← [m]
Z
LCPLA [m]
Description
Operation
Affected flag(s)
Complement Data Memory with result in ACC
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
ACC ← [m]
Z
LDAA [m]
Description
Operation
Affected flag(s)
Decimal-Adjust ACC for addition with result in Data Memory
Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater than 9
or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6
will be added to the high nibble. Essentially, the decimal conversion is performed by adding
00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag
may be affected by this instruction which indicates that if the original BCD sum is greater than
100, it allows multiple precision decimal addition.
[m] ← ACC + 00H or
[m] ← ACC + 06H or [m] ← ACC + 60H or
[m] ← ACC + 66H
C
LDEC [m]
Description
Operation
Affected flag(s)
Decrement Data Memory
Data in the specified Data Memory is decremented by 1.
[m] ← [m] − 1
Z
LDECA [m]
Description
Operation
Affected flag(s)
Decrement Data Memory with result in ACC
Data in the specified Data Memory is decremented by 1. The result is stored in the
Accumulator. The contents of the Data Memory remain unchanged.
ACC ← [m] − 1
Z
LINC [m]
Description
Operation
Affected flag(s)
Increment Data Memory
Data in the specified Data Memory is incremented by 1.
[m] ← [m] + 1
Z
LINCA [m]
Description
Operation
Affected flag(s)
Increment Data Memory with result in ACC
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator.
The contents of the Data Memory remain unchanged.
ACC ← [m] + 1
Z
Rev. 1.00
183
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
LMOV A,[m]
Description
Operation
Affected flag(s)
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ← [m]
None
LMOV [m],A
Description
Operation
Affected flag(s)
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ← ACC
None
LOR A,[m]
Description
Operation
Affected flag(s)
Logical OR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise
logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ [m]
Z
LORM A,[m]
Description
Operation
Affected flag(s)
Logical OR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
[m] ← ACC ″OR″ [m]
Z
LRL [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← [m].7
None
LRLA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left with result in ACC
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain
unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← [m].7
None
LRLC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← C
C ← [m].7
C
LRLCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the
Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← C
C ← [m].7
C
Rev. 1.00
184
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
LRR [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← [m].0
None
LRRA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0
rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the
Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← [m].0
None
LRRC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← C
C ← [m].0
C
LRRCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← C
C ← [m].0
C
LSBC A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
ACC ← ACC − [m] − C
OV, Z, AC, C, SC, CZ
LSBCM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry and result in Data Memory
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m] − C
OV, Z, AC, C, SC, CZ
Rev. 1.00
185
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
LSDZ [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is 0
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
[m] ← [m] − 1
Skip if [m]=0
None
LSDZA [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is zero with result in ACC
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0,
the program proceeds with the following instruction.
ACC ← [m] − 1
Skip if ACC=0
None
LSET [m]
Description
Operation
Affected flag(s)
Set Data Memory
Each bit of the specified Data Memory is set to 1.
[m] ← FFH
None
LSET [m].i
Description
Operation
Affected flag(s)
Set bit of Data Memory
Bit i of the specified Data Memory is set to 1.
[m].i ← 1
None
LSIZ [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is 0
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] + 1
Skip if [m]=0
None
LSIZA [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is zero with result in ACC
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
ACC ← [m] + 1
Skip if ACC=0
None
LSNZ [m].i
Description
Operation
Affected flag(s)
Skip if Data Memory is not 0
If the specified Data Memory is not 0, the following instruction is skipped. As this requires the
insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m].i ≠ 0
None
Rev. 1.00
186
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
LSNZ [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is not 0
If the content of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m] ≠ 0
None
LSUB A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − [m]
OV, Z, AC, C, SC, CZ
LSUBM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with result in Data Memory
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m]
OV, Z, AC, C, SC, CZ
LSWAP [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 ↔ [m].7~[m].4
None
LSWAPA [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory with result in ACC
The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
ACC.3~ACC.0 ← [m].7~[m].4
ACC.7~ACC.4 ← [m].3~[m].0
None
LSZ [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0
If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Skip if [m]=0
None
LSZA [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0 with data movement to ACC
The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
ACC ← [m]
Skip if [m]=0
None
Rev. 1.00
187
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
LSZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is 0
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires
the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is not 0, the program proceeds with the following instruction.
Skip if [m].i=0
None
LTABRD [m]
Description
Operation
Affected flag(s)
Read table (current page) to TBLH and Data Memory
The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
LTABRDL [m]
Description
Operation
Affected flag(s)
Read table (last page) to TBLH and Data Memory
The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
LITABRD [m]
Description
Operation
Increment table pointer low byte first and read table to TBLH and Data Memory
Increment table pointer low byte, TBLP, first and then the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
Affected flag(s)
None
LITABRDL [m]
Description
Operation
Affected flag(s)
Increment table pointer low byte first and read table (last page) to TBLH and Data Memory
Increment table pointer low byte, TBLP, first and then the low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
LXOR A,[m]
Description
Operation
Affected flag(s)
Logical XOR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ [m]
Z
LXORM A,[m]
Description
Operation
Affected flag(s)
Logical XOR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
[m] ← ACC ″XOR″ [m]
Z
Rev. 1.00
188
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website for
the latest version of the package information.
Additional supplementary information with regard to packaging is listed below. Click on the relevant
section to be transferred to the relevant website page.
• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• Packing Meterials Information
• Carton information
Rev. 1.00
189
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
—
0.472 BSC
—
B
—
0.394 BSC
—
C
—
0.472 BSC
—
D
—
0.394 BSC
—
E
—
0.032 BSC
—
F
0.012
0.015
0.018
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
—
7°
Symbol
Rev. 1.00
Dimensions in mm
Min.
Nom.
Max.
A
—
12.00 BSC
—
B
—
10.00 BSC
—
C
—
12.00 BSC
—
D
—
10.00 BSC
—
E
—
0.80 BSC
—
F
0.30
0.37
0.45
G
1.35
1.40
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
—
7°
190
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
48-pin LQFP (7mm×7mm) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
—
0.354 BSC
—
B
—
0.276 BSC
—
C
—
0.354 BSC
—
D
—
0.276 BSC
—
E
—
0.020 BSC
—
F
0.007
0.009
0.011
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
—
7°
Symbol
Rev. 1.00
Dimensions in mm
Min.
Nom.
Max.
A
—
9.00 BSC
—
B
—
7.00 BSC
—
C
—
9.00 BSC
—
D
—
7.00 BSC
—
E
—
0.50 BSC
—
F
0.17
0.22
0.27
G
1.35
1.40
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
—
7°
191
April 17, 2015
HT66F0187
A/D 8-Bit Flash MCU with EEPROM
Copyright© 2015 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw.
Rev. 1.00
192
April 17, 2015