HT46R63/HT46C63 - 8-Bit A/D with LCD Type MCU

HT46R63/HT46C63
A/D with LCD Type 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
- HA0004E HT48 & HT46 MCU UART Software Implementation Method
- HA0005E Controlling the I2C bus with the HT48 & HT46 MCU Series
- HA0047E An PWM application example using the HT46 series of MCUs
Features
· Operating voltage:
· 8-level stack
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
· Operating frequency: External RC or Crystal
· 2 external interrupts (high/low going trigger)
· 32.768kHz crystal oscillator used for timing purposes
· One comparator
· Watchdog enable or disable function
· LCD: 20´3 or 19´4, 1/3 bias with 12 pins logical
· 1x16 bits timer with an overflow interrupt (TMR)
outputs options. (select by options in unit of 4 pins, ´8
high sink)
· Time base generator (clock source: 32.768kHz)
and RTC interrupts
· Built-in R type bias generator
· 4K´15 program memory
· 8 channels 8-bits resolution A/D converter
· 208´8 data memory RAM
· 4 channels PWM outputs
· Maximum of 32 I/O lines (shared with INT0, INT1,
· 56-pin SSOP, 100-pin QFP package
TMR, AN0~AN7, PWM0~PWM3)
General Description
The HT46R63/HT46C63 are 8-bit, high performance,
RISC architecture microcontroller devices specifically
designed for A/D product applications that interface directly to analog signals and which require LCD Interface. The mask version HT46C63 is fully pin and
functionally compatible with the OTP version HT46R63
device.
Rev. 2.30
The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, multi-channel A/D
Converter, Pulse Width Modulation function, HALT and
wake-up functions, in addition to a flexible and
configurable LCD interface enhance the versatility of
these devices to control a wide range of applications requiring analog signal processing and LCD interfacing,
such as electronic metering, environmental monitoring,
handheld measurement tools, motor driving, etc., for
both industrial and home appliance application areas.
1
March 22, 2006
HT46R63/HT46C63
Block Diagram
IN T 0 /IN T 1
M
T M R C
T M R
In te rru p t
C ir c u it
4 k ´ 1 5
P ro g ra m
R O M
S ta c k
8 L e v e ls
P ro g ra m
C o u n te r
IN T C 0
IN T C 1
U
fS
E N /D IS
W D T
G e n e ra to r
R E
V D
V S
A V D
M
M P
S
U
X
D A T A
R A M
(2 0 8 ´ 8 )
P A
P O R T A
P A C
M
W D T
T im e B a s e /R T C /L C D
In s tr u c tio n
R e g is te r
/4
Y S
T M R
X
U
R T C O S C
W D T O S C
fS Y S /4
X
G e n e ra to r
P A 0 ~ P A 7
D
S
P B
D
M U X
In s tr u c tio n
D e c o d e r
8 -C h a n n e l A /D
O S C 4
O S C 2
P C
S h ifte r
T im in g
G e n e ra to r
A C C
O p tio n
P R O M
P D
R -B IA S
L C D
4 ´ 1 9 /3 ´ 2 0
L o g ic a l O u tp u t O p tio n
P O R T D
P D C
P W
H ig h
M id d le
L o w
P O R T C
P C C
O S C 1
P B 0 /A N 0 ~ P B 7 /A N 7
C o n v e rte r
S T A T U S
A L U
O S C 3
P O R T B
P B C
M
C o m p a ra to r
P C 0 ~ P C 7
P D
P D
P D
P D
P D
0 /
4 /
5 /
6 /
7
P W M 0 ~ P D 3 /P W
IN T 0
IN T 1
T M R
M 3
C H G O , C M P O
C M P P , C M P N
V L C D
Rev. 2.30
C O M 0 ~ C O M 3 /S E G 1 9
S E G 0 ~ S E G 1 8
2
E N /D IS
f
H A L T
R T C
March 22, 2006
HT46R63/HT46C63
Pin Assignment
V L
C M
C M
C M
C H
O S
O S
V
O S
O S
R
3
5 4
C M P P
O S C 2
4
5 3
C M P N
O S C 1
5
5 2
V L C D
N C
R E S
6
5 1
C O M 0
N C
P A 0
7
5 0
C O M 1
P A 1
8
4 9
C O M 2
P A 2
9
4 8
C O M 3 /S E G 1 9
P A 3
1 0
4 7
S E G 1 4
P A 4
1 1
4 6
S E G 1 3
P A 5
1 2
4 5
S E G 1 2
P A 6
1 3
4 4
S E G 1 1
P B 0 /A N 0
1 6
4 1
S E G 8
P B 1 /A N 1
1 7
4 0
S E G 7
P B 2 /A N 2
1 8
3 9
S E G 6
P B 3 /A N 3
1 9
3 8
S E G 5
A V D D
2 0
3 7
S E G 4
P C 0
2 1
3 6
S E G 3
P C 1
2 2
3 5
S E G 2
P C 2
2 3
3 4
S E G 1
P C 3
2 4
3 3
S E G 0
P D 0 /P W M 0
2 5
3 2
P D 7
P D 1 /P W M 1
2 6
3 1
P D 6 /T M R
P D 2 /P W M 2
2 7
3 0
P D 5 /IN T 1
P D 3 /P W M 3
2 8
2 9
P D 4 /IN T 0
P
P
H T 4 6 R 6 3 /H T 4 6 C 6 3
1 0 0 Q F P -A
3 0
3 1
5 0
5 1
C O M
C O M
C O M
C O M
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
N C
0
1
2
3 /S E G 1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1 0
9
8
7
6
5
4
3
2
1
0
N C
S E G 9
P
N C
N C
S E G 1 0
4 2
P
N C
N C
N C
4 3
1 5
P
N C
N C
N C
1 4
V
0 /A
1 /A
2 /A
3 /A
4 /A
5 /A
6 /A
7 /A
A V
P
8 0
N C
N C
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
S S
N 0
N 1
N 2
N 3
N 4
N 5
N 6
N 7
D D
N C
N C
N C
N C
N C
N C
N C
N C
P D
P D
P D
P D
P D
P D
P D
P D
P C
P C
P C
P C
P C
P C
P C
P C
P A 7
V S S
P B
P B
P B
P B
P B
P B
P B
P B
P
8 1
1 0 0
1
N C
P
N C
N C
C D
P N
P P
P O
G O
C 4
C 3
D D
C 2
C 1
E S
N C
C M P O
V D D
N C
C H G O
5 5
N C
5 6
2
N C
1
O S C 3
N C
N C
N C
O S C 4
7
6 /T
5 /IN
4 /IN
3 /P
2 /P
1 /P
0 /P
7
6
5
4
3
2
1
0
Rev. 2.30
M R
T 1
T 0
W M 3
W M 2
W M 1
W M 0
H T 4 6 R 6 3 /H T 4 6 C 6 3
5 6 S S O P -A
3
March 22, 2006
HT46R63/HT46C63
Pin Description
Pin Name
I/O
Option
Description
PA0~PA7
I/O
Pull-high
Wake-up
I/O lines with pull-high resistors (bit option). I/O modes of each line are controlled by related control register bit (PAC). Each line of PA can be optioned
as a wake-up input (bit option). I/O configurations: Schmitt trigger/CMOS
PB0/AN0~
PB7/AN7
I/O
Pull-High
I/O lines with pull-high resistors (bit option). I/O modes of each line are controlled by related control register bit (PBC). I/O configurations: Schmitt trigger/CMOS. Each PB line is pin shared with an A/D converter input.
PC0~PC7
I/O
Pull-High
I/O lines with pull-high resistors (bit option). I/O modes of each line are controlled by related control register bit (PCC). I/O configurations: Schmitt trigger/CMOS.
PD0/PWM0~
PD3/PWM3,
PD4/INT0,
PD5/INT1,
PD6/TMR,
PD7
I/O
OSC1
OSC2
I
O
RC or crystal
A resistor across OSC1 and VDD or a crystal across OSC1 and OSC2 will
generate a system clock.
OSC3
OSC4
I
O
¾
32768Hz crystal across OSC3 and OSC4 will generate RTC clock signal
which only provides system timing.
CMPN
I
¾
Negative input for comparator
CMPP
I
¾
Positive input for comparator
CMPO
O
¾
Comparator output
CHGO
O
¾
Comparator output with 32768Hz carrier
VDD
¾
¾
Positive power supply
AVDD
¾
¾
A/D converter Positive power supply, AVDD should be externally connected to VDD
VSS
¾
¾
Negative power supply, ground
RES
I
¾
Schmitt trigger reset input
VLCD
I/O
¾
LCD highest voltage; should be connected to VDD with external resistor.
SEG0~SEG18
O
SEG7~SEG18
logical CMOS
LCD segment signal driving outputs SEG7~SEG10 can be optioned as output lines. SEG11~SEG14, SEG15~SEG18 can be optioned as a high sinking output lines.
COM0~COM2
COM3/SEG19
O
COM3 or
SEG19
I/O lines with pull-high resistors (bit option). I/O modes of each line are conPull-High PWM
trolled by related control register bit (PDC). I/O configurations: Schmitt trigInterrupt Falling
ger/CMOS. The PD0~PD3 can be selected as PWM outputs. INT0/INT1
and/or Rising
are falling/rising edge selectable triggers.
LCD common signal driving outputs
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 2.30
4
March 22, 2006
HT46R63/HT46C63
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
fSYS=4MHz
2.2
¾
5.5
V
fSYS=8MHz
3.3
¾
5.5
V
¾
1
2
¾
3
5
¾
4
8
¾
¾
5
¾
¾
20
¾
¾
1
¾
¾
2
¾
¾
5
¾
¾
15
10
12
16
20
24
32
16
20
26
32
40
52
38
52
68
76
104
136
Conditions
VDD
VDD
IDD1
Operating Voltage
Operating Current
(Crystal OSC, RC OSC)
¾
3V
5V
IDD2
Operating Current
(Crystal OSC, RC OSC)
ISTB1
Standby Current
(*fS=WDT OSC)
3V
Standby Current
(*fS=fSYS OSC)
3V
Standby Current
(*fS=RTC OSC)
3V
Standby Current
(*fS=RTC OSC)
3V
ISTB2
ISTB3
ISTB4
5V
5V
5V
5V
5V
ISTB5
Standby Current
(*fS=RTC OSC)
3V
5V
ISTB6
Standby Current
(*fS=RTC OSC)
3V
5V
VIL1
VIH1
No load, fSYS=4MHz,
ADC Off
No load, fSYS=8MHz,
ADC Off
No load, System HALT,
LCD Off
No load, System HALT,
LCD Off
No load, System HALT,
LCD Off
No load, System HALT,
LCD On at HALT, R type,
VLCD=VDD
(Low bias current option)
No load, System HALT,
LCD On at HALT, R type,
VLCD=VDD
(Middle bias current option)
No load, System HALT,
LCD On at HALT, R type,
VLCD=VDD
(High bias current option)
mA
mA
mA
mA
mA
mA
mA
mA
Input Low Voltage for I/O Ports
¾
¾
0
¾
0.3VDD
V
Input High Voltage for I/O Ports
¾
¾
0.7VDD
¾
VDD
V
V
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLCD
LCD Highest Voltage
¾
¾
0
¾
VDD
V
IOH1
I/O Port Source Current
-2
-4
¾
-5
-8
¾
6
12
¾
10
25
¾
-2
-4
¾
-4
-8
¾
8
¾
¾
16
¾
¾
16
¾
¾
32
¾
¾
¾
¾
-100
VIL2
3V
VOH=0.9VDD
5V
IOL1
3V
I/O Port Sink Current
VOL=0.1VDD
5V
IOH2
IOL2
SEG7~18 Logical Source
Current
3V
VOH=0.9VDD
5V
3V
SEG7~10 Logical Sink Current
VOL=0.1VDD
5V
IOL3
3V
SEG11~18 Logical Sink Current
VOL=0.1VDD
5V
IOHTOTAL I/O Port Total Source Current
Rev. 2.30
¾
¾
5
mA
mA
mA
mA
mA
mA
March 22, 2006
HT46R63/HT46C63
Test Conditions
Symbol
IOLTOTAL
Parameter
I/O Port Total Sink Current
Min.
VDD
Conditions
¾
¾
3V
¾
Typ.
Max.
Unit
mA
¾
¾
100
20
60
100
10
30
50
RPH
Pull-High Resistance (I/O)
VOS
Comparator Input Offset Voltage
¾
¾
-10
¾
10
mV
VI
Comparator Input Voltage
Range
¾
¾
0.2
¾
VDD-0.8
V
VAD
A/D Input Voltage
¾
¾
0
¾
VDD
V
EAD
A/D Conversion Integral
Nonlinearity Error
¾
¾
¾
±0.5
±1
LSB
IADC
Additional Power Consumption
if A/D Converter is Used
3V
¾
0.5
1
mA
¾
1.5
3
mA
Note:
5V
¾
5V
kW
²*fS² please refer to clock option of Watchdog Timer
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
fSYS1
System Clock (Crystal)
fSYS2
System Clock
(32768Hz Crystal OSC)
fTIMER
Timer Input Frequency
tWDTOSC
Min.
Typ.
Max.
Unit
Conditions
¾
2.2V~5.5V
400
¾
4000
¾
3.3V~5.5V
400
¾
8000
¾
2.2V~5.5V
¾
32768
¾
¾
2.2V~5.5V
0
¾
4000
¾
3.3V~5.5V
0
¾
8000
45
90
180
32
65
130
3V
¾
Watchdog Oscillator Period
5V
kHz
Hz
kHz
ms
Watchdog Time-out Period
(WDT OSC)
¾
¾
¾
216
¾
tWDTOSC
Watchdog Time-out Period
( fSYS/4)
¾
¾
¾
218
¾
tSYS
Watchdog Time-out Period
(32768Hz)
¾
¾
¾
216
¾
tRTCOSC
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
¾
1024
¾
tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tAD
A/D Clock Period
¾
¾
1
¾
¾
ms
tADC
A/D Conversion Time
¾
¾
64
¾
¾
tAD
tADCS
A/D Sampling Time
¾
¾
¾
32
¾
tAD
tCOMP
Response Time of Comparator
¾
¾
¾
¾
3
ms
tWDT
Power-up or wake-up
from HALT
Note: tSYS=1/fSYS1 or 1/fSYS2
Rev. 2.30
6
March 22, 2006
HT46R63/HT46C63
Functional Description
When executing a jump instruction, conditional skip execution, loading PCL (program counter lower-order byte
register), subroutine call, initial reset, interrupts or return
from subroutine or interrupts, the program counter manipulates the program transfer by loading the address
corresponding to each instruction.
Execution Flow
The system clock for the microcontroller is derived from
an external RC or crystal oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of 4 system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch and decoding takes an instruction cycle while execution take the next instruction cycle. However, the pipelining scheme causes each instruction to
effectively execute in a cycle. If an instruction changes
the program counter, two cycles are required to complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower-order byte of the program counter (PCL) can
be accessed by using software instructions. Moving
data into the PCL performs a short jump. The destination will be within the current program ROM page.
Program Counter - PC
The program counter controls the sequence in which the
instructions stored in the program memory are executed
and its contents specify full range of program memory.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
Once the control transfer takes place, the execution suffers from having an additional dummy cycle.
Program Memory - PROM
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
T 2
P C
P C
T 3
T 4
T 1
T 2
T 3
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
T 4
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*11~*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0000
0
0
0
0
0
0
0
0
External Interrupt 0
0000
0
0
0
0
0
1
0
0
External Interrupt 1
0000
0
0
0
0
1
0
0
0
Timer/Event Counter Overflow
0000
0
0
0
0
1
1
0
0
Time Base Time-out
0000
0
0
0
1
0
0
0
0
A/D Interrupt
0000
0
0
0
1
0
1
0
0
RTC Interrupt
0000
0
0
0
1
1
0
0
0
@3
@2
@1
@0
Skip
Program Counter+2
Loading PCL
@11~@8
@7
@6
@5
@4
Jump, Call Branch
#11~#8
#7
#6
#5
#4
#3
#2
#1
#0
Return (RET, RETI)
S11~S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
*11~*0: Program counter bits
S11~S0: Stack register bits
#11~#0: Instruction code bits
@7~@0: PCL bits
Rev. 2.30
7
March 22, 2006
HT46R63/HT46C63
0 0 0 H
4096´15 bits, addressed by the program counter and table pointer.
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
E x te r n a l In te r r u p t 0 S u b r o u tin e
0 0 8 H
Certain locations in the program memory are reserved
for special usage:
E x te r n a l In te r r u p t 1 S u b r o u tin e
0 0 C H
· Location 000H
0 1 0 H
This area is reserved for program initialization. After
chip reset, the program always begins execution at location 000H.
0 1 4 H
T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e
T im e B a s e T im e - o u t In te r r u p t S u b r o u tin e
A /D
C o n v e rte r E O C
P ro g ra m
M e m o ry
In te r r u p t S u b r o u tin e
0 1 8 H
· Location 004H
R T C
This area is reserved for the external interrupt 0 service program. If the INT0 input pin is activated, the interrupt is enabled and the stack is not full, the program
begins execution at this location.
T im e - o u t In te r r u p t s u b r o u tin e
n 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
· Location 008H
This area is reserved for the external interrupt 1 service program. If the INT1 input pin is activated, the interrupt is enabled and the stack is not full, the program
begins execution at this location.
F 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
F F F H
1 5 b its
N o te : n ra n g e s fro m
· Location 00CH
0 to F
Program Memory
This area is reserved for the timer/event counter interrupt service program. If a timer interrupt results from a
timer/event counter overflow, and the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
higher-order byte to lower portion of TBLH(08H) and
the remaining bits (1 bits) of TBLH are read as ²0².
The table pointer (TBLP) is read/write register (07H),
which indicates the table location. Before accessing
the table, the location has to be placed in TBLP. The
TBLH is read only and cannot be restored. If the main
routine and the ISR(interrupt service routine) both employ the table read instruction, the contents of TBLH in
the main routine are likely to be changed by the table
read instruction used in the ISR. Errors are thus
brought about. Given this, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read
instruction has to be applied in both main routine and
the ISR, the interrupt is supposed to be disabled prior
to the table read instruction. It will not be enabled until
the TBLH in the main routine has been backup. All table related instructions require two cycles to complete
the operation. These areas may function as normal
program memory depending upon the requirements.
· Location 010H
This area is reserved for the time base interrupt service program. If the a time base time-out occurs, the
interrupt is enabled and the stack is not full, the program begins execution at this location.
· Location 014H
This area is reserved for the A/D converter interrupt
service program. If the interrupt is activated (when the
A/D conversion is completed), the interrupt is enabled
and the stack is not full, the program begins execution
at this location.
· Location 018H
This area is reserved for the RTC interrupt service
program. When the RTC time-out occurs, the interrupt
is enabled and the stack is not full, the program begins
execution at this location.
Stack Register - STACK
· Table location
This is a special part of memory, which is used to save
the contents of the program counter only. The stack is
organized into 8 levels and is neither part of the data not
programmable space, and is not accessible. The acti-
Any location in the program memory can be used as
look-up tables. The instructions ²TABRDC [m]² (the
current page, 1 page=256 words) and ²TABRDL [m]²
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
Table Location
Instruction
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
*11~*0: Table location bits
P11~P8: Current program counter bits
@7~@0: Table pointer bits
Rev. 2.30
8
March 22, 2006
HT46R63/HT46C63
In d ir e c t A d d r e s s in g R e g is te r 0
vated level is indexed by the stack pointer and is not acc e s s ib le . A t a s u b r out i n e c al l or i n t e r r u p t
acknowledgment, the contents of the program counter
are pushed onto the stack. At the end of a subroutine or
an interrupt routine, signaled by a return instruction
(RET or RETI), the program counter is restored to its
previous value from the stack. After a chip reset, the
stack pointer will point to the top of the stack.
0 0 H
0 8 H
T B L H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decreased (by RET or RETI), the interrupt will
be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In
similar case, if the stack is full and a ²call² is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 8 return addresses
are stored).
0 9 H
R T C C
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
T M R H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 D H
T M R L
0 E H
T M R C
0 F H
1 0 H
1 1 H
Data Memory - RAM
The data memory is designed with 239´8 bits. The
data memory is divided into two functional groups: special function registers and general purpose data memory (208´8). Most are read/write, but some are read
only.
The special function registers include the indirect addressing register 0 and 1 (R0;00H, R1;02H), memory
pointer 0 and 1 (MP0;01H, MP1;03H), bank pointer
(BP:04H), accumulator (ACC;05H), program counter
lower-order byte register (PCL;06H), table pointer
(TBLP;07H), table higher-order byte register
(TBLH;08H), real time clock control register
(RTCC;09H), status register (STATUS;0AH), interrupt
control register (INTC0;0BH), timer higher-order byte
register (TMRH;0CH), timer lower-order byte register
(TMRL;0DH), timer control register (TMRC;0EH), I/O
port data registers (PA;12H, PB;14H, PC;16H, PD;18H),
I/O port control registers (PAC;13H, PBC;15H,
PCC;17H, PDC;19H), PWM0 (1AH), PWM1 (1BH),
PWM2 (1CH), PWM3 (1DH), INTC1 (1EH),the A/D result register (ADR;21H), the A/D control register
(ADCR;22H) and the A/D clock setting register
(ACSR;23H). The remaining space before the 30H is reserved for future expansion and reading these locations
will return the result ²00H². The general-purpose data
memory, addressed from 30H to FFH, is used for data
and control information under instruction commands.
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
P D
1 9 H
P D C
1 A H
P W M 0
1 B H
P W M 1
1 C H
P W M 2
1 D H
P W M 3
1 E H
IN T C 1
S p e c ia l P u r p o s e
D A T A M E M O R Y
1 F H
2 0 H
2 1 H
A D R
2 2 H
A D C R
2 3 H
A C S R
2 4 H
2 F H
3 0 H
F F H
G e n e ra l P u rp o s e
D a ta M e m o ry
(2 0 8 B y te s )
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
Indirect Addressing Register
Location 00H (02H) is indirect addressing registers that
are not physically implemented. Any read/write operation of [00H] ([02H]) will access data memory pointed to
by MP0 (MP1). Reading location 00H (02H) itself indirectly will return the result ²00H². Writing indirectly results in no operation.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and cleared by ²SET [m].i² and
²CLR [m].i², respectively. They are also indirectly accessible through memory pointers (MP0 and MP1).
Rev. 2.30
0 1 H
The memory pointers are 8-bit registers. Only the
MP1/R1 can be used to access the LCD RAM (BP=1).
9
March 22, 2006
HT46R63/HT46C63
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
3
OV
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by
executing the ²HALT² instruction.
5
TO
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
set by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
Status (0AH) Register
Bank Pointer
The bank pointer is used to assign the accessed RAM
bank. When the users want to access the RAM bank 0 a
²0² should be loaded onto BP. When the BP is equal to
²1², the LCD RAM will be accessed (use MP1/R1 indirect addressing only). RAM locations before 40H in any
bank are overlapped.
tion operations related to the status register may give
different results from those intended. The TO flag
can be affected only by system power-up, a WDT
time-out or executing the ²CLR WDT² or ²HALT² instruction. The PDF flag can be affected only by executing the ²HALT² or ²CLR WDT² instruction or a
system power-up.
Accumulator
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
Arithmetic and Logic Unit - ALU
Interrupt
This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
The microcontroller provides two external interrupts, an
internal timer/event counter overflow interrupt, a time
b a se t i m e - o u t i n t e r r u p t , a n A / D co n ve r t e r
end-of-conversion interrupt and a real time clock
time-out interrupt. The interrupt control registers
(INTC0: 0BH and INTC1: 1EH) contains the interrupt
control bits to set the enable or disable and the interrupt
request flags.
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation
but also changes the status register.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may happen during this interval but
only the interrupt request flags are recorded. If a certain
interrupt requires servicing within the service routine,
the programmer may set the EMI and the corresponding
bit of INTC0/INTC1 to allow interrupt nesting. If the stack
is full, the interrupt request will not be acknowledged,
even if the related interrupt is enabled, until the SP is decreased. If immediate service is desired, the stack has
to be prevented from becoming full.
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addi-
Rev. 2.30
10
March 22, 2006
HT46R63/HT46C63
During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related
interrupt control bit are set to ²1² (of course, if the stack
is not full). To return from the interrupt subroutine, ²RET²
or ²RETI² may be invoked. RETI will set the EMI bit to
enable an interrupt service, but RET will not.
All these kinds of interrupts have the wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack and then
branching to subroutines at specified location(s) in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register or status
register are altered by the interrupt service program,
which corrupts the desired control sequence, the programmer should save these contents first.
Interrupts, occurring in the interval between rising edge
of two consecutive T2 pulses, will be serviced on the
later of the two T2 pulses, if the corresponding interrupts
are enabled. In the case of simultaneous requests the
priorities in the follow table apply. These can be masked
by clearing the EMI bit.
External interrupts are triggered by a high to low and/or
low to high transition of INT0/INT1 and the related interrupt request flag (bit 4/5 of INTC0 ) will be set. When the
interrupt is enabled, the stack is not full and the external
interrupt is active, a subroutine call to location
004H/008H will occur. The external interrupt request
flag and EMI bits will cleared to disable other interrupts.
Interrupt Source
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag (bit
6 of INTC0), caused by a timer overflow. When the interrupt is enabled, the stack is not full and the timer/event
counter interrupt request flag is set, a subroutine call to
location 00CH will occur. The related interrupt request
flag will be reset and the EMI bit cleared to disable further interrupts.
Vector
External Interrupt 0
1
004H
External Interrupt 1
2
008H
Timer/Event Counter Overflow
Interrupt
3
00CH
Time Base Time-out Interrupt
4
010H
End of A/D Conversion Interrupt
5
014H
RTC Time-out Interrupt
6
018H
The external interrupt 0/1 request flags (EI0F/EI1F),
timer/event counter interrupt request flag (TF), time
base interrupt request flag (TBF), A/D converter interrupt request flag (ADF), RTC interrupt request flag
(RTF), enable external interrupt 0/1 (EE0I/EE1I), enable
timer/event counter interrupt bit (ETI), enable time base
interrupt (ETBI), enable A/D converter interrupt (EADI),
enable RTC interrupt (ERTI) and enable master interrupt bit(EMI) constitute interrupt control registers
(INTC0/INTC1) which is located at 0BH/1EH in the data
memory. EMI, EE0I, EE1I, ETI, EADI and ERTI are used
to control the enabling/disabling of interrupts. These bits
prevent the requested interrupts from being serviced.
Once the interrupt request flags (EI0F, EI1F, TF, TBF,
ADF, RTF) are set, they will remain in the INTC0/INTC1
until the interrupts are serviced or cleared by software
instructions.
The time base time-out interrupt is initialized by setting
the time base time-out interrupt request flag (bit 4 of
INTC1), caused by a time base time-out. When the interrupt is enabled, the stack is not full and the time base
time-out interrupt request flag is set, a subroutine call to
location 010H will occur. The related interrupt request
flag will be reset and the EMI bit cleared to disable further interrupts.
The A/D converter end-of-conversion interrupt is initialized by setting the A/D end-of-conversion interrupt request flag (bit 5 of INTC1), caused by an end of A/D
conversion. When the interrupt is enabled, the stack is
not full and the end of A/D conversion interrupt request
flag is set, a subroutine call to location 014H will occur.
The related interrupt request flag will be reset and the
EMI bit cleared to disable further interrupts.
It is suggested that a program does not use the ²call²
within a interrupt subroutine. It because interrupts often
occur in an unpredictable manner or need to be serviced
immediately in some applications. If only one stack is
left and enabling the interrupt is not well controlled, the
original control sequence will be damaged once the
²CALL² operates in the interrupt subroutine. The definitions of INTC0 and INTC1 registers are as shown.
The real time clock time-out interrupt is initialized by setting the real time clock interrupt request flag (bit 6 of
INTC1), caused by a RTC time-out. When the interrupt
is enabled, the stack is not full and the RTC time-out interrupt request flag is set, a subroutine call to location
018H will occur. The related interrupt request flag will be
reset and the EMI bit cleared to disable further interrupts.
Rev. 2.30
Priority
11
March 22, 2006
HT46R63/HT46C63
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1= enabled; 0= disabled)
1
EEI0
Controls the external interrupt 0 (1= enabled; 0= disabled)
2
EEI1
Controls the external interrupt 1 (1= enabled; 0= disabled)
3
ETI
Controls the timer/event counter overflow interrupt (1= enabled; 0= disabled)
4
EIF0
External interrupt 0 request flag (1= active; 0= inactive)
5
EIF1
External interrupt 1 request flag (1= active; 0= inactive)
6
TF
Timer/Event Counter overflow request flag (1= active; 0= inactive)
7
¾
For test mode used only.
Must be written as ²0²; otherwise may result in unpredictable operation.
INTC0 (0BH) Register
Bit No.
Label
Function
0
ETBI
Controls the time base interrupt (1= enabled; 0= disabled)
1
EADI
Controls the A/D converter interrupt (1= enabled; 0= disabled)
2
ERTI
Controls the real time clock interrupt (1= enabled; 0= disabled)
3
¾
4
TBF
Time base time-out interrupt 0 request flag (1= active; 0= inactive)
5
ADF
End of A/D conversion interrupt request flag (1= active; 0= inactive)
6
RTF
RTC time-out interrupt request flag (1= active; 0= inactive)
7
¾
Unused bit, read as ²0²
Unused bit, read as ²0²
INTC1 (1EH) Register
Oscillator Configuration
and the resistance should range from 24kW to 1MW. The
system clock, divided by 4, is available on OSC2, which
can be used to synchronize external logic.
There are four oscillator circuits implemented in the
microcontroller.
If the system clock uses the crystal oscillator, a crystal
across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no
other external components are demanded. Instead of a
crystal, the resonator can also be connected between
OSC1 and OSC2 to get a frequency reference, but two
external capacitors in OSC1 and OSC2 are required.
Two of them are designed for system clocks, namely the
external RC oscillator and the crystal oscillator, which
are determined by options. The HALT mode stops the
system oscillator and resists the external signal to conserve power. Another one is a 32768Hz crystal oscillator, which only provides use for real time clock. The
other one is a built-in 12KHz RC oscillator, which is used
for WDTOSC.
If the RTCOSC is used, a crystal across OSC3 and
OSC4 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are demanded.
If the system clock uses the external RC oscillator, an
external resistor between OSC1 and VDD is required
V
O S C 3
O S C 4
3 2 7 6 8 H z C r y s ta l/R T C
O s c illa to r
O S C 1
D D
4 7 0 p F
O S C 1
O S C 2
C r y s ta l O s c illa to r
fS
Y S
O S C 2
/4
R C
O s c illa to r
System Oscillator
Note:
The external resistor and capacitor components connected to the 32768Hz crystal are not necessary to provide oscillation. For applications where precise RTC frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances.
Rev. 2.30
12
March 22, 2006
HT46R63/HT46C63
Watchdog Timer - WDT
case that ²CLR WDT1² and ²CLR WDT2² are chosen
(i.e. CLR WDT times equal two), these two instructions
must be executed to clear the WDT; otherwise, the WDT
may reset the chip as a result of time-out. The RTC oscillator should be designed as an auto-speed-up oscillator. After the RTC oscillator is oscillating, the
auto-speed-up should be turned off.
The clock source of WDT (and LCD, RTC, Time Base )
is implemented by a dedicated crystal oscillator
(32.768kHz: RTCOSC) or instruction clock (system frequency divided by 4: fSYS/4) or a dedicated RC oscillator
(12kHz:WDTOSC) decided by options. This timer is designed to prevent a software malfunction or sequence
from jumping to an unknown location with unpredictable
results. The watchdog timer can be disabled by options.
If the watchdog timer is disabled, all the executions related to the WDT result in no operation. The WDT
time-out period is fixed as 216/fS. The fS means the clock
frequency of WDT, time base, RTC and LCD. If
WDTOSC is selected as the WDT clock, the time-out
period may vary with temperatures, VDD and process
variations. The WDTOSC and RTCOSC can be still running (decided by option) at the halt mode if they are selected as the WDT clock source. Once the 32.768kHz
oscillator (with a period of 31.25ms normally) is selected
to be the clock source of WDT (and LCD, RTC, Time
Base), it is directly divided by 216 to get the nominal
time-out period of 2 seconds. If the WDT clock comes
from the instruction clock, the WDT will stop counting
and lose its protecting purpose in halt mode. In this situation the logic can only be restarted by external logic. If
the device operates in a noisy environment, using the
RTCOSC or WDTOSC is strongly recommended, since
the HALT will stop the system clock.
Time Base Generator
There is a time base generator implemented in the micro-controller. The time base generator provides
time-out periods selection whose range from fS/212 to
fS/215. When the time base time-out occurs and the
stack is not full and the time base interrupt is enabled,
an interrupt subroutine call to ROM location 010H will
activate.
RTC Generator
There is an RTC generator implemented in the micro-controller. The RTC generator provides software
configurable real time clock periods whose range from
fS/28 to fS/215. When the RTC time-out occurs and the
stack is not full and the RTC interrupt is enabled, an interrupt subroutine call to ROM location 018H will activate. The RTCC is the real time clock control register
used to select the division ratio of RTC clock sources.
RTCC.7~RTCC.3 cannot be used.
The overflow of WDT under normal operation will initialize ²chip reset² and set the status bit ²TO². But in the
HALT mode, the overflow will initialize a ²warm reset²,
and only the program counter and SP are reset to zero.
To clear the contents of WDT , 3 methods are adopted;
external reset (a low level to RES), software instruction(s) and a HALT instruction. The software instruction(s) include ²CLR WDT² and the other set - ²CLR
WDT1² and ²CLR WDT2² Of these two types of instruction, only one can be active depending on the options ²CLR WDT times selection option². If the ²CLR WDT² is
selected (i.e. CLRWDT times equal one), any execution
of the ²CLR WDT² instruction will clear the WDT. In the
W D T O S C
fS Y S /4
R T C O S C
RTCC.2
RTCC.1
RTCC.0
RTC Clock
Divided Factor
0
0
0
28
0
0
1
29
0
1
0
210
0
1
1
211
1
0
0
212
1
0
1
213
1
1
0
214
1
1
1
215
C L R W D T
M
X
U
fS
1 6 - B it C o u n te r
D
W D T tim e - o u t
R E S
1 5 - B it C o u n te r
O p tio n s
4 to 1 M U X
T im e b a s e : fS /2
O p tio n s
7 to 1 M U X
L C D
R T C C .2 ~ R T C C .0
8 to 1 M U X
R T C : fS /2 8~ fS /2
1 2
~ fS /2
1 5
fre q u e n c y : fS /2 2~ fS /2
8
1 5
Watchdog Timer
Rev. 2.30
13
March 22, 2006
HT46R63/HT46C63
Power Down Operation - HALT
Reset
The HALT mode is initialized by the ²HALT² instruction
and results in the following...
· RES reset during normal operation
· The system oscillator will be turned off but the
· RES reset during HALT
There are three ways in which a reset can occur:
WDTOSC or RTCOSC will stop or keep running decided by option (If the WDTOSC or RTCOSC is selected)
· WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that resets only the program counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions.
Most registers are reset to the ²initial condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
· The contents of the on-chip RAM and registers remain
unchanged.
· WDT will be cleared and recounted again (if the WDT
clock is from the WDTOSC or RTCOSC).
· All of the I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². After the TO and PDF flags are
examined, the reason for chip reset can be determined.
The PDF flag is cleared by system power-up or executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the program counter and SP; the others keep their original status.
TO PDF
Reset Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: ²u² means unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (system start-up timer) provides an
extra-delay to delay 1024 system clock pulses when
system power-up or the system awakes from the HALT
state.
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by the option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it is awakening from an interrupt, two
sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the
program will resume execution at the next instruction. If
the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request
flag is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.
Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other
words, a dummy period will be inserted after wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
When the system power-up occurs, the SST delay is
added during the reset period. But when the reset comes from the RES pin, the SST delay is disabled. Any
wake-up from HALT will enable the SST delay.
An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES
reset).
The chip reset statuses of the functional units are as
shown.
Program Counter
000H
Interrupt
Disable
WDT
Clear. After master reset, WDT
begins counting
Timer/Event Counter Off
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Input/Output Ports
Input mode
Stack Pointer
Points to the top of the stack
The 32.768kHz crystal oscillator still run or stop in the
halt mode. (decided by option)
Rev. 2.30
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March 22, 2006
HT46R63/HT46C63
V
D D
Reading TMRH will also latch the TMRL into the low
byte buffer to avoid the false timing problem. Reading
TMRL returns the contents of the low byte buffer. In
other words, the low byte of timer/event counter cannot
be read directly. It has to read the TMRH first to make
the low byte contents of timer/event counter latched into
the buffer. The TMRC is the timer/event counter control
register, which defines the operating mode, counting enable or disable and active edge.
0 .0 1 m F *
1 0 0 k W
R E S
1 0 k W
0 .1 m F *
Reset Circuit
Note:
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR) pin. The timer mode functions as a normal timer
with the clock source coming from fSYS/4. The pulse
width measurement mode can be used to count the high
or low level duration of the external signal (TMR). The
counting is based on fSYS/4.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to
avoid noise interference.
H A L T
W a rm
R e s e t
W D T
In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current
contents in the timer/event counter to FFFFH. Once
overflow occurs, the counter is reloaded from the
timer/event counter preload register and generates the
corresponding interrupt request flag (TF; bit 6 of INTC0)
at the same time.
R E S
C o ld
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
O S C 1
S y s te m
R e s e t
In pulse width measurement mode with the TON and TE
bits are equal to one, once the TMR has received a transition from low to high (or high to low if the TE bit is 0) it
will start counting until the TMR returns to the original
level and reset the TON. The measured result will remain in the timer/event counter even if the activated
transition occurs again. In other words, only one cycle
measurement can be done. Until setting the TON, the
cycle measurement will function again as long as it receives further transition pulse. Note that, in this operating mode, the timer/event counter starts counting not
according to the logic level but according to the transition edges. In the case of counter overflows, the counter
is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two
modes.
Reset Configuration
V D D
R E S
tS
S T
S S T T im e - o u t
C h ip
R e s e t
Reset Timing Chart
Timer/Event Counter
A timer/event counter is implemented in the device. The
timer/event counter contains a 16-bit programmable
count-up counter and the clock may come from an external source or the internal clock source.
To enable the counting operation, the timer ON bit (TON;
bit 4 of TMRC) should be set to 1. In the pulse width
measurement mode, the TON will be cleared automatically after the measurement cycle is complete. But in the
other two modes the TON can only be reset by instructions. The overflow of the timer/event counter is one of
the wake-up sources. No matter what the operation
mode is, writing a 0 to ETI can disabled the corresponding interrupt service.
The internal clock source is the system clock divided by
4: fSYS/4. The external clock input allows the user to
count external events, measure time intervals or pulse
widths, or to generate an accurate time base.
There are 3 registers related to timer/event counter;
TMRH(0CH), TMRL(0DH), TMRC(0EH). Writing TMRL
only stores the data into a low byte buffer, and writing
TMRH will put the written data and the low contents of
low byte buffer to preload register (16 bits) simultaneously. The timer/event counter preload register is
changed by writing TMRH operations and writing TMRL
will keep the timer/event counter preload register unchanged.
Rev. 2.30
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register will also
load the data to timer/event counter. But if the
timer/event counter is turned on, data written to the
timer/event counter will only be kept in the timer/event
counter preload register. The timer/event counter will
15
March 22, 2006
HT46R63/HT46C63
The registers states are summarized in the following table.
Register
Reset
(Power On)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
BP
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
000H
000H
000H
000H
000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
RTCC
--xx x111
--xx x111
--xx x111
--xx x111
--uu uuuu
PCH.PCL
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRL
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRC
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PWM0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
PWM1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
PWM2
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
PWM3
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
INTC1
-000 -000
-000 -000
-000 -000
-000 -000
-uuu -uuu
ADR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
0--- -100
0--- -100
0--- -100
0--- -100
u--- -uuu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
Rev. 2.30
16
March 22, 2006
HT46R63/HT46C63
Bit No.
Label
0~2
¾
Unused bits, read as ²0²
3
TE
Defines the TMR active edge of the timer/event counter:
In Event Counter Mode (TM1,TM0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (TM1,TM0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
TON
To enable or disable timer counting (0=disabled; 1=enabled)
5
¾
6
7
Function
Unused bit, read as ²0²
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TM0
TM1
TMRC (0EH) Register
fS
Y S
/4
D a ta B u s
T M 1
T M 0
T M R
1 6 - B it
T im e r /e v e n t C o u n te r
P r e lo a d R e g is te r
T E
T M 1
T M 0
T O N
1 6 - B it
T im e r /e v e n t C o u n te r
(T M R H , T M R L )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
8 - B it
L o w B y te B u ffe r
R e lo a d
O v e r flo w
to In te rru p t
Timer/Event Counter
still operate until the overflow occurs (a timer/event
counter reloading will occur at the same time).
sistor is enabled) will be exhibited automatically. The input sources are also dependent on the control register. If
the control register bit is ²1², the input will read the pad
state (²mov² and read-modify-write instructions). If the
control register bit is ²0², the contents of the latches will
move to internal data bus (²mov² and read-modify-write
instructions). The input paths (pad state or latches) of
read-modify-write instructions are dependent on the
control register bits. For output function, CMOS is the
only configuration. These control registers are mapped
to locations 13H, 15H, 17H and 19H.
When the timer/event counter (reading TMRH) is read,
the clock will be blocked to avoid errors. As this may results in a counting error, this must be taken into consideration by the programmer.
Input/Output Ports
There are 32 bi-directional input/output lines in the micro-controller, labeled from PA to PD, which are mapped
to the data memory of [12H], [14H], [16H] and [18H], respectively. All of these I/O ports can be used as input and
output operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at the T2
rising edge of instruction ²MOV A,[m]² (m=12H, 14H,
16H or 18H). For output operation, all the data is latched
and remains unchanged until the output latch is rewritten.
After a chip reset, these input/output lines stay at a high
level (pull-high options) or floating state (non-pull-high
options). Each bit of these input/output latches can be
set or cleared by ²SET [m].i² (m=12H, 14H, 16H or 18H)
instructions. Some instructions first input data and then
follow the output operations. For example, ²SET [m].i²
CLR [m].i², ²CPLA [m]² read the entire port states into
the CPU, execute the defined operations (bit-operation),
and then write the results back to the latches or the accumulator.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC) to control the input/output configuration.
With this control register, CMOS output or schmitt trigger input with or without (depends on options) pull-high
resistor structures can be reconfigured dynamically (i.e.,
on-the fly) under software control. To function as an input, the corresponding latch of the control register has to
be set as ²1². The pull-high resistor (if the pull-high re-
Rev. 2.30
Each line of port A has the capability of waking-up the
device. The pull-high resistor of each I/O line is decided
by options.
17
March 22, 2006
HT46R63/HT46C63
V
C o n tr o l B it
W r ite C o n tr o l R e g is te r
P H
Q
D
D a ta B u s
C K
D D
Q
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
P A
P B
P C
P D
D a ta B it
Q
D
P A
P B
P C
P D
7
7
7
7
Q
C K
W r ite D a ta R e g is te r
0 ~
0 ~
0 ~
0 ~
S
P W M 0 ~ P W M 3
( P D 0 ~ P D 3 O n ly )
M
R e a d D a ta R e g is te r
S y s te m
U
X
W a k e -u p
( P A o n ly )
W a k e - u p o p tio n s
P u ls e G e n e r a to r
D is a b le /H ig h /L o w
H ig h - L o w
T o In te rru p t
E d g e to P u ls e
P D 4 a n d P D 5
Input/Output Ports
Comparator
LCD Display Memory
T h e re is a c o m p a r at or i m p l em ent ed i n t h i s
microcontroller. This comparator can be enabled/disabled by options. Its inputs are CMPP(+) and CMPN(-)
and outputs are CMPO and CHGO. When the CMPN input level is less than the level of CMPP, the CMPO output is VDD. When the CMPN input level is higher than the
level of CMPP, the CMPO output is VSS.
The microcontroller provides an area of embedded data
memory for LCD driver. This area is located from 40H to
53H of he RAM Bank 1. Bank pointer (BP; located at
04H of the RAM) is the switch between the general purpose RAM and the LCD display memory. When the BP
is set to ²1², any data written into 40H~53H (indirect accessing by using the MP1and R1) will effect the LCD
display. When the BP is cleared to ²0², any data written
into 40H to 53H will access the general purpose data
memory. The LCD display memory can be read and written to only by indirect addressing mode using MP1.
When data is written into the display data area it is automatically read by the LCD driver which then generates
the corresponding LCD driving signals. To turn the display on or off, an ²1² or a ²0² is written to the corresponding bit of the display memory, respectively. The figure
illustrates the mapping between the display memory
and LCD pattern for the microcontroller.
The CHGO signal is combined with CMPO and
32768Hz carrier if 32768Hz RTC oscillator is applied.
This comparator also can be disabled by options. When
the system enters halt mode, the comparator is disabled
to reduce power consumption. Once the comparator is
disabled, the CHGO and CMPO will stay at VSS level.
A d d r
C O M
4 0 H
4 1 H
4 2 H
4 3 H
4 F H
5 0 H
5 1 H
5 2 H
5 3 H
B it
0
0
S E G M E N T
1
1
2
2
3
3
0
1
2
3
1 5
1 6
1 7
1 8
1 9
Display Memory
Rev. 2.30
18
March 22, 2006
HT46R63/HT46C63
LCD Driver Output and Bias Circuit
and SEG15~SEG18 can be optioned individually. Once
an LCD segment is optioned as a logical output, the contents of bit 0 of the related segment address in LCD
RAM will appear on the segment.
The output number of the microcontroller LCD driver
can be 20´3 or 19´4 by options (ie., 1/3 duty or 1/4
duty). The bias type of LCD driver is² R² type, no external capacitor is required. The LCD can be optioned as
²LCD on at HALT² or ²LCD off at HALT² which are dependent on options.
The SEG7~SEG18 also can be optioned as logical outputs. Each group of SEG7~SEG10, SEG11~SEG14
Memory
Segment Output
Bit 0=0
Bit 0=1
VSS
VDD
Logical Output Function
D u r in g a r e s e t p u ls e
V 3
V 2
C O M 0 , C O M 1 , C O M 2
V 1
V 0
V 3
V 2
V 1
A ll L C D d r iv e r o u tp u ts
V 0
N o r m a l o p e r a tio n m o d e
V 3
V 2
C O M 0
V 1
V 0
V 3
V 2
C O M 1
V 1
V 0
V 3
V 2
C O M 2
V 1
V 0
V 3
V 2
C O M 3
V 1
V 0
V 3
V 2
L C D s e g m e n ts o n
C O M 0 , 1 , 2 , 3 s id e s a r e u n lig h te d
V 1
V 0
V 3
V 2
O n ly L C D s e g m e n ts o n
C O M 0 s id e s a r e lig h te d
V 1
V 0
V 3
V 2
O n ly L C D s e g m e n ts o n
C O M 2 s id e s a r e lig h te d
V 1
V 0
V 3
V 2
L C D s e g m e n ts o n
C O M 0 , 1 s id e s a r e lig h te d
V 1
V 0
V 3
V 2
L C D s e g m e n ts o n
C O M 0 , 2 s id e s a r e lig h te d
V 1
V 0
V 3
V 2
L C D s e g m e n ts o n
C O M 0 , 1 , 2 s id e s a r e lig h te d
V 1
V 0
H A L T m o d e (L C D o ff a t H A L T )
V 3
V 2
C O M 0 , C O M 1 , C O M 2
V 1
V 0
V 3
V 2
A ll L C D d r iv e r o u tp u ts
V 1
V 0
LCD Driver Outputs (1/4 Duty, 1/3 Bias)
Note:
If LCD is turned on at HALT mode, the LCD outputs are dependent on LCD display memory.
If LCD is turned off at HALT mode, the power will be V3=V2=V1=V0=VDD
Rev. 2.30
19
March 22, 2006
HT46R63/HT46C63
V
D D
E x te rn a l R
V L C D
V 3
V 2
V 1
N o te :
B ia s c u r r e n t ( lo w , m id d le o r h ig h ) is s e le c ta b le b y R O M c o d e o p tio n .
L C D O ff: V 0 = V 1 = V 2 = V 3 = V L C D ( = V D D , if c o n n e c t V L C D to V D D w ith e x te r n a l r e s is to r )
L C D d r iv e r a n d b ia s O n : V 0 = V S S ,V 1 = V L C D /3 ,V 2 = V L C D * 2 /3 ,V 3 = V L C D
* V
D D
** V
D D = 3 V
L o w : 8
M id d le
H ig h : 4
V 0
L C D O n /O ff
=
L o w
M id
H ig
5 V , B ia
: 8 m A ,
d le : 1 6
h : 4 8 m A
, B
m A
: 1
8 m
s fo
e x te
m A ,
, e x
r V LC D =
rn a l R =
e x te rn a
te rn a l R
ia s fo r
, e x te rn
6 m A , e x
A , e x te
V
3 V
2 4 0 k W
l R = 1 2 0 k W
= 4 0 k W
L C D = 3 V
a l R = 0 k W
te rn a l R = 0 k W
rn a l R = 0 k W
LCD Bias Block Diagram and Application Circuit
A/D Converter
pull-high resistor of this I/O line are disabled. The EOCB
bit (bit 6 of the ADCR) is end of A/D conversion flag.
Check this bit to know when A/D conversion is completed. The START bit of the ADCR is used to begin the
conversion of A/D converter. Give START bit a falling
edge that means the A/D conversion has started. The
A/D converter remains in reset state while the START
stays at ²1². In order to ensure the A/D conversion is
completed, the START should stay at ²0² until the EOCB
is cleared to ²0² (end of A/D conversion).
The 8 channels and 8-bit resolution A/D converter are
implemented in this microcontroller. The reference voltage is AVDD. The AVDD pin must be connected to VDD
externally. Conversion accuracy may therefore be degraded by voltage drops and noise in the event of
heavily loaded or badly coupled power supply lines. The
A/D converter contains 3 special registers which are;
ADR (21H), ADCR (22H) and ACSR (23H). The ADR is
A/D result register. After the A/D conversion is completed, the ADR should be read to get the conversion result data. The ADCR is an A/D converter control
register, which defines the A/D channel number, analog
channel select, start A/D conversion control bit and the
end of A/D conversion flag. If the users want to start an
A/D conversion, define PB configuration, select the converted analog channel, and give START bit a rising edge
and falling edge (0®1®0). At the end of A/D conversion, the EOCB bit is cleared and an A/D converter interrupt occurs(if the A/D converter interrupt is enabled).
The ACSR is an A/D clock setting register, which is used
to select the A/D clock source.
Bit 7 of the ACSR register is used for test purposes only
and must not be used for other purposes by the application program. Bit1 and bit0 of the ACSR register are
used to select the A/D clock source.
When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to ²1²
when the START bit is set from ²0² to ²1².
Important Note for A/D initialization:
Special care must be taken to initialize the A/D converter each time the Port B A/D channel selection bits
are modified, otherwise the EOCB flag may be in an undefined condition. An A/D initialization is implemented
by setting the START bit high and then clearing it to zero
within 10 instruction cycles of the Port B channel selection bits being modified. Note that if the Port B channel
selection bits are all cleared to zero then an A/D initialization is not required.
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the ADCR are used to
select an analog input channel. There are a total of 8
channels to select. The bit5~bit3 of the ADCR are used
to set PB configurations. PB can be an analog input or
as digital I/O line decided by these 3 bits. Once a PB line
is selected as an analog input, the I/O functions and
Rev. 2.30
20
March 22, 2006
HT46R63/HT46C63
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
D7
D6
D5
D4
D3
D2
D1
D0
ADR (21H) Register
Bit No.
Label
Functions
ACS0
ACS1
ACS2
ACS2, ACS1, ACS0: A/D channel selection
0,0,0: AN0
0,0,1: AN1
0,1,0: AN2
0,1,1: AN3
1,0,0: AN4
1,0,1: AN5
1,1,0: AN6
1,1,1: AN7
3
4
5
PCR0
PCR1
PCR2
PCR2, PCR1, PCR0: PB7~PB0 pad functions
0,0,0: PB7, PB6, PB5, PB4, PB3, PB2, PB1, PB0
0,0,1: PB7, PB6, PB5, PB4, PB3, PB2, PB1, AN0
0,1,0: PB7, PB6, PB5, PB4, PB3, PB2, AN1, AN0
0,1,1: PB7, PB6, PB5, PB4, PB3, AN2, AN1, AN0
1,0,0: PB7, PB6, PB5, PB4, AN3, AN2, AN1, AN0
1,0,1: PB7, PB6, PB5, AN4, AN3, AN2, AN1, AN0
1,1,0: PB7, PB6, AN5, AN4, AN3, AN2, AN1, AN0
1,1,1: AN7, AN6, AN5, AN4, AN3, AN2, AN1, AN0
6
EOCB
Indicates end of A/D conversion. (0 = end of A/D conversion)
Each time bits 3~5 change state the A/D should be initialized by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See ²Important note for A/D initialization².
7
START Starts the A/D conversion. (0®1®0= start; 0®1= Reset A/D converter and set EOCB to ²1²)
0
1
2
ADCR (22H) Register
Bit No.
Label
Functions
0
1
ADCS1, ADCS0: Selects the A/D converter clock source
0,0: fSYS/2
ADCS0
0,1: fSYS/8
ADCS1
1,0: fSYS/32
1,1: Undefined
2
CMPC
Comparator control (*)
0: Disable
1: Enable
3~6
¾
Unused bit, read as ²0²
7
TEST
For test mode used only
Note:
²*² This bit is 0 during reset.
ACSR (23H) Register
Rev. 2.30
21
March 22, 2006
HT46R63/HT46C63
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using EOCB Polling Method to detect end of conversion
clr
EADI
; disable ADC interrupt
mov
a,00000001B
mov
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
mov
a,00100000B
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov
ADCR,a
; and select AN0 to be connected to the A/D converter
:
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
START
set
START
; reset A/D
clr
START
; start A/D
Polling_EOC:
sz
EOCB
; poll the ADCR register EOCB bit to detect end of A/D conversion
jmp
polling_EOC
; continue polling
mov
a,ADR
; read conversion result high byte value from the ADR register
mov
adr_buffer,a
; save result to user defined memory
:
:
jmp
start_conversion
; start next A/D conversion
Example: using interrupt method to detect end of conversion
clr
EADI
; disable ADC interrupt
mov
a,00000001B
mov
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
mov
mov
a,00100000B
ADCR,a
:
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
; and select AN0 to be connected to the A/D converter
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
START
set
START
clr
START
clr
ADF
set
EADI
set
EMI
:
:
:
; ADC interrupt service routine
ADC_ISR:
mov
acc_stack,a
mov
a,STATUS
mov
status_stack,a
:
:
mov
a,ADR
mov
adr_buffer,a
clr
START
set
START
clr
START
:
:
EXIT_INT_ISR:
mov
a,status_stack
mov
STATUS,a
mov
a,acc_stack
reti
Rev. 2.30
; reset A/D
; start A/D
; clear ADC interrupt request flag
; enable ADC interrupt
; enable global interrupt
; save ACC to user defined memory
; save STATUS to user defined memory
; read conversion result low byte value from the ADR register
; save result to user defined register
; reset A/D
; start A/D
; restore STATUS from user defined memory
; restore ACC from user defined memory
22
March 22, 2006
HT46R63/HT46C63
M in im u m
o n e in s tr u c tio n c y c le n e e d e d , M a x im u m
te n in s tr u c tio n c y c le s a llo w e d
S T A R T
E O C B
A /D s a m p lin g tim e
tA D C S
P C R 2 ~
P C R 0
0 0 0 B
A /D
tA
s a m p lin g tim e
A /D s a m p lin g tim e
tA D C S
D C S
1 0 0 B
1 0 0 B
1 0 1 B
0 0 0 B
1 . P B p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
A C S 2 ~
A C S 0
0 0 0 B
P o w e r-o n
R e s e t
0 1 0 B
0 0 0 B
0 0 1 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
1 : D e fin e P B c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
A /D
N o te :
A /D c lo c k m u s t b e fS
tA D C S = 3 2 tA D
tA D C = 6 4 tA D
Y S
/2 , fS
tA D C
c o n v e r s io n tim e
Y S
/8 o r fS
Y S
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
tA D C
c o n v e r s io n tim e
A /D
d o n 't c a r e
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
/3 2
A/D Conversion Timing
and the output function of PDi is enabled, writing ²1² to
PDi data register will enable the PWMi output function.
Otherwise the PDi will stay at ²0². The PWM modulation
frequency, PWM cycle frequency and PWM cycle duty
are summarized in the following table.
PWM
The micro-controller provides 4 channels (6+2) bits
PWM outputs shared with PD0~PD3. The PWM channels has their data register. The PWMs uses a PWM
counter whose stages are 8 (stage 1~stage 8: fSYS/21 ~
fSYS/28). The frequency source of the PWM counter comes from fSYS. The PWM register is an eight bits register. The waveforms of PWM outputs are as shown.
Once the PDi (i=0~3) is selected as the PWMi output
fS
Y S
PWMi Modulation
Frequency
PWMi Cycle
Frequency
PWMi Cycle
Duty
fSYS/64
fSYS/256
[PWM]/256
/2
[P W M ] = 1 0 0
P W M
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 6 /6 4
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
2 6 /6 4
P W M
m o d u la tio n p e r io d : 6 4 /fS
M o d u la tio n c y c le 0
Y S
M o d u la tio n c y c le 1
P W M
M o d u la tio n c y c le 2
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 3
M o d u la tio n c y c le 0
Y S
PWM Mode
Rev. 2.30
23
March 22, 2006
HT46R63/HT46C63
Options
The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure proper
system function.
No.
Options
1
PA wake-up enable or disable (1/0) options
2
WDT/LCD/RTC/Time Base Clock Source (fS):
RTCOSC(32768Hz crystal), T1 or WDTOSC (*1)
3
CLR WDT instructions: 1/2
4
WDT enable or disable
5
PA pull-high enable or disable (1 option : 4 bits (0~3/4~7))
6
PB pull-high enable or disable (1 option : 4 bits (0~3/4~7))
7
PC pull-high enable or disable (1 option : 4 bits (0~3/4~7))
8
PD pull-high enable or disable (1 option : 4 bits (0~3/4~7))
9
INT0 or INT1 trigger edge: disable; high to low; low to high; low to high or high to low.
10
COM3 or SEG19 (1/4 or 1/3 duty)
11
LCD on/off at halt mode
12
enable or disable Comparator
13
enable or disable PWMi function for PDi (bit optional)
14
fS/212~fS/215: Time base period
15
SEG7~SEG18 logical or LCD output
(1 option: 4 bits (SEG7~SEG10/SEG11~SEG14/SEG15~SEG18))
16
System oscillators: external RC/ external crystal
17
Enable or disable RTCOSC(32.768kHz crystal) or WDTOSC at HALT mode
18
LCD bias current: Low/Middle/High driving current
19
LCD driver clock selection.
There are seven types of frequency signals for the LCD driver circuits: fS/22~fS/28, ²fS² stands for the
clock source selection by options.
Note:
²*1² T1 is stopped at HALT; RTCOSC(32.768kHz crystal) and WDT OSC are stopped or non-stopped at HALT
decided by option(17).
Rev. 2.30
24
March 22, 2006
HT46R63/HT46C63
Application Circuits
V
D D
0 .0 1 m F *
L C D
P A N E L
C O M 0 ~ C O M 3
S E G 0 ~ S E G 1 8
V D D
1 0 0 k W
0 .1 m F
V
R E S
1 0 k W
D D
V L C D
0 .1 m F *
A V D D
V S S
V
D D
P A 0 ~ P A 7
P B 0 /A N 0
P B 7 /A N 7
V
~
O S C
C ir c u it
O S C 1
P C 0 ~ P C 7
O S C 2
D D
R
~
P D 0 /P W M 0
P D 3 /P W M 3
R C S y s te m O s c illa to r
2 4 k W < R O S C < 1 M W
O S C
S e e r ig h t s id e
3 2 7 6 8 H z
O S C 3
O S C 4
P D 4 /IN
P D 5 /IN
P D 6 /T
P
C M P
C M P
C M P
C H G
O S C 1
4 7 0 p F
T 0
T 1
M R
D 7
fS
C 1
N
O
R 1
O
H T 4 6 R 6 3 /H T 4 6 C 6 3
/4
O S C 2
O S C 1
C 2
P
Y S
C ry s ta l S y s te m
F o r th e v a lu e s ,
s e e ta b le b e lo w
O s c illa to r
O S C 2
O S C C ir c u it
The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only)
C1, C2
R1
4MHz Crystal
Crystal or Resonator
0pF
10kW
4MHz Resonator
10pF
12kW
3.58MHz Crystal
0pF
10kW
3.58MHz Resonator
25pF
10kW
2MHz Crystal & Resonator
25pF
10kW
1MHz Crystal
35pF
27kW
480kHz Resonator
300pF
9.1kW
455kHz Resonator
300pF
10kW
429kHz Resonator
300pF
10kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the
MCU operating voltage.
Note:
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is
stable and remains within a valid operating voltage range before bringing RES to high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
Rev. 2.30
25
March 22, 2006
HT46R63/HT46C63
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 2.30
26
March 22, 2006
HT46R63/HT46C63
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 2.30
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
27
March 22, 2006
HT46R63/HT46C63
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 2.30
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
28
March 22, 2006
HT46R63/HT46C63
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 2.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
29
March 22, 2006
HT46R63/HT46C63
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 2.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
30
March 22, 2006
HT46R63/HT46C63
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 2.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
31
March 22, 2006
HT46R63/HT46C63
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 2.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
32
March 22, 2006
HT46R63/HT46C63
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 2.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
33
March 22, 2006
HT46R63/HT46C63
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 2.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
34
March 22, 2006
HT46R63/HT46C63
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 2.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
35
March 22, 2006
HT46R63/HT46C63
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 2.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
36
March 22, 2006
HT46R63/HT46C63
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 2.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
37
March 22, 2006
HT46R63/HT46C63
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 2.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
38
March 22, 2006
HT46R63/HT46C63
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 2.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
39
March 22, 2006
HT46R63/HT46C63
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 2.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
40
March 22, 2006
HT46R63/HT46C63
Package Information
56-pin SSOP (300mil) Outline Dimensions
2 9
5 6
B
A
2 8
1
C
C '
G
H
D
Symbol
Rev. 2.30
a
F
E
Dimensions in mil
Min.
Nom.
Max.
A
395
¾
420
B
291
¾
299
C
8
¾
12
C¢
720
¾
730
D
89
¾
99
E
¾
25
¾
F
4
¾
10
G
25
¾
35
H
4
¾
12
a
0°
¾
8°
41
March 22, 2006
HT46R63/HT46C63
100-pin QFP (14´20) Outline Dimensions
C
H
D
8 0
G
5 1
I
5 0
8 1
F
A
B
E
3 1
1 0 0
K
a
J
1
Symbol
Rev. 2.30
3 0
Dimensions in mm
Min.
Nom.
Max.
A
18.50
¾
19.20
B
13.90
¾
14.10
C
24.50
¾
25.20
D
19.90
¾
20.10
E
¾
0.65
¾
F
¾
0.30
¾
G
2.50
¾
3.10
H
¾
¾
3.40
I
¾
0.10
¾
J
1
¾
1.40
K
0.10
¾
0.20
a
0°
¾
7°
42
March 22, 2006
HT46R63/HT46C63
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor (China) Inc. (Dongguan Sales Office)
Building No. 10, Xinzhu Court, (No. 1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808
Tel: 86-769-2626-1300
Fax: 86-769-2626-1311
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2006 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 2.30
43
March 22, 2006