HOLTEK HT46R47-H

HT46R47-H
Cost-Effective A/D Type 8-Bit OTP MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
- HA0009E HT48 & HT46 MCU I/O Port Application - Rolling LED Light Display
- HA0049E Read and Write Control of the HT1380
- HA0051E Li Battery Charger Demo Board - Using the HT46R47
- HA0052E Microcontroller Application - Battery Charger
Features
· Operating voltage:
· Up to 0.5ms instruction cycle with 8MHz system clock
fSYS=4MHz: VLVR~5.5V with LVR enabled
fSYS=8MHz: 3.3V~5.5V with LVR disabled
at VDD=5V
· 6-level subroutine nesting
· 13 bidirectional I/O lines (max.)
· 4 channels 9-bit resolution A/D converter
· 1 interrupt input shared with an I/O line
· 1 channel 8-bit PWM output shared with an I/O line
· 8-bit programmable timer/event counter with overflow
· Bit manipulation instruction
interrupt and 7-stage prescaler
· 14-bit table read instruction
· On-chip crystal and RC oscillator
· 63 powerful instructions
· Watchdog Timer
· All instructions in one or two machine cycles
· 2048´14 program memory
· Low voltage reset function
· 64´8 data memory RAM
· 18-pin DIP/SOP package
· Supports PFD for sound generation
· HALT function and wake-up feature reduce power
consumption
General Description
The HT46R47-H is an 8-bit high performance, RISC architecture microcontroller devices specifically designed
for A/D applications that interface directly to analog signals, such as those from sensors.
tions, enhance the versatility of these devices to suit a
wide range of A/D application possibilities such as sensor signal processing, motor driving, industrial control,
consumer products, subsystem controllers, etc.
The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions,
oscillator options, multi-channel A/D Converter, Pulse
Width Modulation function, HALT and wake-up func-
The higher operating voltage range and higher operating temperature range of -40°C to +125°C for the
HT46R47-H make this series suitable for automotive applications as well.
Rev. 1.30
1
March 1, 2006
HT46R47-H
Block Diagram
P A 5 /IN T
In te rru p t
C ir c u it
M
T M R C
S T A C K
P ro g ra m
R O M
P ro g ra m
C o u n te r
IN T C
T M R
P A 3 /P F D
In s tr u c tio n
R e g is te r
M
M P
U
X
P o rt D
P D
Y S
P A 4 /T M R
X
P A 4
fS
U
Y S
/4
W D T O S C
X
P D 0 /P W M
M U X
In s tr u c tio n
D e c o d e r
4 -C h a n n e l
A /D C o n v e rte r
S T A T U S
A L U
P B C
S h ifte r
T im in g
G e n e ra to r
S
S
P A 3 , P A 5
C 1
A C C
P o rt B
P B
P A C
O S
R E
V D
V S
fS
P W M
P D C
O S C 2
P r e s c a le r
M
W D T
D A T A
M e m o ry
U
P A
L V R
D
P o rt A
P B 0 /A N 0 ~ P B 3 /A N 3
P A
P A
P A
P A
P A
0 ~ P
3 /P
4 /T
5 /IN
6 ~ P
A 2
F D
M R
T
A 7
Pin Assignment
P A 3 /P F D
1
1 8
P A 4 /T M R
P A 2
2
1 7
P A 5 /IN T
P A 1
3
1 6
P A 6
P A 0
P B 3 /A N 3
4
1 5
5
1 4
P A 7
O S C 2
P B 2 /A N 2
6
1 3
O S C 1
P B 1 /A N 1
7
1 2
V D D
P B 0 /A N 0
8
1 1
R E S
9
1 0
P D 0 /P W M
V S S
H T 4 6 R 4 7 -H
1 8 D IP -A /S O P -A
Rev. 1.30
2
March 1, 2006
HT46R47-H
Pin Description
Pin Name
I/O
Options
Description
I/O
Pull-high
Wake-up
PA3 or PFD
Bidirectional 8-bit input/output port. Each bit can be configured as wake-up
input by options. Software instructions determine the CMOS output or Schmitt
trigger input with or without pull-high resistor (determined by pull-high options: bit
option). The PFD, TMR and INT are pin-shared with PA3, PA4 and PA5, respectively.
I/O
Pull-high
Bidirectional 4-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (determined by pull-high options: bit option) or A/D input.
Once a PB line is selected as an A/D input (by using software control), the I/O
function and pull-high resistor are disabled automatically.
I/O
Pull-high
PD0 or PWM
Bidirectional I/O line. Software instructions determine the CMOS output,
Schmitt trigger input with or without a pull-high resistor (determined by
pull-high options: bit option). The PWM output function is pin-shared with
PD0 (dependent on PWM options).
RES
I
¾
Schmitt trigger reset input. Active low.
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground.
OSC1
OSC2
I
O
Crystal
or RC
PA0~PA2
PA3/PFD
PA4/TMR
PA5/INT
PA6, PA7
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PD0/PWM
OSC1, OSC2 are connected to an RC network or a Crystal (determined by
options) for the internal system clock. In the case of RC operation, OSC2 is
the output terminal for 1/4 system clock.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature.........................-40°C to 125°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.30
3
March 1, 2006
HT46R47-H
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
fSYS=4MHz, LVR enabled
VLVR
¾
5.5
V
fSYS=8MHz, LVR disabled
3.3
¾
5.5
V
Conditions
VDD
VDD
Operating Voltage
¾
IDD1
Operating Current (Crystal OSC)
5V
No load, fSYS=4MHz
ADC disabled
¾
2
4
mA
IDD2
Operating Current (RC OSC)
5V
No load, fSYS=4MHz
ADC disabled
¾
2.5
4
mA
IDD3
Operating Current
(Crystal OSC, RC OSC)
5V
No load, fSYS=8MHz
ADC disabled
¾
4
8
mA
ISTB1
Standby Current (WDT Enabled)
5V
No load, system HALT
¾
¾
10
mA
ISTB2
Standby Current (WDT Disabled)
5V
No load, system HALT
¾
¾
2
mA
VIL1
Input Low Voltage for I/O Ports,
TMR and INT
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR and INT
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset
¾
¾
3.4
3.8
4.2
V
IOL
I/O Port Sink Current
5V
VOL=0.1VDD
10
20
¾
mA
IOH
I/O Port Source Current
5V
VOH=0.9VDD
-5
-10
¾
mA
RPH
Pull-high Resistance
5V
¾
10
30
50
kW
VAD
A/D Input Voltage
¾
¾
0
¾
VDD
V
EAD
A/D Conversion Error
¾
¾
¾
±0.5
±1
LSB
IADC
Additional Power Consumption
if A/D Converter is Used
5V
¾
¾
1.5
3
mA
Rev. 1.30
4
March 1, 2006
HT46R47-H
Ta=125°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
fSYS=4MHz, LVR enabled
VLVR
¾
5.5
V
fSYS=8MHz, LVR disabled
3.3
¾
5.5
V
Conditions
VDD
VDD
Operating Voltage
¾
IDD1
Operating Current
(Crystal OSC, RC OSC)
5V
No load, fSYS=4MHz
ADC disabled
¾
2.5
4
mA
IDD2
Operating Current
(Crystal OSC, RC OSC)
5V
No load, fSYS=8MHz
ADC disabled
¾
4
8
mA
ISTB1
Standby Current (WDT Enabled)
5V
No load, system HALT
¾
¾
40
mA
ISTB2
Standby Current (WDT Disabled)
5V
No load, system HALT
¾
¾
30
mA
VIL1
Input Low Voltage for I/O Ports,
TMR and INT
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR and INT
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset
¾
¾
IOL
I/O Port Sink Current
2.4
2.7
2.9
V
5V
VOL=0.1VDD
7.5
15
¾
mA
VOH=0.9VDD
-5
-10
¾
mA
15
40
60
kW
V
IOH
I/O Port Source Current
5V
RPH
Pull-high Resistance of I/O Ports
5V
¾
VAD
A/D Input Voltage
¾
¾
0
¾
VDD
EAD
A/D Conversion Error
5V
¾
¾
±1
±2
LSB
IADC
Additional Power Consumption
if A/D Converter is Used
5V
¾
¾
1.5
3
mA
Rev. 1.30
5
March 1, 2006
HT46R47-H
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VLVR~5.5V, LVR enabled
400
¾
4000
kHz
3.3V~5.5V, LVR disabled
400
¾
8000
kHz
VLVR~5.5V, LVR enabled
0
¾
4000
kHz
3.3V~5.5V, LVR disabled
0
¾
8000
kHz
¾
32
65
130
ms
15
16
Conditions
VDD
fSYS
fTIMER
tWDTOSC
System Clock
Timer I/P Frequency (TMR)
Watchdog Oscillator Period
¾
¾
5V
tWDT1
Watchdog Time-out Period (RC)
¾
¾
2
¾
2
tWDT2
Watchdog Time-out Period
(System Clock)
¾
¾
217
¾
218
tSYS
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
¾
1024
¾
*tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tAD
A/D Clock Period
¾
¾
1
¾
¾
ms
tADC
A/D Conversion Time
¾
¾
¾
76
¾
tAD
tADCS
A/D Sampling Time
¾
¾
¾
32
¾
tAD
Wake-up from HALT
tWDTOSC
Note: *tSYS=1/fSYS
Ta=125°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VLVR~5.5V, LVR enabled
400
¾
4000
kHz
3.3V~5.5V, LVR disabled
400
¾
8000
kHz
VLVR~5.5V, LVR enabled
0
¾
4000
kHz
3.3V~5.5V, LVR disabled
0
¾
8000
kHz
¾
60
110
200
ms
15
Conditions
VDD
fSYS
fTIMER
tWDTOSC
System Clock
Timer I/P Frequency (TMR)
Watchdog Oscillator Period
¾
¾
5V
16
tWDT1
Watchdog Time-out Period (RC)
¾
¾
2
¾
2
tWDT2
Watchdog Time-out Period
(System Clock)
¾
¾
217
¾
218
tSYS
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
¾
1024
¾
*tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tAD
A/D Clock Period
¾
¾
1
¾
¾
ms
tADC
A/D Conversion Time
¾
¾
¾
76
¾
tAD
tADCS
A/D Sampling Time
¾
¾
¾
32
¾
tAD
Wake-up from HALT
tWDTOSC
Note: *tSYS=1/fSYS
Rev. 1.30
6
March 1, 2006
HT46R47-H
Functional Description
Execution Flow
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
Program Counter - PC
The program counter (PC) controls the sequence in
which the instructions stored in program ROM are executed and its contents specify full range of program
memory.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
S y s te m
O S C 2 (R C
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Program Counter
Mode
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter Overflow
0
0
0
0
0
0
0
1
0
0
0
A/D Converter Interrupt
0
0
0
0
0
0
0
1
1
0
0
Skip
Program Counter+2
Loading PCL
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
*10~*0: Program counter bits
#10~#0: Instruction code bits
Rev. 1.30
S10~S0: Stack register bits
@7~@0: PCL bits
7
March 1, 2006
HT46R47-H
Program Memory - ROM
0 0 0 H
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
2K´14 bits, addressed by the program counter and table
pointer.
0 0 4 H
D e v ic e In itia liz a tio n P r o g r a m
E x te r n a l In te r r u p t S u b r o u tin e
0 0 8 H
T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e
0 0 C H
A /D
C o n v e r te r In te r r u p t S u b r o u tin e
P ro g ra m
M e m o ry
Certain locations in the program memory are reserved
for special usage:
n 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
· Location 000H
This area is reserved for program initialization. After
chip reset, the program always begins execution at location 000H.
7 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
7 F F H
· Location 004H
1 4 b its
N o te : n ra n g e s fro m
This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
0 to 7
Program Memory
Service Routine) both employ the table read
instruction, the contents of the TBLH in the main
routine are likely to be changed by the table read
instruction used in the ISR. Errors can occur. In other
words, using the table read instruction in the main
routine and the ISR simultaneously should be
avoided. However, if the table read instruction has to
be applied in both the main routine and the ISR, the
interrupt is supposed to be disabled prior to the table
read instruction. It will not be enabled until the TBLH
has been backed up. All table related instructions
require two cycles to complete the operation. These
areas may function as normal program memory
depending upon the requirements.
· Location 008H
This area is reserved for the timer/event counter interrupt service program. If a timer interrupt results from a
timer/event counter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
· Location 00CH
This area is reserved for the A/D converter interrupt
service program. If an A/D converter interrupt results
from an end of A/D conversion, and if the interrupt is
enabled and the stack is not full, the program begins
execution at location 00CH.
· Table location
Stack Register - STACK
Any location in the ROM space can be used as
look-up tables. The instructions ²TABRDC [m]² (the
current page, 1 page=256 words) and ²TABRDL [m]²
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
other bits of the table word are transferred to the lower
portion of TBLH, and the remaining 2 bits are read as
²0². The Table Higher-order byte register (TBLH) is
read only. The table pointer (TBLP) is a read/write
register (07H), which indicates the table location.
Before accessing the table, the location must be
placed in TBLP. The TBLH is read only and cannot be
restored. If the main routine and the ISR (Interrupt
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 6 levels and are neither part of
the data nor part of the program space, and is neither
readable nor writeable. The activated level is indexed by
the stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed
onto the stack. At the end of a subroutine or an interrupt
routine, signaled by a return instruction (RET or RETI),
the program counter is restored to its previous value
from the stack. After a chip reset, the SP will point to the
top of the stack.
Table Location
Instruction
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
*10~*0: Table location bits
@7~@0: Table pointer bits
Rev. 1.30
P10~P8: Current program counter bits
8
March 1, 2006
HT46R47-H
The special function registers include the indirect addressing register (00H), timer/event counter
(TMR;0DH), timer/event counter control register
(TMRC;0EH), program counter lower-order byte register (PCL;06H), memory pointer register (MP;01H), accumulator (ACC;05H), table pointer (TBLP;07H), table
higher-order byte register (TBLH;08H), status register
(STATUS;0AH), interrupt control register (INTC;0BH),
PWM data register (PWM;1AH), the A/D result
lower-order byte register (ADRL;20H), the A/D result
higher-order byte register (ADRH;21H), the A/D control
register (ADCR;22H), the A/D clock setting register
(ACSR;23H), I/O registers (PA;12H, PB;14H, PD;18H)
and I/O control registers (PAC;13H, PBC;15H,
PDC;19H). The remaining space before the 40H is reserved for future expanded usage and reading these locations will get ²00H². The general purpose data
memory, addressed from 40H to 7FH, is used for data
and control information under instruction commands.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 6 return addresses are stored).
Data Memory - RAM
The data memory is designed with 85´8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(64´8). Most are read/write, but some are read only.
0 0 H
In d ir e c t A d d r e s s in g R e g is te r
0 1 H
M P
0 2 H
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer register (MP;01H).
0 3 H
0 4 H
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
0 A H
S T A T U S
0 B H
IN T C
Indirect Addressing Register
Location 00H is an indirect addressing register that is
not physically implemented. Any read/write operation of
[00H] accesses data memory pointed to by MP (01H).
Reading location 00H itself indirectly will return the result 00H. Writing indirectly results in no operation.
0 C H
0 D H
T M R
0 E H
T M R C
0 F H
1 0 H
1 1 H
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
S p e c ia l P u r p o s e
D a ta M e m o ry
The memory pointer register MP (01H) is a 7-bit register.
The bit 7 of MP is undefined and reading will return the
result ²1². Any writing operation to MP will only transfer the
lower 7-bit data to MP.
1 6 H
Accumulator
1 7 H
1 8 H
P D
1 9 H
P D C
1 A H
1 B H
P W M
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
1 C H
1 D H
1 E H
Arithmetic and Logic Unit - ALU
1 F H
2 0 H
A D R L
2 1 H
A D R H
2 2 H
2 3 H
2 4 H
A D C R
3 F H
4 0 H
This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
A C S R
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
G e n e ra l P u rp o s e
D a ta M e m o ry
(6 4 B y te s )
7 F H
· Increment and Decrement (INC, DEC)
: U n u s e d
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
R e a d a s "0 0 "
The ALU not only saves the results of a data operation but
also changes the status register.
RAM Mapping
Rev. 1.30
9
March 1, 2006
HT46R47-H
Status Register - STATUS
terrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of INTC may be set to
allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate
service is desired, the stack must be prevented from becoming full.
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addition operations related to the status register may give
different results from those intended. The TO flag
can be affected only by system power-up, a WDT
time-out or executing the ²CLR WDT² or ²HALT² instruction. The PDF flag can be affected only by executing the ²HALT² or ²CLR WDT² instruction or a
system power-up.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the contents should be saved in advance.
External interrupts are triggered by a high to low transition of INT and the related interrupt request flag (EIF; bit
4 of INTC) will be set. When the interrupt is enabled, the
stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable
other interrupts.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag
(TF;bit 5 of INTC), caused by a timer overflow. When the
interrupt is enabled, the stack is not full and the TF bit is
set, a subroutine call to location 08H will occur. The related interrupt request flag (TF) will be reset and the EMI
bit cleared to disable further interrupts.
Interrupt
The device provides an external interrupt, internal
timer/event counter interrupt and A/D converter interrupts. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable or disable
and the interrupt request flags.
The A/D converter interrupt is initialized by setting the
A/D converter request flag (ADF; bit 6 of INTC), caused
by an end of A/D conversion. When the interrupt is enabled, the stack is not full and the ADF is set, a subroutine call to location 0CH will occur. The related interrupt
request flag (ADF) will be reset and the EMI bit cleared
to disable further interrupts.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may happen during this interval but
only the interrupt request flag is recorded. If a certain inBit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction, otherwise AC is cleared.
2
Z
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa, otherwise OV is cleared.
4
PDF
PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set
by executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO
is set by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.
Status (0AH) Register
Rev. 1.30
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March 1, 2006
HT46R47-H
Oscillator Configuration
During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (of course, if the stack is
not full). To return from the interrupt subroutine, RET or
RETI may be invoked. RETI will set the EMI bit to enable
an interrupt service, but RET will not.
There are two oscillator circuits in the microcontroller.
V
O S C 1
Priority
C r y s ta l O s c illa to r
1
04H
Timer/Event Counter Overflow
2
08H
A/D Converter Interrupt
3
0CH
fS Y S /4
N M O S O p e n D r a in
O S C 2
R C
O s c illa to r
System Oscillator
Both are designed for system clocks, namely the RC oscillator and the Crystal oscillator, which are determined
by the options. No matter what oscillator type is selected, the signal provides the system clock. The HALT
mode stops the system oscillator and ignores an external signal to conserve power.
Vector
External Interrupt
O S C 1
O S C 2
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
D D
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance must
range from 30kW to 750kW. The system clock, divided
by 4, is available on OSC2, which can be used to synchronize external logic. The RC oscillator provides the
most cost effective solution. However, the frequency of
oscillation may vary with VDD, temperatures and the
chip itself due to process variations. It is, therefore, not
suitable for timing sensitive operations where an accurate oscillator frequency is desired.
The timer/event counter interrupt request flag (TF), external interrupt request flag (EIF), A/D converter request
flag (ADF), enable timer/event counter bit (ETI), enable
external interrupt bit (EEI), enable A/D converter interrupt bit (EADI) and enable master interrupt bit (EMI)
constitute an interrupt control register (INTC) which is
located at 0BH in the data memory. EMI, EEI, ETI, EADI
are used to control the enabling/disabling of interrupts.
These bits prevent the requested interrupt from being
serviced. Once the interrupt request flags (TF, EIF, ADF)
are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction.
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to
get a frequency reference, but two external capacitors in
OSC1 and OSC2 are required (If the oscillating frequency is less than 1MHz).
It is recommended that a program does not use the CALL
subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack
is left and enabling the interrupt is not well controlled, the
original control sequence will be damaged once the
²CALL² operates in the interrupt subroutine.
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works with a
period of approximately 65ms at 5V. The WDT oscillator
can be disabled by options to conserve power.
Bit No.
Label
0
EMI
Controls the master (global) interrupt (1=enabled; 0=disabled)
Function
1
EEI
Controls the external interrupt (1=enabled; 0=disabled)
2
ETI
Controls the Timer/Event Counter interrupt (1=enabled; 0=disabled)
3
EADI
4
EIF
External interrupt request flag (1=active; 0=inactive)
5
TF
Internal Timer/Event Counter request flag (1=active; 0=inactive)
6
ADF
7
¾
Controls the A/D converter interrupt (1=enabled; 0=disabled)
A/D converter request flag (1=active; 0=inactive)
For test mode used only.
Must be written as ²0²; otherwise may result in unpredictable operation.
INTC (0BH) Register
Rev. 1.30
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HT46R47-H
· The contents of the on chip RAM and registers remain
Watchdog Timer - WDT
unchanged.
The clock source of WDT is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), decided by options. This timer is
designed to prevent a software malfunction or sequence
from jumping to an unknown location with unpredictable
results. The Watchdog Timer can be disabled by an option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation.
· WDT will be cleared and recounted again (if the WDT
clock is from the WDT oscillator).
· All of the I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². After the TO and PDF flags are
examined, the reason for chip reset can be determined.
The PDF flag is cleared by system power-up or executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the program counter and SP; the others keep their original status.
Once the internal oscillator (RC oscillator with a period
of 65ms at 5V normally) is selected, it is divided by
32768~65536 to get the time-out period of approximately 2.1s~4.3s. This time-out period may vary with
temperatures, VDD and process variations. If the WDT
oscillator is disabled, the WDT clock may still come from
the instruction clock and operate in the same manner
except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the
logic can only be restarted by external logic.
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by the options. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it is awakening from an interrupt, two
sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the
program will resume execution at the next instruction. If
the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request
flag is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.
Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other
words, a dummy period will be inserted after wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
²chip reset² and set the status bit ²TO². But in the HALT
mode, the overflow will initialize a ²warm reset², and
only the program counter and SP are reset to zero. To
clear the contents of WDT, three methods are adopted;
external reset (a low level to RES), software instruction
and a HALT instruction. The software instruction include
²CLR WDT² and the other set - ²CLR WDT1² and ²CLR
WDT2². Of these two types of instruction, only one can
be active depending on the options - ²CLR WDT times
selection option². If the ²CLR WDT² is selected (i.e. CLR
WDT times equal one), any execution of the ²CLR
WDT² instruction will clear the WDT. In the case that
²CLR WDT1² and ²CLR WDT2² are chosen (i.e. CLR
WDT times equal two), these two instructions must be
executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following...
Reset
· The system oscillator will be turned off but the WDT
· RES reset during normal operation
There are three ways in which a reset can occur:
oscillator keeps running (if the WDT oscillator is selected).
S y s te m
· RES reset during HALT
· WDT time-out reset during normal operation
C lo c k /4
O p tio n
S e le c t
fS
8 - b it C o u n te r
7 - b it C o u n te r
W D T
O S C
T
T
W D T T im e - o u t
1 5
1 6
fS /2 ~ fS /2
C L R
W D T
Watchdog Timer
Rev. 1.30
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HT46R47-H
V D D
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that resets only the program counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions.
Most registers are reset to the ²initial condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
TO PDF
R E S
tS
C h ip
R e s e t
Reset Timing Chart
V
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
1 0 0 k W
R E S
1 0 k W
0 .1 m F *
Reset Circuit
Note: ²u² means ²unchanged²
Note:
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
Disable
WDT
Clear. After master reset,
WDT begins counting
R e s e t
R E S
O S C 1
The functional unit chip reset status are shown below.
Interrupt
W a rm
W D T
An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES
reset).
000H
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to
avoid noise interference.
H A L T
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will enable the SST delay.
Program Counter
D D
0 .0 1 m F *
RESET Conditions
0
S T
S S T T im e - o u t
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
C o ld
R e s e t
R e s e t
Reset Configuration
Timer/Event Counter Off
Input/Output Ports
Input mode
Stack Pointer
Points to the top of the stack
Rev. 1.30
13
March 1, 2006
HT46R47-H
The registers¢ states are summarized in the following table.
Reset
(Power On)
WDT Time-out
(Normal Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Times-out
(HALT)*
MP
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Register
Program Counter
000H
000H
000H
000H
000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRC
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PBC
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PD
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
PDC
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
PWM
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADRL
x--- ----
x--- ----
x--- ----
x--- ----
u--- ----
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
1--- --00
1--- --00
1--- --00
1--- --00
u--- --uu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR) pin. The timer mode functions as a normal timer
with the clock source coming from the fINT clock. The
pulse width measurement mode can be used to count the
high or low level duration of the external signal (TMR). The
counting is based on the fINT.
Timer/Event Counter
A timer/event counter (TMR) is implemented in the
microcontroller. The timer/event counter contains an
8-bit programmable count-up counter and the clock may
come from an external source or the system clock.
Using external clock input allows the user to count external events, measure time internals or pulse widths, or
generate an accurate time base. While using the internal clock allows the user to generate an accurate time
base.
In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current
contents in the timer/event counter to FFH. Once overflow occurs, the counter is reloaded from the timer/event
counter preload register and generates the interrupt request flag (TF; bit 5 of INTC) at the same time.
The timer/event counter can generate PFD signal by using external or internal clock and PFD frequency is determine by the equation fINT/[2´(256-N)].
There are 2 registers related to the timer/event counter;
TMR ([0DH]), TMRC ([0EH]). Two physical registers are
mapped to TMR location; writing TMR makes the starting value be placed in the timer/event counter preload
register and reading TMR retrieves the contents of the
timer/event counter. The TMRC is a timer/event counter
control register, which defines some options.
Rev. 1.30
In the pulse width measurement mode with the TON
and TE bits equal to one, once the TMR has received a
transient from low to high (or high to low if the TE bits is
²0²) it will start counting until the TMR returns to the original level and resets the TON. The measured result will
remain in the timer/event counter even if the activated
14
March 1, 2006
HT46R47-H
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register will also
reload that data to the timer/event counter. But if the
timer/event counter is turned on, data written to it will
only be kept in the timer/event counter preload register.
The timer/event counter will still operate until overflow
occurs. When the timer/event counter (reading TMR) is
read, the clock will be blocked to avoid errors. As clock
blocking may results in a counting error, this must be
taken into consideration by the programmer.
transient occurs again. In other words, only one cycle
measurement can be done. Until setting the TON, the
cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the timer/event counter starts counting not
according to the logic level but according to the transient
edges. In the case of counter overflows, the counter is
reloaded from the timer/event counter preload register
and issues the interrupt request just like the other two
modes. To enable the counting operation, the timer ON
bit (TON; bit 4 of TMRC) should be set to 1. In the pulse
width measurement mode, the TON will be cleared automatically after the measurement cycle is completed.
But in the other two modes the TON can only be reset by
instructions. The overflow of the timer/event counter is
one of the wake-up sources. No matter what the operation mode is, writing a 0 to ETI can disable the interrupt
service.
Bit No.
The bit0~bit2 of the TMRC can be used to define the
pre-scaling stages of the internal clock sources of
timer/event counter. The definitions are as shown. The
overflow signal of timer/event counter can be used to
generate the PFD signal.
Label
PSC0
PSC1
PSC2
0
1
2
Function
Defines the prescaler stages, PSC2, PSC1, PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
Defines the TMR active edge of the timer/event counter:
In Event Counter Mode (TM1,TM0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (TM1,TM0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
3
TE
4
TON
5
¾
6
7
TM0
TM1
Enable or disable the timer counting (0=disable; 1=enable)
Unused bits, read as ²0²
Defines the operating mode (TM1, TM0)=
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMRC (0EH) Register
P W M
(6 + 2 ) C o m p a re
fS
Y S
T o P D 0 C ir c u it
8 - s ta g e P r e s c a le r
f IN
8 -1 M U X
P S C 2 ~ P S C 0
D a ta B u s
T
T M 1
T M 0
T M R
8 - B it T im e r /E v e n t
C o u n te r P r e lo a d
R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
8 - B it T im e r /E v e n t
C o u n te r
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
1 /2
P F D
Timer/Event Counter
Rev. 1.30
15
March 1, 2006
HT46R47-H
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Input/Output Ports
There are 13 bidirectional input/output lines in the
microcontroller, labeled as PA, PB and PD, which are
mapped to the data memory of [12H], [14H] and [18H]
respectively. All of these I/O ports can be used for input
and output operations. For input operation, these ports
are non-latching, that is, the inputs must be ready at the
T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H
or 18H). For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Each line of port A has the capability of waking-up the
device. The highest 4-bit of port B and 7 bits of port D
are not physically implemented; on reading them a ²0² is
returned whereas writing then results in a no-operation.
See Application note.
Each I/O line has a pull-high option. Once the pull-high
option is selected, the I/O line has a pull-high resistor,
otherwise, there¢s none. Take note that a non-pull-high
I/O line operating in input mode will cause a floating
state.
Each I/O line has its own control register (PAC, PBC,
PDC) to control the input/output configuration. With this
control register, CMOS output or Schmitt trigger input
with or without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software
control. To function as an input, the corresponding latch
of the control register must write ²1². The input source
also depends on the control register. If the control register bit is ²1², the input will read the pad state. If the control register bit is ²0², the contents of the latches will
move to the internal bus. The latter is possible in the
²read-modify-write² instruction.
The PA3 is pin-shared with the PFD signal. If the PFD
option is selected, the output signal in output mode of
PA3 will be the PFD signal generated by the timer/event
counter overflow signal. The input mode always remaining its original functions. Once the PFD option is selected, the PFD output signal is controlled by PA3 data
register only. Writing ²1² to PA3 data register will enable
the PFD output function and writing ²0² will force the
PA3 to remain at ²0². The I/O functions of PA3 are
shown below.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H and 19H.
I/O
Mode
After a chip reset, these input/output lines remain at high
levels or floating state (dependent on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H or
18H) instructions.
Logical
Input
PA3
Note:
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
I/P
O/P
(Normal) (Normal)
C o n tr o l B it
W r ite C o n tr o l R e g is te r
Q
D
C K
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
Q B
S
P A 0
P A 3
P A 4
P A 5
P A 6
P B 0
P D 0
W a k e -u p
( P A o n ly )
~ P
/P
/T
/IN
, P
/A
/P
A 2
F D
M R
T
A 7
N 0 ~ P B 3 /A N 3
W M
Q B
S
M
M
S y s te m
D D
P U
(P D 0 o r P W M ) P A 3
P F D
R e a d D a ta R e g is te r
Logical
PFD
Input (Timer on)
The PA5 and PA4 are pin-shared with INT and TMR pins
respectively.
D a ta B it
Q
D
C K
O/P
(PFD)
The PFD frequency is the timer/event counter
overflow frequency divided by 2.
V
D a ta B u s
Logical
Output
I/P
(PFD)
U
U
X
P F D E N
(P A 3 )
X
W a k e - u p o p tio n
IN T fo r P A 5 O n ly
T M R
fo r P A 4 O n ly
Input/Output Ports
Rev. 1.30
16
March 1, 2006
HT46R47-H
In a PWM cycle, the duty cycle of each modulation cycle
is shown in the table.
The PB can also be used as A/D converter inputs. The
A/D function will be described later. There is a PWM
function shared with PD0. If the PWM function is enabled, the PWM signal will appear on PD0 (if PD0 is operating in output mode). Writing ²1² to PD0 data register
will enable the PWM output function and writing ²0² will
force the PD0 to remain at ²0². The I/O functions of PD0
are as shown.
I/O
Mode
PD0
I/P
O/P
(Normal) (Normal)
Logical
Input
Logical
Output
I/P
(PWM)
O/P
(PWM)
Logical
Input
PWM
Parameter
Modulation cycle i
(i=0~3)
i³AC
PWM Modulation
Frequency
PWM Cycle
Frequency
PWM Cycle
Duty
fSYS/64
fSYS/256
[PWM]/256
A/D Converter
The 4 channels and 9-bit resolution A/D converter is implemented in this microcontroller. The reference voltage
is VDD. The A/D converter contains 4 special registers;
ADRL (20H), ADRH (21H), ADCR (22H) and ACSR
(23H). The ADRH and ADRL are A/D result register
higher-order byte and lower-order byte which are
read-only. After the A/D conversion is completed, the
ADRL, ADRH should be read to get the conversion result data. The ADCR is an A/D converter control register, which defines the A/D channel number, analog
channel select, start A/D conversion control bit and the
end of A/D conversion flag. If the users want to start an
A/D conversion, define PB configuration, select the converted analog channel, and give START bit a raising
edge and a falling edge (0®1®0). At the end of A/D
conversion, the EOCB bit is cleared and an A/D converter interrupt occurs (if the A/D converter interrupt is
enabled). The ACSR is A/D clock setting register, which
is used to select the A/D clock source.
PWM
The microcontroller provides 1 channel (6+2) bits PWM
output shared with PD0. The PWM channel has its data
register denoted as PWM (1AH). The frequency source
of the PWM counter comes from fSYS. The PWM register
is an eight bits register. The waveforms of PWM output
are as shown. Once the PD0 is selected as the PWM
output and the output function of PD0 is enabled
(PDC.0=²0²), writing 1 to PD0 data register will enable
the PWM output function and writing ²0² will force the
PD0 to stay at ²0².
A PWM cycle is divided into four modulation cycles
(modulation cycle 0~modulation cycle 3). Each modulation cycle has 64 PWM input clock period. In a (6+2) bit
PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is
denoted by DC which is the value of PWM.7~PWM.2.
The group 2 is denoted by AC which is the value of
PWM.1~PWM.0.
Y S
i<AC
Duty Cycle
DC+1
64
DC
64
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
fS
AC (0~3)
/2
[P W M ] = 1 0 0
P W M
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 6 /6 4
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
2 6 /6 4
P W M
m o d u la tio n p e r io d : 6 4 /fS
M o d u la tio n c y c le 0
Y S
M o d u la tio n c y c le 1
P W M
M o d u la tio n c y c le 2
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 3
M o d u la tio n c y c le 0
Y S
PWM
Rev. 1.30
17
March 1, 2006
HT46R47-H
Bit 7 of the ACSR register is used for test purposes only
and must not be used for other purposes by the application program. Bit1 and bit0 of the ACSR register are
used to select the A/D clock source.
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the ADCR are used to
select an analog input channel. There are a total of four
channels to select. The bit5~bit3 of the ADCR are used
to set PB configurations. PB can be an analog input or
as digital I/O line decided by these 3 bits. Once a PB line
is selected as an analog input, the I/O functions and
pull-high resistor of this I/O line are disabled, and the
A/D converter circuit is power on. The EOCB bit (bit6 of
the ADCR) is end of A/D conversion flag. Check this bit
to know when A/D conversion is completed. The START
bit of the ADCR is used to begin the conversion of A/D
converter. Give START bit a raising edge and falling
edge that means the A/D conversion has started. In order to ensure the A/D conversion is completed, the
START should stay at ²0² until the EOCB is cleared to
²0² (end of A/D conversion).
When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to ²1²
when the START bit is set from ²0² to ²1².
Important Note for A/D initialization:
Special care must be taken to initialize the A/D converter each time the Port B A/D channel selection bits
are modified, otherwise the EOCB flag may be in an undefined condition. An A/D initialization is implemented
by setting the START bit high and then clearing it to zero
within 10 instruction cycles of the Port B channel selection bits being modified. Note that if the Port B channel
selection bits are all cleared to zero then an A/D initialization is not required.
Register
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ADRL
D0
¾
¾
¾
¾
¾
¾
¾
ADRH
D8
D7
D6
D5
D4
D3
D2
D1
Note:
D0~D8 is A/D conversion result data bit LSB~MSB.
ADRL (20H), ADRH (21H) Register
M in im u m
o n e in s tr u c tio n c y c le n e e d e d , M a x im u m
te n in s tr u c tio n c y c le s a llo w e d
S T A R T
E O C B
A /D
tA
P C R 2 ~
P C R 0
A /D
tA
s a m p lin g tim e
D C S 1
0 0 0 B
s a m p lin g tim e
A /D
tA
D C S 1
1 0 0 B
1 0 0 B
s a m p lin g tim e
D C S 1
1 0 1 B
0 0 0 B
1 . P B p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
A C S 2 ~
A C S 0
0 0 0 B
P o w e r-o n
R e s e t
0 1 0 B
0 0 0 B
0 0 1 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
1 : D e fin e P B c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
A /D
N o te :
A /D
tA D
tA
c lo c k m u s t b e fS
= 3 2 tA D
1 = 7 6 tA D
Y S
/2 , fS
tA D C 1
c o n v e r s io n tim e
Y S
/8 o r fS
Y S
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
A /D
tA D C 1
c o n v e r s io n tim e
d o n 't c a r e
E n d o f A /D
c o n v e r s io n
A /D
tA D C 1
c o n v e r s io n tim e
/3 2
D C
C S 1
A/D Conversion Timing
Rev. 1.30
18
March 1, 2006
HT46R47-H
Bit No.
Label
Function
ACS0
ACS1
ACS2
ACS2, ACS1, ACS0: Select A/D channel
0, 0, 0: AN0
0, 0, 1: AN1
0, 1, 0: AN2
0, 1, 1: AN3
1, X, X: undefined, cannot be used
PCR0
PCR1
PCR2
PCR2, PCR1, PCR0: PB3~PB0 configurations
0, 0, 0: PB3 PB2 PB1 PB0 (The ADC circuit is power off to reduce power consumption.)
0, 0, 1: PB3 PB2 PB1 AN0
0, 1, 0: PB3 PB2 AN1 AN0
0, 1, 1: PB3 AN2 AN1 AN0
1, x, x: AN3 AN2 AN1 AN0
6
EOCB
Indicates end of A/D conversion. (0 = end of A/D conversion)
Each time bits 3~5 change state the A/D should be initialized by issuing a START signal,
otherwise the EOCB flag may have an undefined condition. See ²Important note for A/D initialization².
7
START
Start the A/D conversion
0®1®0= Start
0®1= Reset A/D converter and set EOCB to ²1²
0
1
2
3
4
5
ADCR (22H) Register
Bit No.
0
1
Label
ADCS0
ADCS1
2~6
¾
7
TEST
Function
Select the A/D converter clock source.
0, 0: fSYS/2
0, 1: fSYS/8
1, 0: fSYS/32
1, 1: Undefined
Unused bit, read as ²0².
For internal test only.
ACSR (23H) Register
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using EOCB Polling Method to detect end of conversion
clr
EADI
; disable ADC interrupt
mov
a,00000001B
mov
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
mov
a,00100000B
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov
ADCR,a
; and select AN0 to be connected to the A/D converter
:
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
START
set
START
; reset A/D
clr
START
; start A/D
Polling_EOC:
sz
EOCB
; poll the ADCR register EOCB bit to detect end of A/D conversion
jmp
polling_EOC
; continue polling
mov
a,ADRH
; read conversion result high byte value from the ADRH register
mov
adrh_buffer,a
; save result to user defined memory
mov
a,ADRL
; read conversion result low byte value from the ADRL register
mov
adrl_buffer,a
; save result to user defined memory
:
:
jmp
start_conversion
; start next A/D conversion
Rev. 1.30
19
March 1, 2006
HT46R47-H
Example: using interrupt method to detect end of conversion
clr
EADI
; disable ADC interrupt
mov
a,00000001B
mov
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
mov
mov
a,00100000B
ADCR,a
:
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
; and select AN0 to be connected to the A/D converter
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
START
set
START
clr
START
clr
ADF
set
EADI
set
EMI
:
:
:
; ADC interrupt service routine
ADC_ISR:
mov
acc_stack,a
mov
a,STATUS
mov
status_stack,a
:
:
mov
a,ADRH
mov
adrh_buffer,a
mov
a,ADRL
mov
adrl_buffer,a
clr
START
set
START
clr
START
:
:
EXIT_INT_ISR:
mov
a,status_stack
mov
STATUS,a
mov
a,acc_stack
reti
; reset A/D
; start A/D
; clear ADC interrupt request flag
; enable ADC interrupt
; enable global interrupt
; save ACC to user defined memory
; save STATUS to user defined memory
; read conversion result high byte value from the ADRH register
; save result to user defined register
; read conversion result low byte value from the ADRL register
; save result to user defined register
; reset A/D
; start A/D
; restore STATUS from user defined memory
; restore ACC from user defined memory
Low Voltage Reset - LVR
The relationship between VDD and VLVR is shown below.
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~3.3V, such as changing a battery, the LVR will automatically reset the device internally.
V D D
5 .5 V
O P R
5 .5 V
V
The LVR includes the following specifications:
L V R
3 .0 V
· The low voltage (0.9V~VLVR) has to remain in their
2 .2 V
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
0 .9 V
· The LVR uses the ²OR² function with the external RES
Note:
signal to perform chip reset.
Rev. 1.30
V
20
VOPR is the voltage range for proper chip
operation at 4MHz system clock.
March 1, 2006
HT46R47-H
V
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
R e s e t
*1
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since the low voltage has to maintain in its original state and exceed 1ms, therefore 1ms delay enter the
reset mode.
Options
The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure proper
system functioning.
No.
Options
1
WDT clock source: WDTOSC or T1 (fSYS/4)
2
WDT function: enable or disable
3
CLRWDT instruction(s): one or two clear WDT instruction(s)
4
System oscillator: RC or crystal
5
Pull-high resistors (PA, PB, PD): none or pull-high
6
PWM enable or disable
7
PA0~PA7 wake-up: enable or disable
8
PFD enable or disable
9
Low voltage reset selection: enable or disable LVR function.
Rev. 1.30
21
March 1, 2006
HT46R47-H
Application Circuits
V
D D
0 .0 1 m F *
P A 0 ~ P A 2
V D D
V
P A 3 /P F D
1 0 0 k W
P A 5 /IN T
1 0 k W
R
P A 6 ~ P A 7
0 .1 m F *
V S S
P B 0 /A N 0
P B 3 /A N 3
P D 0 /P W M
O S C 1
O S C
O S C 1
fS
C 1
~
O S C
C ir c u it
4 7 0 p F
P A 4 /T M R
R E S
0 .1 m F
D D
/4
O S C 2
O S C 1
C 2
O S C 2
Y S
R 1
R C S y s te m O s c illa to r
3 0 k W < R O S C < 7 5 0 k W
C ry s ta l S y s te m
F o r th e v a lu e s ,
s e e ta b le b e lo w
O s c illa to r
O S C 2
S e e R ig h t S id e
H T 4 6 R 4 7 -H
O S C
C ir c u it
The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only)
Crystal or Resonator
C1, C2
R1
4MHz Crystal
0pF
10kW
4MHz Resonator
10pF
12kW
3.58MHz Crystal
0pF
10kW
3.58MHz Resonator
25pF
10kW
2MHz Crystal & Resonator
25pF
10kW
1MHz Crystal
35pF
27kW
480kHz Resonator
300pF
9.1kW
455kHz Resonator
300pF
10kW
429kHz Resonator
300pF
10kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the
MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.
Note:
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is
stable and remains within a valid operating voltage range before bringing RES to high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
Rev. 1.30
22
March 1, 2006
HT46R47-H
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.30
23
March 1, 2006
HT46R47-H
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.30
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
24
March 1, 2006
HT46R47-H
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
25
March 1, 2006
HT46R47-H
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
26
March 1, 2006
HT46R47-H
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
27
March 1, 2006
HT46R47-H
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
28
March 1, 2006
HT46R47-H
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
29
March 1, 2006
HT46R47-H
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
30
March 1, 2006
HT46R47-H
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
31
March 1, 2006
HT46R47-H
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
32
March 1, 2006
HT46R47-H
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
33
March 1, 2006
HT46R47-H
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
34
March 1, 2006
HT46R47-H
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
35
March 1, 2006
HT46R47-H
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
36
March 1, 2006
HT46R47-H
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.30
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
37
March 1, 2006
HT46R47-H
Package Information
18-pin DIP (300mil) Outline Dimensions
A
B
1 8
1 0
1
9
H
C
D
E
a
G
I
F
Symbol
Rev. 1.30
Dimensions in mil
Min.
Nom.
Max.
A
895
¾
915
B
240
¾
260
C
125
¾
135
D
125
¾
145
E
16
¾
20
F
50
¾
70
G
¾
100
¾
H
295
¾
315
I
335
¾
375
a
0°
¾
15°
38
March 1, 2006
HT46R47-H
18-pin SOP (300mil) Outline Dimensions
1 0
1 8
B
A
9
1
C
C '
G
H
D
E
Symbol
Rev. 1.30
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
447
¾
460
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
39
March 1, 2006
HT46R47-H
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 18W
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1.0
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13.0+0.5
-0.2
D
Key Slit Width
2.0±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
Rev. 1.30
40
March 1, 2006
HT46R47-H
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
SOP 18W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24.0+0.3
-0.1
P
Cavity Pitch
16.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5±0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.9±0.1
B0
Cavity Width
12.0±0.1
K0
Cavity Depth
2.8±0.1
t
Carrier Tape Thickness
0.3±0.05
C
Cover Tape Width
Rev. 1.30
21.3
41
March 1, 2006
HT46R47-H
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031
Tel: 0755-8346-5589
Fax: 0755-8346-5590
ISDN: 0755-8346-5591
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
Fax: 010-6641-0125
Holmate Semiconductor, Inc. (North America Sales Office)
46712 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2006 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.30
42
March 1, 2006