ISL22343 Datasheet

ISL22343
Quad Digitally Controlled Potentiometer (XDCP™)
Data Sheet
August 17, 2015
FN6423.2
Low Noise, Low Power, I2C Bus, 256 Taps
Features
The ISL22343 integrates four digitally controlled
potentiometers (DCP), control logic and non-volatile memory
on a monolithic CMOS integrated circuit.
• Four potentiometers in one package
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. The potentiometer has an associated
volatile Wiper Register (WRi) and a non-volatile Initial Value
Register (IVRi) that can be directly written to and read by the
user. The contents of the WRi control the position of the
corresponding wiper. At power up the device recalls the
contents of the DCP’s IVRi to the correspondent WRi.
The ISL22343 also has 11 general purpose non-volatile
registers that can be used as storage of lookup table for
multiple wiper position or any other valuable information.
The ISL22343 features a dual supply, that is beneficial for
applications requiring a bipolar range for DCP terminals
between V- and VCC.
Each DCP can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• 256 resistor taps
• I2C serial interface
- Three address pins, up to eight devices per bus
• Non-volatile EEPROM storage of wiper position
• 11 General Purpose non-volatile registers
• High reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T 55°C
• Wiper resistance: 70 typical @ 1mA
• Standby current <4µA max
• Shutdown current <4µA max
• Dual power supply
- VCC = 2.25V to 5.5V
- V- = -2.25V to -5.5V
• 10k 50kor 100k total resistance
• Extended industrial temperature range: -40°C to +125°C
• 20 Ld TSSOP or 20 Ld QFN
• Pb-free (RoHS compliant)
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
RESISTANCE
OPTION
(k)
TEMP.
RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL22343TFV20Z
22343 TFVZ
(No longer available, recommended replacement: ISL22343WFR20Z-TK)
100
-40 to +125 20 Ld TSSOP M20.173
ISL22343TFR20Z
22343 TFRZ
(No longer available, recommended replacement: ISL22343WFR20Z-TK
100
-40 to +125 20 Ld QFN
ISL22343UFV20Z
22343 UFVZ
(No longer available, recommended replacement: ISL22343WFR20Z-TK
50
-40 to +125 20 Ld TSSOP M20.173
ISL22343UFR20Z
22343 UFRZ
(No longer available, recommended replacement: ISL22343WFR20Z-TK
50
-40 to +125 20 Ld QFN
ISL22343WFV20Z
22343 WFVZ
10
-40 to +125 20 Ld TSSOP M20.173
ISL22343WFR20Z
22343 WFRZ
10
-40 to +125 20 Ld QFN
L20.5x5
L20.5x5
L20.5x5
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte
tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
2. Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas LLC
Copyright Intersil Americas LLC 2007, 2008, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL22343
Block Diagram
VCC
VRH3
WR3
SCL
SDA
I2C
INTERFACE
A0
A1
A2
POWER-UP,
CONTROL
AND
STATUS
LOGIC
RW3
RL3
RH2
WR2
RW2
RL2
RH1
WR1
NON-VOLATILE
REGISTERS
RW1
RL1
RH0
WR0
RW0
RL0
GND
Pinouts
ISL22343
(20 LEAD QFN)
TOP VIEW
RH3
1
20 RW0
RL3
RH3
RW0
RL0
RH0
ISL22343
(20 LEAD TSSOP)
TOP VIEW
RL3
2
19 RL0
20
19
18
17
16
RW3
3
18 RH0
A2
4
17 V-
SCL
5
16 VCC
8
13 RH1
RL2
9
12 RL1
RH2 10
11 RW1
2
2
14
VCC
SCL
3
13
A1
SDA
4
12
A0
GND
5
11
RH1
6
7
8
9
10
RL1
RW2
A2
RW1
14 A0
V-
RH2
15 A1
7
15
RL2
6
1
RW2
SDA
GND
RW3
FN6423.2
August 17, 2015
ISL22343
Pin Descriptions
TSSOP PIN
QFN PIN
SYMBOL
1
19
RH3
“High” terminal of DCP3
2
20
RL3
“Low” terminal of DCP3
3
1
RW3
“Wiper” terminal of DCP3
4
2
A2
5
3
SCL
Open drain I2C interface clock input
6
4
SDA
Open drain Serial data I/O for the I2C interface
7
5
GND
Device ground pin
8
6
RW2
“Wiper” terminal of DCP2
9
7
RL2
“Low” terminal of DCP2
10
8
RH2
“High” terminal of DCP2
11
9
RW1
“Wiper” terminal of DCP1
12
10
RL1
“Low” terminal of DCP1
13
11
RH1
“High” terminal of DCP1
14
12
A0
Device address input for the I2C interface
15
13
A1
Device address input for the I2C interface
16
14
VCC
Positive power supply pin
17
15
V-
Negative power supply pin
18
16
RH0
“High” terminal of DCP0
19
17
RL0
“Low” terminal of DCP0
20
18
RW0
“Wiper” terminal of DCP0
EPAD*
DESCRIPTION
Device address input for the I2C interface
Exposed Die Pad internally connected to V-
NOTE: *PCB thermal land for QFN EPAD should be connected to V- plane or left floating. For more information refer to
http://www.intersil.com/data/tb/TB389.pdf
3
FN6423.2
August 17, 2015
ISL22343
Absolute Maximum Ratings
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage at any Digital Interface Pin
with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to 0.3V
Voltage at any DCP Pin with
respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to VCC
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A at +125°C
ESD
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400V
Thermal Resistance (Typical, Note 3)
JA (°C/W)
JC (°C/W)
20 Lead TSSOP . . . . . . . . . . . . . . . . . . . . . . . .95
N/A
20 Lead QFN (Note 4) . . . . . . . . . . . . . . . . . . .32
3.0
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range (Full Industrial) . . . . . . . . . . . .-40°C to +125°C
Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 5.5V
V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.25V to -5.5V
Max Wiper Current Iw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Analog Specifications
SYMBOL
RTOTAL
Over recommended operating conditions unless otherwise stated.
PARAMETER
RHi to RLi Resistance
TEST CONDITIONS
VRHi, VRLi
RW
CH/CL/CW
(Note 19)
ILkgDCP
TYP
(Note 5)
MAX
(Note 21)
UNIT
W option
10
k
U option
50
k
T option
100
k
RHi to RLi Resistance tolerance
End-to-End Temperature Coefficient
MIN
(Note 21)
-20
+20
%
W option
±85
ppm/°C
U, T option
±45
ppm/°C
DCP Terminal Voltage
VRH and VRL to GND
Wiper Resistance
RH - floating, VRL = V-, force Iw current to
the wiper, IW = (VCC - VRL)/RTOTAL
Potentiometer Capacitance
See Macro Model below.
Leakage on DCP pins
Voltage at pin from V- to VCC
V70
VCC
V
250

10/10/25
pF
0.1
1
µA
VOLTAGE DIVIDER MODE (V- @ RLi; VCC @ RHi; measured at RWi, unloaded)
INL
(Note 10)
DNL
(Note 9)
Integral Non-linearity
Differential Non-linearity
ZSerror
(Note 7)
Zero-scale Error
FSerror
(Note 8)
Full-scale Error
4
W option
-1.5
±0.5
1.5
LSB
(Note 6)
U, T option
-1.0
±0.2
1.0
LSB
(Note 6)
Monotonic over all tap positions,
W option
-1.0
±0.4
1.0
LSB
(Note 6)
U, T option
-0.5
±0.15
0.5
LSB
(Note 6)
W option
0
1
5
U, T option
0
0.1
2
LSB
(Note 6)
W option
-5
-2
0
U, T option
-2
-0.2
0
LSB
(Note 6)
FN6423.2
August 17, 2015
ISL22343
Analog Specifications
SYMBOL
VMATCH
(Note 11)
Over recommended operating conditions unless otherwise stated. (Continued)
PARAMETER
TEST CONDITIONS
DCP-to-DCP Matching
Wipers at the same tap position, the same
voltage at all RH terminals and the same
voltage at all RL terminals
TCV (Note 12) Ratiometric Temperature Coefficient
fcutoff
(Note 19)
-3dB Cut Off Frequency
MIN
(Note 21)
TYP
(Note 5)
-2
DCP register set to 80 hex
MAX
(Note 21)
2
UNIT
LSB
(Note 6)
±4
ppm/°C
Wiper at midpoint (80hex) W option (10k)
1000
kHz
Wiper at midpoint (80hex) U option (50k)
250
kHz
Wiper at midpoint (80hex) T option (100k)
120
kHz
RESISTOR MODE (Measurements between RWi and RLi with RHi not connected, or between RWi and RHi with RLi not connected)
RINL
(Note 16)
RDNL
(Note 15)
Roffset
(Note 14)
RMATCH
(Note 17)
Integral Non-linearity
Differential Non-linearity
Offset
DCP-to-DCP matching
TCR
Resistance Temperature Coefficient
(Notes 18, 19)
W option
-3
±1
3
MI
(Note 13)
U, T option
-1
±0.3
1
MI
(Note 13)
W option
-1.5
±0.5
1.5
MI
(Note 13)
U, T option
-0.5
±0.04
0.5
MI
(Note 13)
W option
0
1
5
MI
(Note 13)
U, T option
0
0.25
2
MI
(Note 13)
Wipers at the same tap position with the
same terminal voltages
-3
3
MI
(Note 13)
DCP register set between 32 hex and FFhex
±40
ppm/°C
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
ICC1
IV-1
PARAMETER
VCC Supply Current
(Volatile Write/Read)
TYP
(Note 5)
MAX
(Note 21)
UNIT
VCC = 5.5V, fSCL = 400kHz; (for I2C Active, Read and
0.006
0.5
mA
VCC = 2.25V, fSCL = 400kHz; (for I2C Active, Read and
Volatile Write states only)
0.003
0.25
mA
TEST CONDITIONS
Volatile Write states only)
V- Supply Current (Volatile V- = -5.5V, VCC = 5.5V, fSCL = 400kHz; (for I2C Active,
Write/Read)
Read and Volatile Write states only)
V- = -2.25V, VCC = 2.25V, fSCL = 400kHz; (for I2C
Active, Read and Volatile Write states only)
ICC2
MIN
(Note 21)
-0.5
-0.012
mA
-0.25
-0.045
mA
VCC Supply Current (Non- VCC = 5.5V, V- = 5.5V, fSCL = 400kHz; (for I2C Active,
volatile Write/Read)
Read and Non-volatile Write states only)
VCC = 2.25V, V- = -2.25V, fSCL = 400kHz; (for I2C
Active, Read and Non-volatile Write states only)
IV-2
1.0
2.0
mA
0.3
1.0
mA
V- Supply Current
(Non-Volatile Write/Read)
V- = -5.5V, VCC = 5.5V, fSCL = 400kHz; (for I2C Active,
Read and Non-volatile Write states only)
-2.0
-1.2
mA
V- Supply Current
(Non-Volatile Write/Read)
V- = -2.25V, VCC = 2.25V, fSCL = 400kHz; (for I2C
Active, Read and Non-volatile Write states only)
-1.0
-0.4
mA
5
FN6423.2
August 17, 2015
ISL22343
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
ISB
IV-SB
ISD
IV-SD
ILkgDig
TYP
(Note 5)
MAX
(Note 21)
UNIT
VCC = +5.5V, V- = -5.5V @ +85°C, I2C interface in
0.5
2.0
µA
VCC = +5.5V, V- = -5.5V @ +125°C, I2C interface in
standby state
1.0
4.0
µA
VCC = +2.25V, V- = -2.25V @ +85°C, I2C interface in
standby state
0.2
1.0
µA
VCC = +2.25V, V- = -2.25V @ +125°C, I2C interface in
standby state
0.5
2.0
µA
PARAMETER
VCC Current (Standby)
V- Current (Standby)
VCC Current (Shutdown)
V- Current (Shutdown)
TEST CONDITIONS
MIN
(Note 21)
standby state
V- = -5.5V, VCC = +5.5V @ +85°C, I2C interface in
standby state
-4.0
-0.7
µA
V- = -5.5V, VCC = +5.5V @ +125°C, I2C interface in
standby state
-5.0
-1.5
µA
V- = -2.25V, VCC = +2.25V @ +85°C, I2C interface in
standby state
-2.0
-0.3
µA
V- = -2.25V, VCC = +2.25V @ +125°C, I2C interface in
standby state
-3.0
-0.4
µA
VCC = +5.5V, V- = -5.5V @ +85°C, I2C interface in
standby state
0.5
2.0
µA
VCC = +5.5V, V- = -5.5V @ +125°C, I2C interface in
standby state
1.0
4.0
µA
VCC = +2.25V, V- = -2.25V @ +85°C, I2C interface in
standby state
0.2
1.0
µA
VCC = +2.25V, V- = -2.25V @ +125°C, I2C interface in
standby state
0.5
2.0
µA
V- = -5.5V, VCC = +5.5V @ +85°C, I2C interface in
standby state
-4.0
-0.7
µA
V- = -5.5V, VCC = +5.5V @ +125°C, I2C interface in
standby state
-5.0
-1.5
µA
V- = -2.25V, VCC = +2.25V @ +85°C, I2C interface in
standby state
-2.0
-0.3
µA
V- = -2.25V, VCC = +2.25V @ +125°C, I2C interface in
standby state
-3.0
-0.4
µA
Leakage Current, at Pins Voltage at pin from GND to VCC
A0, A1, A2, SDA, and SCL
-1
1
µA
tWRT
(Note 19)
DCP Wiper Response
Time
SCL falling edge of last bit of DCP data byte to wiper
new position
1.5
µs
tShdnRec
(Note 19)
DCP Recall Time from
Shutdown Mode
SCL falling edge of last bit of ACR data byte to wiper
stored position and RH connection
1.5
µs
Power-on Recall Voltage
Minimum VCC at which memory recall occurs
Vpor
VCCRamp
VCC Ramp Rate
tD
Power-up Delay
1.9
2.1
0.2
V
V/ms
VCC above Vpor, to DCP Initial Value Register recall
completed, and I2C Interface in standby state
5
ms
EEPROM SPECIFICATION
EEPROM Endurance
EEPROM Retention
tWC
(Note 20)
Non-volatile Write Cycle
Time
6
Temperature T +55°C
1,000,000
Cycles
50
Years
12
20
ms
FN6423.2
August 17, 2015
ISL22343
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 21)
TYP
(Note 5)
MAX
(Note 21)
UNIT
0.3*VCC
V
SERIAL INTERFACE SPECS
VIL
A1, A0, A2, SDA, and SCL
Input Buffer LOW Voltage
VIH
A1, A0, A2, SDA, and SCL
Input Buffer HIGH Voltage
0.7*VCC
V
Hysteresis
(Note 19)
SDA and SCL Input Buffer
Hysteresis
0.05*VCC
V
VOL
(Note 19)
SDA Output Buffer LOW
Voltage, Sinking 4mA
Cpin
(Note 19)
fSCL
0
0.4
V
A1, A0, A2, SDA, and SCL
Pin Capacitance
10
pF
SCL Frequency
400
kHz
tsp
Pulse Width Suppression
Time at SDA and SCL
Inputs
Any pulse narrower than the max spec is suppressed
50
ns
tAA
(Note 19)
SCL Falling Edge to SDA
Output Data Valid
SCL falling edge crossing 30% of VCC, until SDA exits
the 30% to 70% of VCC window
900
ns
tBUF
(Note 19)
Time the Bus Must be Free SDA crossing 70% of VCC during a STOP condition, to
Before the Start of a New SDA crossing 70% of VCC during the following START
Transmission
condition
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing
600
ns
tSU:STA
START Condition Setup
Time
SCL rising edge to SDA falling edge; both crossing 70%
of VCC
600
ns
tHD:STA
START Condition Hold
Time
From SDA falling edge crossing 30% of VCC to SCL
falling edge crossing 70% of VCC
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VCC window, to
SCL rising edge crossing 30% of VCC
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VCC to SDA
entering the 30% to 70% of VCC window
0
ns
tSU:STO
STOP Condition Setup
Time
From SCL rising edge crossing 70% of VCC, to SDA
rising edge crossing 30% of VCC
600
ns
tHD:STO
STOP Condition Hold
Time for Read, or Volatile
Only Write
From SDA rising edge to SCL falling edge; both
crossing 70% of VCC
1300
ns
tDH
(Note 19)
Output Data Hold Time
From SCL falling edge crossing 30% of VCC, until SDA
enters the 30% to 70% of VCC window
0
ns
tR
(Note 19)
SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1*Cb
250
ns
tF
(Note 19)
SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1*Cb
250
ns
7
FN6423.2
August 17, 2015
ISL22343
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
Cb
(Note 19)
Capacitive Loading of SDA Total on-chip and off-chip
or SCL
Rpu
(Note 19)
SDA and SCL Bus Pull-up
Resistor Off-chip
Maximum is determined by tR and tF
For Cb = 400pF, max is about 2~2.5k
For Cb = 40pF, max is about 15~20k
tSU:A
A1 and A0 Setup Time
tHD:A
A1 and A0 Hold Time
MIN
(Note 21)
TYP
(Note 5)
10
MAX
(Note 21)
UNIT
400
pF
1
k
Before START condition
600
ns
After STOP condition
600
ns
NOTES:
5. Typical values are for TA = +25°C and 3.3V supply voltage.
6. LSB: [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
7. ZS error = V(RW)0/LSB.
8. FS error = [V(RW)255 – VCC]/LSB.
9. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting.
10. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 255.
11. VMATCH= [V(RWx)i -V(RWy)i]/LSB, for i = 0 to 255, x = 0 to 3, y = 0 to 3.
Max  V  RW  i  – Min  V  RW  i 
10 6
12. TC = ---------------------------------------------------------------------------------------------  ----------------- for i = 16 to 240 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper
V
 Max  V  RW  i  + Min  V  RW  i    2 +165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.
13. MI = |RW255 – RW0|/255. MI is a minimum increment. RW255 and RW0 are the measured resistances for the DCP register set to FF hex and
00 hex respectively.
14. Roffset = RW0/MI, when measuring between RW and RL.
Roffset = RW255/MI, when measuring between RW and RH.
15. RDNL = (RWi – RWi-1)/MI -1, for i = 16 to 255.
16. RINL = [RWi – (MI • i) – RW0]/MI, for i = 16 to 255.
17. RMATCH= [(Rx)i -(Ry)i]/MI, for i = 0 to 255, x = 0 to 3, y = 0 to 3.
6 for i = 16 to 240, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min ( ) is
 Max  Ri  – Min  Ri  
10
TC R = ----------------------------------------------------------------  ----------------- the minimum value of the resistance over the temperature range.
 Max  Ri  + Min  Ri    2 +165°C
19. This parameter is not 100% tested.
18.
20. tWC is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal nonvolatile write cycle.
21. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
8
FN6423.2
August 17, 2015
ISL22343
DCP Macro Model
RTOTAL
RH
CL
CH
CW
10pF
RL
10pF
25pF
RW
SDA vs SCL Timing
tHIGH
tF
SCL
tLOW
tsp
tR
tSU:DAT
tSU:STA
tHD:DAT
tHD:STA
SDA
(INPUT TIMING)
tSU:STO
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
A2, A1 and A0 Pin Timing
STOP
START
SCL
CLK 1
SDA
tSU:A
tHD:A
A2, A1, A0
9
FN6423.2
August 17, 2015
ISL22343
Typical Performance Curves
80
2.0
T = +125°C
1.5
60
STANDBY CURRENT (µA)
WIPER RESISTANCE ()
70
T = +25°C
50
40
30
T = -40°C
20
10
1.0
ICC
0.5
0
-0.5
IV-
-1.0
-1.5
0
0
50
100
150
200
-2.0
-40
250
0
TAP POSITION (DECIMAL)
40
80
120
TEMPERATURE (°C)
FIGURE 2. STANDBY ICC and IV- vs TEMPERATURE
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[ I(RW) = VCC/RTOTAL ] FOR 10k (W)
0.50
0.50
VCC = 5.5V
T = +25°C
T = +25°C
VCC = 2.25V
0.25
INL (LSB)
DNL (LSB)
0.25
0
0
-0.25
-0.25
VCC = 5.5V
VCC = 2.25V
-0.50
-0.50
0
50
100
150
200
250
0
50
100
150
200
250
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10k (W)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10k (W)
2.0
0
10k
-1
1.2
0.8
50k
VCC = 2.25V
VCC = 5.5V
0.4
0
-40
FS ERROR (LSB)
ZS ERROR (LSB)
1.6
VCC = 2.25V
50k
VCC = 5.5V
-2
-3
10k
-4
0
40
80
TEMPERATURE (ºC)
FIGURE 5. ZS ERROR vs TEMPERATURE
10
120
-5
-40
0
40
80
120
TEMPERATURE (ºC)
FIGURE 6. FS ERROR vs TEMPERATURE
FN6423.2
August 17, 2015
ISL22343
Typical Performance Curves
(Continued)
0.5
2.0
T = +25°C
T = +25°C
VCC = 5.5V
1.5
VCC = 2.25V
1.0
RINL (MI)
RDNL (MI)
0.25
0
0.5
-0.25
0
VCC = 2.25V
-0.50
0
50
VCC = 5.5V
100
150
200
-0.5
250
0
50
TAP POSITION (DECIMAL)
100
150
200
250
TAP POSITION (DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR
10k (W)
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR
10k (W)
200
1.60
10k
160
10k
0.80
TCv (ppm/ºC)
RTOTAL CHANGE (%)
1.20
5.5V
0.40
120
80
50k
40
0.00
50k
2.25V
0
-0.40
-40
0
40
80
120
16
66
116
166
216
266
TAP POSITION (DECIMAL)
TEMPERATURE (ºC)
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
FIGURE 9. END TO END RTOTAL % CHANGE vs
TEMPERATURE
500
INPUT
TCr (ppm/ºC)
OUTPUT
10k
400
300
200
50k
100
0
WIPER AT MID POINT (POSITION 80h)
RTOTAL = 10k
16
66
116
166
216
TAP POSITION (DECIMAL)
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm
11
FIGURE 12. FREQUENCY RESPONSE (1MHz)
FN6423.2
August 17, 2015
ISL22343
Typical Performance Curves
(Continued)
CS
SCL
WIPER UNLOADED,
WIPER
MOVEMENT FROM 0h to FFh
FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h
FIGURE 14. LARGE SIGNAL SETTLING TIME
ISL22343. A maximum of eight ISL22343 devices may
occupy the I2C serial bus (See Table 3).
Pin Description
Potentiometers Pins
RHI AND RLI
Principles of Operation
The high (RHi) and low (RLi) terminals of the ISL22343 are
equivalent to the fixed terminals of a mechanical
potentiometer. RHi and RLi are referenced to the relative
position of the wiper and not the voltage potential on the
terminals. With WRi set to 255 decimal, the wiper will be
closest to RHi, and with the WRi set to 0, the wiper is closest
to RLi.
The ISL22343 is an integrated circuit incorporating four
DCPs with its associated registers, non-volatile memory and
an I2C serial interface providing direct communication
between a host and the potentiometer and memory. The
resistor arrays are comprised of individual resistors
connected in a series. At either end of the array and
between each resistor is an electronic switch that transfers
the potential at that point to the wiper.
RWI
RWi is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WRi register.
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for I2C
interface. It receives device address, operation code, wiper
address and data from an I2C external master device at the
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock.
SDA requires an external pull-up resistor, since it is an open
drain input/output.
SERIAL CLOCK (SCL)
This input is the serial clock of the I2C serial interface. SCL
requires an external pull-up resistor, since it is an open drain
input.
DEVICE ADDRESS (A2, A1, A0)
The address inputs are used to set three least significant bits
of the 7-bit I2C interface slave address. A match in the slave
address serial data stream must match with the Address
input pins in order to initiate communication with the
12
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
When the device is powered down, the last value stored in
IVRi will be maintained in the non-volatile memory. When
power is restored, the contents of the IVRi are recalled and
loaded into the corresponding WRi to set the wipers to their
initial positions.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RHi and RLi pins). The RWi pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WRi). When the WRi of a DCP
contains all zeroes (WRi[7:0]= 00h), its wiper terminal (RWi)
is closest to its “Low” terminal (RLi). When the WRi register
of a DCP contains all ones (WRi[7:0] = FFh), its wiper
terminal (RWi) is closest to its “High” terminal (RHi). As the
value of the WRi increases from all zeroes (0) to all ones
(255 decimal), the wiper moves monotonically from the
position closest to RLi to the position closest to RHi. At the
FN6423.2
August 17, 2015
ISL22343
same time, the resistance between RWi and RLi increases
monotonically, while the resistance between RHi and RWi
decreases monotonically.
While the ISL22343 is being powered up, the WRi is reset to
80h (128 decimal), which locates RWi roughly at the center
between RLi and RHi. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the WRi will be reloaded with the value stored in
corresponding non-volatile Initial Value Register (IVRi).
The WRi and IVRi can be read or written to directly using the
I2C serial interface as described in the following sections.
Memory Description
The ISL22343 contains four non-volatile 8-bit Initial Value
Register (IVRi), eleven General Purpose non-volatile 8-bit
registers and five volatile 8-bit registers: four Wiper Registers
(WRi) and Access Control Register (ACR). Memory map of
ISL22343 is in Table 1. The non-volatile registers (IVRi) at
address 0, 1, 2 and 3 contain initial wiper position and volatile
registers (WRi) contain current wiper position.
The VOL bit (ACR[7]) determines whether the access to
wiper registers WRi or initial value registers IVRi.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT #
7
6
5
4
3
2
1
0
NAME
VOL
SHDN
WIP
0
0
0
0
0
If VOL bit is 0, the non-volatile IVRi registers are accessible.
If VOL bit is 1, only the volatile WRi are accessible.
Note: value is written to IVRi register also is written to the
corresponding WRi. The default value of this bit is 0.
The SHDN bit (ACR[6]) disables or enables Shutdown mode.
When this bit is 0, DCPs are in Shutdown mode. Default value
of the SHDN bit is 1.
RHi
RWi
RLi
TABLE 1. MEMORY MAP
FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE
ADDRESS
(hex)
NON-VOLATILE
VOLATILE
10
N/A
ACR
F
Reserved
The WIP bit (ACR[5]) is a read-only bit. It indicates that nonvolatile write operation is in progress. It is impossible to write
to the WRi or ACR while WIP bit is 1.
E
General Purpose
N/A
I2C Serial Interface
D
General Purpose
N/A
C
General Purpose
N/A
B
General Purpose
N/A
A
General Purpose
N/A
9
General Purpose
N/A
8
General Purpose
N/A
7
General Purpose
N/A
The ISL22343 supports an I2C bidirectional bus oriented
protocol. The protocol defines any device that sends data onto
the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both transmit
and receive operations. Therefore, the ISL22343 operates as
a slave device in all applications.
6
General Purpose
N/A
5
General Purpose
N/A
4
General Purpose
N/A
3
IVR3
WR3
2
IVR2
WR2
1
IVR1
WR1
0
IVR0
WR0
The non-volatile IVRi and volatile WRi registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described below in Table 2.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions
(see Figure 16). On power-up of the ISL22343, the SDA pin
is in the input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL22343 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 16). A START condition is ignored during the powerup of the device.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
13
FN6423.2
August 17, 2015
ISL22343
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
SCL is HIGH (see Figure 16). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.
A valid Identification Byte contains 1010 as four MSBs, and
the following three bits matching the logic values present at
pins A2, A1 and A0. The LSB is the Read/Write bit. Its value
is “1” for a Read operation and “0” for a Write operation (See
Table 3).
An ACK (Acknowledge) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 17).
TABLE 3. IDENTIFICATION BYTE FORMAT
LOGIC VALUES AT PINS A2, A1 AND A0, RESPECTIVELY
The ISL22343 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL22343 also responds with an ACK after receiving a Data
1
0
1
0
A2
A1
(MSB)
A0
R/W
(LSB)
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
SIGNALS FROM
THE SLAVE
S
T
A
R
T
IDENTIFICATION
BYTE
ADDRESS
BYTE
1 0 1 0 A2 A1 A0 0
S
T
O
P
DATA
BYTE
0 0 0 0
A
C
K
A
C
K
A
C
K
FIGURE 18. BYTE WRITE SEQUENCE
14
FN6423.2
August 17, 2015
ISL22343
SIGNALS
FROM THE
MASTER
S
T
A
R
T
SIGNAL AT SDA
IDENTIFICATION
BYTE WITH
R/W = 0
ADDRESS
BYTE
1 0 1 0 A2 A1 A0 0
A
C
K
S
A T
C O
K P
A
C
K
1 0 1 0 A2 A1 A0 1
0 0 0 0
A
C
K
SIGNALS FROM
THE SLAVE
S
T
A IDENTIFICATION
R
BYTE WITH
T
R/W = 1
A
C
K
A
C
K
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 19. READ SEQUENCE
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL22343 responds with an ACK. At this time, the device
enters its standby state (see Figure 18).
The non-volatile write cycle starts after STOP condition is
determined and it requires up to 20ms delay for the next
non-volatile write. Thus, non-volatile registers must be
written individually.
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (see Figure 19). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL22343 responds with an ACK. Then the ISL22343
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The Data Bytes are from the registers indicated by an
internal pointer. This pointers initial value is determined by
the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 0Fh, the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.The master terminates the read
operation issuing a NACK (ACK) and a STOP condition
following the last bit of the last Data Byte (See Figure 19).
reduce the useful bandwidth of the circuit, thus this may not
be a good solution for some applications. It may be a good
idea, in that case, to use fast amplifiers in a signal chain for
fast recovery.
Application Example
Figure 20 shows an example of using ISL22343 for gain
setting and offset correction in a high side current
measurement application. DCP0 applies a programmable
offset voltage of ±25mV to the FB+ pin of the Instrumentation
Amplifier ISL28272 to adjust output offset to zero voltages.
DCP1 programs the gain of the ISL28272 from 90 to 110
with 5V output for 10A current through current sense
resistor. DCP2 and DCP3 are used for another channel of
dual ISL28272 correspondently (not shown in Figure 20).
More application examples can be found at
http://www.intersil.com/data/an/AN1145.pdf
Applications Information
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients (or overshoot/undershoot) resulting from the
sudden transition from a very low impedance “make” to a
much higher impedance “break within an extremely short
period of time (<50ns). Two such code transitions are EFh to
F0h, and 0Fh to 10h. Note that all switching transients will
settle well within the settling time as stated on the datasheet.
A small capacitor can be added externally to reduce the
amplitude of these voltage transients, but that will also
15
FN6423.2
August 17, 2015
ISL22343
1.2V
DC/DC CONVERTER
OUTPUT
PROCESSOR LOAD
10A, MAX
0.005
10k
+5V
10k
0.1µF
16
V+
6 IN+
1/2 ISL28272
EN
7
VOUT
2
5 INVOUT = 0V TO +5V TO ADC
3 FB+
+5V
8
RH1
RH0
RW1
R2
1k, 1%
RW0
RL0
50k
R4
150k, 1%
4 FB- V-
R1
50k, 1%
R5
309, 1%
RL1
50k
DCP1 (1/4 ISL22343U)
DCP0 (1/4 ISL22343U)
PROGRAMMABLE OFFSET ±25mV
PROGRAMMABLE GAIN 90 TO 110
R3
R6
50k, 1%
1.37k, 1%
-5V
ISL22343UFV20Z
+5V
16
5
6
4
15
14
I2C bus
7
-5V
17
VCC
SCL
SDA
A2
A1
A0
GND
V-
RH0
RL0
RW0
RH1
RL1
RW1
RH2
RL2
RW2
RH3
RL3
RW3
18
19
20
DCP0
13
12
11
DCP1
10
9
8
DCP2
1
2
3
DCP3
FIGURE 20. CURRENT SENSING WITH GAIN AND OFFSET CONTROL
16
FN6423.2
August 17, 2015
ISL22343
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
August 17, 2015
FN6423.2
Updated Ordering Information Table on page 1.
Added Revision History and About Intersil sections.
Updated POD M20.173 to current revision. Changes: Converted to new POD format and added land pattern.
No dimension changes.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
17
FN6423.2
August 17, 2015
ISL22343
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L20.5x5
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
0.02
0.05
-
A2
-
0.65
1.00
9
0.38
5, 8
A3
b
0.20 REF
0.23
0.30
9
D
5.00 BSC
-
D1
4.75 BSC
9
D2
2.95
E
E1
E2
3.10
3.25
7, 8
5.00 BSC
-
4.75 BSC
2.95
e
3.10
9
3.25
7, 8
0.65 BSC
-
k
0.20
-
-
-
L
0.35
0.60
0.75
8
N
20
2
Nd
5
3
Ne
5
3
P
-
-
0.60
9

-
-
12
9
Rev. 4 11/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P &  are present when
Anvil singulation method is used and not present for saw
singulation.
10. Compliant to JEDEC MO-220VHHC Issue I except for the "b"
dimension.
18
FN6423.2
August 17, 2015
ISL22343
Package Outline Drawing
M20.173
20 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 5/10
A
1
3
6.50 ±0.10
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
SEE DETAIL "X"
10
20
3
0.20 C B A
1
9
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
H
- 0.05
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
GAUGE
PLANE
0.25 +0.05/-0.06 5
0.10 M C B A
0.10 C
0°-8°
0.05 MIN
0.15 MAX
SIDE VIEW
0.25
0.60 ±0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
is 0.07mm.
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153.
19
FN6423.2
August 17, 2015