ISL22414 ® Single Digitally Controlled Potentiometer (XDCP™) Data Sheet December 16, 2010 FN6424.1 Low Noise, Low Power, SPI® Bus, 256 Taps Features The ISL22414 integrates a single digitally controlled potentiometer (DCP), control logic and non-volatile memory on a monolithic CMOS integrated circuit. • 256 resistor taps The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wiper is controlled by the user through the SPI serial interface. The potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR control the position of the wiper. At power-up the device recalls the contents of the DCP’s IVR to the WR. • Daisy Chain Configuration The ISL22414 also has 14 General Purpose non-volatile registers that can be used as storage of lookup table for multiple wiper position or any other valuable information. • Wiper resistance: 70Ω typical @ 1mA • SPI serial interface with write/read capability • Shutdown mode • Non-volatile EEPROM storage of wiper position • 14 General Purpose non-volatile registers • High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T ≤ +55°C • Standby current <2.5µA max • Shutdown current <2.5µA max The ISL22414 features a dual supply that is beneficial for applications requiring a bipolar range for DCP terminals between V- and VCC. • Dual power supply - VCC = 2.25V to 5.5V The DCP can be used as three-terminal potentiometer or as two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. - V- = -2.25V to -5.5V • 10kΩ, 50kΩ or 100kΩ total resistance • Extended industrial temperature range: -40°C to +125°C • Military temperature range: -55 to +125°C Pinout • 10 Lead MSOP ISL22414 (10 LD MSOP) TOP VIEW O • Pb-free (RoHS compliant) 10 Vcc 2 9 RH SDI 3 8 RW CS 4 7 RL V- 5 6 GND SCK 1 SDO Ordering Information PART NUMBER (NOTES 1, 2) PART MARKING RESISTANCE OPTION (kΩ) TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL22414TFU10Z 414TZ 100 -40 to +125 10 Ld MSOP M10.118 ISL22414UFU10Z 414UZ 50 -40 to +125 10 Ld MSOP M10.118 ISL22414WFU10Z 414WZ 10 -40 to +125 10 Ld MSOP M10.118 ISL22414WMU10Z 414WM 10 -55 to +125 10 Ld MSOP M10.118 NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020. 2. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright Intersil Americas Inc. 2007, 2010. All Rights Reserved 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCPis a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL22414 Block Diagram V- VCC RH SCK SDO SPI INTERFACE SDI CS POWER UP INTERFACE, CONTROL AND STATUS LOGIC WR VOLATILE REGISTER AND WIPER CONTROL CIRCUITRY NON-VOLATILE REGISTERS RL RW GND Pin Descriptions MSOP PIN SYMBOL 1 SCK SPI interface clock input 2 SDO Data Output of the SPI serial interface 3 SDI Data Input of the SPI serial interface 4 CS Chip Select active low input 5 V- Negative power supply pin 6 GND 7 RL “Low” terminal of DCP 8 RW “Wiper” terminal of DCP 9 RH “High” terminal of DCP 10 VCC 2 DESCRIPTION Device ground pin Power supply pin FN6424.1 December 16, 2010 ISL22414 Absolute Maximum Ratings Thermal Information Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage at any Digital Interface Pin with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to 0.3V Voltage at any DCP pin with Respect to GND . . . . . . . . . . V- to VCC IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A @ +125°C ESD Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400V Thermal Resistance (Typical, Note 3) θJA (°C/W) 10 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Maximum Junction Temperature (Plastic Package). . . . . . . .+150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature Range Full Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 5.5V V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.25V to -5.5V Max Wiper Current Iw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Analog Specifications SYMBOL RTOTAL Over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range. PARAMETER RH to RL Resistance TEST CONDITIONS VRH, VRL RW CH/CL/CW ILkgDCP TYP (Note 4) MAX (Note 18) UNIT W option 10 kΩ U option 50 kΩ T option 100 kΩ RH to RL Resistance Tolerance End-to-End Temperature Coefficient MIN (Note 18) -20 +20 % W option ±150 ppm/°C U, T option ±50 ppm/°C DCP Terminal Voltage VRH and VRL to GND Wiper Resistance RH - floating, VRL = V-, force Iw current to the wiper, IW = (VCC - VRL)/RTOTAL Potentiometer Capacitance See “DCP Macro Model” on page 7 Leakage on DCP Pins Voltage at pin from V- to VCC V70 VCC V 250 Ω 10/10/25 pF -1 0.1 1 µA W option -1.5 ±0.5 1.5 LSB (Note 5) U, T option -1.0 ±0.2 1.0 LSB (Note 5) W option -1.0 ±0.4 1.0 LSB (Note 5) U, T option -0.5 ±0.15 0.5 LSB (Note 5) LSB (Note 5) VOLTAGE DIVIDER MODE (V- @ RL; VCC @ RH; measured at RW, unloaded) INL (Note 9) DNL (Note 8) Integral Non-linearity Monotonic Over All Tap Positions Differential Non-linearity Monotonic Over All Tap Positions ZSerror (Note 6) Zero-scale Error FSerror (Note 7) Full-scale Error TCV (Note 10) Ratiometric Temperature Coefficient 3 W option 0 1 5 U, T option 0 0.5 2 W option -5 -1 0 U, T option -2 -1 0 DCP register set to 80 hex ±4 LSB (Note 5) ppm/°C FN6424.1 December 16, 2010 ISL22414 Analog Specifications SYMBOL fcutoff Over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range. (Continued) PARAMETER -3dB Cut Off Frequency TEST CONDITIONS MIN (Note 18) TYP (Note 4) MAX (Note 18) UNIT Wiper at midpoint (80hex) W option (10k) 1000 kHz Wiper at midpoint (80hex) U option (50k) 250 kHz Wiper at midpoint (80hex) T option (100k) 120 kHz RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) RINL (Note 14) RDNL (Note 13) Roffset (Note 12) TCR (Notes 15) Integral Non-linearity Differential Non-linearity Offset Resistance Temperature Coefficient W option -3 ±1.5 3 MI (Note 11) U, T option -1 ±0.3 1 MI (Note 11) W option -1.5 ±0.4 1.5 MI (Note 11) U, T option -0.5 ±0.15 0.5 MI (Note 11) W option 0 1 5 MI (Note 11) U, T option 0 0.5 2 MI (Note 11) DCP register set between 32 hex and FF hex ±50 ppm/°C Operating Specifications Over the recommended operating conditions unless otherwise specified. Boldface limits apply over the operating temperature range. SYMBOL ICC1 IV-1 ICC2 IV-2 ISB PARAMETER VCC Supply Current (volatile write/read) V- Supply Current (volatile write/read) VCC Supply Current (non-volatile write/read) MIN TYP MAX (Note 18) (Note 4) (Note 18) UNIT VCC = 5.5V, V- = 5.5V, fSCK = 5MHz; (for SPI Active, Read and Volatile Write states only) 0.36 1 mA VCC = 2.25V, V- = -2.25V, fSCK = 5MHz; (for SPI Active, Read and Volatile Write states only) 0.13 0.4 mA TEST CONDITIONS V- = -5.5V, VCC = 5.5V, fSCK = 5MHz; (for SPI Active, Read and Volatile Write states only) -1 -0.18 mA V- = -2.25V, VCC = 2.25V, fSCK = 5MHz; (for SPI Active, Read and Volatile Write states only) -0.4 -0.06 mA VCC = 5.5V, V- = 5.5V, fSCK = 5MHz; (for SPI Active, Read and Non-volatile Write states only) 1 2 mA VCC = 2.25V, V- = -2.25V, fSCK = 5MHz; (for SPI Active, Read and Non-volatile Write states only) 0.3 0.7 mA V- Supply Current (non-volatile write/read) V- = -5.5V, VCC = 5.5V, fSCK = 5MHz; (for SPI Active, Read and Non-volatile Write states only) -2 -1.2 mA V- Supply Current (non-volatile write/read) V- = -2.25V, VCC = 2.25V, fSCK = 5MHz; (for SPI Active, Read and Non-volatile Write states only) -0.7 -0.4 mA VCC Current (standby) VCC = +5.5V, V- = -5.5V @ +85°C, SPI interface in standby state 4 0.2 1.5 µA VCC = +5.5V, V- = -5.5V @ +125°C, SPI interface in standby state 1 2.5 µA VCC = +2.25V, V- = -2.25V @ +85°C, SPI interface in standby state 0.1 1 µA VCC = +2.25V, V- = -2.25V @ +125°C, SPI interface in standby state 0.5 2 µA FN6424.1 December 16, 2010 ISL22414 Operating Specifications Over the recommended operating conditions unless otherwise specified. Boldface limits apply over the operating temperature range. (Continued) SYMBOL IV-SB ISD IV-SD ILkgDig tWRT tShdnRec Vpor PARAMETER V- Current (Standby) VCC Current (Shutdown) V- Current (Shutdown) TEST CONDITIONS V- = -5.5V, VCC = +5.5V @ +85°C, SPI interface in standby state MIN TYP MAX (Note 18) (Note 4) (Note 18) UNIT -2.5 -0.7 µA V- = -5.5V, VCC = +5.5V @ +125°C, SPI interface in standby state -4 -3 µA V- = -2.25V, VCC = +2.25V @ +85°C, SPI interface in standby state -1.5 -0.3 µA V- = -2.25V, VCC = +2.25V @ +125°C, SPI interface in standby state -3 -1 µA VCC = +5.5V, V- = -5.5V @ +85°C, SPI interface in standby state 0.2 1.5 µA VCC = +5.5V, V- = -5.5V @ +125°C, SPI interface in standby state 1 2.5 µA VCC = +2.25V, V- = -2.25V @ +85°C, SPI interface in standby state 0.1 1 µA VCC = +2.25V, V- = -2.25V @ +125°C, SPI interface in standby state 0.5 2 µA V- = -5.5V, VCC = +5.5V @ +85°C, SPI interface in standby state -2.5 -0.7 µA V- = -5.5V, VCC = +5.5V @ +125°C, SPI interface in standby state -4 -3 µA V- = -2.25V, VCC = +2.25V @ +85°C, SPI interface in standby state -1.5 -0.3 µA V- = -2.25V, VCC = +2.25V @ +125°C, SPI interface in standby state -3 -1 µA Leakage Current, at Pins SCK, SDI, SDO and CS Voltage at pin from GND to VCC DCP Wiper Response Time CS rising edge to wiper new position 1.5 µs DCP Recall Time From Shutdown Mode CS rising edge to wiper stored position and RH connection 1.5 µs Power-on Recall Voltage Minimum VCC at which memory recall occurs VccRamp VCC Ramp Rate tD Power-up Delay -0.5 0.5 1.9 2.1 0.2 µA V V/ms 5 VCC above Vpor, to DCP Initial Value Register recall completed, and SPI Interface in standby state ms EEPROM SPECIFICATION EEPROM Endurance EEPROM Retention tWC (Note 16) Temperature T ≤ +55ºC 1,000,000 Cycles 50 Years Non-volatile Write Cycle Time 12 20 ms SERIAL INTERFACE SPECIFICATIONS VIL SCK, SDI, and CS Input Buffer LOW voltage -0.3 0.3*VCC V VIH SCK, SDI, and CS Input Buffer HIGH Voltage 0.7*VCC VCC+0.3 V SCK, SDI, and CS Input Buffer Hysteresis 0.05*VCC Hysteresis VOL SDO Output Buffer LOW Voltage 5 IOL = 4mA for Open Drain output, pull-up voltage Vpu = VCC 0 V 0.4 V FN6424.1 December 16, 2010 ISL22414 Operating Specifications Over the recommended operating conditions unless otherwise specified. Boldface limits apply over the operating temperature range. (Continued) SYMBOL Rpu (Note 17) PARAMETER TEST CONDITIONS SDO Pull-up Resistor Off-chip MIN TYP MAX (Note 18) (Note 4) (Note 18) Maximum is determined by tRO and tFO with maximum bus load Cb = 30pF, fSCK = 5MHz 2 UNIT kΩ Cpin SCK, SDI, SDO and CS Pin Capacitance 10 pF fSCK SPI Frequency tCYC SPI Clock Cycle Time 200 ns tWH SPI Clock High Time 100 ns tWL 5 MHz SPI Clock Low Time 100 ns tLEAD Lead Time 250 ns tLAG Lag Time 250 ns tSU SDI, SCK and CS Input Setup Time 50 ns tH SDI, SCK and CS Input Hold Time 50 ns tRI SDI, SCK and CS Input Rise Time 10 ns tFI SDI, SCK and CS Input Fall Time 10 20 ns tDIS SDO output Disable Time 0 100 ns tSO SDO Output Setup Time 50 ns tV SDO Output Valid Time 150 ns tHO SDO Output Hold Time 0 ns tRO SDO Output Rise Time Rpu = 2k, Cbus = 30pF tFO SDO Output Fall Time Rpu = 2k, Cbus = 30pF tCS CS Deselect Time 60 60 2 ns ns µs NOTES: 4. Typical values are for TA = +25°C and 3.3V supply voltage. 5. LSB: [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 6. ZS error = V(RW)0/LSB. 7. FS error = [V(RW)255 – VCC]/LSB. 8. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting. 9. INL = [V(RW)i – i • LSB – V(RW)]/LSB for i = 1 to 255 6 Max ( V ( RW ) i ) – Min ( V ( RW ) i ) 10 10. TC = --------------------------------------------------------------------------------------------- × --------------- for i = 16 to 255 decimal, T = -40°C to +125°C or T = -55°C to +125°C. Max( ) is the V [ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] ⁄ 2 ΔT°C maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 11. MI = |RW255 – RW0|/255. MI is a minimum increment. RW255 and RW0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively. 12. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW255/MI, when measuring between RW and RH. 13. RDNL = (RWi – RWi-1)/MI -1, for i = 1 to 255. 14. RINL = [RWi – (MI • i) – RW0]/MI, for i = 1 to 255. 15. 6 [ Max ( Ri ) – Min ( Ri ) ] 10 for i = 16 to 255, T = -40°C to +125°C or T = -55°C to +125°C. Max( ) is the maximum value of the TC R = ---------------------------------------------------------------- × --------------[ Max ( Ri ) + Min ( Ri ) ] ⁄ 2 ΔT°C resistance and Min( ) is the minimum value of the resistance over the temperature range. 16. tWC is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle. 17. Rpu is specified for the highest data rate transfer for the device. Higher value pull-up can be used at lower data rates. 18. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 6 FN6424.1 December 16, 2010 ISL22414 DCP Macro Model RTOTAL RH CL CH CW 10pF RL 10pF 25pF RW Timing Diagrams Input Timing tCS CS SCK tSU tH ... tWH tWL tRI tFI ... MSB SDI tLAG tCYC tLEAD LSB HIGH IMPEDANCE SDO Output Timing CS SCK ... tSO tHO tDIS ... MSB SDO LSB tV SDI ADDR XDCP Timing (for All Load Instructions) CS tWRT SCK SDI ... ... MSB LSB VW SDO HIGH IMPEDANCE 7 FN6424.1 December 16, 2010 ISL22414 Typical Performance Curves 80 2.0 T = +125ºC 1.5 60 STANDBY CURRENT (µA) WIPER RESISTANCE (Ω) 70 T = +25ºC 50 40 30 T = -40ºC 20 10 1.0 ICC 0.5 0 -0.5 IV- -1.0 -1.5 0 0 50 100 150 200 -2.0 -40 250 0 TAP POSITION (DECIMAL) 40 80 120 TEMPERATURE (°C) FIGURE 2. STANDBY ICC AND IV- vs TEMPERATURE FIGURE 1. WIPER RESISTANCE vs TAP POSITION [ I(RW) = VCC/RTOTAL ] FOR 10kΩ (W) 0.50 0.50 VCC = 5.5V T = +25ºC T = +25ºC VCC = 2.25V 0.25 INL (LSB) DNL (LSB) 0.25 0 0 -0.25 -0.25 VCC = 5.5V VCC = 2.25V -0.50 -0.50 0 50 100 150 200 250 0 50 100 150 200 250 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W) FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W) 2.0 0 10k -1 1.2 0.8 50k VCC = 2.25V VCC = 5.5V 0.4 0 -40 FS ERROR (LSB) ZS ERROR (LSB) 1.6 VCC = 2.25V 50k VCC = 5.5V -2 -3 10k -4 0 40 80 TEMPERATURE (ºC) FIGURE 5. ZS ERROR vs TEMPERATURE 8 120 -5 -40 0 40 80 120 TEMPERATURE (ºC) FIGURE 6. FS ERROR vs TEMPERATURE FN6424.1 December 16, 2010 ISL22414 Typical Performance Curves (Continued) 0.5 2.0 T = +25ºC T = +25ºC VCC = 5.5V 1.5 VCC = 2.25V 1.0 RINL (MI) RDNL (MI) 0.25 0 0.5 -0.25 0 VCC = 2.25V -0.50 0 50 VCC = 5.5V 100 150 200 -0.5 250 0 50 TAP POSITION (DECIMAL) 100 150 200 250 TAP POSITION (DECIMAL) FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 10kΩ (W) FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 10kΩ (W) 200 1.60 10k 160 10k 0.80 TCv (ppm/ºC) RTOTAL CHANGE (%) 1.20 5.5V 0.40 80 50k 40 0.00 50k 2.25V -0.40 -40 0 40 80 120 0 16 66 116 166 216 266 TAP POSITION (DECIMAL) TEMPERATURE (ºC) FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm FIGURE 9. END TO END RTOTAL % CHANGE vs TEMPERATURE 500 INPUT OUTPUT 10k 400 TCr (ppm/ºC) 120 300 200 50k 100 0 WIPER AT MID POINT (POSITION 80h) RTOTAL = 10kΩ 16 66 116 166 216 TAP POSITION (DECIMAL) FIGURE 11. TC FOR RHEOSTAT MODE IN ppm 9 FIGURE 12. FREQUENCY RESPONSE (1MHz) FN6424.1 December 16, 2010 ISL22414 Typical Performance Curves (Continued) CS SCL WIPER UNLOADED, WIPER MOVEMENT FROM 0h to FFh FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h Pin Description FIGURE 14. LARGE SIGNAL SETTLING TIME shifted in at the rising edge of the serial clock SCK, while the CS input is low. Potentiometer Pins CHIP SELECT (CS) RH AND RL The high (RH) and low (RL) terminals of the ISL22414 are equivalent to the fixed terminals of a mechanical potentiometer. RH and RL are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WR set to 255 decimal, the wiper will be closest to RH, and with the WR set to 0, the wiper is closest to RL. RW RW is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WR register. Bus Interface Pins SERIAL CLOCK (SCK) This is the serial clock input of the SPI serial interface. CS LOW enables the ISL22414, placing it in the active power mode. A HIGH to LOW transition on CS is required prior to the start of any operation after power up. When CS is HIGH, the ISL22414 is deselected and the SDO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. Principles of Operation The ISL22414 is an integrated circuit incorporating one DCP with its associated registers, non-volatile memory and the SPI serial interface providing direct communication between host and potentiometer and memory. The resistor array is comprised of individual resistors connected in a series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. SERIAL DATA OUTPUT (SDO) The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. The SDO is a serial data output pin. During a read cycle, the data bits are shifted out on the falling edge of the serial clock SCK and will be available to the master on the following rising edge of SCK. When the device is powered down, the last value stored in IVR will be maintained in the non-volatile memory. When power is restored, the content of the IVR is recalled and loaded into the WR to set the wiper to the initial position. The output type is configured through ACR[1] bit for PushPull or Open Drain operation. Default setting for this pin is Push-Pull. An external pull up resistor is required for Open Drain output operation. Note, the external pull up voltage not allowed beyond VCC. DCP Description SERIAL DATA INPUT (SDI) The SDI is the serial data input pin for the SPI interface. It receives device address, operation code, wiper address and data from the SPI remote host device. The data bits are 10 The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WR). When the WR of a DCP contains all zeroes (WR[7:0]= 00h), its wiper terminal (RW) FN6424.1 December 16, 2010 ISL22414 is closest to its “Low” terminal (RL). When the WR register of a DCP contains all ones (WR[7:0]= FFh), its wiper terminal (RW) is closest to its “High” terminal (RH). As the value of the WR increases from all zeroes (0) to all ones (255 decimal), the wiper moves monotonically from the position closest to RL to the closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. The register at address 0Fh is a read-only reserved register. Information read from this register should be ignored. While the ISL22414 is being powered up, the WR is reset to 80h (128 decimal), which locates RW roughly at the center between RL and RH. After the power supply voltage becomes large enough for reliable non-volatile memory reading, the WR will be reloaded with the value stored in a non-volatile Initial Value Register (IVR). TABLE 2. ACCESS CONTROL REGISTER (ACR) The WR and IVR can be read or written to directly using the SPI serial interface as described in the following sections. Memory Description The ISL22414 contains one non-volatile 8-bit Initial Value Register (IVR), fourteen non-volatile 8-bit General Purpose (GP) registers, volatile 8-bit Wiper Register (WR), and volatile 8-bit Access Control Register (ACR). The memory map of ISL22414 is in Table 1. The non-volatile IVR and volatile WR registers are accessible with the same address. The Access Control Register (ACR) contains information and control bits described below in Table 2. The VOL bit (ACR[7]) determines whether the access to wiper registers WR or initial value registers IVR. BIT # BIT NAME 7 6 5 VOL SHDN WIP 4 3 2 1 0 0 0 0 SDO 0 If VOL bit is 0, the non-volatile IVR register is accessible. If VOL bit is 1, only the volatile WR is accessible. Note, value is written to IVR register also is written to the WR. The default value of this bit is 0. The SHDN bit (ACR[6]) disables or enables Shutdown mode. When this bit is 0, DCP is in Shutdown mode, i.e. DCP is forced to end-to-end open circuit and RW is shorted to RL as shown on Figure 15. Default value of SHDN bit is 1. RH TABLE 1. MEMORY MAP ADDRESS (hex) NON-VOLATILE VOLATILE 10 N/A ACR F RW Reserved RL E General Purpose N/A FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE D General Purpose N/A C General Purpose N/A Setting SHDN bit to 1 is returned wiper to prior to Shutdown Mode position. B General Purpose N/A A General Purpose N/A 9 General Purpose N/A 8 General Purpose N/A 7 General Purpose N/A 6 General Purpose N/A 5 General Purpose N/A 4 General Purpose N/A 3 General Purpose N/A SPI Serial Interface 2 General Purpose N/A 1 General Purpose N/A 0 IVR WR The ISL22414 supports an SPI serial protocol, mode 0. The device is accessed via the SDI input and SDO output with data clocked in on the rising edge of SCK, and clocked out on the falling edge of SCK. CS must be LOW during communication with the ISL22414. SCK and CS lines are controlled by the host or master. The ISL22414 operates only as a slave device. The non-volatile register (IVR) at address 0, contains initial wiper position and volatile register (WR) contains current wiper position. 11 The WIP bit (ACR[5]) is a read-only bit. It indicates that nonvolatile write operation is in progress. The WIP bit can be read repeatedly after a non-volatile write to determine if the write has been completed. It is impossible to write or read to the WR or ACR while WIP bit is 1. The SDO bit (ACR[1]) configures type of SDO output pin. The default value of SDO bit is 0 for Push - Pull output. SDO pin can be configured as Open Drain output for some application. In this case, an external pull up resistor is required. See “Applications Information” on page 13. FN6424.1 December 16, 2010 ISL22414 All communication over the SPI interface is conducted by sending the MSB of each byte of data first. LOW. Then host send a valid Instruction Byte, followed by one or more Data Bytes to SDI pin. The host terminates the write operation by pulling the CS pin from LOW to HIGH. Instruction is executed on rising edge of CS. For a write to address 0, the MSB of the byte at address 10h (ACR[7]) determines if the Data Byte is to be written to volatile or both volatile and non-volatile registers. Refer to “Memory Description” and Figure 16. Note, the internal non-volatile write cycle starts with the rising edge of CS and requires up to 20ms. During non-volatile write cycle the read operation to ACR register is allowed to check WIP bit. Protocol Conventions The SPI protocol contains Instruction Byte followed by one or more Data Bytes. A valid Instruction Byte contains instruction as the three MSBs, with the following five register address bits (see Table 3). The next byte sent to the ISL22414 is the Data Byte. TABLE 3. INSTRUCTION BYTE FORMAT BIT # 7 6 5 4 3 2 1 0 I2 I1 I0 R4 R3 R2 R1 R0 Read Operation A Read operation to the ISL22414 is a four byte operation. It requires first, the CS transition from HIGH to LOW. Then host send a valid Instruction Byte, followed by “dummy” Data Byte, NOP Instruction Byte and another “dummy” Data Byte to SDI pin. The SPI host receives the Instruction Byte (instruction code + register address) and requested Data Byte from SDO pin on the rising edge of SCK during third and fourth bytes respectively. The host terminates the read operation by pulling the CS pin from LOW to HIGH (see Figure 17). Reading from the IVR will not change the WR, if its contents are different. Table 4 contains a valid instruction set for ISL22414. There are only sixteen register addresses possible for this DCP. If the [R4:R0] bits are zero, then the read or write is to either the IVR or the WR register (depends of VOL bit at ACR). If the [R4:R0] are 10000, then the operation is on the ACR. Write Operation A Write operation to the ISL22414 is a two or more bytes operation. It requires first, the CS transition from HIGH to TABLE 4. INSTRUCTION SET INSTRUCTION SET I2 I1 I0 R4 R3 R2 R1 R0 OPERATION 0 0 0 X X X X X NOP 0 0 1 X X X X X ACR READ 0 1 1 X X X X X ACR WRITE 1 0 0 R4 R3 R2 R1 R0 WR, IVR, GP or ACR READ 1 1 0 R4 R3 R2 R1 R0 WR, IVR, GP or ACR WRITE where X means “do not care” CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK SDI WR INSTRUCTION ADDR DATA BYTE SDO FIGURE 16. TWO BYTE WRITE SEQUENCE 12 FN6424.1 December 16, 2010 ISL22414 CS 1 8 16 24 32 SCK SDI RD NOP ADDR RD SDO ADDR READ DATA FIGURE 17. FOUR BYTE READ SEQUENCE Applications Information Communicating with ISL22414 Communication with ISL22414 proceeds using SPI interface through the ACR (address 10000b), IVR (address 00000b), WR (addresses 00000b) and General Purpose registers (addresses from 00001b to 01110b). The wiper of the potentiometer is controlled by the WR register. Writes and reads can be made directly to these register to control and monitor the wiper position without any non-volatile memory changes. This is done by setting MSB bit at address 10000b to 1 (ACR[7] = 1). The non-volatile IVR stores the power up position of the wiper. IVR is accessible when MSB bit at address 10000b is set to 0 (ACR[7] = 0). Writing a new value to the IVR register will set a new power up position for the wiper. Also, writing to this register will load the same value into the corresponding WR as the IVR. Reading from the IVR will not change the WR, if its contents are different. Daisy Chain Configuration When application needs more then one ISL22414, it can communicate with all of them without additional CS lines by daisy chaining the DCPs as shown on Figure 18. In Daisy Chain configuration the SDO pin of previous chip is connected to SDI pin of the following chip, and each CS and SCK pins are connected to the corresponding microcontroller pins in parallel, like regular SPI interface implementation. The Daisy Chain configuration can also be used for simultaneous setting of multiple DCPs. Note, the number of daisy chained DCPs is limited only by the driving capabilities of SCK and CS pins of microcontroller; for larger number of SPI devices buffering of SCK and CS lines is required. Daisy Chain Write Operation The write operation starts by HIGH to LOW transition on CS line, followed by N number of two bytes write instructions on SDI line with reversed chain access sequence: the instruction byte + data byte for the last DCP in chain is going first, as shown on Figure 19, where N is a number of DCPs in chain. The serial data is going through DCPs from DCP0 13 to DCP(N-1) as follow: DCP0 --> DCP1 --> DCP2 --> ... --> DCP(N-1). The write instruction is executed on the rising edge of CS for all N DCPs simultaneously. Daisy Chain Read Operation The read operation consists two parts: first, send read instructions (N two bytes operation) with valid address; second, read the requested data while sending NOP instructions (N two bytes operation) as shown on Figure 20, and Figure 21. The first part starts by HIGH to LOW transition on CS line, followed by N two bytes read instruction on SDI line with reversed chain access sequence: the instruction byte + dummy data byte for the last DCP in chain is going first, followed by LOW to HIGH transition on CS line. The read instructions are executed during second part of read sequence. It also starts by HIGH to LOW transition on CS line, followed by N number of two bytes NOP instructions on SDI line and LOW to HIGH transition of CS. The data is read on every even byte during second part of read sequence while every odd byte contains instruction code + address from which the data is being read. Wiper Transition When stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance “make” to a much higher impedance “break within an extremely short period of time (<50ns). Two such code transitions are EFh to F0h, and 0Fh to 10h. Note, that all switching transients will settle well within the settling time as stated in the datasheet. A small capacitor can be added externally to reduce the amplitude of these voltage transients, but that will also reduce the useful bandwidth of the circuit, thus may not be a good solution for some applications. It may be a good idea, in that case, to use fast amplifiers in a signal chain for fast recovery. FN6424.1 December 16, 2010 ISL22414 N DCP IN A CHAIN CS SCK DCP0 MOSI MISO µC DCP1 DCP2 DCP(N-1) CS CS CS CS SCK SCK SCK SCK SDI SDO SDI SDO SDI SDO SDI SDO FIGURE 18. DAISY CHAIN CONFIGURATION CS SCK 16 CLKLS WR SDI 16 CLKS 16 CLKS D C P2 SDO 0 WR D C P1 WR D C P0 WR D C P2 WR D C P1 WR D C P2 SDO 1 SDO 2 FIGURE 19. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK SDI INSTRUCTION ADDR SDO DATA IN DATA OUT FIGURE 20. TWO BYTE OPERATION 14 FN6424.1 December 16, 2010 ISL22414 CS SCK 16 CLKS SDI RD DCP2 SDO 16 CLKS RD DCP1 16 CLKS 16 CLKS 16 CLKS 16 CLKS RD DCP0 NOP NOP NOP DCP2 OUT DCP1 OUT DCP0 OUT FIGURE 21. DAISY CHAIN READ SEQUENCE OF N = 3 DCP 15 FN6424.1 December 16, 2010 ISL22414 Mini Small Outline Plastic Packages (MSOP) N M10.118 (JEDEC MO-187BA) 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 E INCHES SYMBOL -B- INDEX AREA 1 2 0.20 (0.008) A B C TOP VIEW 4X θ 0.25 (0.010) R1 R GAUGE PLANE A SEATING PLANE -C- A2 A1 b -He D 0.10 (0.004) 4X θ L SEATING PLANE C -A0.20 (0.008) C C a SIDE VIEW CL E1 0.20 (0.008) C D -B- MILLIMETERS MAX MIN MAX NOTES A 0.037 0.043 0.94 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.030 0.037 0.75 0.95 - b 0.007 0.011 0.18 0.27 9 c 0.004 0.008 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4 e L1 MIN 0.020 BSC 0.50 BSC - E 0.187 0.199 4.75 5.05 - L 0.016 0.028 0.40 0.70 6 L1 0.037 REF 0.95 REF - N 10 10 7 R 0.003 - 0.07 - - R1 0.003 - 0.07 - - θ 5o 15o 5o 15o - α 0o 6o 0o 6o - END VIEW Rev. 0 12/02 NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN6424.1 December 16, 2010