Application Note 1648 Author: David Sorlien ISL9110IRTNEVAL1Z, ISL9110IRT7EVAL1Z, ISL9110IRTAEVAL1Z Evaluation Board User Guide Evaluation Board Features • ISL9110IRTAZ high efficiency buck-boost regulator with adjustable output voltage • Input voltage rating from 1.8V to 5.5V TABLE 2. DESCRIPTION OF CONNECTORS CONNECTOR DESCRIPTION J1 Header for connecting input power J2 Header for connecting external load • Resistor programmable output voltage, set to 3.3V • 1200mA output current at VIN ≥ 3V and VOUT = 3.3V • 2.5MHz switching frequency • Jumper selectable EN (enabled/disabled) • Jumper selectable MODE (auto-PFM/forced-PWM) • LED indicators for PG and BAT status outputs TABLE 3. DESCRIPTION OF JUMPERS JUMPER DESCRIPTION J3 Jumper to select EN input logic state. Set EN = VIN to enable device, or set EN = GND to disable device. J4 Jumper to select MODE input logic state. Set MODE = VIN to enable auto-PFM mode, or set MODE = GND to select forced PWM mode. • Connectors, test points and jumpers for easy evaluation To use external sync feature, remove this jumper and apply an external clock between 2.75MHz and 3.25MHz on the MODE test point (TP10) or center pin on the J4 header. Required Equipment • Power supply capable of delivering up to 5.5V and 3A • Electronic load • Multimeter to measure voltages and currents • Oscilloscope Test Points, Connectors and Jumpers TABLE 1. DESCRIPTION OF TEST POINTS J5 Jumper to enable PG LED. Remove this jumper when measuring quiescent current. J6 Jumper to enable BAT LED. Remove this jumper when measuring quiescent current. Quick Setup Guide 1. Install jumpers on J5 and J6 to enable the status LEDs. 2. Install jumper on J3, shorting EN to VIN. TEST POINT(S) DESCRIPTION TP1 VOUT Kelvin connection for efficiency measurements TP2 LX1 (Input side of power inductor) 4. Connect power supply to J1, with voltage setting between 1.8V and 5.5V. TP3 PGND (Power ground) 5. Connect electronic load to J2. TP4 LX2 (Output side of power inductor) TP5 PVIN Kelvin connection for efficiency measurements 6. Place scope probes on VOUT test point, and other test points of interest. TP6 VIN (supply input for internal reference) TP7 PG (Open drain status output) TP8 BAT (Open drain status output) TP9 EN (Enable input, drive high to enable device) TP10 MODE/SYNC (Mode input, drive low for forced PWM, or apply external clock between 2.75MHz and 3.25MHz for external sync) TP11, TP13, GND (Ground) TP14 TP12 July 10, 2012 AN1648.1 FB (Voltage feedback input, connected to resistive divider network that sets VOUT) 1 3. Install jumper on J4, shorting MODE to VIN. 7. Turn on the power supply. 8. Monitor the output voltage start-up sequence on the scope. The waveforms will look similar to those shown in Figure 1 and Figure 2. 9. Turn on the electronic load. 10. Measure the output voltage with the voltmeter. The voltage should regulate within data sheet spec limits (FN7649). 11. To determine efficiency, first remove jumpers J5 and J6 to eliminate LED currents. Then measure input and output voltages at the Kelvin test points TP5 and TP1, and measure the input and output currents. Calculate efficiency based on these measurements. 12. To test external sync, remove the jumper at J4, then apply an external clock between 2.75MHz and 3.25MHz on the MODE input (test point TP10, or the center pin of header J4). CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright Intersil Americas Inc. 2011, 2012. All Rights Reserved. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Application Note 1648 Typical Start-up Waveforms LX1 2V/DIV To change the output voltage, resistor R2 should be removed and replaced with a resistor value corresponding to the desired output voltage, as shown in Table 4. A precision resistor with 1% tolerance should be used. VIN = 2V VOUT = 3.3V IOUT = 200mA LX2 2V/DIV TABLE 4. OUTPUT VOLTAGE PROGRAMMING VOUT 2V/DIV EN 2V/DIV 400µs/DIV FIGURE 1. ISL9110 START-UP WITH VIN = 2V AND VOUT = 3.3V LX1 2V/DIV Output Voltage Programming VIN = 4V VOUT = 3.3V IOUT = 200mA DESIRED OUTPUT VOLTAGE (V) R2 RESISTOR VALUE (kΩ) 2.0 665 2.5 470 3.0 365 3.3 324 3.4 309 4.0 249 4.5 215 5.0 191 LX2 2V/DIV VOUT 2V/DIV EN 2V/DIV 400µs/DIV FIGURE 2. ISL9110 START-UP WITH VIN = 4V AND VOUT = 3.3V 2 AN1648.1 July 10, 2012 Application Note 1648 Evaluation Board Schematics J2 VOUT C2 10µF 0805 TP2 2 L1 2.2µH 3 4 J1 TP4 1 2 3 4 C1 10µF 0805 5 HDR4 6 R5 TP5 0 TP6 VOUT LX2 GND PGND MODE LX1 EN PVIN nBAT VIN TP12 TP10 VIN MODE FB PG 12 11 J4 HDR3 1 2 3 TP11 10 J3 HDR3 TP9 VIN EN 9 8 nBAT 7 PG VIN J6 VIN D2 J5 TP13 TP14 R4 1k TP7 HDR2 C3 1µF TP3 1 2 3 TP8 PD VIN 1.8V TO 5.5V U1 ISL9110IRTAZ 1 VOUT 3.3V HDR4 R2 324k FB TP1 1 2 3 4 C4 56pF/50V R1 1.00M D1 HDR2 R3 1k FIGURE 3. ISL9110IRTAEVAL1Z EVALUATION BOARD SCHEMATIC TABLE 5. ISL9110IRTAEVAL1Z EVALUATION BOARD BILL OF MATERIALS ITEM# QTY DESIGNATORS PART TYPE FOOTPRINT DESCRIPTION VENDORS 1 1 U1 ISL9110IRTAZ L12.3x3C TQFN Intersil ISL9110 Buck-Boost Regulator with Adjustable Output Voltage INTERSIL 2 1 L1 2.2µH 5x5x1.4 NRS5020T2R2 TAIYO YUDEN 3 2 C1, C2 10µF/10V/X5R 0805 LMK212BJ106KG TAIYO YUDEN 4 1 C3 1µF/10V/X5R 0603 LMK107BJ105KK TAIYO YUDEN 5 1 C4 56pF/50V 0603 Capacitor, Generic ANY 6 1 R1 1MΩ, 1% 0603 Resistor, Generic ANY 7 1 R2 324kΩ, 1% 0603 Resistor, Generic ANY 8 2 R3, R4 1kΩ 0603 Resistor, Generic ANY 9 1 R5 0Ω 0603 Resistor, Generic ANY 10 2 D1, D2 LED, RED 1.6x0.8 LED, RED, SMD ANY 11 2 J1, J2 HDR-4 HDR-4 Vert. Pin Header, 4-Pin, 0.1” Spacing, Generic ANY 12 2 J3, J4 HDR-3 HDR-3 Vert. Pin Header, 3-Pin, 0.1” Spacing, Generic ANY 13 2 J5, J6 HDR-2 HDR-2 Vert. Pin Header, 2-Pin, 0.1” Spacing, Generic ANY 14 14 TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP9, TP10, TP11, TP12, TP13, TP14 TEST POINT TEST POINT Test Point, Thru-Hole, White, Mouser 534-5002 KEYSTONE 3 AN1648.1 July 10, 2012 Application Note 1648 Evaluation Board Schematics (continued) J2 VOUT C2 10µF 0805 2 L1 2.2µH VIN 1.8V TO 5.5V J1 TP4 1 2 3 4 C1 10µF 0805 3 4 5 R5 TP5 0 TP6 MODE FB LX2 GND PGND MODE LX1 EN PVIN nBAT VIN PG VIN J4 HDR3 1 2 3 VIN J3 HDR3 1 2 3 TP10 12 TP11 11 10 TP9 EN 9 8 nBAT 7 PG VIN TP8 PD HDR4 6 VOUT TP12 FB TP1 TP2 J6 D2 R4 HDR2 1k J5 D1 R3 VIN TP7 C3 1µF TP3 VOUT 3.3V HDR4 R2 OPEN U1 ISL9110IRTNZ 1 1 2 3 4 C4 OPEN R1 0 TP13 TP14 HDR2 1k FIGURE 4. ISL9110IRTNEVAL1Z EVALUATION BOARD SCHEMATIC TABLE 6. ISL9110IRTNEVAL1Z EVALUATION BOARD BILL OF MATERIALS ITEM# QTY DESIGNATORS PART TYPE FOOTPRINT DESCRIPTION VENDORS 1 1 U1 ISL9110IRTAZ L12.3x3C TQFN Intersil ISL9110 Buck-Boost Regulator with Adjustable Output Voltage INTERSIL 2 1 L1 2.2µH 5x5x1.4 NRS5020T2R2 TAIYO YUDEN 3 2 C1, C2 10µF/10V/X5R 0805 LMK212BJ106KG TAIYO YUDEN 4 1 C3 1µF/10V/X5R 0603 LMK107BJ105KK TAIYO YUDEN 5 1 C4 OPEN 0603 Not installed 6 1 R1 0Ω 0603 Resistor, Generic 7 1 R2 OPEN 0603 Not installed 8 2 R3, R4 1kΩ 0603 Resistor, Generic ANY 9 1 R5 0Ω 0603 Resistor, Generic ANY 10 2 D1, D2 LED, RED 1.6x0.8 LED, RED, SMD ANY 11 2 J1, J2 HDR-4 HDR-4 Vert. Pin Header, 4-Pin, 0.1” Spacing, Generic ANY 12 2 J3, J4 HDR-3 HDR-3 Vert. Pin Header, 3-Pin, 0.1” Spacing, Generic ANY 13 2 J5, J6 HDR-2 HDR-2 Vert. Pin Header, 2-Pin, 0.1” Spacing, Generic ANY 14 16 TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP9, TP10, TP11, TP12, TP13, TP14 TEST POINT TEST POINT Test Point, Thru-Hole, White, Mouser 534-5002 KEYSTONE 4 ANY AN1648.1 July 10, 2012 Application Note 1648 Evaluation Board Schematics (continued) J2 1 2 3 4 VOUT C4 OPEN R1 0 C2 10µF 0805 HDR4 R2 OPEN TP1 TP2 2 L1 2.2µH VIN 1.8V TO 5.5V J1 TP4 1 2 3 4 C1 10µF 0805 3 4 5 TP5 MODE FB LX2 GND PGND MODE LX1 EN PVIN nBAT VIN PG 0 TP6 VIN J4 HDR3 1 2 3 VIN J3 HDR3 1 2 3 TP10 12 TP11 11 10 TP9 9 EN 8 nBAT 7 PG TP8 PD HDR4 6 R5 VOUT TP12 FB U1 ISL9110IRT7Z 1 VOUT 5.0V VIN J6 VIN TP7 C3 1µF TP13 TP14 R4 1k HDR2 J5 TP3 D2 D1 HDR2 R3 1k FIGURE 5. ISL9110IRT7EVAL1Z EVALUATION BOARD SCHEMATIC TABLE 7. ISL9110IRT7EVAL1Z EVALUATION BOARD BILL OF MATERIALS ITEM# QTY DESIGNATORS PART TYPE FOOTPRINT DESCRIPTION VENDORS 1 1 U1 ISL9110IRTAZ L12.3x3C TQFN Intersil ISL9110 Buck-Boost Regulator with Adjustable Output Voltage INTERSIL 2 1 L1 2.2µH 5x5x1.4 NRS5020T2R2 TAIYO YUDEN 3 2 C1, C2 10µF/10V/X5R 0805 LMK212BJ106KG TAIYO YUDEN 4 1 C3 1µF/10V/X5R 0603 LMK107BJ105KK TAIYO YUDEN 5 1 C4 OPEN 0603 Not installed 6 1 R1 0Ω 0603 Resistor, Generic 7 1 R2 OPEN 0603 Not installed 8 2 R3, R4 1kΩ 0603 Resistor, Generic ANY 9 1 R5 0Ω 0603 Resistor, Generic ANY 10 2 D1, D2 LED, RED 1.6x0.8 LED, RED, SMD ANY 11 2 J1, J2 HDR-4 HDR-4 Vert. Pin Header, 4-Pin, 0.1” Spacing, Generic ANY 12 2 J3, J4 HDR-3 HDR-3 Vert. Pin Header, 3-Pin, 0.1” Spacing, Generic ANY 13 2 J5, J6 HDR-2 HDR-2 Vert. Pin Header, 2-Pin, 0.1” Spacing, Generic ANY 14 16 TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP9, TP10, TP11, TP12, TP13, TP14 TEST POINT TEST POINT Test Point, Thru-Hole, White, Mouser 534-5002 KEYSTONE 5 ANY AN1648.1 July 10, 2012 Application Note 1648 Evaluation Board Layout FIGURE 6. ISL9110 EVALUATION BOARD SILKSCREEN TOP FIGURE 7. ISL9110 EVALUATION BOARD TOP COPPER 6 AN1648.1 July 10, 2012 Application Note 1648 Evaluation Board Layout (Continued) FIGURE 8. ISL9110 EVALUATION BOARD MID LAYER 1 (GND) FIGURE 9. ISL9110 EVALUATION BOARD MID LAYER 2 (VIN AND VOUT) 7 AN1648.1 July 10, 2012 Application Note 1648 Evaluation Board Layout (Continued) FIGURE 10. ISL9110 EVALUATION BOARD BOTTOM LAYER (GND) Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 8 AN1648.1 July 10, 2012