EL7457 Data Sheet January 26, 2012 40MHz Non-Inverting Quad CMOS Driver Features The EL7457 is a high speed, non-inverting, quad CMOS driver. It is capable of running at clock rates up to 40MHz and features 2A peak drive capability and a nominal on-resistance of just 3Ω. The EL7457 is ideal for driving highly capacitive loads, such as storage and vertical clocks in CCD applications. It is also well suited to ATE pin driving, level-shifting, and clock-driving applications. • Clocking speeds up to 40MHz The EL7457 is capable of running from single or dual power supplies while using ground referenced inputs. Each output can be switched to either the high (VH) or low (VL) supply pins, depending on the related input pin. The inputs are compatible with both 3V and 5V CMOS and TTL logic. The output enable (OE) pin can be used to put the outputs into a high-impedance state. This is especially useful in CCD applications, where the driver should be disabled during power down. • Low quiescent current - <1mA The EL7457 also features very fast rise and fall times which are matched to within 1ns. The propagation delay is also matched between rising and falling edges to within 2ns. The EL7457 is available in 16-pin QSOP, 16-pin SO (0.150"), and 16-pin QFN packages. All are specified for operation over the full -40°C to +85°C temperature range. FN7288.4 • 4 channels • 12ns tR/tF at 1000pF CLOAD • 1ns rise and fall time match • 1.5ns prop delay match • Fast output enable function - 12ns • Wide output voltage range • 8V ≥ VL ≥ -5V • -2V ≤ VH ≤ 16.5V • 2A peak drive • 3Ω on resistance • Input level shifters • TTL/CMOS input-compatible • Pb-free (RoHS compliant) Applications • CCD drivers Pinouts • Digital cameras 3 INB OUTB 14 VL 2 NC 13 VL 3 5 GND VH 12 GND 4 6 NC OUTC 11 7 INC OUTD 10 8 IND VS- 9 • Ultrasound transducer drivers • Ultrasonic and RF generators 12 OUTB • Level shifting 11 VH THERMAL PAD* 10 VH 9 OUTC INC 5 4 VL • Clock/line drivers 13 OUTA INB 1 • Pin drivers OUTD 8 OUTA 15 VS- 7 2 OE IND 6 VS+ 16 14 VS+ 16 OE 1 INA 15 INA EL7457 [16-PIN QFN (4X4MM)] TOP VIEW EL7457 [16-PIN SO (0.150”), QSOP (0.150”)] TOP VIEW * THERMAL PAD CONNECTED TO PIN 7 (VS-) 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2002-2005, 2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. EL7457 Ordering Information PART NUMBER (Notes 2, 3) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # EL7457CUZ 7457CUZ -40°C to +85°C 16 Ld QSOP (0.150”) MDP0040 EL7457CUZ-T13 (Note 1) 7457CUZ -40°C to +85°C 16 Ld QSOP (0.150”) MDP0040 EL7457CUZ-T7 (Note 1) 7457CUZ -40°C to +85°C 16 Ld QSOP (0.150”) MDP0040 EL7457CUZ-T7A (Note 1) 7457CUZ -40°C to +85°C 16 Ld QSOP (0.150”) MDP0040 EL7457CSZ EL7457CSZ -40°C to +85°C 16 Ld SO (0.150”) MDP0027 EL7457CSZ-T13 (Note 1) EL7457CSZ -40°C to +85°C 16 Ld SO (0.150”) MDP0027 EL7457CSZ-T7 (Note 1) EL7457CSZ -40°C to +85°C 16 Ld SO (0.150”) MDP0027 EL7457CSZ-T7A (Note 1) EL7457CSZ -40°C to +85°C 16 Ld SO (0.150”) MDP0027 EL7457CLZ 7457CLZ -40°C to +85°C 16 Ld QFN (4x4mm) L16.4X4H EL7457CLZ-T13 (Note 1) 7457CLZ -40°C to +85°C 16 Ld QFN (4x4mm) L16.4X4H EL7457CLZ-T7 (Note 1) 7457CLZ -40°C to +85°C 16 Ld QFN (4x4mm) L16.4X4H EL7457CLZ-T7A (Note 1) 7457CLZ -40°C to +85°C 16 Ld QFN (4x4mm) L16.4X4H NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for EL7457. For more information on MSL please see tech brief TB363. 2 FN7288.4 January 26, 2012 EL7457 Absolute Maximum Ratings (TA = 25°C) Thermal Information Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.3V, VS+ +0.3V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Thermal Resistance θJA (°C/W) θJC (°C/W) 16 Ld QFN (Notes 4, 5) . . . . . . . . . . . . 43 5 16 Ld SOIC (Notes 6, 7). . . . . . . . . . . . 73 45 16 Ld QSOP (Note 6). . . . . . . . . . . . . . 112 N/A Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 6. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 7. For θJC, the “case temp” location is taken at the package top center. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, VH = +5V, VL = -5V, TA = 25°C, unless otherwise specified. DESCRIPTION CONDITION MIN (Note 8) TYP MAX (Note 8) UNIT INPUT VIH Logic “1” Input Voltage 2.0 IIH Logic “1” Input Current VIL Logic “0” Input Voltage IIL Logic “0” Input Current CIN Input Capacitance 3.5 pF RIN Input Resistance 50 MΩ VIH = 5V VIL = 0V V 0.1 0.1 10 µA 0.8 V 10 µA OUTPUT ROH ON Resistance VH to OUTx IOUT = -100mA 4.5 6 Ω ROL ON Resistance VL to OUTx IOUT = +100mA 4 6 Ω ILEAK Output Leakage Current VH = VS+, VL = VS- 0.1 10 µA IPK Peak Output Current Source 2.0 A Sink 2.0 A Inputs = VS+ 0.5 POWER SUPPLY IS Power Supply Current 1.5 mA SWITCHING CHARACTERISTICS tR Rise Time CL = 1000pF 13.5 ns tF Fall Time CL = 1000pF 13 ns tRFΔ tR, tF Mismatch CL = 1000pF 0.5 ns tD+ Turn-Off Delay Time CL = 1000pF 12.5 ns tD- Turn-On Delay Time CL = 1000pF 14.5 ns tDD tD-1 - tD-2 Mismatch CL = 1000pF 2 ns tENABLE Enable Delay Time 12 ns 3 FN7288.4 January 26, 2012 EL7457 Electrical Specifications PARAMETER tDISABLE VS+ = +5V, VS- = -5V, VH = +5V, VL = -5V, TA = 25°C, unless otherwise specified. DESCRIPTION CONDITION MIN (Note 8) TYP Disable Delay Time Electrical Specifications PARAMETER MAX (Note 8) 12 UNIT ns VS+ = +15V, VS- = 0V, VH = +15V, VL = 0V, TA = 25°C, unless otherwise specified DESCRIPTION CONDITION MIN (Note 8) TYP MAX (Note 8) UNIT INPUT VIH Logic “1” Input Voltage 2.4 V IIH Logic “1” Input Current VIL Logic “0” Input Voltage IIL Logic “0” Input Current CIN Input Capacitance 3.5 pF RIN Input Resistance 50 MΩ VIH = 5V 0.1 VIL = 0V 0.1 10 µA 0.8 V 10 µA OUTPUT ROH ON Resistance VH to OUT IOUT = -100mA 3.5 5 Ω ROL ON Resistance VL to OUT IOUT = +100mA 3 5 Ω ILEAK Output Leakage Current VH = VS+, VL = VS- 0.1 10 µA IPK Peak Output Current Source 2.0 A Sink 2.0 A Inputs = VS+ 0.8 POWER SUPPLY IS Power Supply Current 2 mA SWITCHING CHARACTERISTICS tR Rise Time CL = 1000pF 11 ns tF Fall Time CL = 1000pF 12 ns tRFΔ tR, tF Mismatch CL = 1000pF 1 ns tD + Turn-Off Delay Time CL = 1000pF 11.5 ns tD - Turn-On Delay Time CL = 1000pF 13 ns tDD tD-1 - tD-2 Mismatch CL = 1000pF 1.5 ns tENABLE Enable Delay Time 12 ns tDISABLE Disable Delay Time 12 ns NOTE: 8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 4 FN7288.4 January 26, 2012 EL7457 Typical Performance Curves 1.8 2 HIGH LIMIT=2.4V T=25°C 1.6 HYSTERESIS 1.4 1.2 SUPPLY CURRENT (V) INPUT VOLTAGE (V) T=25°C ALL INPUTS=0 1.6 1.2 0.8 0.4 ALL INPUTS=VS+ LOW LIMIT=0.8V 0 1 5 7 10 12 5 15 7 10 12 15 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) FIGURE 1. SWITCH THRESHOLD vs SUPPLY VOLTAGE FIGURE 2. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE 9 25 RISE/FALL TIME (ns) “ON” RESISTANCE (Ω) IOUT=100mA 8 T=25°C 7 6 VH TO OUT 5 VL TO OUT 4 tR 20 tF 15 10 3 CL=1000pF T=25°C 2 5 5 7 10 12 15 5 7 SUPPLY VOLTAGE (V) 12 15 SUPPLY VOLTAGE (V) FIGURE 3. “ON” RESISTANCE vs SUPPLY VOLTAGE FIGURE 4. RISE/FALL TIME vs SUPPLY VOLTAGE 16 25 CL=1000pF VS+=15V CL=1000pF 14 12 DELAY TIME (ns) RISE/FALL TIME (ns) 10 tF 10 tR tD2 15 tD1 10 8 6 -50 20 5 -25 0 25 50 75 100 125 TEMPERATURE (°C) FIGURE 5. RISE/FALL TIME vs TEMPERATURE 5 5 7 10 12 15 SUPPLY VOLTAGE (V) FIGURE 6. PROPAGATION DELAY vs SUPPLY VOLTAGE FN7288.4 January 26, 2012 EL7457 Typical Performance Curves (Continued) 18 VS+=15V 120 14 RISE/FALL TIME (ns) DELAY TIME (ns) 16 140 CL=1000pF VS+=15V tD2 12 tD1 10 100 8 6 -50 80 60 tF 40 tR 20 -25 0 25 50 75 100 0 100 125 470 TEMPERATURE (°C) 1K 2.2K 4.7K 10K LOAD CAPACITANCE (pF) FIGURE 7. PROPAGATION DELAY vs TEMPERATURE FIGURE 8. RISE/FALL TIME vs LOAD SUPPLY CURRENT (mA) 12 VS+=VH=10V VS-=VL=0V 10 f=100kHz 8 6 4 2 0 100 1K 10K LOAD CAPACITANCE (pF) FIGURE 9. SUPPLY CURRENT PER CHANNEL vs CAPACITIVE LOAD 6 FN7288.4 January 26, 2012 EL7457 Timing Diagram TABLE 1. NOMINAL OPERATING VOLTAGE RANGE PIN MIN MAX VS+ to VS- 5V 16.5V VS- to GND -5V 0V VH VS- + 2.5V VS+ VL VS- VS+ VH to VL 0V 16.5V VL to VS- 0V 8V 5V INPUT 2.5V 0 OUTPUT 90% 10% t D+ tDtR tF Standard Test Configuration (CS/CU) VS+ 0.1µF 4.7µF VS+ 10kΩ 1 INA 16 OUTA 1000pF EN INB 2 15 3 14 OUTB 1000pF VL 4.7µF 4 13 0.1µF 0.1µF 5 12 6 11 VH 4.7µF OUTC 1000pF INC 7 10 IND 8 9 OUTD 1000pF VS0.1µF 7 4.7µF FN7288.4 January 26, 2012 EL7457 Pin Descriptions 16-PIN QSOP (0.150”), SO (0.150”) 16-PIN QFN (4x4mm) NAME 1 15 INA FUNCTION EQUIVALENT CIRCUIT Input channel A VS+ VS+ INPUT VS- VS- CIRCUIT 1 2 16 OE Output Enable (Reference Circuit 1) 3 1 INB Input channel B (Reference Circuit 1) 4 2, 3 VL Low voltage input pin 5 4 GND 6, 13 Input logic ground NC No connection 7 5 INC Input channel C (Reference Circuit 1) 8 6 IND Input channel D (Reference Circuit 1) 9 7 VS- Negative supply voltage 10 8 OUTD Output channel D VH VS+ OUTPUT VSVSVL CIRCUIT 2 11 9 OUTC 12 10, 11 VH 14 12 OUTB Output channel B (Reference Circuit 2) 15 13 OUTA Output channel A (Reference Circuit 2) 16 14 VS+ 8 Output channel C (Reference Circuit 2) High voltage input pin Positive supply voltage FN7288.4 January 26, 2012 EL7457 Block Diagram OE VH VS+ INPUT GND LEVEL SHIFTER 3-STATE CONTROL OUTPUT VSVL Applications Information Product Description The EL7457 is a high performance 40MHz high speed quad driver. Each channel of the EL7457 consists of a single P-channel high side driver and a single N-channel low side driver. These 3Ω devices will pull the output (OUTX) to either the high or low voltage, on VH and VL respectively, depending on the input logic signal (INX). It should be noted that there is only one set of high and low voltage pins. A common output enable (OE) pin is available on the EL7457. This pin, when pulled low will put all outputs in to the high impedance state. The EL7457 is available in 16-pin SO (0.150"), 16-pin QSOP, and ultra-small 16-pin QFN packages. The relevant package should be chosen depending on the calculated power dissipation. Supply Voltage Range and Input Compatibility The EL7457 is designed for operation on supplies from 5V to 15V with 10% tolerance (i.e. 4.5V to 18V). The table on page 6 shows the specifications for the relationship between the VS+, VS-, VH, VL, and GND pins. The EL7457 does not contain a true analog switch and therefore VL should always be less than VH. All input pins are compatible with both 3V and 5V CMOS signals With a positive supply (VS+) of 5V, the EL7457 is also compatible with TTL inputs. Power Supply Bypassing When using the EL7457, it is very important to use adequate power supply bypassing. The high switching currents developed by the EL7457 necessitate the use of a bypass capacitor on both the positive and negative supplies. It is recommended that a 4.7µF tantalum capacitor be used in parallel with a 0.1µF low-inductance ceramic MLC capacitor. These should be placed as close to the supply pins as possible. It is also recommended that the VH and VL pins have some level of bypassing, especially if the EL7457 is driving highly capacitive loads. 9 Power Dissipation Calculation When switching at high speeds, or driving heavy loads, the EL7457 drive capability is limited by the rise in die temperature brought about by internal power dissipation. For reliable operation die temperature must be kept below TJMAX (125°C). It is necessary to calculate the power dissipation for a given application prior to selecting package type. Power dissipation may be calculated: 4 PD = ( V S × I S ) + 2 2 × f) ∑ ( CINT × VS × f ) + ( CL × VOUT (EQ. 1) 1 where: VS is the total power supply to the EL7457 (from VS+ to VS-) VOUT is the swing on the output (VH - VL) CL is the load capacitance CINT is the internal load capacitance (80pF max) IS is the quiescent supply current (3mA max) f is frequency Having obtained the application’s power dissipation, the maximum junction temperature can be calculated: T JMAX = T MAX + Θ JA × PD (EQ. 2) where: TJMAX is the maximum junction temperature (125°C) TMAX is the maximum ambient operating temperature PD is the power dissipation calculated above θJA is the thermal resistance, junction to ambient, of the application (package + PCB combination). Refer to the Package Power Dissipation curves on page 6. FN7288.4 January 26, 2012 EL7457 Quarter Size Outline Plastic Packages Family (QSOP) MDP0040 A QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY D (N/2)+1 N INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES E PIN #1 I.D. MARK E1 1 (N/2) A 0.068 0.068 0.068 Max. - A1 0.006 0.006 0.006 ±0.002 - A2 0.056 0.056 0.056 ±0.004 - b 0.010 0.010 0.010 ±0.002 - c 0.008 0.008 0.008 ±0.001 - D 0.193 0.341 0.390 ±0.004 1, 3 E 0.236 0.236 0.236 ±0.008 - E1 0.154 0.154 0.154 ±0.004 2, 3 e 0.025 0.025 0.025 Basic - L 0.025 0.025 0.025 ±0.009 - L1 0.041 0.041 0.041 Basic - N 16 24 28 Reference - B 0.010 C A B e H C SEATING PLANE 0.007 0.004 C b C A B Rev. F 2/07 NOTES: L1 A 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. c SEE DETAIL "X" 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 0.010 A2 GAUGE PLANE L A1 4°±4° DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 FN7288.4 January 26, 2012 EL7457 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 11 FN7288.4 January 26, 2012 EL7457 Package Outline Drawing L16.4x4H 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 1/12 2.40 4X 1.95 4.00 12X 0.65 A B 13 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 16 1 4.00 12 2.40 9 4 (4X) 0.15 5 8 0.10 M C A B 16x 0.550±0.05 TOP VIEW BOTTOM VIEW 4 0.30 ±0.05 SEE DETAIL "X" 0.90±0.10 0.10 C C BASE PLANE SEATING PLANE ( 3 . 6 TYP ) SIDE VIEW ( (12x0.65) 2.40) (16x0.30) C 0 . 20 REF 5 (16x0.75) +0.03/-0.02 TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 12 FN7288.4 January 26, 2012