EL7155CSZ - Intersil

DATASHEET
High Performance Pin Driver
EL7155
Features
The EL7155 high performance pin driver with 3-state is suited
to many ATE and level-shifting applications. The 3.5A peak
drive capability makes this part an excellent choice when
driving high capacitance loads.
• Clocking speeds up to 40MHz
• 15ns tr/tf at 2000pF CLOAD
• 0.5ns rise and fall times mismatch
• 0.5ns tON-tOFF prop delay mismatch
• 3.5pF typical input capacitance
Output pins OUTH and OUTL are connected to input pins VH and
VL respectively, depending on the status of the IN pin. One of
the output pins is always in tri-state, except when the OE pin is
low, in which case both outputs are in tri-state mode. The
isolation of the output FETs from the power supplies enables
VH and VL to be set independently, enabling level-shifting to be
implemented.
• 3.5A peak drive
• Low ON-resistance of 3.5Ω
• High capacitive drive capability
• Operates from 4.5V up to 16.5V
This pin driver has improved performance over existing pin
drivers. It is specifically designed to operate at voltages down
to 0V across the switch elements while maintaining good
speed and ON-resistance characteristics.
• Pb-free (RoHS compliant)
Applications
• ATE/burn-in testers
Available in an 8 Ld SOIC package, the EL7155 is specified for
operation over the full -40°C to +85°C temperature range.
• Level shifting
• IGBT drivers
• CCD drivers
VH
OE
VS+
IN
LEVEL
SHIFTER
3-STATE
CONTROL
GND
OUTH
OUTL
VL
FIGURE 1. BLOCK DIAGRAM
October 24, 2014
FN7279.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas LLC 2003, 2005-2006, 2014. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
EL7155
Pin Configuration
Ordering Information
EL7155
(8 LD SOIC)
TOP VIEW
VS+
1
OE
2
IN
3
GND
4
L
O
G
I
C
PART NUMBER
(Notes 1, 2)
FUNCTION
1
VS+
Positive Supply
Voltage
2
OE
Output Enable
PACKAGE
(Pb-Free)
PKG.
DWG. #
EL7155CSZ
7155CSZ
8 Ld SOIC
M8.15E
EL7155CSZ-T7
(Note 3)
7155CSZ
8 Ld SOIC
M8.15E
OUTH
8 Ld SOIC
M8.15E
OUTL
EL7155CSZ-T7A
(Note 3)
7155CSZ
6
5
VL
EL7155CSZ-T13
(Note 3)
7155CSZ
8 Ld SOIC
M8.15E
8
VH
7
NOTE:
1. Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pin Descriptions
PIN PIN
# NAME
PART
MARKING
EQUIVALENT CIRCUIT
2. For Moisture Sensitivity Level (MSL), please see product information
page for EL7155. For more information on MSL, please see tech brief
TB363.
VS+
3. Please refer to TB347 for details on reel specifications.
INPUT
VL
Circuit 1
3
IN
4
GND
5
VL
6
Input
Reference Circuit 1
Ground
Negative Supply
and Lower
Output Voltage
OUTL Lower Switch
Output
VS+
OUTL
VL
Circuit 2
7
OUTH Upper Switch
Output
VH
VS+
VL
OUTH
VL
Circuit 3
8
VH
Upper Output
Voltage
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FN7279.3
October 24, 2014
EL7155
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage (VS+ to VL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +18V
VH-VL, VH to GND, VS+ to VH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . -0.3V below VL to +0.3V above VS
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
Electrical Specifications
VS+ = +15V, VH = +15V, VL = 0V, TA = +25°C, all tests are at the specified temperature and are pulsed tests,
therefore: TJ = TC = TA, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 4)
TYP
(Note 5)
MAX
(Note 4)
UNITS
INPUT
VIH
Logic ‘1’ Input Voltage
IIH
Logic ‘1’ Input Current
VIL
Logic ‘0’ Input Voltage
IIL
Logic ‘0’ Input Current
CIN
Input Capacitance
3.5
pF
RIN
Input Resistance
50
MΩ
2.4
VIH = VS+
V
0.1
VIL = 0V
0.1
10
µA
0.8
V
10
µA
OUTPUT
ROVH
ON-Resistance VH to OUTH
IOUT = -200mA
2.7
4.5
Ω
ROVL
ON-Resistance VL to OUTL
IOUT = +200mA
3.5
5.5
Ω
IOUT
Output Leakage Current
OE = 0V, OUTH = VL, OUTL = VS+
0.1
10
µA
IPK
Peak Output Current
(linear resistive operation)
Source
3.5
A
Sink
3.5
A
Continuous Output Current
Source/Sink
IDC
200
mA
POWER SUPPLY
IS
Power Supply Current
Inputs = VS+
IVH
Off Leakage at VH
VH = 0V
1.3
3
mA
4
10
µA
SWITCHING CHARACTERISTICS
tR
Rise Time
CL = 2000pF
14.5
ns
tF
Fall Time
CL = 2000pF
15
ns
tRF
tR, tF Mismatch
CL = 2000pF
0.5
ns
tD-1
Turn-Off Delay Time
CL = 2000pF
9.5
ns
tD-2
Turn-On Delay Time
CL = 2000pF
10
ns
tD
tD-1 - tD-2 Mismatch
CL = 2000pF
0.5
ns
tD-3
3-state Delay Enable
10
ns
tD-4
3-state Delay Disable
10
ns
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EL7155
Electrical Specifications
PARAMETER
VS+ = +5V, VH = +5V, VL = -5V, TA = +25°C, all tests are at the specified temperature and are pulsed tests,
therefore: TJ = TC = TA, unless otherwise specified.
DESCRIPTION
CONDITION
MIN
(Note 4)
TYP
(Note 5)
MAX
(Note 4)
UNIT
INPUT
VIH
Logic ‘1’ Input Voltage
IIH
Logic ‘1’ Input Current
VIL
Logic ‘0’ Input Voltage
IIL
Logic ‘0’ Input Current
CIN
Input Capacitance
3.5
pF
RIN
Input Resistance
50
MΩ
2.0
VIH = VS+
V
0.1
VIL = 0V
0.1
10
µA
0.8
V
10
µA
OUTPUT
ROVH
ON-Resistance VH to OUTH
IOUT = -200mA
3.4
5
Ω
ROVL
ON-Resistance VL to OUTL
IOUT = +200mA
4
6
Ω
IOUT
Output Leakage Current
OE = 0V, OUTH = VL, OUTL = VS+
0.1
10
µA
IPK
Peak Output Current
(linear resistive operation)
Source
3.5
A
Sink
3.5
A
Continuous Output Current
Source/Sink
IDC
200
mA
POWER SUPPLY
IS
Power Supply Current
Inputs = VS+
1
2.5
mA
IVH
Off Leakage at VH
VH = 0V
4
10
µA
SWITCHING CHARACTERISTICS
tR
Rise Time
CL = 2000pF
17
ns
tF
Fall Time
CL = 2000pF
17
ns
tRF
tR, tF Mismatch
CL = 2000pF
0
ns
tD-1
Turn-Off Delay Time
CL = 2000pF
11.5
ns
tD-2
Turn-On Delay Time
CL = 2000pF
12
ns
tD
tD-1 - tD-2 Mismatch
CL = 2000pF
0.5
ns
tD-3
3-state Delay Enable
11
ns
tD-4
3-state Delay Disable
11
ns
NOTES:
4. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
5. Typical values are for information purposes only.
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EL7155
Typical Performance Curves
1.8
Max TJ = +125°C
1.0
0.6
INPUT VOLTAGE (V)
POWER DISSIPATION (W)
HIGH THRESHOLD
1.6
0.8
SO8
0.4
JA = 160°C/W
HYSTERESIS
1.4
1.2
LOW THRESHOLD
0.2
0
1.0
0
25
50
75
85 100
125
150
5
10
AMBIENT TEMPERATURE (°C)
FIGURE 2. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE JEDEC JESD51-3 LOW EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
FIGURE 3. INPUT THRESHOLD vs SUPPLY VOLTAGE, T = 25°C
2.0
6
ON-RESISTANCE (Ω)
SUPPLY CURRENT (mA)
VOUT - VL
5
1.6
ALL INPUTS = GND
1.2
0.8
4
3
ALL INPUTS = VS+
0.4
VOUT - VH
2
1
0
0
5
10
15
5.0
7.5
SUPPLY VOLTAGE (V)
10.0
12.5
15.0
SUPPLY VOLTAGE (V)
FIGURE 4. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE,
T = +25°C
FIGURE 5. ON-RESISTANCE vs SUPPLY VOLTAGE, IOUT = 200mA,
T = +25°C, VS+ = VH, VL = 0V
30
20
18
RISE/FALL TIME (ns)
25
RISE/FALL TIME (ns)
15
SUPPLY VOLTAGE (V)
tR
20
tF
tF
15
tF
16
14
tR
12
tR
10
5
10
SUPPLY VOLTAGE (V)
FIGURE 6. RISE/FALL TIME vs SUPPLY VOLTAGE
CL = 2000pF, T = +25°C
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5
15
10
-50
0
50
100
150
TEMPERATURE (°C)
FIGURE 7. RISE/FALL TIME vs TEMPERATURE
CL = 2000PF, VS+ = 15V
FN7279.3
October 24, 2014
EL7155
Typical Performance Curves (Continued)
14
17
12
tD-2
13
tD-1
11
tD-2
DELAY TIME (ns)
DELAY TIME (ns)
15
10
tD-1
8
9
5
6
-50
15
10
-25
0
SUPPLY VOLTAGE (V)
25
50
75
100
125
TEMPERATURE (°C)
FIGURE 8. PROPAGATION DELAY vs SUPPLY VOLTAGE
CL = 2000pF, T = +25°C
FIGURE 9. PROPAGATION DELAY vs TEMPERATURE
CL = 2000pF, VS+ = 15V
5
70
60
SUPPLY CURRENT (mA)
RISE/FALL TIME (ns)
4
50
40
tF
30
20
3
2
1
tR
10
0
100
1000
0
100
10000
1000
LOAD CAPACITANCE (pF)
10000
LOAD CAPACITANCE (pF)
FIGURE 10. RISE/FALL TIME vs LOAD CAPACITANCE
VS+ = +15V, T = +25°C
FIGURE 11. SUPPLY CURRENT vs LOAD CAPACITANCE,
VS+ = VH = 15V, VL = 0V, T = +25°C, f = 20kHz
SUPPLY CURRENT (mA)
100
10
VS+ = 15V
VS+ = 10V
1.0
VS+ = 5V
0.1
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 12. SUPPLY CURRENT vs FREQUENCY, CL = 1000pF, T = +25°C
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EL7155
TABLE 1. TRUTH TABLE
TABLE 2. OPERATING VOLTAGE RANGE
OE
IN
VH to OUTH
OUTL to VL
PIN
MIN (V)
MAX (V)
0
0
Open
Open
VL - GND
-5
0
0
1
Open
Open
VS+ - VL
5
16.5
1
0
Closed
Open
V H - VL
0
16.5
1
1
Open
Closed
VS+ - VH
0
16.5
VS+ - GND
5
16.5
3-State Output
VL
VH
TimingDiagrams
5V
INPUT
2.5V
0
90%
INVERTED
OUTPUT
10%
tD1
tD2
tF
tR
Standard Test Configuration
VS+
VH
1
10k
0.1µ
0.1µ
2
OE
IN
3
4.7µ
7
LOGIC
4.7µ
VS+
8
OUT
6
2000p
GND
4
5
-
EL7155
0.1µ
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7
VL
4.7µ
FN7279.3
October 24, 2014
EL7155
Applications Information
Product Description
The EL7155 is a high performance 40MHz pin driver. It contains
two analog switches connecting VH to OUTH and VL to OUTL.
Depending on the value of the IN pin, one of the two switches will
be closed and the other switch open. An output enable (OE) is
also supplied, which opens both switches simultaneously.
Due to the topology of the EL7155, VL should always be
connected to a voltage equal to or lower than GND. VH can be
connected to any voltage between VL and the positive supply,
VS+.
Power Dissipation Calculation
When switching at high speeds, or driving heavy loads, the
EL7155 drive capability is limited by the rise in die temperature
brought about by internal power dissipation. For reliable
operation die temperature must be kept below TJMAX (+125°C).
It is necessary to calculate the power dissipation for a given
application prior to selecting the package type.
Power dissipation may be calculated:
2
2
PD =  V S  I S  +  C INT  V S  f  +  C L  V OUT  f 
(EQ. 1)
where:
The EL7155 is available in the 8 Ld SOIC package. Application
dependent power dissipation should be calculated to ensure that
the maximum junction temperature isn’t violated.
VS is the total power supply to the EL7155 (from VS+ to GND)
3-state Operation
CINT is the internal load capacitance (100pF max)
When the OE pin is low, the output is 3-state (floating.) The
disabled output voltage is the parasitic capacitance’s voltage. It
can be any voltage between VH and VL, depending on the
previous state. At 3-state, the output voltage can be driven to any
voltage between VH and VL. The output voltage can’t be driven
higher than VH or lower than VL since the body diode at the
output stage will turn on.
Supply Voltage Range and Input
Compatibility
The EL7155 is designed for operation on supplies from 5V to 15V
(4.5V to 16.5V maximum). Table 2 on page 7 shows the
specifications for the relationship between the VS+, VH, VL, and
GND pins.
All input pins are compatible with both 3V and 5V CMOS signals.
With a positive supply (VS+) of 5V, the EL7155 is also compatible
with TTL inputs.
Power Supply Bypassing
When using the EL7155, it is very important to use adequate
power supply bypassing. The high switching currents developed
by the EL7155 necessitate the use of a bypass capacitor
between the VS+ and GND pins. It is recommended that a 2.2µF
tantalum capacitor be used in parallel with a 0.1µF
low-inductance ceramic MLC capacitor. These should be placed
as close to the supply pins as possible. It is also recommended
that the VH and VL pins have some level of bypassing, especially
if the EL7155 is driving highly capacitive loads.
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VOUT is the swing on the output (VH - VL)
CL is the load capacitance
IS is the quiescent supply current (3mA max)
f is frequency
Having obtained the application’s power dissipation, a maximum
package thermal coefficient may be determined, to maintain the
internal die temperature below TJMAX:
 T JMAX – T MAX 
 JA = ---------------------------------------------PD
(EQ. 2)
where:
TJMAX is the maximum junction temperature (+125°C)
TMAX is the maximum operating temperature
PD is the power dissipation calculated above
JA thermal resistance on junction to ambient
JA is 160°C/W for the SO8 package when using a standard
JEDEC JESD51-3 single-layer test board. If TJMAX is greater than
+125°C when calculated using the Equation 2, then one of the
following actions must be taken:
1. Reduce JA the system by designing more heatsinking into
the PCB (as compared to the standard JEDEC JESD51-3).
2. Derate the application either by reducing the switching
frequency, the capacitive load, or the maximum operating
(ambient) temperature (TMAX).
FN7279.3
October 24, 2014
EL7155
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
October 24, 2014
FN7279.3
Updated datasheet to new Intersil template.
Updated the Ordering Information table on page 2 by removing the obsolete products and adding the -T7A part.
Added revision history and about Intersil.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN7279.3
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EL7155
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
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