TXS25-4 Evaluation Kit User Guide

User’s Guide: TXS25-4 Evaluation Kit
®
Application Note
February 25, 2009
AN1435.0
Complete Amplifier Evaluation System
Selectable DSP Processing Functions
• TXS25-4: 4-Channel Digital Amplifier
• Input Selection (Analog, S/PDIF, I2S/Left-Justified)
• Single Power Supply (+25V) Operation
• Internally Generated Negative Rail High-voltage Supply
(-25V)
• Internally Generated and Regulated Low-voltage Supplies
(+5V/+3.3V/1.8V)
• D2Audio Canvas II™ Installation CD-ROM (includes USB
Driver and D2Audio Canvas II User’s Guide)
• Detachable Digital/Analog Audio/Control I/O and Power
Assembly Boards
• “SCAMP III” Header Pins on Digital/Analog Audio/Control
I/O Board Enables In-system Firmware Upgradeability
• Optical (TOSLINK) and Coax Digital S/PDIF Inputs that
Accept an IEC60958 Compliant Interconnect Carrying
Linear PCM with an Fs of 32kHz~192kHz
• 4 Independent Channels of Audio Processing
- Tone Control
- Matrix Mixing
- Programmable Crossover with Butterworth,
Linkwitz/Riley, Bessel Filter Types
- 5-Band and 3-Band Parametric EQ
- Master Volume Control
- Loudness Contour
- Individual Channel Time Delay
- Per Channel Dynamic Range Compression/Limiting
- Independent Channel Level Controls - Enables
Independent Level Control for Amplified Channels 1, 2,
3 and 4 Outputs as well as Digital Audio Outputs
D2Audio SoundSuite™ Immersive Processing
• Mono2Stereo™
• Optical (TOSLINK) Digital S/PDIF Output
• WideSound™
• 4 Channels of Analog Audio Inputs Using
High-Performance 4-Channel Analog-to-Digital Converter
(ADC)
• DeepBass™
• 2 I2S/Left-Justified Digital Audio Input Headers
The TXS25-4 Evaluation Kit is a complete amplifier
evaluation system for the TXS25-4 digital amplifier module.
Audio system designers can quickly evaluate all of the
features and functions of the TXS25-4 design with this
system.
• 2 I2S/Left-Justified Digital Audio Output Headers
• Rotary Knob Connected to GPIO Lines Enables Simple
Master Volume Control for Channels 1 and 2
• Subwoofer Analog Audio Output (Passive Filtered PWM
Line Level Output)
• High-Quality Speaker Banana-Jack Connectors
D2Audio Canvas II™GUI Simplifies System Design
• Intuitive, “Point-and-click” Audio-Centric User Interface
Simplifies Evaluation of All Audio Processing
Configurations
• Configuration for Stereo, Dual Zone, Stereo Bi-Amp or
Powered 2.1 Systems Takes Less than a Minute
• AudioAlign™
This system offers the ultimate in configurations,
digital/analog I/O and power supply connection. It offers
headers for all digital audio inputs and outputs so that the
system designer can quickly and easily “wire-wrap” into the
board. This enables any I2S/Left-Justified digital audio
source to be delivered from any digital audio source such as
an HDMI™ receiver or a Media Networking Processor and
input into the TXS25-4 amplifier with minimum effort. A
header is also offered for the control communication bus
(2-wire interface), which enables fast connection of a system
microcontroller for rapid prototyping.
The D2Audio Canvas GUI software simplifies system design
with an intuitive, audio-centric user interface with
“point-and-click” options on a Windows™ PC. Organized
processing blocks are included for audio input selection,
Tone Control, Crossovers, Parametric Equalizers, Adjustable
Time Delay, Signal Limiter/Compressor, Volume Control,
Loudness Contour, and Independent Level Control.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Application Note 1435
TXS25-4 Evaluation Kit
• Complete Evaluation Platform for TXS25-4
• 4 Channels of Amplified Speaker Outputs
• 4 Channels of Analog Inputs
• 4 Channels of Digital Audio Inputs
(1 S/PDIF and 2 x I2S/Left-Justified Inputs)
• 4 Channels of Digital Audio Inputs (1 S/PDIF and
2 x I2S/Left-Justified Outputs)
• All necessary voltages are generated from single +25V
power source reducing cost and complexity of the system
power supply
• Internally Regulated Low-voltage supplies
(+5V/+3.3V/1.8V)
• Master Volume Knob (Channels 1 and 2)
2
AN1435.0
February 25, 2009
Application Note 1435
Getting Started
WARNING
This symbol is used to warn operators that uninsulated “dangerous voltages”
are present within this equipment that may impose risk of electrical shock
FIGURE 1. TSX25-4 AMPLIFIER BOARDS
Overview
The TXS25-4 Amplifier evaluation kit consists of 3 boards.
These boards, shown in Figure 1, consist of the main
amplifier board, an input board, and an output board. Each
of these 3 boards are shown in detail in Figures 2, 3, and 4.
Ribbon cables (supplied) interconnect the 3 boards.
The system can be configured either through software (refer
also to D2Audio Canvas II Software Configuration
Documentation found on the D2Audio Canvas II Software
CD) or configured by hardware settings (see “Input Source
Options” on page 17).
Platform Configurations
The TXS25-4 Amplifier kit may be configured as a stereo
amplifier with a single or multiple inputs, and is also capable
of providing a summed and low-pass filtered output which
can then be sent to an external powered subwoofer. The
flexible signal processing flow and extensive digital audio
inputs and outputs of the TXS25-4 also allows for processed
output to be connected (as on this evaluation platform) to an
external DAC to enable post-processed Line-Level Outputs
or Headphone Outputs.
3
AN1435.0
February 25, 2009
Application Note 1435
FIGURE 2. DIGITAL/ANALOG AUDIO/CONTROL I/O BOARD - TOP VIEW
4
AN1435.0
February 25, 2009
Application Note 1435
FIGURE 3. TXS25-4 AMPLIFIER BOARD - TOP VIEW
5
AN1435.0
February 25, 2009
Application Note 1435
FIGURE 4. AMPLIFIER OUTPUT BOARD - TOP VIEW
6
AN1435.0
February 25, 2009
Application Note 1435
Connection Diagram
AUDIO AUDIO AUDIO AUDIO
IN1
IN2
IN3
IN4
Sub Out
AIN4
S/PDIF
COAX
IN
S/PDIF
COAX IN
AIN3
AIN2
AIN1
COAX S/PDIF
Status LED
CHANNEL 3 PWM
SUBWOOFER
OUT
Digital/Analog Audio/Control I/O Board
ERROR
LED
J8
MASTER
VOLUME
J5
J19
S/PDIF
OPTICAL IN
OPT
SCLK0
LRCK0
SDIN0
SCLK1
LRCK1
SDIN1
S/PDIF
OPT
IN
COAX
RESET
J7
J6
OPTICAL S/PDIF
Status LED
USB
USB
+5V
+3.3V
+1.8
GND
J9
MCLKT
SCLKT
LRCKT
SDOUT0
SDOUT1
nRESET
BOOT_EE
nERROR
GPIO0
GPIO1
PSSYNC
S/PDIF
COAX
OUT
S/PDIF
OPTICAL OUT
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
STATUS LEDs:
Load Complete
Load Active
I2C Active
USB Active
J4
J2
D2-814xx IC
TXS25-4 Amplifier Board
+
CHANNEL 4
OUT
12
11
10
9
8
7
6
5
4
3
2
1
J3
12
11
10
9
8
7
6
5
4
3
2
1
J27
+
Amplifier Output Board
-
-
+25V
+25V
GND
GND
+
CHANNEL 3
OUT
J28: +25 VDC
Power Supply
Connection
J28
+
-
CHANNEL 1
OUT
CHANNEL 2
OUT
FIGURE 5. TXS25-4 AMPLIFIER PLATFORM CONNECTION AND JUMPER DIAGRAM
7
AN1435.0
February 25, 2009
Application Note 1435
Required Power Source
6. Connect Speakers
The TXS25-4 Amplifier requires external operating power of
a single DC power supply of 12V (minimum) up to 25V
(maximum), with a minimum current sourcing capability of
5A. Maximum amplifier output power requires 25V, and
maximum output power will be reduced as the DC supply
voltage is also reduced. A well-filtered and regulated power
supply is recommended. Supply voltage filtering, as well as
input surge current limiting is provided on the amplifier
output board where the power supply is connected. However
amplifier noise performance may be impaired from power
sources with excessive output ripple.
- Output Device Connection (Stereo) . . . . . . . . Figure 12
- Output Device Connection (Channel System) Figure 13
7. Turn system on by switching on the DC power supply.
Quick Start
1. Set up in an ESD-approved work area.
2. Power supply must be OFF and power cord disconnected
from AC outlet.
3. Observing correct polarity, connect DC output from a 25V,
5A power supply to connector J28 of the amplifier output
board (Refer to “ Required Power Source” for J28
location and polarity.)
4. Ensure the supplied interconnect ribbon cables are
connected between J4 of the Input Board and J2 of the
TXS25-4 Amplifier board, and also between J3 of the
TXS25-4 Amplifier Board and J27 of the Amplifier Output
Board.
5. Select input source
- Analog Audio Input . . . . . . . . . . . . . . . . . . . . . . Figure 8
- Optical S/PDIF . . . . . . . . . . . . . . . . . . . . . . . . . Figure 9
- Coax S/PDIF . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 10
8
8. Play audio source. Adjust master volume for Channels 1
and 2 using the master volume knob.
Speaker Channel Pair Matching and Drive
Requirements
Each of the TXS25-4 output channels are half-bridge, thus a
load of equal size and content MUST be placed on
corresponding channel pairs (e.g. Channel 1 and 2,
Channel 3 and 4). This means that TXS25-4 is not meant to
drive a 16Ω speaker on Channel 1 with an 8Ω speaker on
Channel 2. This also means that if Channel 1 is high-pass
filtered and connected to a tweeter, then Channel 2 must
also be high-pass filtered and connected to a tweeter.
Speaker Output Phase Relationship Requirements
All TXS25-4 outputs are ground referenced. Channels 2 and
4 are driven intentionally out of phase with Channels 1 and
3. The audio heard on all 4-Channels will actually be
in-phase, as Channels 2 and 4 are inverted inside the
D2-814xx firmware. Please refer to Figure 5 for connection
diagram. Speaker loads should also be connected or
disconnected only when the power to the evaluation kit is
turned off.
The user need only follow the standard connection method
of RED terminal to the + lead and the BLACK terminal to the
- lead of the speaker, as all of these inversions are already
compensated within both the firmware and in the PCB trace
connections.
AN1435.0
February 25, 2009
Application Note 1435
TXS25-4 Amplifier Module
Speaker Out 1+: J3/1
Required Speaker
Connections
+
-
Speaker Out 2-: J3/4
+
Speaker Out 3+: J3/9
+
-
Speaker Out 4-: J3/12
Channel 1
Channel 2
Channel 3
+
Channel 4
Note: Channels 2, 4 are 180 degrees out of phase vs. Channels 1, 3.
The above speaker connections are necessary to have all channels in phase.
FIGURE 6. REQUIRED LOUDSPEAKER CONNECTIONS
9
AN1435.0
February 25, 2009
INPUT
SELECT
Tone Control
5-Band
Parametric EQ
Tone Control
5-Band
Parametric EQ
D2Audio SoundSuite
Mono2Stereo
SPDIFRX
WideSound
DeepBass
3-Band
Parametric EQ
AudioAlign
3-Band
Parametric EQ
SDIN0
Matrix
Mixer
SDIN1
Stereo
Router
10
Tone Control
Router
LP Filter
Time Delay
Loudness
Compressor
HP Filter
LP Filter
Time Delay
Loudness
Compressor
Channel
Attenuation
Channel
Attenuation
2
Channel
Attenuation
2
SDOUT0 (Left Subframe)
Channel
Attenuation
Loudness
Compressor
Channel
Attenuation
Time Delay
Loudness
Compressor
Channel
Attenuation
Time Delay
Loudness
Compressor
HP Filter
LP Filter
Time Delay
HP Filter
LP Filter
LP Filter
Master
Volume
AN1435.0
February 25, 2009
FIGURE 7. TXS25-4 SIGNAL FLOW DIAGRAM
Channel
Attenuation
Channel
Attenuation
Speaker 1 PWM Output (+/-)
Speaker 2 PWM Output (+/-)
SDOUT0 (Right Subframe)
2
2
Speaker 3 PWM Output (+/-)
Speaker 4 PWM Output (+/-)
SDOUT1 (Left Subframe)
SDOUT1 (Right Subframe)
Application Note 1435
HP Filter
Application Note 1435
Analog
Inputs
L
R
R
L
Sub Out
AIN4
AIN3
AIN2
AIN1
S/PDIF
COAX
IN
Digital/Analog Audio/Control I/O Board
J8
MASTER
VOLUME
J5
J19
OPT
SCLK0
LRCK0
SDIN0
SCLK1
LRCK1
SDIN1
S/PDIF
OPT
IN
COAX
J6
USB
+5V
+3.3V
+1.8
GND
MCLKT
SCLKT
LRCKT
SDOUT0
SDOUT1
nRESET
BOOT_EE
nERROR
GPIO0
GPIO1
PSSYNC
S/PDIF
OPT
OUT
J9
J7
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
J4
J2
DAE-1
D2-814xx IC
TXS25-4 Amplifier Board
+
+
11
10
9
8
7
6
5
4
3
2
1
J3
12
11
10
9
8
7
6
5
4
3
2
1
J27
Amplifier Output Board
+
+
+25V
+25V
GND
GND
-
12
J28
-
FIGURE 8. STEP 5: ANALOG INPUT
11
AN1435.0
February 25, 2009
Application Note 1435
COAX
OPTICAL S/PDIF INPUT
JUMPER
OPTICAL
J8
S/PDIF
Optical Input
Sub Out
AIN4
AIN3
AIN2
AIN1
S/PDIF
COAX
IN
Digital/Analog Audio/Control I/O Board
MASTER
VOLUME
J5
J19
OPT
SCLK0
LRCK0
SDIN0
SCLK1
LRCK1
SDIN1
S/PDIF
OPT
IN
COAX
J7
J6
USB
+5V
+3.3V
+1.8
GND
J9
MCLKT
SCLKT
LRCKT
SDOUT0
SDOUT1
nRESET
BOOT_EE
nERROR
GPIO0
GPIO1
PSSYNC
S/PDIF
OPT
OUT
OPTICAL S/PDIF
Status LED
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
J4
J2
DAE-1
D2-814xx IC
TXS25-4 Amplifier Board
+
11
10
9
8
7
6
5
4
3
2
1
J3
12
11
10
9
8
7
6
5
4
3
2
1
J27
Amplifier Output Board
+
+
+
+25V
+25V
GND
GND
-
12
J28
-
FIGURE 9. STEP 5: OPTICAL (TOSLINK) S/PDIF INPUT
12
AN1435.0
February 25, 2009
Application Note 1435
COAX
COAX S/PDIF INPUT
JUMPER
Sub Out
AI N4
AI N3
AI N2
AI N1
COAX S/PDIF
Status LED
OPTICAL
S/PDIF
COAX
IN
Digital/Analog Audio/Control I/O Board
J8
MASTER
VOLUME
J5
J19
COAX
OPT
SCLK0
LRCK0
SDIN0
SCLK1
LRCK1
SDIN1
S/PDIF
OPT
IN
S/PDIF
COAX Input
J6
USB
+5V
+3.3V
+1.8
GND
MCLKT
SCLKT
LRCKT
SDOUT0
SDOUT1
nRESET
BOOT_EE
nERROR
GPIO0
GPIO1
PSSYNC
S/PDI F
OPT
OUT
J9
J7
30
28 26 24 22 20 18 16 14 12 10
8
6
4
2
29
27 25 23 21 19 17 15 13 11
9
7
5
3
1
30
28 26 24 22 20 18 16 14 12 10
8
6
4
2
29
27 25 23 21 19 17 15 13 11
7
5
3
1
9
J4
J2
DAE-1
D2-814xx IC
TXS25-4 Amplifier Board
+
11
10
9
8
7
6
5
4
3
2
1
J3
12
11
10
9
8
7
6
5
4
3
2
1
J27
Amplifier Output Board
+
+
+
+25V
+25V
GND
GND
-
12
J28
-
FIGURE 10. STEP 5: COAXIAL S/PDIF INPUT
13
AN1435.0
February 25, 2009
Application Note 1435
Sub Out
AIN 4
AIN 3
AIN 2
AIN 1
S/PDIF
COAX
IN
Digital/Analog Audio/Control I/O Board
MASTER
VOLUME
J5
J8
J19
OPT
SCLK0
LRCK0
SDIN0
SCLK1
LRCK1
SDIN1
S/PDIF
OPT
IN
COAX
J6
USB
MCLKT
SCLKT
LRCKT
SDOUT0
SDOUT1
+5V
+3.3V
+1.8
GND
nRESET
BOOT_EE
nERROR
GPIO0
GPIO1
PSSYNC
S/PDIF
OPT
OUT
J9
J7
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
J4
J2
DAE-1
D2-814xx IC
CHANNEL 4 OUT
(Right)
TXS25-4 Amplifier Board
+
Subwoofers
+
11
10
9
8
7
6
5
4
3
2
1
J3
12
11
10
9
8
7
6
5
4
3
2
1
J27
Amplifier Output Board
+
-
Tweeters
+
+25V
+25V
GND
GND
-
12
CHANNEL 1 OUT
(Left)
J28
CHANNEL 2 OUT
(Right)
CHANNEL 3 OUT
(Left)
FIGURE 11. STEP 6: OUTPUT DEVICE CONNECTION FOR A STEREO/BI-AMP SYSTEM
14
AN1435.0
February 25, 2009
Application Note 1435
Sub Out
AIN4
AIN3
AIN2
AIN1
S/PDIF
COAX
IN
Digital/Analog Audio/Control I/O Board
MASTER
VOLUME
J5
J8
J19
OPT
SCLK0
LRCK0
SDIN0
SCLK1
LRCK1
SDIN1
S/PDIF
OPT
IN
COAX
J7
J6
USB
MCLKT
SCLKT
LRCKT
SDOUT0
SDOUT1
+5V
+3.3V
+1.8
GND
nRESET
BOOT_EE
nERROR
GPIO0
GPIO1
PSSYNC
S/PDIF
OPT
OUT
J9
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
J4
J2
DAE-1
D2-814xx IC
CHANNEL 1 OUT
(Left)
TXS25-4 Amplifier Board
CHANNEL 4 OUT
(Right)
+
+
11
10
9
8
7
6
5
4
3
2
1
J3
12
11
10
9
8
7
6
5
4
3
2
1
J27
Amplifier Output Board
+
+
+25V
+25V
GND
GND
BridgeTied
Load
12
J28
Full-Range
Speakers
-
CHANNEL 3 OUT
(Left)
Subwoofer
CHANNEL 2 OUT
(Right)
FIGURE 12. STEP 6: OUTPUT DEVICE CONNECTION FOR A 2.1 CHANNEL SYSTEM
15
AN1435.0
February 25, 2009
Application Note 1435
CHANNEL 3 PWM
LINE-LEVEL
SUBWOOFER
OUT
Sub Out
AIN4
AIN3
AIN2
AIN1
S/PDIF
COAX
IN
Digital/Analog Audio/Control I/O Board
J8
MASTER
VOLUME
J5
J19
OPT
SCLK0
LRCK0
SDIN0
SCLK1
LRCK1
SDIN1
S/PDIF
OPT
IN
COAX
J7
J6
USB
+5V
+3.3V
+1.8
GND
MCLKT
SCLKT
LRCKT
SDOUT0
SDOUT1
nRESET
BOOT_EE
nERROR
GPIO0
GPIO1
PSSYNC
S/PDIF
OPT
OUT
J9
Powered
Subwoofer
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
J4
J2
DAE-1
D2-814xx IC
CHANNEL 1 OUT
(Left)
TXS25-4 Amplifier Board
CHANNEL 4 OUT
(Center)
+
12
11
10
9
8
7
6
5
4
3
2
1
J3
12
11
10
9
8
7
6
5
4
3
2
1
J27
Amplifier Output Board
+
+
+25V
+25V
GND
GND
-
+
J28
Full-Range
Speakers
-
Full-Range
Speaker
CHANNEL 2 OUT
(Right)
FIGURE 13. STEP 6: OUTPUT DEVICE CONNECTION FOR A 3.1 CHANNEL SYSTEM
16
AN1435.0
February 25, 2009
Application Note 1435
Input Source Options
The TXS25-4 amplifier design contains 4 audio input
channels. Several audio input source connections are
available on the evaluation kit for these inputs.
select the Optical S/PDIF input. The user must still select the
S/PDIF input mode.
TABLE 1. EVALUATION KIT SOURCE OPTIONS
INPUT
CHANNEL
AVAILABLE DIGITAL AVAILABLE ANALOG
SOURCE
SOURCE
CONNECTIONS ON
CONNECTIONS ON
EVALUATION KIT
EVALUATION KIT
Channels 1 thru 4 Coax S/PDIF receiver
Optical S/PDIF
receiver
I2S/Left-Justified input
headers
Direct connection to 4
Channel ADC, which is
connected to the
I2S/Left-Justified
Selecting an Audio Input Type (S/PDIF, I2S/LJ or
Analog)
The default (which includes after a reset or power cycle)
settings for the TXS25-4 firmware select the S/PDIF input.
The selection of the audio input can only be changed using
the Input Select Window inside the D2Audio Canvas II user
interface GUI.
Selecting Between I2S/Left-Justified Header Input
and Analog Input
In order to use the Analog Inputs, the user must select the
“I2S” input. Additionally they must make sure that J18 is
jumpered. By jumpering both the top and bottom J18
jumpers, both I2S streams from the 4 Channel ADC are sent
to both the SAI0 input (labeled I2S0 on the board) and the
SAI1 input (labeled I2S1 on the board). In order to use the
I2S/Left-Justified input headers for both SAI0 and SAI1
input, the user must select the same “I2S” input in the
D2Audio Canvas II menu in addition to making sure that J18
is NOT jumpered. Figure 14 shows how the board needs to
be configured to route both I2S streams from the 4-Channel
ADC to both the SAI0 input (labeled I2S0 on the board) and
the SAI1 input (labeled I2S1 on the board). If the user wants
to send I2S or Left-Justified data into the SAI0 or SAI1 input
ports, they are free to “wire-wrap” into the input headers
located at J5 and J8. If they choose to do this, they must
remove both jumpers from J18.
FIGURE 15. SELECTING BETWEEN COAXIAL AND OPTICAL
S/PDIF INPUT
When the S/PDIF input mode is selected (SPDIFRX), the
COAX/OPT jumper (J19) determines which S/PDIF interface
will be used.
TABLE 2. J13 - S/PDIF INPUT SELECTION OPTIONS
S/PDIF INPUT
SELECTION
COAX/OPT
COAX
When S/PDIF input
mode is enabled the
Coax S/PDIF connector
is selected
OPT
When S/PDIF input
mode is enabled the
Optical S/PDIF
connector is selected
NOTE: These jumpers are not only read at power-up and after a
reset to the amplifier design, but also during run time. Changes to the
jumpers at any time will cause the settings to have an immediate
effect and do not require a reset of the amplifier design to take effect.
Default Configuration
Table 3 highlights the SPDIF I/O board jumper configuration
for the default factory setting for the TXS25-4 evaluation
platform. NOTE: The jumpers are stored on the ground pins
for this configuration. If N/A is listed in the Default Jumper
Setting column then a jumper is not provided nor should the
associated header ever be shorted.
J18
EN ADC TO I2S0
EN ADC TO I2S1
FIGURE 14. ROUTING I2S DATA FROM THE 4-CHANNEL ADC
TO THE SAI0 AND SAI1 INPUTS
Selecting Between Coaxial and Optical S/PDIF
Input
J19 can be jumpered between Coax and Opt during
operation with out a need for a board reset in order to select
Coaxial or Optical S/PDIF input. Figure 15 shows how to
17
AN1435.0
February 25, 2009
Application Note 1435
.
TABLE 3. DEFAULT DIGITAL/ANALOG AUDIO/CONTROL I/O BOARD FACTORY JUMPER SELECTION
JUMPER NUMBER
J7
DEFAULT JUMPER
SETTING
DESCRIPTION
ADDITIONAL
INFORMATION
MCI Header
N/A
2-Wire Communication Header
I2S/Left-Justified Output
N/A
Serial Audio Output 0, Serial Audio Output 1, associated LRCLKT,
SCLKT, MCLKT. Connected to on board DAC
Header
J5
I2S/Left-Justified Input Header
N/A
Serial Audio Input 0 (SAI0)
J8
I2S/Left-Justified Input Header
N/A
Serial Audio Input 1 (SAI1)
J6
Control Header
N/A
Refer to TXS25-4 Data Sheet for more information.
J19
SPDIF Input Select Header
Jumper pins 1 to 2
S/PDIF (SPDIFRX) Coax Input selected
Sub Out
AIN4
AIN3
AIN2
AIN1
S/PDIF
COAX
IN
Digital/Analog Audio/Control I/O Board
MASTER
VOLUME
S/PDIF
OPT
IN
USB
S/PDIF
OPT
OUT
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
FIGURE 16. MASTER VOLUME CONTROL KNOB
Master Volume Control
Each time the board is reset or powered up, the master
volume will revert back to the default setting as stored in the
EEPROM within the amplifier design. These settings can be
saved to different levels by using D2Audio Canvas II
software with the “Save Settings to EEPROM” command.
When shipped from the factory, these value are -20dB. While
the board is powered up, the master volume for only
Channels 1 and 2 may be adjusted by turning the Master
Volume Control knob located on the input board. Adjusting
the Master Volume knob will adjust the Master Volume slider
inside the D2Audio Canvas II GUI, provided that polling has
been enabled within the D2Audio Canvas II program.
18
AN1435.0
February 25, 2009
Application Note 1435
Optional I2S/Left-Justified Connection
The TXS25-4 evaluation board may be connected to
external I2S (or Left-Justified) audio sources. Three pins on
jumpers J8 and J5 are available for I2S (or Left-Justified)
connections (see Tables 4 and 5). The user must remove
both jumpers on J18 in order to avoid clock and data
contention from that being sent by the 4 channel ADC. The
interface is a 3.3V signaling level with the I2S data format
selected. Sample rates from 32kHz up to 192kHz are
accepted. In addition, the TXS25-4 evaluation board is
capable of driving up to 4-Channels of post-processed 24-bit
PCM data on jumper J7 (see Table 6). MCLKT = 256Fs.
SCLKT = 64Fs. LRCKT = Fs. Fs for data on SDOUT0 and
SDOUT1 is fixed at 48kHz regardless of audio input Fs.
J8
TABLE 6. J7 - I2S/LEFT-JUSTIFIED (SAO0, SAO1) OUTPUT
HEADER PINS
FUNCTION
SELECTION
FUNCTION
SDOUT1
I2S Channel 1 - Serial Audio Data Output
SDOUT0
I2S Channel 0 - Serial Audio Data Output
LRCKT
I2S Serial Audio Data Left/Right Frame Clock
Output
SCLKT
I2S Serial Audio Data Clock Output
MCLKT
I2S Master Clock Output
Advanced Configuration with D2Audio
Canvas II Software
SCLK0
LRCK0
SDIN0
SCLK1
LRCK1
SDIN1
All amplifier settings can be changed through the 2-wire
control interface within the amplifier design. The D2Audio
Canvas II software supplied with the evaluation kit provides
a graphical interface and USB connection to a PC to adjust
these settings on the evaluation kit. See the “D2Audio
Canvas II Users Guide” for further details.
J5
Hardware vs Software Configuration
J7
MCLKT
SCLKT
LRCKT
SDOUT0
SDOUT1
FIGURE 17. OPTIONAL I2S/LEFT-JUSTIFIED CONNECTIONS
TABLE 4. J5 - I2S/LEFT-JUSTIFIED (SAI0) INPUT HEADER PINS
FUNCTION
(I2S CHANNEL 0)
SIGNAL
LRCLK0
3.3V Serial Audio Data Left/Right Frame
Clock
SCLK0
3.3V Serial Audio Data Shift Clock
SDIN0
3.3V Serial Audio Data
TABLE 5. J8 - I2S/LEFT-JUSTIFIED (SAI1) INPUT HEADER PINS
FUNCTION
(I2S CHANNEL 1)
SIGNAL
The D2Audio Canvas II software can be used to configure
the TXS25-4 to select between I2S/Left-Justified inputs
SAI0, which is connected to an ADC on this evaluation kit vs
I2S/Left-Justified SAI1 which is available for designers to
wire-wrap in an external digital audio device to the amplifier
design. SAI0 and SPDIFRX can be accepted by the amplifier
design simultaneously. The user is responsible for
configuring the routing/mixing/processing of these two audio
inputs using the D2Audio Canvas II GUI. With only 2
channels of audio physically connected to the board, this
audio can be sent to all output channels using the Matrix
Mixer and Routers, accessible through the D2Audio Canvas
II software.
All settings, including master volume, are stored in an
EEPROM within the amplifier design and are loaded upon
reset or power-up. After power-up, the D2Audio Canvas II
software can be used to change these settings and can
update the EEPROM with a new set of defaults if desired.
The only exception to this is the input selection settings
which will always default back to the settings defined by the
firmware.
Note the following:
LRCLK1
3.3V Serial Audio Data Left/Right Frame
Clock
SCLK1
3.3V Serial Audio Data Shift Clock
SDIN1
3.3V Serial Audio Data
19
Once the D2Audio Canvas II software is running, the Master
Volume Control knob may still be used, however the Master
Volume Control knob should not be adjusted when any
D2Audio Canvas II hardware communication is taking place
such as:
AN1435.0
February 25, 2009
Application Note 1435
• Changing any D2Audio Canvas II controls including
sliders, text fields, buttons, etc.
• Initial all-data transmit or receive performed during launch
of D2Audio Canvas II and the associated “Connect to
Module” process
• An all-data transmit or receive as triggered by the D2Audio
Canvas II menu File->Transmit or File->Receive
selections
• The D2Audio Canvas II menu Tools->Save Settings to
EEPROM or Tools->Module Firmware Status selections
Alternatively, the designer can use the D2Audio Canvas II
software to adjust the master volume, but just not at the
same time as when the Master Volume Control knob is used.
Testing Methodology
The following sections detail the testing methodology for
obtaining optimal test results using an Audio Precision
System Two.
AES17 Filter Requirement
The test and measurement of a class-D audio amplifier
requires additional considerations beyond that of a class-AB
or class-A linear design. All Intersil amplifier products use
noise-shaping techniques which provide extremely good
noise and distortion performance within the audio band
(20Hz to 20kHz) in exchange for increased out-of-band
noise (>20kHz). Each amplifier design contains a low-pass
audio output filter, which attenuates this out-of-band noise
present in the amplified signal.
Despite the presence of this filter, a small amount of
out-of-band noise is still present in the amplifier output.
When a standard 8Ω speaker is connected to the amplifier,
this out-of-band noise has no effect on performance.
However, the high-frequency nature of the out-of-band noise
can exceed the maximum slew rate of the Audio Precision
analog inputs, which can create erroneous measurements.
In order to properly interface the Audio Precision test
equipment to a class-D audio amplifier, the AES17 filter
option must be installed and enabled. The response of the
AES17 20kHz filter is shown in Figure 18.
It is important to note that the AES17 filter does not artificially
improve the test results of a class-D amplifier to make them
appear similar to those of a traditional class-AB or class-A
amplifier. The filter is only present to reduce the high slew
rate content of the amplifier output so that the Audio
Precision may perform a proper test.1
1.For further information, see the white paper
Measuring Switch-mode Power Amplifiers, by Bruce Hofer, Audio
Precision, 2003, available at www.audioprecision.com.
FIGURE 18. AES17 FILTER PASSBAND AND STOPBAND RESPONSE, WITH 20kHZ SETTING
20
AN1435.0
February 25, 2009
Application Note 1435
• The master volume of the amplifier must be set to 0dB.
• Each individual channel volume of the amplifier must be
set to -6dB.
• All Equalizers, Tone Controls, Compression and
Adjustable Time Delay should set to flat (0dB) or disabled.
Either analog or digital inputs may be used for testing.
However, it is recommended that digital input sources (either
I2S, Left-Justified or S/PDIF) be used for testing, as this will
result in the most accurate measurement.
TXS25-4 EVALUATION BOARD OUTPUT POWER NOTES
The TXS25-4 is a reference and evaluation board, and
therefore does not include heatsinking capability for
extended high power use. Its heatsinking, simply through the
copper pads on the pc board, was designed for a maximum
of 1/8th continuous power on all channels in an open-air
ambient of +25°C. Do not run high power sine waves
continuously unless you have added additional heatsinking
to the TXS25-4, as without additional heatsinking capability
for output devices, generate excessive heat will be
generated.
TESTING WITH DIGITAL INPUTS (RECOMMENDED
SETUP)
FIGURE 19. AUDIO PRECISION AES17 20kHZ FILTER
SELECTION
AUX-0025 Filter
In addition to the AES17 filter, Audio Precision has an
AUX-0025 filter product for measuring class-D amplifiers that
either have no output filter, or an output filter with a limited
rolloff. However, the AUX-0025 filter is NOT necessary when
testing Intersil products, as all Intersil amplifier designs
contain an output filter with steep low-pass rolloff.
Testing Setup
For proper amplifier characterization, the following
conditions should be met:
• Measurements should be taken with only one amplifier
channel driven.
All Intersil amplifier designs are digital by nature, and
therefore will perform best when used with a digital input
source. For proper test results, 24-bits of resolution or more
are required. For this reason, a CD player cannot be used as
a digital source, as it only provides 16-bit resolution.
When using the digital outputs of the Audio Precision, the
following settings should be made:
• The TXS25-4 amplifier must be configured for the
appropriate digital input (see “Input Source Options” on
page 17)
• Data resolution should be 24 bits in the AP Digital
Generator
• Pre-emphasis should be off in the AP Digital Generator
• Volts/FS reference should be set to 1V
• An 8Ω resistive load should be used on the output of the
channel under test, with the Audio Precision input
connected in parallel and set for high impedance (100kΩ).
Tests should not be run on a channel without an 8Ω load
connected.
Either S/PDIF or I2S/Left-Justified interfaces can be used.
Specific settings for each interface are provided in the
following:
The software settings in the amplifier design should be set
for “flat” response with 0dB of gain. Verify each of the
following settings before proceeding with a test: (Refer to the
D2Audio Canvas II operation manual for setting “flat
response”).
In addition to the general digital configuration above, the
following settings should be made in order to use the Audio
Precision S/PDIF output:
21
S/PDIF Source Setup
• Either the optical or BNC electrical output can be used
from the Audio Precision. Select the appropriate output in
AN1435.0
February 25, 2009
Application Note 1435
the Digital I/O panel. Also select the appropriate position
for the S/PDIF Input Select Jumper on the TXS25-4 board.
• Set the sample rate to 48kHz in the Digital I/O panel
(though any values from 32kHz to 192kHz are
acceptable).
• Set the output voltage to 5VP-P in the Digital I/O panel
FIGURE 20. AUDIO PRECISION S/PDIF OUTPUT
CONFIGURATION
I2S Source Setup
The I2S/Left-Justified inputs on the TXS25-4 board can be
connected to the output of an Audio Precision PSIA:
• Select the “PSIA” output in the Digital I/O panel.
• Select 3.3V CMOS as the output logic level in the PSIA
Transmitter panel.
• Press the “I2S” button in the PSIA Transmitter panel to
format the data for I2S.
• Press the “Outputs ON” button in the PSIA Transmitter
panel to enable the PSIA output. Note that this button
must be on in addition to the “Outputs ON” button in the
Digital Generator panel in order for the PSIA output to
function.
22
AN1435.0
February 25, 2009
Application Note 1435
FIGURE 21. AUDIO PRECISION I2S OUTPUT CONFIGURATION
TESTING WITH ANALOG INPUTS
Analog-to-digital converters are present on the TXS25-4
amplifier design. These can provide a secondary input
source to the amplifier design. However, it is suggested that
digital inputs be used for testing if at all possible, since
analog input performance will be slightly less than that
measured with the digital input.
When using the analog outputs of the Audio Precision, the
following settings should be made:
• The dBr Reference Voltage should be set to 2V in the
Analog Generator Panel if using the analog inputs of the
amplifier design.
• The dBr Reference Voltage should be set to 1V in the
Analog Generator Panel if using the external
high-performance ADCs.
• The Watts reference should be set to 8Ω in the Analog
Generator Panel
• Z-Out should be set to 20Ω in the Analog Generator
Panel.
• Configuration should be set for Unbal-Float in the Analog
Generator Panel. Unbal-GND may yield better results.
23
AN1435.0
February 25, 2009
Application Note 1435
TXS25-4 Evaluation Platform Hardware
Power Supplies
The TXS25-4 amplifier design operates from a single +25V,
5A DC power supply. This external power supply connects to
header J28 of the amplifier output board, where DC power
filtering is also provided. All other operating voltages are
internally generated from this 25V source. The TXS25-4
amplifier board internally generates -25V for the FETs. (This
is a half-bridge design.) The first switching stage takes the
+25V primary input supply voltage and generates the
required -25V, under the control of the D2-814xx IC. The
+25V is also sent to a DC/DC circuit which regulates down to
+5V; the second stage regulates +5V down to +3.3V and
+1.8V for the control input functions using parallel linear
regulators. The low voltage regulation provides proper power
sequencing in addition to low power dissipation (high
efficiency).
Remote Input Board
FIGURE 22. AUDIO PRECISION ANALOG OUTPUT
CONFIGURATION
Typical Basic Measurements
The following measurements in Table 7 can be made by
using the Analog Analyzer panels in the Audio Precision
software. The measurements in Table 8 were made using a
digital input source.
TABLE 7. TXS25-4 BASIC MEASUREMENTS, RATED
POWER, 8Ω LOAD (-0.5DBFS INPUT)
MEASUREMENT DESCRIPTION
Output voltage on speaker terminals
Total Harmonic Distortion + Noise Percentage
(THD+N) 20Hz to 20kHz
Signal to Noise+Distortion Ratio (Total Harmonic
Distortion + Noise Amplitude relative to full scale
output (31VRMS))
The TXS25-4 evaluation PCB allows the Digital/Analog
Audio/Control I/O Board and Amplifier Output sections of the
board to be separated from the TXS25-4 amplifier board.
The ribbon cables may be extended by replacing the
provided ribbon cables. This allows the Digital/Analog
Audio/Control I/O Board section to be mounted remotely
from the TXS25-4 and output boards as well as allowing for
easier design-in for prototyping. Extension of the ribbon
cable may result in degradation of the digital audio input
signal (I2S/LJ (from headers or 4-Channel ADC) or S/PDIF)
signal integrity. Extension should be limited to six inches or
less.
TYPICAL
RESULT UNITS
31
VRMS
<0.2
%
>-105
dBr
NOTE:
1. These results are preliminary, based on Rev 1 of the TXS25-4
Evaluation Kit.
TABLE 8. TXS25-4 BASIC MEASUREMENTS, 1W POWER, 8Ω
LOAD (-21DBFS INPUT) @ 1kHz
MEASUREMENT DESCRIPTION
TYPICAL
RESULT UNITS
Output voltage on speaker terminals
2.8
VRMS
Total Harmonic Distortion + Noise Percentage
(THD+N) 20Hz to 20kHz
<.05
%
NOTE:
2. These results are preliminary, based on Rev 1 of the TXS25-4
Evaluation Kit.
24
AN1435.0
February 25, 2009
Application Note 1435
RIBBON CABLE
DETACHED AMPLIFIER
OUTPUT BOARD
RIBBON CABLE
DETACHED TXS25-4
AMPLIFIER BOARD
DETACHED DIGITAL/ANALOG AUDIO/
CONTROL I/O BOARD
FIGURE 23. DIGITAL/ANALOG AUDIO/CONTROL I/O BOARD, AMPLIFIER BOARD, AND OUTPUT BOARD
USB Interface
A USB interface is provided on the TXS25-4 evaluation
platform to provide communications between the TXS25-4
amplifier design and an external PC based system. The USB
interface provides a means of upgrading the amplifier design
system parameters, input sources, and DSP firmware. The
D2Audio Canvas II utility provided with the TXS25-4
evaluation platform utilizes this interface. Refer to the
D2Audio Canvas II Users Guide for USB driver installation
and instructions.
25
AN1435.0
February 25, 2009
Hardware Schematics
Block Diagram
OPTIONAL
OPTIONAL
Breakaway Input Board
DSP, Input Header & V-Regs
D
PWM1H
PWM1L
26
nPWM_ERR1
PWM2H
PWM2L
nPWM_ERR2
PWM3H
PWM3L
nPWM_ERR3
PWM4H
C
nPWM_ERR4
PUMPHI
PUMPLO
nPWM_ERR_PUMP
SYNC_2670
+25V
-25V
+5V
+3.3V
B
PWM1L
nPWM_ERR1
PWM2H
PWM2L
nPWM_ERR2
PWM3H
PWM3L
nPWM_ERR3
PWM4H
PWM4L
nPWM_ERR4
PUMPHI
PUMPLO
nPWM_ERR_PUMP
SYNC_2670
+25V
-25V
+5V
+3.3V
Breakaway Output Board
PWM1H
PWM1L
nPWM_ERR1
PWM2H
PWM2L
nPWM_ERR2
PWM3H
PWM3L
nPWM_ERR3
PWM4H
PWM4L
Application Note 1435
PWM4L
Output Power Stages
PWM1H
nPWM_ERR4
PUMPHI
PUMPLO
nPWM_ERR_PUMP
SYNC_2670
+25V
-25V
+5V
+3.3V
This schematic contains sections for both the TXS 25-4
AMPLIFIER DESIGN and it’s evaluation components.
The design of the amplifier and evaluation kit includes a single PCB that can be broken into 3 pieces: Input,
Amplifier, Output & Power Supply Connections.
Schematic Page
1
Overview
2-5
Core Amplifier (some sections may be marked optional)
A
D2Audio
7600 B Capital Of Te
Suite 130
Austin, TX 78731
6-10
Optional for Eval Kit
Title
TXS25-4 Reference
AN1435.0
February 25, 2009
Hardware Schematics (Continued)
Reference Schematic
5
4
3
2
1
R76
10K
0603
+3.3V
System Test Port
+1.8V
C1
C2
C3
0.1uF
0603
0.1uF
0603
0.1uF
0603
+3.3V
D
R7
33.2
0603
HDR 15X2
0.1uF
0603
0.1uF
0603
R77
33.2
R78
33.2
R79
33.2
R80
33.2
0603
SDOUT1
0603
SDOUT0
0603
SCLKT
0603
J2
+ C14
(same footprint)
SCL
C25
0.1uF
0603
XSCLK0
XSDIN0
XLRCK0
C26
22uF
6.3VDC
+
+1.8V
C27
NS
6.3VDC
+
C28
0.1uF
0603
MCLKT
(same footprint)
XSCLK1
XSDIN1
XLRCK1
R81
33.2
0603
+1.8V
Optional
Tantalum
C32
22uF
6.3VDC
+
+1.8V
C33
NS
6.3VDC
+
C36
0.1uF
0603
GPIO0
(same footprint)
GPIO1
+3.3V
C39
0.1uF
0603
nRED_LED
2
LED2
1
2
GRN LED
LED0603
AT24C512
1
2
3
4
A0
A1
A2
GND
0.1uF
0603
VCC
WP
SCL
SDA
D2-81412-LR
U3
R26
10K
0603
R27
10K
0603
R28
10K
0603
8
7
6
5
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PWM2H
PWM2L
SYNC_2670
C8
0.1uF
0603
+
C5
100uF
6.3V
Operating Mode Configuration
+3.3V
0.1uF
0603
0.1uF
0603
+3.3V
+3.3V
C47
0.1uF
0603
0.1uF
0603
+3.3V
BOOT_EE/I2C
R193
10K
0603
+1.8V
LM1117MPX-1.8V
3 VIN
TAB 4
VOUT 2
CONFIG3
GND
1
AN1435.0
February 25, 2009
C84
0.1uF
0603
U7
C7
0.1uF
0603
+
22uF
6.3VDC
R197
NS
0603
C4
100uF
6.3V
R194
10K
0603
CONFIG2
R198
NS
0603
R195
10K
0603
CONFIG1
R199
NS
0603
R196
10K
0603
CONFIG0
PWM4H
PWM4L
+
nTRST
0805
C24
NS
6.3VDC
C
+1.8V
Optional
Tantalum
PWM4H
PWM4L
C29
22uF
6.3VDC
C31
0.1uF
0603
+
+
+1.8V
nRAIL_OVER
nPWM_ERR1
nPWM_ERR1
nPWM_ERR2
nPWM_ERR2
nPWM_ERR3
nPWM_ERR3
nPWM_ERR_PUMP
nPWM_ERR4
nPWM_ERR_PUMP
nPWM_ERR4
C30
NS
6.3VDC
(same footprint)
+3.3V
Optional
Tantalum
C34
0.1uF
0603
+
C37 +
22uF
6.3VDC
+3.3V
C35
NS
6.3VDC
(same footprint)
C38
0.1uF
0603
+1.8V
+3.3V
SYNC_2670
NS
1 HST
OS
R25
1K
0603
+25V
PUMPLO
R73
10K
0603
VCC
4
D4
EP05Q04
C82
NS
0603
C41
0.1uF
0603
Optional Temp Sensor
PUMPHI
R35
10K
0603
R36
R34
162
0603
1K
0603
Q3
MMBT2222A
SOT-23
-25V
Rail Over-Voltage Protection
Q4
MMBT2222A
SOT-23
A
B
MMBT2222
C
D2Audio
7600 B Capital Of Texas HWY N
Suite 130
Austin, TX 78731
D2-81412-LR Boot Modes
Boot Source
IRQ [D:A]
BOOT_EE/I2C
nBOOT_EE/I2C
2-wire ROM on GPIO6,7
0111
1
0
2-wire slave, addr = 1000 100x
1100
0
1
Title
Size
C
Date:
4
NS
0603
U5
D16
BZX84C39
SOT-23
+39V
R85
5
2 GND
3 V
TEMP
PSSYNC
C45
0.1uF
0603
+3.3V
E
R200
NS
0603
Local Power Supplies
5
600-Ohm@100MHz
Optional
Tantalum
+ C19
PWM3H
PWM3L
R33
10K
0603
A
+5V
C23
0.1uF
0603
R32
4.75K
0603
nBOOT_EE/I2C
U6
C46
+3.3V
1
C6
100uF
6.3V
+3.3V
+1.8V
+
C44
+3.3V
+3.3V
C9
0.1uF
0603
C43
+1.8V
+5V
GND
C22
0.1uF
0603
3
R82
PUMPHI
LM1117MPX-3.3V
TAB 4
VIN
VOUT 2
C21
0.1uF
0603
(same footprint)
33.2
0603
PUMPLO
3
C20
0.1uF
0603
PWM2H
PWM2L
PWM3H
PWM3L
33.2
0603
C83
0.1uF
0603
+3.3V
PWM1H
PWM1L
B
R86
nERROR
+5V
L2
PWMVDD
PWM1H
PWM1L
+3.3V
EEWP
EESCL
EESDA
U2
+5V
SYS2
PWMVDD
PWMVDD
PWMH0
PWML0
PWMGND
PWMVDD
PWMH1
PWML1
PWMGND
PWMVDD
PWMH2
PWML2
PWMGND
PWMVDD
PWMH3
PWML3
PWMGND
CGND
CVDD
PROTECTA0
PROTECTB0
PROTECTC0
PROTECTA1
PROTECTB1
PROTECTC1
RGND
RVDD
CGND
CVDD
PROTECTA2
PROTECTB2
PROTECTC2
PROTECTA3
PROTECTB3
PROTECTC3
OTSEL
N/C
CONFIG3
CONFIG2
CONFIG1
CONFIG0
33.2
0603
SCL
SDA
TIO2
TIO1
TIO0
nRESET
nRSTOUT
CGND
CVDD
SRD1
SCK1
STD1
SC10
SC11
SC12
RGND
RVDD
SYS3
SYS4
SYS2
SYS0
CGND
CVDD
SYS1
nTRST
PLLAVDD
PLLAGND
OSCGND
XTALO
XTALI
OSCVDD
NC
NC
PLLVDD
PLLGND
OSCOUT
+3.3V
C40
R24
B
SPDIFTX
SPDIFRX
TXD
RXD
SCLK
RVDD
RGND
SCKR0
SDIN0
LRCKR0
CVDD
CGND
SCKR1
SDIN1
LRCKR1
MCLK
SCKT
SDO
LRCLKT
STD0
SCK0
SRD0
SC00
SC01
SC02
GPIO0
CVDD
CGND
GPIO1
RVDD
RGND
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
nGRN_LED
RED LED
LED0603
SYS0
R22
OSCGND
GPIO7
XGPIO15
XGPIO14
XGPIO10
XGPIO9
XGPIO8
XGPIO7
CVDD
CGND
XGPIO6
RVDD
RGND
XGPIO5
XGPIO4
XGPIO3
XGPIO2
XGPIO1
XGPIO0
XGPIO12
XGPIO11
XGPIO13
TEST
CVDD
CGND
BMS0
BMS1
RVDD
RGND
BMS2
BMS3
CTRL0
CTRL1
CTRL2
NC
NC
CTRL3
1
33.2
0603
EP05Q04
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
R23
LED1
D
2 nTRST
Y2
NS
1
Optional
Tantalum
TP8
TP7
D3
1
Optional
2
+3.3V
C
R10
3
2
TXS25-4 Reference
Document Number
System Enginering
Rev
02R1
DSP
0070-C00085-000
Sheet
Monday, January 30, 2006
1
2
of
10
Application Note 1435
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
+3.3V
+3.3V
0-Ohm
0805
33.2
0603
SPDIFRX
TP6
C17
18pF
0603
Y1
24.576MHZ
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
SPDIFTX
TP5
100
0603
C18
18pF
0603
OSCGND
SDA
R72
C15
NS
6.3VDC
+
22uF
6.3VDC
0.1uF
0603
GPIO0 = I2C Address Select
GPIO1 = Standby/Sleep
TP4
Optional
Tantalum
C16
LRCKT
PWM3H
PWM3L
GPIO1
PSSYNC
+5V
TP3
nRESET
600-Ohm@100MHz
2
C198
NS
6.3V
C12
XTALO
XTALI
+
R5
10K
0603
TP2
0805
SYS1
nTRST
C199
0.1uF
0603
+1.8V
C11
10K
0603
R11
10K
0603
C13
0.1uF
0603
SYS3
SYS4
SYS2
SYS0
+1.8V
GND
LRCKT
SDOUT1
SCLKT
SCL
nRESET
SPDIFRX
XSDIN0
XSCLK1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
TIO-0
1
3
5
7
9
SPDIFTX
11
XSCLK0
13
XLRCK0
15
XSDIN1
17
XLRCK1
19
MCLKT
21
GPIO0
23
nERROR
25
BOOT_EE/I2C 27
29
R8
10K
0603
L1
OSCVDD
R9
nRSTOUT
+3.3V
+1.8V
SDOUT0
SDA
C196
NS
6.3V
TSW-115-06-T-D-LL
27
+
R4
10K
0603
1
EP05Q04
Q1
MMBT2222A
SOT-23
R3
10K
0603
SYS4
D2
2
nRESET
R2
10K
0603
SYS3
SYS1
1
R6
1M
0603
2
Stuff Bulks If No Local Reg's
+3.3V
C197
0.1uF
0603
R1
10K
0603
TP1
D1
EP05Q04
1
R75
10K
0603
+3.3V
R74
10K
0603
XLRCK1
R21
10K
0603
XSCLK1
SCL
R20
10K
0603
XSDIN1
R19
10K
0603
nERROR
R18
10K
0603
GPIO1
R17
10K
0603
GPIO0
R16
10K
0603
SDA
XLRCK0
R15
10K
0603
BOOT_EE/I2C
R14
10K
0603
XSCLK0
R13
10K
0603
XSDIN0
SPDIFRX
R12
10K
0603
+1.8V
+3.3V
Hardware Schematics (Continued)
Power Stages 1-2
5
+3.3V
+3.3V
+5V
+5V
+5V
+25V
+25V
+25V
-25V
-25V
-25V
+3.3V
4
3
2
1
+25V
C49
5
.47uF
1206
X7R
6
U4C
74VHC04
D
D
2
1
U4A
R39
10K
0603
74VHC04
D5
EP05Q04
2
4
1
74VHC04
Q5
ZXMP6A17G
SOT-223
C52
0.68uF
X7R
50V
C53
0.033uF
X7R
50VDC
2
4
0.1uF
0805
Kelvin Connections
L3
R42
DRAIN1
2
4
0-ohm
0805
1
0.1uF
0805
R45
10K
0603
D8
EP05Q04
6
U3B
PWR_GND
+3.3V
2
1
5
C57
R46
74VHC125
Q9
FMMT593-PNP
SOT-23
4
100
0603
R48
820
0603
C59
100pF
0603
C60
100pF
0603
R47
1K
0603
nPWM_ERR1
R49
820
0603
R51
100
0603
R52
+5V
U3E
74VHC125
7
74VHC04
C48
1uF
0805
-25V
7
U4G
C81
0.1uF
0603
C
R53
681
0603
14
14
+5V
C61
100pF
0603
Q11
FMMT493A
SOT-23
2K
0603
C64
1uF
0805
D9
EP05Q04
R50
4.99K
0603
R68
0-Ohm
0805
R69
13
U4D
0-Ohm
0805
12
PWR_GND
74VHC04
R70
+25V
10
R55
10K
0603
74VHC04
D10
EP05Q04
U4F
8
1
Q12
ZXMP6A17G
SOT-223
0.1uF
0805
C70
0.033uF
X7R
50VDC
2
4
74VHC04
C69
0.68uF
X7R
50V
Kelvin Connections
L4
R56
DRAIN2
2
4
33uH
DO3340P-333
U3D
11
74VHC125
PWR_GND
3
R58
10K
0603
D13
EP05Q04
+3.3V
R59
Q14
FMMT593-PNP
SOT-23
100
0603
13
12
1
0.1uF
0805
OUT2-
C73
2200pF
0805
C72
0.1uF
0805
1
8
74VHC125
2
U3C
10
9
PWM2L
OUT2C71
.47uF
50 VDC
Film
0.15
1210
Q13
ZXMN6A11G
SOT-223
C74
R61
820
0603
Q15
FMMT593-PNP
SOT-23
C76
100pF
0603
C77
100pF
0603
R60
1K
0603
nPWM_ERR2
R62
820
0603
1
9
B
2
C67
R64
100
0603
D14
EP05Q04
R63
4.99K
0603
C78
100pF
0603
2
U4E
B
3
11
1
PWM2H
0-Ohm
0805
R65
Q16
FMMT493A
SOT-23
A
2K
0603
A
R66
681
0603
C79
D2Audio
7600 B Capital Of Texas HWY N
Suite 130
Austin, TX 78731
.47uF
1206
X7R
Title
-25V
AN1435.0
February 25, 2009
5
4
3
2
TXS25-4 Reference
Size
C
Document Number
Date:
Monday, January 30, 2006
0070-C00085-000
System Engineering
Rev
02R1
Power Stages 1-2
Sheet
1
3
of
10
Application Note 1435
Q10
FMMT593-PNP
SOT-23
C
C80
0.1uF
0603
OUT1+
C56
2200pF
0805
C55
0.1uF
0805
3
R71
3
74VHC125
U3A
C54
.47uF
50 VDC
Film
1
2
PWM1L
OUT1+
0.15
1210
33uH
DO3340P-333
Q8
ZXMN6A11G
SOT-223
1
U4B
2
28
C50
3
3
1
PWM1H
Hardware Schematics (Continued)
Power Stages 3-4
5
+3.3V
+3.3V
+3.3V
+5V
+5V
+25V
+25V
+25V
-25V
-25V
-25V
+5V
4
3
2
1
+25V
C85
5
.47uF
1206
X7R
6
U8C
74VHC04
D
D
2
1
U8A
R87
10K
0603
74VHC04
D17
EP05Q04
2
29
C86
3
3
1
PWM3H
4
U8B
1
74VHC04
Q17
ZXMP6A17G
SOT-223
C87
0.68uF
X7R
50V
C88
0.033uF
X7R
50VDC
2
4
0.1uF
0805
Kelvin Connections
L5
R88
DRAIN3
2
4
0-ohm
0805
C92
1
0.1uF
0805
R90
10K
0603
1
D18
EP05Q04
PWR_GND
3
R89
3
74VHC125
U9A
OUT3+
C91
2200pF
0805
C90
0.1uF
0805
1
2
PWM3L
OUT3+
C89
.47uF
50 VDC
Film
0.15
1210
33uH
DO3340P-333
Q18
ZXMN6A11G
SOT-223
+3.3V
R91
74VHC125
Q19
FMMT593-PNP
SOT-23
4
100
0603
R93
820
0603
C94
100pF
0603
nPWM_ERR3
R94
820
0603
R96
100
0603
R97
+5V
U9E
74VHC125
7
74VHC04
C99
1uF
0805
-25V
7
U8G
C98
0.1uF
0603
C
R98
681
0603
14
14
+5V
C97
1uF
0805
C95
100pF
0603
Q21
FMMT493A
SOT-23
2K
0603
C96
0.1uF
0603
D19
EP05Q04
R95
4.99K
0603
R99
0-Ohm
0805
R100
13
U8D
0-Ohm
0805
12
PWR_GND
74VHC04
R101
+25V
9
U8F
R102
10K
0603
74VHC04
B
D20
EP05Q04
8
1
Q22
ZXMP6A17G
SOT-223
0.1uF
0805
C101
0.68uF
X7R
50V
C102
0.033uF
X7R
50VDC
2
4
74VHC04
B
2
C100
3
U8E
0-Ohm
0805
10
1
PWM4H
11
Kelvin Connections
L6
R103
DRAIN4
2
4
Q23
ZXMN6A11G
SOT-223
C106
1
0.1uF
0805
R104
10K
0603
D21
EP05Q04
PWR_GND
3
8
74VHC125
OUT4-
C105
2200pF
0805
C104
0.1uF
0805
1
U9C
10
9
PWM4L
OUT4C103
.47uF
50 VDC
Film
0.15
1210
33uH
DO3340P-333
+3.3V
R105
Q24
FMMT593-PNP
SOT-23
100
0603
R107
820
0603
Q25
FMMT593-PNP
SOT-23
C107
100pF
0603
C108
100pF
0603
R106
1K
0603
nPWM_ERR4
R108
820
0603
1
11
74VHC125
R110
100
0603
D22
EP05Q04
R109
4.99K
0603
C109
100pF
0603
2
U9D
13
12
2
+3.3V
R111
Q26
FMMT493A
SOT-23
A
2K
0603
A
R112
681
0603
C110
D2Audio
7600 B Capital Of Texas HWY N
Suite 130
Austin, TX 78731
.47uF
1206
X7R
Title
-25V
AN1435.0
February 25, 2009
5
4
3
2
TXS25-4 Reference
Size
C
Document Number
Date:
Monday, January 30, 2006
0070-C00085-000
System Engineering
Rev
02R1
Power Stages 3-4
Sheet
1
4
of
10
Application Note 1435
Q20
FMMT593-PNP
SOT-23
C
C93
100pF
0603
R92
1K
0603
1
6
U9B
2
5
2
+3.3V
Hardware Schematics (Continued)
Pump, Output Header, +5V SMPS
5
+3.3V
+5V
+3.3V
+3.3V
+5V
+5V
4
3
2
1
+25V
C111
.47uF
1206
X7R
Anti-Pump / Negative Rail Source
+5V
C112
0.1uF
0603
C113
1uF
0805
VCC
PUMPHI
PUMPHI
2
NC7SZ04
4
U10
N/C
1
30
3
GND
+5V
C114
0.1uF
0805
Q27
Si7415DN
POWERPAK-1212
C115
0.68uF
X7R
50V
C116
0.033uF
X7R
50VDC
R115
Kelvin Connections
5
NS
DO3340P-333
NC7SZ125
1
2
3
1
15.65uH
Attwood2
+3.3V
2
1
PWR_GND
L11
POWERPAK-1212
R119
10K
0603
D24
EP05Q04
0-Ohm
0805
0.047
1210
Q28
Si7414DN
4
0.1uF
0805
GND
3
C119
4
U11
R116
R117
DRAIN-PUMP
2
0-Ohm
0805
PWR_GND
L7
C118
1uF
0805
VCC
PUMPLO
PUMPLO
D
0-Ohm
0805
4
5
C117
0.1uF
0603
R113
R114
10K
0603
D23
EP05Q04
5
D
1
2
3
-25V
5
+25V
-25V
1
+25V
-25V
2
+25V
R121
1K
0603
This is the source of -25V
nPWM_ERR_PUMP
C120
4700pF
0805
1
R122
820
0603
R124
4.99K
R125
R126
Q31
FMMT493A
SOT-23
2K
0603
C
R127
681
0603
C123
.47uF
1206
X7R
-25V
B
Output Header
Optional +5V Switching Regulator
B
C124
0.01uF
0603
3
SYNC_2670
BOOTSTRAP
+25V
VIN
5
SYNC
SWITCH
+25V
7
ON/OFF
8
TAB
GND
U12
GND
OUT1+
OUT2-
OUT2-
OUT3+
OUT3+
OUT4-
OUT4-
+25V
22uH
10%
FDBK
OUT1+
+25V
L8
1
LM2670S-ADJ
C130
100pF
0603
4
C125
0.1uF
0805
2
SWITCH
SYNC_2670
R128
+
4.53K
0603
6
R129
D29
SS36
R130
1K
0603
16.2K
0603
C191
1000uF
25V
PW SERIES
C192
0.1uF
0805
+
C126
1000uF
25V
PW SERIES
C127
0.1uF
0805
+5V
C131
C136
0.1uF
0603
+100uF
+
6.3VDC
TANT
C193
1000uF
25V
PW SERIES
R131
NS
0603
C194
0.1uF
0805
+
C135
1000uF
25V
PW SERIES
1
2
3
4
5
6
7
8
9
10
11
12
C138
0.1uF
0805
TSW-112-06-T-S-LL
HDR12X1
Speaker Out 1+
Speaker Out 1Speaker Out 2+
Speaker Out 2+V Input
+V Input
PWRGND
PWRGND
Speaker Out 3+
Speaker Out 3Speaker Out 4+
Speaker Out 4-
J3
-25V
-25V
SWGND
-25V
PWR_GND
R132
LM2670
TO-263
0-Ohm
0805
A
8 - Tab = GND
7 - On/Off
6 - Feedback
5 - Sync Input
4 - GND
3 - BootStrap
2 - Input
1 - Switch Output
Vout = Vfb ( 1 + R2 / R1 )
A
R1 = 1k, Vfb = 1.21V
R2 = R1 ( Vout / Vfb - 1 )
Vout = +5V : R2 = 3.13K
D2Audio
7600 B Capital Of Texas HWY N
Suite 130
Austin, TX 78731
Vout = +6.4V : R2 = 4.29K
Title
5
4
3
2
TXS25-4 Reference
Size
C
Document Number
Date:
Monday, January 30, 2006
System Engineering
Rev
02R1
Pump, Output Header, +5V SMPS
0070-C00085-000
Sheet
1
5
of
10
Application Note 1435
100
0603
2
Q30
FMMT593-PNP
SOT-23
C
C122
100pF
0603
D25
EP05Q04
0603
AN1435.0
February 25, 2009
Hardware Schematics (Continued)
Breakway - Headers and Sub-Out
5
4
3
Misc Signal Header
HDR 15X2
31
1
3
5
7
9
B-SPDIFTX
11
B-XSCLK0
13
B-XLRCK0
15
B-XSDIN1
17
B-XLRCK1
19
B-MCLKT
21
B-GPIO0
23
B-nERROR
25
B-BOOT_EE/I2C27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
TSW-115-06-T-D-LL
D
HDR 3X2
1
3
5
GNDB
B-ADC_MCLK
GNDB
D
B-MCLKT-H
B-SCLKT
B-LRCKT
B-SDOUT0
B-SDOUT1
J7
J8
+1.8VB
HDR 4X1
+3.3VB
+5VB
+5VB
+3.3VB
+1.8VB
4
3
2
1
B-MCLKT-H
C144
0.1uF
0603
J9
LED3
1 B-nERROR
2
+5VB
+5VB
+3.3VB
+3.3VB
+1.8VB
+1.8VB
To/From USB & Reset Page
B-BOOT_EE/I2C
+
C142
22uF
6.3VDC
C143
0.1uF
0603
+
C140
0.1uF
0603
C141
22uF
6.3VDC
B-SDA
C139
22uF
6.3VDC
+
B-SCL
B-nRESET
RED LED
LED0603
B-nRESET
B-ADC_MCLK
B-XSCLK0
B-XLRCK0
B-XSDIN0
B-XSCLK1
Subwoofer Low Pass Filter and Output Jack
B-XLRCK1
B
B-XSDIN1
L9
B-PWM3H
TP10
R137
10K
0603
22uF
6.3VDC
330uH
1210
R136
33.2
0603
R139
10K
0603
GNDB
C148
L10
+
B-PWM3L
22uF
6.3VDC
330uH
1210
1
B-SCL
B-nRESET
C146
0.1uF
0603
C147
0.1uF
0603
R138
10K
0603
B-nRESET
ADC_MCLK
B-XSCLK0
B-XLRCK0
B-XSDIN0
B-XSCLK1
B-XLRCK1
B
B-XSDIN1
J10
2
C145
+
TP9
B-SDA
To/From ADC Page
GNDB
Ground Loop Test Points
C
B-BOOT_EE/I2C
To/From SPDIF Page
B-SPDIFRX
B-SPDIFRX
B-SPDIFTX
B-SPDIFTX
R140
10K
0603
R141
33.2
0603
AGND
A
A
D2Audio
7600 B Capital Of Texas HWY N
Suite 130
Austin, TX 78731
Title
5
4
3
2
TXS25-4 Reference
Size
B
Document Number
Date:
Monday, January 30, 2006
0070-C00085-000
System Engineering
Rev
02R1
Breakaway - Headers & Sub Out
Sheet
1
6
of
10
Application Note 1435
100
0603
B-XSCLK1
B-XLRCK1
B-XSDIN1
2
4
6
2
4
6
8
10
Power Header
33.2
0603
R135
HDR 5X2
1
3
5
7
9
J5
GNDB
R134
+3.3VB
I2S Output Header
B-XSCLK0
B-XLRCK0
B-XSDIN0
2
4
6
GNDB
GNDB
33.2
0603
B-MCLKT
B-nRESET
2
4 B-BOOT_EE/I2C
B-nERROR
6
B-GPIO0
8
B-GPIO1
10
B-PSSYNC
12
J6
B-PWM3H
B-PWM3L
B-GPIO1
B-PSSYNC
+5VB
R133
C
HDR 3X2
1
3
5
HDR6X2
1
3
5
7
9
11
Global Power Rails
J4
GNDB
GNDB
B-LRCKT
B-SDOUT1
B-SCLKT
B-SCL
B-nRESET
B-SPDIFRX
B-XSDIN0
B-XSCLK1
1
I2S Input Headers
Interconnect Header
+3.3VB
+1.8VB
B-SDOUT0
B-SDA
2
AN1435.0
February 25, 2009
Hardware Schematics (Continued)
Breakway - USB and Reset
5
4
3
2
1
+3.3VB
+3.3VB
R143
10K
0603
LED6
GRN LED
LED0603
8
18pF
7
Y3
16MHZ
1.5K
0603
USB_VREF 14
USB_DUSB_D+
R150
22
0603
nATMEL_RST
USB_PLLF
J12
GNDB
C153
2200pF
0805
NPO
R151
100
0603
XTALO
VREF
DD+
P4.0/SCL
P4.1/SDA
23
RST
11
PLLF
9
22
1
SW2
2
System
Reset
Switch
12
13
XTALI
AVSS
VSS
LED3/P3.7
LED2/P3.6
LED1/P3.5
T0/P3.4
LED0/P3.3
INT0/P3.2
TxD/P3.1
RxDP3.0
4
5
21
20
19
18
17
16
15
10
5
+3.3VB
Jumper to
Re-Program
Atmel
Flash
1
J11
2
R147
4.75K
0603
R148
4.75K
0603
GNDB
B-SCL
B-SDA
C
HDR1X2
B-SCL
B-SDA
USB_LED3
USB_LED2
USB_LED1
1
3
USB_LED0
2
4
J13
I2C
Header
HDR2X2
GNDB
AT89C5131A
+3.3VB
B-nRESET
3
C154
0.01uF
0603
U16
B-nRESET
+3.3VB
R152
10K
0603
Vcc
nRESET
R153
2
B
Q32
MMBT2907A
SOT23
1
10K
0603
C155
0.01uF
0603
LED8
RED LED
LED0603
Reset
1
1
GNDB
GND
DS1233AZ
B
2
1
2
3
4
5
6
UNBUFF_BOOT_I2C/EE
3
2
1
28
27
26
25
24
R154
100
0603
GNDB
R155
NS
0603
Optional if Q6
not needed.
2
GNDB
ATMEL_RST_CTRL
R156
A
3
4.75K
0603
A
Q33
MMBT2907A
SOT23
1
D2Audio
7600 B Capital Of Texas HWY N
Suite 130
Austin, TX 78731
GNDB
Title
5
4
3
2
TXS25-4 Reference
Size
B
Document Number
Date:
Monday, January 30, 2006
0070-C00085-000
System Engineering
Rev
02R1
Breakaway - USB & Reset
Sheet
1
7
of
10
Application Note 1435
PWR
DD+
GND
CASE
CASE
6
18pF
MOSI/P1.7
SCK/P1.6
MISO/P1.5
P1.4
P1.3
P1.2
SS/P1.1
P1.0
23
USB
Input
C152
VDD
GND
22
0603
B-BOOT_EE/I2C
GNDB
4
C
USB-B Conn
B-BOOT_EE/I2C
OE
U15
C151
0603
R149
R145
10K
0603
NC7SZ125
4
nBOOTMODE_BUFFER_EN
0.1uF
0603 GNDB
GNDB
LED7
GRN LED
LED0603
U14
GND
C150
GNDB
R146
VCC
2
C149
0.1uF
0603
+3.3VB
SW1
0603
+3.3VB
USB
Active
1
LED5
GRN LED
LED0603
2
5
LED4
GRN LED
LED0603
I2C
Active
D
1
Case
Load
Active
2
4
Load
Complete
1
Case
VOL1
2
3
2
2
B
1
32
COM
+3.3VB
R144
10K
0603
VOL0
1
Master
Volume
+3.3VB
+3.3VB
2-BIT ENCODER
1
A
3
R142
10K
0603
D
AN1435.0
February 25, 2009
Hardware Schematics (Continued)
Breakway - ADC
5
+3.3VB
4
+3.3VB
+5VB
C156
2
R160
10K
0603
D
R158
+
1
22uF
6.3VDC
C157
2700pF
0805
C160
NPO
+
C158
22uF
6.3VDC
R159
10K
0603
C159
0.1uF
0603
AGND
AGND
+
C163
+
1
2
33
R164
10K
0603
AIN2+
100
0603
22uF
6.3VDC
C161
22uF
6.3VDC
C162
0.1uF
0603
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ADC_VCOM
ADC_AVDD
+5VB
DIF
10
0603
C164
2700pF
0805
NPO
C168
ADC_MCLK
ADC_OVFLW
ADC_MCLK
AIN2-
+
22uF
6.3VDC
1
R168
10K
0603
2
C
GNDB
LIN1+
LIN1RIN1+
RIN1M/S
CKS
PDN
DVSS
DVDD
TVDD
SDTO1
SDTO2
SCLK
LRCLK
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+5VB
AIN1+
AIN1AIN2+
AIN2-
D
R161
10K
0603
CKS
ADC_RESET
D30
2
+5VB
1
B-nRESET
B-nRESET
EP05Q04
+3.3VB
ADC_SDAT0
ADC_SDAT1
ADC_SCLK
ADC_LRCK
R192
10K
0603
C167
0.1uF
0603
C166
0.1uF
0603
+
C165
22uF
6.3VDC
U17
R167
100
0603
R166
R165
47.5
0603
AIN3+
100
0603
22uF
6.3VDC
ADC
OVFLW
LED9
RED LED
LED0603
GNDB
C171
2700pF
0805
NPO
C172
C170
33pF
0603
C
1
C169
+
AIN3
LIN2+
LIN2RIN2+
RIN2TEST
VCOM
AVSS
AVDD
DIF
TDM1
TDM0
TDMIN
MCLK
OVF
2
AGND
J16
0-ohm
0603
AK5384
R162
R163
AGND
AIN3+
AIN3AIN4+
AIN4-
+
22uF
6.3VDC
J15
1
R157
AIN1+
100
0603
AIN1-
AIN2
2
+5VB
J14
AIN1
3
+5VB
AIN3-
+
GNDB
22uF
6.3VDC
AGND
+3.3VB
5
R169
VCC
2
4
U19
NC7SZ125
C176
0.1uF
0603
GND
AIN4-
B-XSCLK0
ADC_SCLK
2
B-XSCLK0
33.2
0603
R170
4
U18
NC7SZ125
C175
0.1uF
0603
GND
+
B-XSCLK1
B-XSCLK1
B-XLRCK1
B-XLRCK1
B-XSDIN1
B-XSDIN1
33.2
0603
nEN_ADC_I2S1
nEN_ADC_I2S0
22uF
6.3VDC
AGND
R171
1
C174
2700pF
0805
C177
NPO
3
ADC_SCLK
100
0603
22uF
6.3VDC
VCC
1
R172
10K
0603
AIN4+
3
2
1
GNDB
GNDB
+3.3VB
5
5
+3.3VB
B
B
VCC
R173
VCC
U21
NC7SZ125
C179
0.1uF
0603
3
GND
R174
B-XLRCK0
ADC_LRCK
2
B-XLRCK0
33.2
0603
4
U20
NC7SZ125
C178
0.1uF
0603
GND
33.2
0603
1
4
3
2
1
ADC_LRCK
nEN_ADC_I2S1
nEN_ADC_I2S0
+3.3VB
GNDB
GNDB
R176
10K
0603
+3.3VB
5
+3.3VB
5
R175
10K
0603
VCC
HDR2X2
R177
VCC
2
C181
0.1uF
0603
J18
GNDB
4
U23
NC7SZ125
GND
R178
B-XSDIN0
33.2
0603
ADC_SDAT1
2
B-XSDIN0
C180
0.1uF
0603
NC7SZ125
GND
33.2
0603
nEN_ADC_I2S1
nEN_ADC_I2S0
A
4
U22
1
ADC_SDAT0
3
nEN_ADC_I2S0
nEN_ADC_I2S1
1
2
4
3
1
3
A
D2Audio
7600 B Capital Of Texas HWY N
Suite 130
Austin, TX 78731
GNDB
GNDB
Title
5
4
3
2
TXS25-4 Reference
Size
B
Document Number
Date:
Monday, January 30, 2006
0070-C00085-000
System Engineering
Rev
Breakaway - ADC
Sheet
1
02R1
8
of
10
Application Note 1435
C173
+
AIN4
5
+3.3VB
J17
AN1435.0
February 25, 2009
Hardware Schematics (Continued)
Breakway - SPDIF I-O
+3.3VB
5
+5VB
TORX173
2
+5VB
GND
C182
0.1uF
0603
+5VB
4
B-SPDIFRX
GND
R180
100
0603
+3.3VB
U24
GNDB
+3.3VB
+3.3VB
5
6
+3.3VB
B-SPDIFRX
100
0603
2
C183
0.1uF
0603
GND 2
R179
GNDB
34
SPDIF
Input
Selector
1
2
3
J19
HDR 3X1
Coaxial
SPDIF
Enabled
LED10
GRN LED
LED0603
R181
1K
0603
1
VCC 3
U25
1
SPDIF
Optical
Input
1
3
OUT
NC7SZ125
4
VCC
Optical RX
R182
COAX/OPTICAL
Q34
MMBT2222A
SOT-23
4.75K
0603
GNDB
GNDB
+3.3VB
+3.3VB
3
4
C185
0.1uF
0603
NC7SZ04
4
U26
GND
VCC
2
U27
C186
0.1uF
0603
N/C
GND
R183
4
NC7SZ126
4.75K
0603
T1
GNDB
GNDB
R187
1
R186
+3.3VB
10K
0603
GNDB
R189
10K
0603
NS
0603
Optical
SPDIF
Enabled
LED11
GRN LED
LED0603
GNDB
Application Note 1435
R185
0-ohm
0603
Q35
MMBT2907A
SOT23
2
2
0.01uF
0603
1
6
3
1
R184
75
0603
3
VCC
C184
1
1
5
J20
2
SPDIF
Coax
Input
5
+3.3VB
R188
100
0603
R190
10K
0603
GNDB
GNDB
GNDB
TOTX173
Optical TX
B-SPDIFTX
+5VB
R191
8.06K
0603
IN
3
VCC
2
I-LIM
1
SPDIF
Sub/Downmix
Out
GND
5
C187
0.1uF
0603
4
6
B-SPDIFTX
U28
GNDB
D2Audio
7600 B Capital Of Texas H
Suite 130
Austin, TX 78731
Title
5
4
3
2
TXS25-4 Reference
Size
B
Document Number
Date:
Monday, January 30, 2006
0070-C00085-000
System
Breakaway - SPDIF I-O
Sheet
1
9
of
AN1435.0
February 25, 2009
Hardware Schematics (Continued)
Breakway Output Board
B-OUT1+
2
1
B-OUT1-
J23
NS
J36
1
2
Red
Retrofit
Option
B-OUT1+
B-OUT2+
J37
2
1
2
1
1
35
B-OUT1-
2
Black
B-OUT2-
J26
J38
1
B-OUT2+
J39
B-OUT1+
B-OUT1B-OUT2+
B-OUT2B-HV+
B-HV+
B-PWRGND
B-PWRGND
B-OUT3+
B-OUT3B-OUT4+
B-OUT4-
C188
+
4700uF
35V
PW SERIES
C189
4700uF
35V
PW SERIES
C190
0.1uF
0805
1
2
3
4
2
2
+25V
GND
J40
Red
J28
2
+
1
C195
0.1uF
0805
B-OUT2-
1
1
Black
HDR4X1
Application Note 1435
TSW-112-06-T-S-LL
HDR12X1
1
2
3
4
5
6
7
8
9
10
11
12
2
Red
NS
Retrofit
Option
B-OUT3+
J27
J41
2
2
1
1
Black
B-OUT3B-OUT3+
J42
1
2
Red
B-OUT3-
2
1
B-OUT4+
J31
J43
2
2
B-OUT4-
Retrofit
Option
1
1
Black
NS
B-OUT4+
2
1
B-OUT4-
D2Audio
7600 B Capital Of Texas HWY N
Suite 130
Austin, TX 78731
J34
NS
Title
Retrofit
Option
Size
B
Date:
5
4
3
2
TXS25-4 Reference
Document Number
0070-C00085-000
System Engineering
Rev
Breakaway Output Board
Monday, January 30, 2006
Sheet
1
10
of
02R1
10
AN1435.0
February 25, 2009
Application Note 1435
Revisions
09/30/08
02/6/06
• Updated Intersil and D2Audio name references.
Revision 0.0.1 - First Internal Release.
Revision 1.0.2 (revision 1.0.1 not released)
Leveraged existing TXS25-2 evaluation document and
updated with basic TXS25-4 information including signal
flow, connection diagrams, jumper configurations,
schematics, and images.
• Updated and revised photos to better represent platform
02/14/06
• Update to signal flow diagram to include D2Audio
SoundSuite
Revision 0.0.2 - Second Internal Release.
• Moved Master Volume in “ Required Power Source”
• Updated 8/4 ohm text and ground referencing text on
page 7
• Added updates to power supply references.
• Rewording and text additions throughout for clarity.
10/14/08 Revision 1.0.3 (revision 1.0.1 not released)
• Conversion from book file to Frame
• Updated “TABLE 3. DEFAULT DIGITAL/ANALOG
AUDIO/CONTROL I/O BOARD FACTORY JUMPER
SELECTION” values
• Added continuous sine wave note in See “Testing Setup”
on page 21.
• Added 32-192kHz range in See “Testing with Digital Inputs
(Recommended Setup)” on page 21. and See “Testing
with Analog Inputs” on page 23.
• Updated full scale output text in Table 7 on page 24
Replaced mentions of “module” with “amplifier design”
02/15/06
Revision 1.0.0 - First Public Release.
• Updated verbiage on page 7 to improve clarity.
• Updated “ ”
• Updated verbiage and added additional graphics to page
16 in order to describe exactly how to select an analog
input, S/PDIF input or I2S/Left-Justified input.
D2™, D2A™, D2Audio™, D2Audio 360°Sound™, D2Audio AccuMatrix™, D2Audio Acoustical Speaker Detect™, D2Audio AFRC
(Automatic Frequency Response Compensation)™, D2Audio ARMC (Automatic Room Mode Correction)™, D2Audio Audio
Canvas™, D2Audio AudioAlign™, D2Audio Canvas™, D2Audio Canvas 2.0™, D2Audio Canvas II™, D2Audio ClearVoice™,
D2Audio DeepBass™, D2Audio DigitalEQ™, D2Audio Electrical Speaker Detect™, D2Audio HILO™, D2Audio LEO (Listenting
Environment Optimization)™, D2Audio LEOxpc™, D2Audio Load Monitor™, D2Audio Mono2Stereo™, D2Audio Multi-Crossover
Digital Bass Management™, D2Audio MultiMix™, D2Audio Multi-Mix™, D2Audio Page-In™, D2Audio Sound Pressure
Normalization™, D2Audio SoundSuite™, D2Audio Speaker Detect™, D2Audio Speaker Distance™, D2Audio Speaker EQ
(SPEQ)™, D2Audio Speaker Fingerprint™, D2Audio Speaker Impedance™, D2Audio Speaker Polarity™, D2Audio WideSound™,
Digital Audio Engine™ and DAE-3™ are trademarks of D2Audio Corporation.
Audistry™ by Dolby, Dolby Headphone™, Dolby Pro Logic II, Dolby Pro Logic II/IIx™, Dolby Pro Logic II™, Dolby Virtual
Speaker™, and Surround EX™ are trademarks of Dolby Laboratories Licensing Corporation. Audyssey 2EQ™, Audyssey EQ™,
Audyssey MultEQ Pro™, Audyssey MultEQ XT™ and Audyssey MultEQ™ are trademarkss of Audyssey Laboratories, Inc. BBE™
is a trademark of BBE Sound, Inc. DTS Neo:6™ is a trademark of Digital Theater Systems, Inc. Logic 7™ is a trademark of
Harman International Industries, Incorporated. Microsoft™, Windows™ XP, Windows™ 2000 are trademarks of Microsoft
Corporation. SRS Definition™, SRS Dialog Clarity™, SRS FOCUS™, SRS Headphone 360™, SRS TruBass™, SRS TruSurround
HD™, SRS TruSurround HD4™, SRS TruSurround XT HD/HD4™, SRS TruSurround XT™, SRS TruSurround™, SRS WOW
HD™ and SRS WOW™ are trademarks of SRS Labratories, Inc. THX Adaptive De-Correlation™, THX Advanced Speaker Array
(ASA)™, THX Bass Management with Bass Peak Limiter™, THX Boundary Gain Compensation (BGC)™, THX Cinema Re-EQ™,
THX™ Ultra2™ and THX™ Select™ are trademarks of THX Ltd.
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
36
AN1435.0
February 25, 2009