DATASHEET Low-Voltage, Single and Dual Supply, Quad SPDT, High Performance Analog Switch ISL43240 Features The Intersil ISL43240 device is a CMOS, precision, quad SPDT analog switch designed to operate from a single +2V to +12V supply or from a ±2V to ±6V supply. Targeted applications include battery powered equipment that benefit from the devices’ low power consumption (5µW), low leakage currents (5nA max), and fast switching speeds (tON = 52ns, tOFF = 40ns). A 5Ω maximum rON flatness ensures signal fidelity, while channel-to-channel mismatch is guaranteed to be less than 2Ω. • Fully specified for 10% tolerances at VS = ±5V and V+ = 12V, 5V and 3.3V • Four separately controlled SPDT switches • ON-resistance (rON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Ω • rON matching between channels . . . . . . . . . . . . . . . . . . . . . . . <1Ω • Low charge injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5pC (Max) • Low power consumption (PD) . . . . . . . . . . . . . . . . . . . . . . . . <5µW The ISL43240 is a quad single-pole/double-throw (SPDT) device and can be used as a quad SPDT, a quad 2:1 multiplexer, a single 4:1 multiplexer or a dual 2-channel differential multiplexer. • Low off leakage current (max at +85°C) . . . . . . . . . . . 2.5nA • Fast switching action - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Table 1 summarizes the performance of this family. • Guaranteed break-before-make • Minimum 2000V ESD protection per Method 3015.7 TABLE 1. FEATURES AT A GLANCE CONFIGURATION ±4.5V rON • Pb-free (RoHS compliant) 18Ω ±4.5V tON/tOFF Applications 52ns/40ns 10.8V rON 14Ω 10.8V tON/tOFF • Battery powered, handheld, and portable equipment - Barcode scanners - Laptops, notebooks, palmtops 40ns/27ns 4.5V rON 30Ω 4.5V tON/tOFF 64ns/29ns 3V rON 51Ω 3V tON/tOFF Packages • TTL, CMOS compatible QUAD SPDT 120ns/50ns 20 Ld SSOP, 20 Ld QFN 4x4 Related Literature • TB363, “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • AN557, “Recommended Test Procedures for Analog Switches” December 15, 2014 FN6036.3 1 • Communications systems - Radios - XDSL and PBX/PABX - RF “Tee” switches - Base stations • Test equipment - Medical ultrasound - Electrocardiograph - ATE • Audio and video switching • General purpose circuits - +3V/+5V DACs and ADCs - Digital filters - Operational amplifier gain switching networks - High frequency analog switching - High speed multiplexing CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2003, 2004, 2014. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL43240 Pin Configurations (Note 1) IN1 1 20 IN4 NO1 IN1 IN4 NO4 ISL43240 (QFN) TOP VIEW N.C. ISL43240 (SSOP) TOP VIEW NO1 2 19 NO4 20 19 18 17 16 15 COM4 NC1 2 14 NC4 V- 3 13 V+ GND 4 12 NC3 NC2 5 11 COM3 16 V+ GND 6 15 N.C. NC2 7 14 NC3 COM2 8 13 COM3 NO2 9 12 NO3 IN2 10 11 IN3 6 7 8 9 10 NO3 1 IN3 V- 5 COM1 IN2 17 NC4 NO2 18 COM4 NC1 4 COM2 COM1 3 NOTE: 1. Switches shown for Logic “0” input. Truth Table Pin Descriptions ISL43240 ISL43240 PIN V+ Positive Power Supply Input V- Negative Power Supply Input. Connect to GND for Single Supply Configurations. LOGIC NO SW NC SW 0 OFF ON 1 ON OFF NOTE: Logic “0” ≤ 0.8V. Logic “1” ≥2.4V. FUNCTION GND Ground Connection IN Digital Control Input COM NO Analog Switch Common Pin Analog Switch Normally Open Pin NC Analog Switch Normally Closed Pin N.C. No Internal Connection Ordering Information PART NO. (Notes 2, 3, 4) PART MARKING TEMP. RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # ISL43240IAZ 43240 IAZ -40 to 85 20 Ld SSOP M20.209 ISL43240IRZ 43240IRZ -40 to 85 20 Ld QFN L20.4x4 NOTES: 2. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. For Moisture Sensitivity Level (MSL), please see product information page for ISL43240. For more information on MSL, please see tech brief TB363. Submit Document Feedback 2 FN6036.3 December 15, 2014 ISL43240 Absolute Maximum Ratings Thermal Information V+ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to 0.3V All Other Pins (Note 5) . . . . . . . . . . . . . . . . . . . . .((V-) - 0.3V) to ((V+) + 0.3V) Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current, IN, NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . . . . . . . 100mA ESD Rating (Per MIL-STD-883 Method 3015) . . . . . . . . . . . . . . . . . . . . >2kV Thermal Resistance (Typical) Operating Conditions JA (°C/W) 150 20 Ld SSOP Package (Note 6) . . . . . . . . . . . . . . . . . . . . 20 Ld QFN Package (Note 7). . . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C Moisture Sensitivity (See TB363) All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . +300°C (SSOP - Lead Tips Only) Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Temperature Range ISL43240IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. Signals on NC, NO, COM, or IN exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings. 6. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 7. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. Electrical Specifications ±5V Supply Test Conditions: VSUPPLY = 4.5V to 5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 7), Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP (°C) MIN (Note 8) Full V- - V+ V 25 - 18 25 Ω TYP MAX (Note 8) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, rON VS = 4.5V, ICOM = 10mA, VNO or VNC = 3.5V, See Figure 5 Full - - 30 Ω rON Matching Between Channels, rON VS = 4.5V, ICOM = 10mA, VNO or VNC = 3V 25 - 0.5 2 Ω rON Flatness, RFLAT(ON) VS = 4.5V, ICOM = 10mA, VNO or VNC = 0V, 3V, Note 10 Full - - 4 Ω 25 - - 5 Ω Full - - 5 Ω - 0.2 nA NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) VS = 5.5V, VCOM = 4.5V, VNO or VNC = +4.5V, Note 9 25 -0.2 Full -2.5 - 2.5 nA COM ON Leakage Current, ICOM(ON) VS = 5.5V, VCOM = VNO or VNC = 4.5V, Note 9 25 -0.4 - 0.4 nA Full -5 - 5 nA Input Voltage High, VINH Full 2.4 1.6 - V Input Voltage Low, VINL Full - 1.5 0.8 V VS = 5.5V, VIN = 0V or V+ Full -1 - 1 µA VS = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 1 25 - 52 65 ns Full - - 75 ns 25 - 40 50 ns DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF VS = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 1 Full - - 55 ns Break-before-make Time Delay, tD VS = 5.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 3 Full 10 19 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - - 5 pC NO OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 10 - pF NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 10 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 30 - pF OFF Isolation RL = 50Ω, CL = 15pF, f = 1MHz, VNO or VNC = 1VRMS, See Figures 4 and 6 25 - 71 - dB Crosstalk, Note 11 25 - -92 - dB Power Supply Rejection Ratio RL = 50Ω, CL = 5pF, f = 1MHz 25 - 59 - dB Submit Document Feedback 3 FN6036.3 December 15, 2014 ISL43240 Electrical Specifications ±5V Supply Test Conditions: VSUPPLY = 4.5V to 5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 7), Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP (°C) MIN (Note 8) Full 25 TYP MAX (Note 8) 2 - 6 V -1 0.01 1 µA UNITS POWER SUPPLY CHARACTERISTICS Power Supply Range VS = 5.5V, VIN = 0V or V+, Switch On or Off Positive Supply Current, I+ Negative Supply Current, I- Full -1 - 1 µA 25 -1 0.01 1 µA Full -1 - 1 µA NOTES: 8. VIN = Input voltage to perform proper function. 9. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 10. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at +25°C. 11. Flatness is defined as the delta between the maximum and minimum rON values over the specified voltage range. 12. Between any two switches. Electrical Specifications 5V Supply Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 7), Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP (°C) MIN (Note 8) Full 0 - V+ V 25 - 30 40 Ω TYP MAX (Note 8) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-resistance, rON V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V, See Figure 5 Full - - 50 Ω rON Matching Between Channels, rON V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3V 25 - 0.5 3 Ω rON Flatness, RFLAT(ON) V+ = 5.5V, ICOM = 1.0mA, VNO or VNC = 1V, 2V, 3V, Note 10 NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V, Note 9 COM ON Leakage Current, ICOM(ON) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 1V, 4.5V Note 9 Full - - 4 Ω 25 - 4.4 6 Ω Full - - 8 Ω nA 25 -0.2 - 0.2 Full -2.5 - 2.5 nA 25 -0.4 - 0.4 nA Full -5 - 5 nA Input Voltage High, VINH Full 2.4 1.5 - V Input Voltage Low, VINL Full - 1.4 0.8 V V+ = 5.5V, VIN = 0V or V+ Full -1 - 1 µA V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 1 25 - 64 80 ns Full - - 90 ns V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 1 25 - 29 40 ns Full - - 45 ns DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-before-make Time Delay, tD V+ = 5.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 3 Full 15 39 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0ΩSee Figure 2 25 - 1.2 2 pC NO OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 10 - pF NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 10 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 30 - pF OFF Isolation 25 - 71 - dB Crosstalk, Note 11 RL = 50Ω, CL = 15pF, f = 1MHz, VNO or VNC = 1VRMS, See Figures 4 and 6 25 - -92 - dB Power Supply Rejection Ratio RL = 50Ω, CL = 5pF, f = 1MHz 25 - 59 - dB Submit Document Feedback 4 FN6036.3 December 15, 2014 ISL43240 Electrical Specifications 5V Supply Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 7), Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP (°C) MIN (Note 8) TYP MAX (Note 8) UNITS 25 -1 0.01 1 µA POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 5.5V, V- = 0V, VIN = 0V or V+, Switch On or Off Negative Supply Current, I- Electrical Specifications 3.3V Supply Full -1 - 1 µA 25 -1 0.01 1 µA Full -1 - 1 µA Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 7), Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP (°C) MIN (Note 8) TYP MAX (Note 8) UNITS Full 0 - V+ V ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, rON V+ = 3V, ICOM = 1.0mA, VNO or VNC = 1.5V, See Figure 5 25 - 51 60 Ω Full - - 70 Ω rON Matching Between Channels, rON V+ = 3V, ICOM = 1.0mA, VNO or VNC = 1.5V 25 - 0.5 3 Ω rON Flatness, RFLAT(ON) V+ = 3V, ICOM = 1.0mA, VNO or VNC = 0.5V, 1.5V, Note 10 NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 3.6V, VCOM = 1V, 3V, VNO or VNC = 3V, 1V, Note 9 COM ON Leakage Current, ICOM(ON) V+ = 3.6V, VCOM = 1V, 3V, VNO or VNC = 1V, 3V, Note 9 Full - - 4 Ω 25 - 12 17 Ω Full - - 17 Ω 25 -0.2 - 0.2 nA Full -2.5 - 2.5 nA 25 -0.4 - 0.4 nA Full -5 - 5 nA Input Voltage High, VINH Full 2.4 1.0 - V Input Voltage Low, VINL Full - 0.9 0.8 V V+ = 3.6V, VIN = 0V or V+ Full -1 - 1 µA Turn-ON Time, tON V+ = 3.0V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 1 25 - 120 138 ns Turn-OFF Time, tOFF V+ = 3.0V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 1 DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL DYNAMIC CHARACTERISTICS Full - - 160 ns 25 - 50 60 ns Full - - 65 ns V+ = 3.6V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 3 Full 30 60 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0ΩSee Figure 2 25 - 1 2 pC NO OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 10 - pF NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 10 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 30 - pF OFF Isolation 25 - 71 - dB Crosstalk, Note 11 RL = 50Ω, CL = 15pF, f = 1MHz, VNO or VNC = 1VRMS, See Figures 4 and 6 25 - -92 - dB Power Supply Rejection Ratio RL = 50Ω, CL = 5pF, f = 1MHz 25 - 59 - dB µA Break-before-make Time Delay, tD POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 3.6V, V- = 0V, VIN = 0V or V+, Switch On or Off Negative Supply Current, I- Submit Document Feedback 5 25 -1 0.01 1 Full -1 - 1 µA 25 -1 0.01 1 µA Full -1 - 1 µA FN6036.3 December 15, 2014 ISL43240 Electrical Specifications 12V Supply Test Conditions: V+ = +10.8V to +13.2V, V- = GND = 0V, VINH = 3.0V, VINL = 0.8V (Note 7), Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP (°C) MIN (Note 9) TYP MAX (Note 9) UNITS Full 0 - V+ V ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-resistance, rON V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 9V, See Figure 5 25 - 14 20 Ω Full - - 30 Ω rON Matching Between Channels, rON V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 9V 25 - 0.3 2 Ω rON Flatness, RFLAT(ON) V+ = 13.2V, ICOM = 1.0mA, VNO or VNC = 3V, 6V, 9V, Note 10 NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 13V, VCOM = 1V, 12V, VNO or VNC = 12V, 1V, Note 9 COM ON Leakage Current, ICOM(ON) V+ = 13V, VCOM = 1V, 12V, VNO or VNC = 1V, 12V Note 9 Full - - 4 Ω 25 - 1.7 2 Ω Full - - 3 Ω 25 -0.2 - 0.2 nA Full -2.5 - 2.5 nA 25 -0.4 - 0.4 nA Full -5 - 5 nA Input Voltage High, VINH Full 3.0 2.8 - V Input Voltage Low, VINL Full - 2.2 0.8 V V+ = 13.2V, VIN = 0V or V+ Full -1 - 1 µA Turn-ON Time, tON V+ = 10.8V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 1 25 - 40 50 ns Turn-OFF Time, tOFF V+ = 10.8V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 1 DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL DYNAMIC CHARACTERISTICS Full - - 83 ns 25 - 27 35 ns Full - - 40 ns V+ = 13.2V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, See Figure 3 Full 5 20 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0ΩSee Figure 2 25 - 12 14 pC NO OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 10 - pF NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 10 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 30 - pF OFF Isolation 25 - 71 - dB Crosstalk, Note 11 RL = 50Ω, CL = 15pF, f = 1MHz, VNO or VNC = 1VRMS, See Figures 4 and 6 25 - -92 - dB Power Supply Rejection Ratio RL = 50Ω, CL = 5pF, f = 1MHz 25 - 59 - dB µA Break-before-make Time Delay, tD POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 13V, VIN = 0V or V+, Switch On or Off Negative Supply Current, I- Submit Document Feedback 6 25 -1 0.01 1 Full -1 - 1 µA 25 -1 0.01 1 µA Full -1 - 1 µA FN6036.3 December 15, 2014 ISL43240 Test Circuits and Waveforms tr < 20ns tf < 20ns 3V LOGIC INPUT 50% V+ tON NC SWITCH INPUTS VOUT VNO tOFF LOGIC INPUT tOFF V- Logic input waveform is inverted for switches that have the opposite logic sense. CL 35pF RL 300Ω GND 25% 25% VOUT IN 75% 75% VNC COM NO VNO SWITCH OUTPUT C VNC 0V tON C C C Repeat test for all switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R L ON FIGURE 1A. MEASUREMENT POINTS FIGURE 1B. TEST CIRCUIT FIGURE 1. SWITCHING TIMES V+ SWITCH OUTPUT VOUT RG VOUT C COM VOUT NO or NC 3V LOGIC INPUT ON ON OFF VG GND IN CL 0V C Q = VOUT x CL Logic input waveform is inverted for switches that have the opposite logic sense. V- LOGIC INPUT Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 2B. TEST CIRCUIT FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION V+ 3V C C LOGIC INPUT VNX 0V NO SWITCH OUTPUT VOUT 0V tD RL 300Ω IN 80% LOGIC INPUT VOUT COM NC CL 35pF GND Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 3A. MEASUREMENT POINTS FIGURE 3B. TEST CIRCUIT FIGURE 3. BREAK-BEFORE-MAKE TIME Submit Document Feedback 7 FN6036.3 December 15, 2014 ISL43240 Test Circuits and Waveforms (Continued) V+ V+ C C rON = V1/1mA SIGNAL GENERATOR NO or NC NO or NC VNX 0V or 2.4V IN 1mA COM ANALYZER 0.8V or 2.4V IN V1 COM GND GND RL C V- V- Repeat test for all switches. C Repeat test for all switches. FIGURE 4. OFF ISOLATION TEST CIRCUIT FIGURE 5. RON TEST CIRCUIT V+ V+ C SIGNAL GENERATOR NO1 or NC1 50Ω COM1 NO or NC IN1 IN 0V or 2.4V IN2 0V or 2.4V COM2 ANALYZER NO CONNECTION NO2 or NC2 GND 0V or 2.4V IMPEDANCE ANALYZER COM GND RL V- C FIGURE 6. CROSSTALK TEST CIRCUIT Detailed Description The ISL43240 quad analog switches offer precise switching capability from a bipolar 2V to 6V or a single 2V to 12V supply with low on-resistance (18Ω) and high speed operation (tON = 52ns, tOFF = 40ns). The devices are especially well suited for portable battery powered equipment thanks to the low operating supply voltage (2V), low power consumption (5µW), low leakage currents (5nA max). High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection. Supply Sequencing and Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to V- (see Figure 8). Submit Document Feedback 8 V- FIGURE 7. CAPACITANCE TEST CIRCUIT To prevent forward biasing these diodes, V+ and V- must be applied before any input signals, and input signal voltages must remain between V+ and V-. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1kΩ resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. Adding a series resistor to the switch input defeats the purpose of using a low rON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These additional diodes limit the analog signal from 1V below V+ to 1V above V-. FN6036.3 December 15, 2014 ISL43240 The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. operating with dual or single 5V supplies the device draws only 10µA of current (see Figure 18 for VIN = 3V). Similar devices of competitors can draw 8 times this amount of current. High-Frequency Performance OPTIONAL PROTECTION DIODE V+ OPTIONAL PROTECTION RESISTOR INX VNO or NC VCOM VOPTIONAL PROTECTION DIODE FIGURE 8. OVERVOLTAGE PROTECTION In 50Ωsystems, signal response is reasonably flat even past 200MHz (see Figure 19). Figure 19 also illustrates that the frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An off switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed-through from a switch’s input to its output. Off Isolation is the resistance to this feed-through, while Crosstalk indicates the amount of feed-through from one switch to another. Figure 20 details the high Off Isolation and Crosstalk rejection provided by this switch. At 10MHz, off isolation is about 50dB in 50Ωsystems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage Considerations Power-Supply Considerations The ISL43240 construction is typical of most CMOS analog switches, in that they have three supply pins: V+, V-, and GND. V+ and V- drive the internal CMOS switches and set their analog voltage limits, so there are no connections between the analog signal path and GND. Unlike switches with a 13V maximum supply voltage, the ISL43240 15V maximum supply voltage provides plenty of room for the 10% tolerance of 12V supplies (6V or 12V single supply), as well as room for overshoot and noise spikes. This family of switches performs equally well when operated with bipolar or single voltage supplies. The minimum recommended supply voltage is 2V or 2V. It is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. Refer to the electrical specification tables starting on page 3 and Typical Performance curves on page 10 for details. Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and V-. One of these diodes conducts if any analog signal exceeds V+ or V-. Virtually all the analog leakage current comes from the ESD diodes to V+ or V-. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or V- and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and Vpins constitutes the analog-signal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and GND. V+ and GND power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switched V+ and V- signals to drive the analog switch gate terminals. Logic-Level Thresholds V+ and GND power the internal logic stages, so V- has no affect on logic thresholds. This switch family is TTL compatible (0.8V and 2.4V) over a V+ supply range of 2.5V to 10V (see Figure 17). At 12V the VIH level is about 2.8V. For best results with a 12V supply, use a logic family that provides a VOH greater than 3V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails (see Figure 18). Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. The ISL43240 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0V to V+). For example driving the device with 3V logic (0V to 3V) while Submit Document Feedback 9 FN6036.3 December 15, 2014 ISL43240 Typical Performance Curves 25 20 70 VCOM = (V+) - 1V ICOM = 1mA -40°C 30 20 35 +85oC +25°C V- = 0V +85°C +25°C -40°C 3 4 5 6 +85°C V+ = 5V 30 -40°C 7 8 V+ (V) 9 10 11 12 13 25 +25°C 20 -40°C 15 20 18 16 14 12 10 8 +85°C ICOM = 1mA 40 35 25 0 1 2 3 4 5 6 7 VCOM (V) 8 9 +25°C 20 -40°C 15 10 25 20 VS =5V V+ = 3V 0 VS =5V +85°C +25°C 12 V+ = 5V 5 Q (pC) +85°C 25 11 V+ = 12V VS =3V 30 10 10 -40°C 20 35 rON (Ω) V- = 0V 15 +25°C 30 V+ = 12V +25°C FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE VS =2V +85°C V- = 0V -40°C FIGURE 9. ON RESISTANCE vs POSITIVE SUPPLY VOLTAGE 45 ICOM = 1mA V- = 0V +25°C 40 V- = -3V 2 +85°C 50 +25°C -40°C V+ = 3V 60 rON (Ω) rON (Ω) 15 10 35 30 25 20 15 10 200 150 125 100 75 50 25 0 V- = -5V +85°C TA = 25°C, Unless Otherwise Specified -5 15 -40°C 10 -10 5 -5 -4 -3 -2 -1 0 1 2 3 4 5 -5 -2.5 0 VCOM (V) 7.5 10 50 VCOM = (V+) - 1V VCOM = (V+) - 1V V- = 0V 250 12.5 FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE 300 2.5 5 VCOM (V) V- = 0V 40 tOFF (ns) tON (ns) 200 +85°C 150 +25°C +85°C 30 +25°C 100 20 -40°C 50 0 2 3 4 5 6 7 8 9 10 11 V+ (V) FIGURE 13. TURN - ON TIME vs POSITIVE SUPPLY VOLTAGE Submit Document Feedback 10 12 10 -40°C 2 3 4 5 6 7 8 9 10 11 12 V+ (V) FIGURE 14. TURN - OFF TIME vs POSITIVE SUPPLY VOLTAGE FN6036.3 December 15, 2014 ISL43240 Typical Performance Curves 150 300 -40°C 250 200 -40°C 0 250 200 V- = -3V -40°C 50 2 50 3 4 5 6 7 V+ (V) 8 9 VINH 10 11 25°C 12 2 3 4 5 6 7 V+ (V) 8 9 10 11 12 FIGURE 16. TURN - OFF TIME vs POSITIVE SUPPLY VOLTAGE 70 V- = -5V to 0V V+ = +5V 60 85°C 1.5 50 1.0 V- = 0V to -5V 0.5 3.0 VINL 2.5 I+CC (A) -40°C 25°C 2.0 30 20 1.5 10 1.0 0.5 40 85°C 2 3 4 V- = 0V to -5V 6 5 7 8 V+ (V) 9 10 11 12 0 13 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 FIGURE 18. POSITIVE SUPPLY CURRENT vs DIGITAL INPUT VOLTAGE FIGURE 17. DIGITAL SWITCHING POINT vs POSITIVE SUPPLY VOLTAGE -10 VS = 2V or V+ = 5V (VIN = 4VP-P) -3 0 PHASE VS = 2V (VIN = 4VP-P) V+ = 5V (VIN = 4VP-P) VS = 5V (VIN = 5VP-P) V+ = 2.7V (VIN = 2VP-P) 45 90 135 180 RL = 50Ω 1 10 100 FREQUENCY (MHz) FIGURE 19. FREQUENCY RESPONSE Submit Document Feedback 11 600 CROSSTALK (dB) VS = 5V (VIN = 5VP-P) GAIN PHASE (DEGREES) 0 10 V+ = 3V to 12V or -20 VS = ±2V to ±5V RL = 50Ω -30 V+ = 2.7V (VIN = 2VP-P) 3 5 VIN (V) 20 30 -40 40 -50 50 -60 60 ISOLATION -70 70 -80 80 OFF ISOLATION (dB) VINH AND VINL (V) +85°C 0 -40°C 2.0 NORMALIZED GAIN (dB) +25°C 100 FIGURE 15. TURN - ON TIME vs POSITIVE SUPPLY VOLTAGE 2.5 V- = -3V -40°C 150 +85°C -40oC 0 3.0 0 300 200 +25°C +85°C -40°C 250 150 100 +25°C 50 +85°C tOFF (ns) 50 VCOM = (V+) - 1V V- = -5V +25°C 100 +25°C 100 -40°C VCOM = (V+) - 1V V- = -5V +25°C 150 tON (ns) TA = 25°C, Unless Otherwise Specified (Continued) CROSSTALK -90 90 ALL HOSTILE CROSSTALK -100 -110 1k 10k 100k 1M 10M 100 110 100M 500M FREQUENCY (Hz) FIGURE 20. CROSSTALK AND OFF ISOLATION FN6036.3 December 15, 2014 ISL43240 Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued) Die Characteristics V+ = 3V to 12V or VS = 2V to 5V RL = 50Ω 0 SUBSTRATE POTENTIAL (POWERED UP): VIN = 1VP-P V- PSRR (dB) 10 TRANSISTOR COUNT: 20 ISL43240: 418 30 PROCESS: -PSRR, SWITCH ON 40 Si Gate CMOS 50 60 +PSRR, SWITCH ON 70 0.3 1 10 100 FREQUENCY (MHz) 1000 FIGURE 21. PSRR vs FREQUENCY Submit Document Feedback 12 FN6036.3 December 15, 2014 ISL43240 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE December 15, 2014 FN6036.3 Made updates throughout datasheet to Intersil Standard. On page 2, updated the Ordering Information table to standard. -Removed Obsolete products (ISL43240IA, ISL43240IA, ISL43240IR and ISL43240IR-T). -Added Note 2, “Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.” -Added Note 4, “For Moisture Sensitivity Level (MSL), please see product information page for ISL43240. For more information on MSL, please see tech brief TB363” Added Revision History and About Intersil sections. Updated the L20.4x4 Package Outline Drawing on page 15 to the latest revision: Rev 1 to Rev 2 change: Change to Issue to "I" Change A1 to add 0.02 to Nominal Change A2 to add 0.65 to Nominal Change "b" Nominal to 0.25 Change D2 and E2, min to 1.95, nominal to 2.10 Change "L" min to 0.35, nominal to 0.60, max to 0.75 delete "L1" line and note 10 Change "k" min to 0.20 Remove the "5" from the "Ne" line under the min column Change Rev to Rev. 2 11/04 Rev 2 to Rev 3 change: Updated to new POD format by removing table listing dimensions and moving dimensions onto drawing. Added Typical Recommended Land Pattern. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 13 FN6036.3 December 15, 2014 ISL43240 Shrink Small Outline Plastic Packages (SSOP) M20.209 (JEDEC MO-150-AE ISSUE B) N INDEX AREA 20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE H 0.25(0.010) M E 2 3 0.25 0.010 SEATING PLANE -A- INCHES SYMBOL GAUGE PLANE -B1 B M A D -C- e A1 B 0.25(0.010) M L C 0.10(0.004) C A M B S MILLIMETERS MIN MAX NOTES A 0.068 0.078 1.73 1.99 0.002 0.008’ 0.05 0.21 A2 0.066 0.070’ 1.68 1.78 B 0.010’ 0.015 0.25 0.38 C 0.004 0.008 0.09 0.20’ D 0.278 0.289 7.07 7.33 3 E 0.205 0.212 5.20’ 5.38 4 0.026 BSC 0.301 0.311 7.65 7.90’ L 0.025 0.037 0.63 0.95 8 deg. 0 deg. N 20 0 deg. 9 0.65 BSC H NOTES: MAX A1 e A2 MIN 6 20 7 8 deg. Rev. 3 11/02 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. Submit Document Feedback 14 FN6036.3 December 15, 2014 ISL43240 Package Outline Drawing L20.4x4 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 11/06 4X 4.00 2.0 16X 0.50 A B 16 6 PIN #1 INDEX AREA 20 6 PIN 1 INDEX AREA 1 15 4.00 2 . 10 ± 0 . 15 11 5 0.15 (4X) 6 10 0.10 M C A B 4 0.25 +0.05 / -0.07 TOP VIEW 20X 0.6 +0.15 / -0.25 BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 ± 0 . 1 C BASE PLANE ( 3. 6 TYP ) ( SEATING PLANE 0.08 C ( 20X 0 . 5 ) 2. 10 ) SIDE VIEW ( 20X 0 . 25 ) C 0 . 2 REF 5 0 . 00 MIN. 0 . 05 MAX. ( 20X 0 . 8) TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance: Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. Submit Document Feedback 15 FN6036.3 December 15, 2014