Highly Integrated Single-Cell Li-ion/Li-Polymer Battery Charger ® Application Note Introduction The ISL6291 is a highly integrated single-cell Li-ion/Li-polymer battery charger designed for handheld devices. The ISL6291EVAL1 provides a convenient platform to evaluate the integrated charger. This application note first describes the components on this board so a user can perform their own evaluation. Then it presents the evaluations that can be carried out with this board. At the end of this application note are the schematics, the layout of each layer, and the bill-of-materials. May 5, 2009 The other end of the thermistor is expected to be connected to the ground of the battery pack. DIP Switch A 9-bit DIP switch is located on the bottom edge of the board. This DIP switch allows users to set up various TIMEOUT lengths, charger current levels, end-of-charge current, and to simulate battery removal, and so on. The function of each bit is summarized in Table 1. TABLE 1. DIP SWITCH FUNCTIONALITY BIT Board Description Figure 1 shows a simplified top view of the evaluation board. In the center of the board is a rectangular box that contains the components essential to the charger circuit. All components outside the box are for evaluation convenience. The following describes each component needed for evaluation in detail. The schematic of the evaluation board is given at the end of this application note. JP1 JP1 is a two-pin connector for the input power located on the left edge of the evaluation board. Connect the pin labeled with “+” to the positive output of the power source and the pin labeled with “GND” to the ground output of the power source. The input voltage is expected to be between 4.3V to 10V, and the current up to 2A. AN1049.1 NAME WHEN OFF WHEN ON 1 TIMEOUT 3.5 hrs TIMEOUT 5.8 hrs TIMEOUT 2 TOEN Enable TIMEOUT Disable TIMEOUT 3 EN Enable Charger Disable Charger 4 IREF1 5 IREF2 When both OFF, the Additional 0.5A Charge current charge current is 0.5A Additional 1A Charge Current 6 IMIN End-of-charge current is 100mA End-of-charge current is 200mA 7 TEMP1 Simulate Normal Temp 8 TEMP2 All OFF to simulate battery removal 9 TEMP3 Simulate High Temp Simulate Low Temp Jumpers JP2 JP2 is a three-pin connector located on the right edge. JP2 interfaces the charger output to a Li-ion battery pack. The pins labeled with “+” and “GND” should be connected to the positive and ground terminals of the battery pack respectively. The pin labeled with “TEMP” should be connected to the NTC thermistor output of the battery pack. Three 2-pin jumpers are used in this evaluation board. JP3 connects the input power source to the VIN pin of the charger IC when it is shorted. JP4 connects the charger output to connector JP2. These two jumpers are employed for the convenience of input and output current measurement. A current meter can be inserted when the jumper is opened. Opening the third jumper, JP5, disconnects the TEMP pin to the thermistor of the battery pack. When JP5 is disconnected, the DIP switch can be used to simulate high temperature, low temperature, and battery removal cases. Refer to the schematic for more information. Test Points Five test points are available on the board for the convenience of evaluation. GND1 and GND2 are two ground connection points. The VIN, the VBAT, and the TIME test point connects to the charger IC pins of the same name. O N 123456789 FIGURE 1. TOP VIEW OF THE ISL6291EVAL1 EVALUATION BOARD 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Application Note 1049 this power supply is available, the charger takes about 200 ms to reset all internal logic and for the control circuit to stabilize. During this 200 ms, the FAULT pin outputs a logic LOW, and the STATUS pin stays HIGH. Once the power-on reset is finished, the charger starts a new charge cycle. The STATUS pin outputs a LOW signal and the FAULT pin jumps to HIGH since there is no fault situation. TIME (1m s/div) VIN (2V/div) V2P8 (2V/div) A Complete Charge and Recharge Cycle Figure 3 shows a complete charge cycle and a recharge cycle. The battery being charged was completely discharged, to the extent that the internal over-discharge protection circuit was triggered, before the charge began. At t1, the charger is powered. The charger quickly goes through the trickle mode and the charge current rises to a 1A set constant current. At t2, the battery voltage rises to 4.2V and the charge current starts to fall. The charge cycle finishes at t3 when the charge current falls to the end-ofcharge current set by the IMIN pin. The battery voltage maintains at 4.2V during t2 and t3. At t4, a 500mA current is applied to the battery, and the battery starts to drop. As the battery voltage drops to 4.0V in the middle of t4 and t5, the charger starts to re-charge the battery. At t5, the 500mA load is removed, and this portion of the current is removed from the charger, causing a step drop of the charge current. At the end of Figure 3, the charge current once again reaches the end-of-charge current and stops charging. STATUS (5V/div) FAULT (5V/div) FIGURE 2. V2P8, STATUS, FAULT WAVEFORMS DURING POR LED Indications A green LED (D1) and a red LED (D2) are used to indicate the charger status. When it is charging, the green LED lights up. When a fault occurs, the red LED turns on. Refer to the datasheet for more information. Evaluation Various evaluation of the ISL6291 can be carried out with this evaluation board. The following evaluations demonstrate typical behaviors of the power-on reset, a complete charge and recharge cycle, the TIMEOUT accuracy examination, and the charge current thermal foldback feature. TIME Pin Waveform The waveform on the TIME pin can give an accurate TIMEOUT calculation. Figure 4 shows the TIME pin waveform. The TIME-pin waveform is a triangular waveform. The amplitude is 1V with a 0.5V valley and 1.5V peak voltage. When a 15pF timing capacitor is used, the typical oscillation period is 3ms and the typical TIMEOUT period is 3.5 hours with the internal 22-stage binary counter. Power-On Reset Figure 2 shows how the charger response to the power-on. As the input voltage rises to the POR threshold, the V2P8 pin starts to output a 2.8V supply. This pin can usually be used as an input power presence indication. The 2.8V also supplies power to the internal control and logic circuit. After TIME (1ks/div) Fully Discharged Battery Pack VBAT (1V/div) 1.0A 4.2V Charge Current (200mA/div) Apply 5V Input t1 t2 t3 t4 t5 500mA Load Current FIGURE 3. A COMPLETE CHARGE AND RECHARGE CYCLE 2 AN1049.1 May 5, 2009 Application Note 1049 Schematic and Layout The schematic, the layout layers, and the bill-of-materials are given at the end of the application note. For Intersil documents available on the internet, see web site www.intersil.com Intersil Technical Support 1-888-INTERSIL Layout Drawings Amplitude Silk Screen Period FIGURE 4. THE WAVEFORM MEASURED AT THE TIME PIN 10V 600mA 1.0A Charge Current (200mA/div) 5V Input Voltage (2V/div) Top Layer TIME (0.2ks/div) FIGURE 5. THE CHARGE CURRENT THERMAL FOLDBACK IN REACTION TO AN INPUT VOLTAGE RISE AND FALL Charge Current Thermal Foldback The charge current thermal foldback is a key feature of the ISL6291 charger. Figure 5 demonstrates how the charge current reacts to a temperature rise in the charger. The charger starts with 5V input voltage a 1A charge current. The VBAT pin voltage is set at 3.5V. Then the input voltage jumps to 10V, generating more heat in the charger IC. As the internal temperature rises, typically to +100°C, the charge current starts to fall and stabilize, to approximately 600mA, to lower the heat generation. Summary This application note described in detail the ISL6291EVAL1 evaluation board. The typical behavior of the start-up, a complete charge and recharge cycle, the TIME pin waveform, and the charge current thermal foldback are demonstrated. The complete layout, schematic and the bill-of-materials for the evaluation board are also provided. 3 AN1049.1 May 5, 2009 Application Note 1049 Ground Layer Bottom Layer Power Layer 4 AN1049.1 May 5, 2009 Application Note 1049 Schematic 5 AN1049.1 May 5, 2009 Application Note 1049 Bill of Materials PART DESCRIPTION PCB FOOTPRINT ITEM QTY REFERENCE 1 1 C1 1µF/10V X5R ceramic cap 2 2 C2 10µF/6.3V Tantalum Cap 2.05X1.3X1.2 3 1 C3 15nF/16V, X7R ceramic 4 1 C4 5 1 6 0603 PART NUMBER VENDOR C1608X5R1A105K TDK TAJR106M006 AVX 0402 C1005X7R1C153K TDK 0.1µF/16V, Y5V ceramic 0402 C1005Y5V1C104ZT TDK C5 10nF/16V, X7R Ceramic 0402 C1005X7R1C103K TDK 1 C6 10µF/16V Tantalum Cap 3.2X1.6X1.6 TAJA106M016 AVX 7 1 D1 Green LED 0805 67-1553-1-ND DigiKey 8 1 D2 Red LED 0805 67-1552-1-ND DigiKey 9 2 R1, R2 5k, 5% 0603 Various 10 1 R3 10k, 1% 0402 Various 11 1 R4 160k, 1% 0402 Various 12 1 R5 80k, 1% 0402 Various 13 1 R6 160k, 1% 0402 Various 14 1 R7 80k, 1% 0402 Various 15 1 R8 80k, 1% 0402 Various 16 1 R9 5k, 1% 0402 Various 17 1 R10 500, 1% 0402 Various 18 1 R11 18k, 1% 0402 Various 19 1 JP1 2.54mm Male Header, 2 ckt A19423-ND DigiKey 20 1 JP2 2.54mm Male Header, 3 ckt A19430-ND DigiKey 21 3 JP3, JP4, JP5 22 1 SW1 23 5 VIN, VBAT, GND1, GND2, TIME 24 1 U1 2.54mm jumper, 2 ckt Various DIP Switch, 9 Pos, SMT CKN1323-ND DigiKey Test Point 5002K-ND DigiKey ISL6291-2CR Intersil Single-Cell Li-ion Battery Charger 16-pin 5X5 QFN All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 6 AN1049.1 May 5, 2009