isl8272m - ISL8272M - 50A Digital DC/DC PMBus Power

DATASHEET
50A Digital DC/DC PMBus Power Module
ISL8272M
Features
The ISL8272M is a 50A step-down PMBus compliant digital
power module. Integrated in the module is a high performance
digital PWM controller, dual-phase power MOSFETs, inductors
and the passives. This high efficiency power module is capable
of delivering 50A without the need for airflow and heatsink.
The ISL8272M can be placed in a current sharing
configuration with up to 4 modules in parallel to deliver 200A
continuous current.
• Complete digital switch mode power supply
The ISL8272M operates with the ChargeMode™ control
architecture, which responds to a transient load within a single
switching cycle. The ISL8272M comes with operating in a pin
strap mode; output voltage, switching frequency device, SMBus
address, input UVLO, soft-start/stop and current sharing can be
programmed through external resistors. More configuration such
as fault limits, fault response, margining and sequencing can be
easily programmed via the PMBus interface. PMBus can be used
to monitor voltages, currents, temperatures and fault status. The
ISL8272M is supported by the PowerNavigator™ software, a
graphical user interface (GUI) that can be used to configure
modules to a desired solution.
The ISL8272M is built in a compact (18mmx23mmx7.5mm)
and low profile overmolded HDA package, suitable for
automated assembly by standard surface mount equipment.
• Wide input voltage range: 4.5V to 14V
• Programmable output voltage range: 0.6V to 5V
• PMBus compliant communication interface
• Programmable VOUT, margining, UV/OV, UC/OC, UT/OT,
soft-start/stop, sequencing and external synchronization
• Monitor of VIN, VOUT, IOUT, temperature, duty cycle, switching
frequency, power-good and faults
• Fast response ChargeModeTM control architecture
• Multiphase current sharing with up to 4 modules
• ±1.0% VOUT accuracy over line, load and temperature
• Internal nonvolatile memory and fault logging
• Thermally enhanced HDA package
Applications
• Server, telecom, storage and datacom
• Industrial/ATE and networking equipment
• General purpose power for ASIC, FPGA, DSP and memory
Related Literature
• UG003, “ISL8272MEVAL1Z Evaluation Board User Guide”
• UG004, “ISL8272MEVAL2Z Evaluation Board User Guide”
VIN
VIN
CIN
VOUT
VDD
VSENP
ENABLE
EN
VOUT
18m
COUT
VSENN
VR5
10µF
10µF
VR6
VDRV
m
23
VR
ISL8272M
m
m
VR55
VCC
SDA
2x10µF
PMBUS
INTERFACE
SALRT
VMON
6.65k 
7.5mm
SCL
VDRV1
100k 
SGND
PGND
NOTE:
1. Figure 1 represents a typical implementation of the ISL8272M. For PMBus
operation, it is recommended to tie the enable pin (EN) to SGND.
FIGURE 1. 50A APPLICATION CIRCUIT
January 14, 2015
FN8670.2
1
FIGURE 2. A SMALL PACKAGE FOR HIGH POWER DENSITY
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014, 2015. All Rights Reserved
Intersil (and design), ChargeMode, PowerNavigator and Digital-DC are trademarks owned by Intersil Corporation
or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
ISL8272M
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typical Application Circuit - Single Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Application Circuit - Three Module Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Efficiency Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Transient Response Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Derating Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMBus Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-Start/Stop Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Undervoltage Lockout (UVLO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMBus Module Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Prebias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital-DC™ Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Active Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitoring Via SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Snapshot Parameter Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nonvolatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
17
17
18
18
18
19
19
20
20
20
20
21
21
22
22
22
22
22
22
Layout Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB Layout Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stencil Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reflow Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
23
24
24
24
24
PMBus Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PMBus™ Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PMBus Commands Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Firmware Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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FN8670.2
January 14, 2015
ISL8272M
Ordering Information
PART NUMBER
(Notes 2, 3, 4)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
-40 to +85
PKG.
DWG. #
ISL8272MAIRZ
ISL8272M
58 LD 18x23 HDA
Y58.18x23
ISL8272MEVAL1Z
Single-Module Evaluation Board (see UG003, “ISL8272MEVAL1Z Evaluation Board User Guide”)
ISL8272MEVAL2Z
Three-Module Current Sharing Evaluation Board (see UG004, “ISL8272MEVAL2Z Evaluation Board User Guide”)
NOTES:
2. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL8272M. For more information on MSL, please see tech brief TB363.
ISL
xxxxM
INTERSIL DEVICE DESIGNATOR
BASE PART NUMBER
FIRMWARE REVISION
A: FC01
OPERATING TEMPERATURE
I: INDUSTRIAL (‐ 40°C TO +85°C)
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3
F
T
R
Z
S
SHIPPING OPTION
BLANK: BULK
T: TAPE AND REEL
ROHS
Z: ROHS COMPLIANT
PACKAGE DESIGNATOR
R: HIGH DENSITY ARRAY (HDA)
FN8670.2
January 14, 2015
ISL8272M
Pin Configuration
ISL8272M
(58 LD HDA)
TOP VIEW
1
2
3
4
A
TEST
D
E
9
10 11 12 13 14 15 16 17 18
SA
VMON
CS
PAD2
VOUT
MGN
SCL
SALRT SDA
EN
TEST
PAD6
VSENN VSENP
P
R
T
U
PGND
ASCR V25
SGND
VDD
L
N
PGND
TEST
TEST
K
M
TEST
TEST
SYNC
PG
DDC
PAD7
J
8
VOUT
VSET
SS/UVLO
PGND
PGND
PAD5
H
7
PAD4
PAD3
C
G
6
PAD1
B
F
5
VR SWD1
VCC
VR6 SGND
VR55
PAD8
SGND
PGND
VR5
PGND
PGND VDRV
VDRV1
DCM
VIN
PAD9
PAD10
VIN
PGND
SGND
SWD2
VDRV
VDRV1
DCM
PAD11
PAD12
VIN
PGND
SGND
V
W
PGND
SW1
Y
AA
AB
AC
SW2
PGND
PAD15
PAD13
PAD14
PAD16
Pin Descriptions
PIN
LABEL
TYPE
DESCRIPTION
PAD1, 2
VOUT
PWR
Power supply output voltage. Output voltage from 0.6V to 5V. Tie these two pins together to achieve a single output.
For higher output voltage, refer to the derating curves starting on page 15 to set the maximum output current from
these pads.
PAD 3, 4, 5, 7,
10, 12, 13, 15
PGND
PWR
Power ground. Refer to the “Layout Guide” on page 23 for the PGND pad connections and I/O capacitor placement.
PAD 6
SGND
PWR
Signal ground. Refer to “Layout Guide” on page 23 for the SGND pad connections.
PAD 8, 9, 11
VIN
PWR
Input power supply voltage to power the module. Input voltage range from 4.5V to 14V.
PAD 14, 16
SW1,
SW2
PWR
Switching node pads. The SW pads are used to dissipate the heat and provide the good thermal performance. Refer
to “Layout Guide” on page 23 for the SW pad connections.
C6
VSET
I
Output voltage selection pin. Used to set VOUT set point and VOUT max.
C7
CS
I
Current sharing configuration pin. Used to program current sharing configurations such as SYNC selection, phase
spreading and VOUT droop.
C8
MGN
I
External VOUT margin control pin. Active high (>2V) sets VOUT margin high; active low (<0.8V) sets VOUT margin low;
high impedance (floating) sets VOUT to normal voltage. Factory default range for margining is nominal VOUT ±5%.
When using PMBus to control margin command, leave this pin as no connection.
C9
VMON
I
Driver voltage monitoring. Use this pin to monitor VDRV through an external 16:1 resistor divider.
C10
SA
I
Serial address selection pin. Used to assign unique address for each individual device or to enable certain
management features.
C11
SALRT
O
Serial alert. Connect to external host if desired. SALRT is asserted low upon a warning or a fault event and
deasserted when warning or fault is cleared. A pull-up resistor is required.
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4
FN8670.2
January 14, 2015
ISL8272M
Pin Descriptions
(Continued)
PIN
LABEL
TYPE
C12
SDA
I/O
Serial data. Connect to external host and/or to other Digital-DC™ devices. A pull-up resistor is required.
C13
SCL
I/O
Serial clock. Connect to external host and/or to other Digital-DC™ devices. A pull-up resistor is required.
D4
SS/
UVLO
I
Soft-start/stop and undervoltage lockout selection pin. Used to set turn on/off delay and ramp time as well as input
UVLO threshold levels.
D5
PG
O
Power-good output. Power-good output can be an open drain that requires a pull-up resistor or push-pull output that
can drive a logic input.
D13
SYNC
I/O
Clock synchronization input. Used to set the frequency of the internal switch clock, to sync to an external clock or to
output internal clock.
E14
EN
I
E4
DDC
I/O
C5, D14, E15,
F4, F15, G4
TEST
-
Test pins. Don’t connect these pins.
G14
ASCR
I
ChargeMode™ control ASCR parameters selection pin. Used to set ASCR gain and residual values.
G15
V25
PWR
Internal 2.5V reference used to power internal circuitry. No external capacitor required for this pin.
H3
VSENN
I
Differential output voltage sense feedback. Connect to negative output regulation point.
H4
VSENP
I
Differential output voltage sense feedback. Connect to positive output regulation point.
H16, J16, K16,
M14
SGND
PWR
Signal grounds. Using multiple vias to connect the SGND pins to the internal SGND layer.
K14
VDD
PWR
Input supply voltage for controller. Connect VDD pad to VIN supply.
L2
VR
PWR
Internal LDO bias pin. Tie VR to VR55 directly with a short loop trace.
L3, P11
SWD1,
SWD2
PWR
Switching node driving pins. Directly connect to the SW1 and SW2 pads with short loop wires.
L14
VR5
PWR
Internal 5V reference used to power internal circuitry. Place a 10µF decoupling capacitor for this pin.
M1
VCC
PWR
Internal LDO output. Connect VCC to VDRV for internal LDO driving.
M5, M17, N5
PGND
PWR
Power grounds. Using multiple vias to connect the PGND pins to the internal PGND layer.
M10
VR55
PWR
Internal 5.5V bias voltage for internal LDO use only. Tie VR55 pin directly to VR pin.
M13
VR6
PWR
Internal 6V reference used to power internal circuitry. Place a 10µF decoupling capacitor for this pin.
N6, N16
VDRV
PWR
Power supply for internal FET drivers. Connect 10μF bypass capacitor to each of these pins. These pins can be driven
by the internal LDO through VCC pin or by the external power supply directly. Keep the driving voltage between 4.5V
and 5.5V. For 5V input application, use external supply or connect this pin to VIN.
R8, R17
VDRV1
I
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DESCRIPTION
Enable pin. Logic high to enable the module output.
A Digital-DC bus. This dedicated bus provides the communication between devices for features such as sequencing,
fault spreading and current sharing. The DDC pin on all Digital-DC devices should be connected together. A pull-up
resistor is required.
Bias pin of the internal FET drivers. Always tie to VDRV.
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January 14, 2015
ISL8272M
VDRV1
VDRV
VCC
VIN
VR
VR55
V25
VR5
VR6
VDD
ISL8272M Internal Block Diagram
LDO
VDRV
VIN
FILTER
SWD2
LDOs
VOUT
VDRV1
OV/UV
CURRENT SHARE
INTERLEAVE
OT/UT
OC/UC
POWER
MANAGEMENT
SEQUENCE
FAULT SPREADING
MARGINING
PGND
SS
SNAPSHOT
0.27µH
LOGIC
ASCR
CS
VSET
SS/UVLO
EN
PG
MGN
DDC
SW2
SYNC
OUT
PWM2
SYNC
PLL
D-PWM
PWM1
ChargeModeTM
CONTROL
SUPERVISOR
VIN
VDRV
NVM
SWD1
SW1
ADC
CSA
VDRV1
ADC
0.27µH
LOGIC
PROTECTION
VOUT
CSA
ADC
PGND
VSA
VDD
ADC
INTERNAL
TEMP SENSOR
SCL
SDA
SALRT
PMBus/I2C
INTERFACE
22Ohm
SA
VSENP
VSENN
SGND
22Ohm
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6
PGND
SGND
VMON
DIGITAL CONTROLLER
FN8670.2
January 14, 2015
DDC
DDC
SCL
SCL
SDA
SDA
SALRT
PG
MGN
CS
R11 R12
VR55
VR
SALRT
4x22µF
CERAMIC
C2
SWD1
ISL8272M
470µF
BULK
C1
R10
ASCR
R4
Note 5 Note 5 Note 6
R9
SYNC
R3
R8
SS/UVLO
R2
R7
VSET
7
R1
12V
PG
10k  10k  10k  10k 
Note 7
VIN
EN
VAUX OR VCC
3.3V TO 5V
EN
MGN
PIN STRAP RESISTORS
(OPTIONAL)
SA
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Typical Application Circuit - Single Module
SW1
VIN
SWD2
C3
VDD
10µF
VR5
10µF
10µF
C4
C5
SW2
ISL8272M
8x100µF
CERAMIC
VR6
4x470µF
POSCAP
VOUT
VDRV
VMON
R6
6.65k 
C8
VDRV1
FN8670.2
January 14, 2015
NOTES:
5. R2 and R3 are not required if the PMBus host already has I2C pull-up resistors.
6. Only one R4 per DDC bus is required when multiple modules share the same DDC bus.
7. R7 thru R12 can be selected according to the tables for the pin-strap resistor setting in this document.
If the PMBus configuration is chosen to overwrite the pin-strap configuration, R8 thru R12 can be non-populated.
8. V25, VR and VR55 do not need extenal capacitors. V25 can be no connection.
VSENN
C7
VSENP
C6
VCC
PGND
R5
100k
10µF
SGND
VCC 10µF
C9
VOUT
1.2V 50A
ISL8272M
Typical Application Circuit - Three Module Current Sharing
VIN
12V
2X470µF
BULK
PG1
PG
R9
R10
R11
SDA
SDA
SALRT
SYNC
SYNC
C2
VR55
VR
SALRT
4x22µ F
CERAMIC
CS
SCL
ASCR
DDC
SCL
VSET
DDC
C1
R8
R4
SS/UVLO
R3
SA
R2
MGN
51.1k 
R7
R1
EN
4.7k  4.7k  4.7k  4.7k 
EN
SMBus Address= 0x2A
VAUX or VCC
3.3V to 5V
MGN
PIN STRAP RESISTORS
(OPTIONAL)
SWD1
SW1
VIN
C3
SWD2
VDD
10µF
10µF
10µF
C4
C5
SW2
ISL8272M
VR5
4x100µF
CERAMIC
VR6
12x100µ F
CERAMIC
12x470µ F
POSCAP
VOUT
VCC
C8
VSENP
VSENN
MGN
PG2
PG
SGND
VMON
R6
6.65k 
EN
VDRV1
EN
C7
MGN
C6
PGND
R5
100k 
VOUT
1.2V 150A
VDRV
10µF
VCC1 10µF
C23
C24
PIN STRAP RESISTORS
(OPTIONAL)
SMBus Address = 0x2B
56.2k 
SCL
R18
CS
VSET
R17
SS/UVLO
DDC
R16
ASCR
R15
SA
R14
VR55
SDA
VR
SALRT
SYNC
4x22µF
CERAMIC
C9
SWD1
SW1
VIN
C10
SWD2
VDD
10µF
10µF
10µF
SW2
ISL8272M
VR5
4x100µF
CERAMIC
VR6
C12
C11
VOUT
VDRV
VCC
C15
VSENP
VSENN
PG3
PG
SGND
VMON
R13
6.65k
MGN
VDRV1
EN
C14
EN
C13
10µF
PGND
VCC2 10µF
R12
100k 
PIN STRAP RESISTORS
(OPTIONAL)
SMBus Address = 0x2C
61.9k 
SCL
MGN
R25
CS
R24
ASCR
VSET
R23
SS/UVLO
DDC
R22
SA
R21
VR55
SDA
VR
SALRT
SWD1
SYNC
4x22µF
CERAMIC
C16
SW1
VIN
C17
SWD2
VDD
10µF
10µF
10µF
C18
SW2
ISL8272M
VR5
4x100µF
CERAMIC
VR6
C19
VOUT
VDRV
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8
VCC
C22
VDRV1
VMON
VSENP
C21
VSENN
R20
6.65k
C20
PGND
R19
100k 
10µF
SGND
VCC3 10µF
FN8670.2
January 14, 2015
ISL8272M
TABLE 1. ISL8272M DESIGN GUIDE MATRIX AND OUTPUT VOLTAGE RESPONSE
VIN
(V)
VOUT
(V)
CIN (BULK)
(Note 9)
(µF)
CIN
(CERAMIC)
(µF)
COUT
(BULK)
(µF)
COUT
(CERAMIC)
(µF)
ASCR GAIN
(Note 10)
ASCR
RESIDUAL
(Note 10)
P-P
DEVIATION
(mV)
RECOVERY
TIME
(µs)
LOAD STEP
(A)
(Note 11)
FREQ.
(kHz)
5
1
1x470
6x47
4x470
12x100
220
90
50
20
0/25
300
5
1
1x470
4x47
4x470
8x100
550
100
45
15
0/25
533
12
1
1x470
6x22
4x470
12x100
220
90
55
22
0/25
300
12
1
1x470
4x22
4x470
8x100
550
100
50
15
0/25
533
5
1.8
1x470
6x47
4x470
8x100
200
90
60
25
0/25
300
5
1.8
1x470
4x47
2x470
6x100
250
90
70
20
0/25
533
12
1.8
1x470
6x22
4x470
8x100
220
90
70
20
0/25
300
12
1.8
1x470
4x22
2x470
6x100
280
100
70
20
0/25
533
5
2.5
1x470
6x47
2x470
6x100
120
90
100
30
0/25
300
5
2.5
1x470
4x47
2x470
4x100
250
90
80
20
0/25
533
12
2.5
1x470
6x22
2x470
6x100
110
90
100
20
0/25
300
12
2.5
1x470
4x22
2x470
4x100
220
90
100
15
0/25
533
5
3.3
1x470
6x47
2x470
4x100
100
90
120
50
0/25
300
5
3.3
1x470
4x47
2x470
4x100
220
90
100
30
0/25
533
12
3.3
1x470
4x22
2x470
4x100
220
90
100
10
0/25
533
12
5
1x470
6x22
2x470
4x100
230
90
120
10
0/25
533
NOTES:
9. CIN bulk capacitor is optional only for energy buffer from the long input power supply cable.
10. ASCR gain and residual are selected to ensure phase margin higher than 60° and gain margin higher than 6dB at room temperature and full load
(50A).
11. Output voltage response is tested with load step slew rate higher than 100A/µs.
TABLE 2. RECOMMENDED INPUT/OUTPUT CAPACITOR
VENDORS
VALUE
PART NUMBER
MURATA, Input Ceramic
47µF, 16V, 1210
GRM32ER61C476ME15L
MURATA, Input Ceramic
22µF, 16V, 1210
GRM32ER61E226KE15L
TAIYO YUDEN, Input Ceramic
47µF, 16V, 1210
EMK325BJ476MM-T
TAIYO YUDEN, Input Ceramic
22µF, 25V, 1210
TMK325BJ226MM-T
MURATA, Output Ceramic
100µF, 6.3V, 1210
GRM32ER60J107M
TDK, Output Ceramic
100µF, 6.3V, 1210
C3225X5R0J107M
AVX, Output Ceramic
100µF, 6.3V, 1210
12106D107MAT2A
SANYO POSCAP, Output Bulk
470µF, 4V
4TPE470MCL
SANYO POSCAP, Output Bulk
470µF, 6.3V
6TPF470MAH
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FN8670.2
January 14, 2015
ISL8272M
Absolute Maximum Ratings
Thermal Information
Input Supply Voltage, VIN Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 17V
Input Supply Voltage for Controller, VDD Pin . . . . . . . . . . . . . . -0.3V to 17V
MOSFET Switch Node Voltage, SW1/2, SWD1/2 . . . . . . . . . . . -0.3V to 17V
MOSFET Driver Supply Voltage, VDRV, VDRV1 Pin . . . . . . . . . -0.3V to 6.0V
Output Voltage, VOUT pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 6.0V
Internal Reference Supply Voltage, VR6 Pin . . . . . . . . . . . . . . -0.3V to 6.6V
Internal Reference Supply Voltage, VR, VR5, VR55 Pin. . . . . -0.3V to 6.5V
Internal Reference Supply Voltage, V25 Pin . . . . . . . . . . . . . . . . -0.3V to 3V
Logic I/O Voltage for DDC, EN, MGN, PG, ASCR, CS
SA, SCL, SDA, SALRT, SYNC, SS/UVLO, VMON, VSET . . . . . -0.3V to 6.0V
Analog Input Voltages for
VSENP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
VSENN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . 2000V
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . . 750V
Latch-Up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
58 LD HDA Package (Notes 12, 13). . . . . .
6.55
1.6
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to Figure 27
Recommended Operating Conditions
Input Supply Voltage Range, VIN . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 14V
Input Supply Voltage Range for Controller, VDD . . . . . . . . . . . 4.5V to 14V
Output Voltage Range, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.6V to 5V
Output Current Range, IOUT(DC) (Note 16). . . . . . . . . . . . . . . . . . . 0A to 50A
Operating Junction Temperature Range, TJ. . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
12. JA is measured in free air with the module mounted on an 6-layer evaluation board 4.7x4.8inch in size with 2oz surface and 2oz buried planes and
multiple via interconnects as specified in ISL8272MEVAL1Z Evaluation Board User Guide.
13. For JC, the “case temp” location is the center of the package underside.
Electrical Specifications
VIN = VDD= 12V, fSW = 533kHz, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MAX
(Note 14)
UNITS
40
50
mA
5.5
6.1
6.6
V
4.5
5.2
5.5
V
2.25
2.5
2.75
V
MIN
(Note 14)
INPUT AND SUPPLY CHARACTERISTICS
IDD
Input Supply Current for Controller
VR6
6V Internal Reference Supply Voltage
VR5
5V Internal Reference Supply
V25
2.5V Internal Reference Supply
Vcc
Internal LDO Output Voltage
IVCC
Internal LDO Output Current
VDD_READ_RES
Input Supply Voltage for Controller
Read Back Resolution
VDD_READ_ERR
Input Supply Voltage for Controller
Read Back Total Error (Note 17)
VIN = VDD = 12V, VOUT = 0V, module
not enabled
IVR5 <5mA
5.3
VIN = VDD = 12V, VCC connected to
VDRV, module enabled
V
50
PMBus Read
mA
10
Bits
±2
%FS
OUTPUT CHARACTERISTICS
VOUT_RANGE
Output Voltage Adjustment Range
VIN > VOUT + 1.8V
VOUT_RES
Output Voltage Set-Point Range
Configured using PMBus
VOUT_ACCY
Output Voltage Set-Point Accuracy
(Notes 15, 17)
Includes line, load and temperature
(-20°C ≤ TA ≤ +85°C)
VOUT_READ_RES
Output Voltage Read Back Resolution
VOUT_READ_ERR
Output Voltage Read Back Total Error
(Note 17)
IOUT_READ_RES
Output Current Read Back Resolution
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10
0.54
5.5
±0.025
-1
%
+1
10
PMBus read
-2
%VOUT
Bits
+2
10
V
%VOUT
Bits
FN8670.2
January 14, 2015
ISL8272M
Electrical Specifications
VIN = VDD= 12V, fSW = 533kHz, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
IOUT_RANGE
IOUT_READ_ERR
PARAMETER
TEST CONDITIONS
MIN
(Note 14)
TYP
Output Current Range (Note 16)
Output Current Read back Total Error
MAX
(Note 14)
50
PMBus read at max load. VOUT = 1V
UNITS
A
±3
A
SOFT-START AND SEQUENCING
tON_DELAY
tON_DELAY_ACCY
Delay Time From Enable to VOUT Rise
Configured using PMBus
tON_DELAY Accuracy
Output Voltage Ramp-Up Time
Configured using PMBus. Single
module standalone
tON_RISE_ACCY
Output Voltage Ramp-Up Time
Accuracy
Single module standalone
Delay Time From disable to VOUT Fall
Configured using PMBus
tOFF_DELAY_ACCY
tOFF_FALL
tON_FALL_ACCY
5000
±2
tON_RISE
tOFF_DELAY
2
0.5
ms
100
±250
2
tOFF_DELAY Accuracy
ms
µs
5000
±2
0.5
ms
ms
ms
Output Voltage Fall Time
Configured using PMBus. Single
module standalone
100
Output Voltage Fall Time Accuracy
Single module standalone
Power-Good Delay
Configured using PMBus
0
5000
ms
Configurable via PMBus
-50
150
C
-5
+5
C
4.18
16
V
±250
ms
µs
POWER-GOOD
VPG_DELAY
TEMPERATURE SENSE
TSENSE_RANGE
Temperature Sense Range
INT_TEMPACCY
Internal Temperature Sensor Accuracy Tested at +100°C
FAULT PROTECTION
VDD_UVLO_RANGE
VDD Undervoltage Threshold Range
Measured internally
VDD_UVLO_ACCY
VDD Undervoltage Threshold Accuracy
(Note 17)
±2
%FS
VDD_UVLO_DELAY
VDD Undervoltage Response Time
10
µs
VOUT_OV_RANGE
VOUT Overvoltage Threshold Range
1.15VOUT
V
VOUT_UV_RANGE
VOUT Undervoltage Threshold Range
Factory default
Configured using PMBus
Configured using PMBus
VOUT_OV/UV_ACCY
VOUT OV/UV Threshold Accuracy
(Note 15)
VOUT_OV/UV_DELAY
VOUT OV/UV Response Time
1.05VOUT
Factory default
VOUT_MAX
0.85VOUT
V
V
0
0.95VOUT
V
-2
+2
%
10
µs
±10
% FS
ILIMIT_ACCY
Output Current Limit Set-Point
Accuracy (Note 17)
Tested at IOUT_OC_FAULT_LIMIT = 50A
ILIMIT_DELAY
Output Current Fault Response Time
(Note 18)
Factory default
3
tSW
Over-temperature Protection
Threshold
(Controller Junction Temperature)
Factory default
125
C
TJUNCTION
TJUNCTION_HYS
Thermal Protection Hysteresis
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11
Configured using PMBus
-40
125
15
C
C
FN8670.2
January 14, 2015
ISL8272M
Electrical Specifications
VIN = VDD= 12V, fSW = 533kHz, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MAX
(Note 14)
UNITS
296
1067
kHz
-5
+5
%
MIN
(Note 14)
TYP
OSCILLATOR AND SWITCHING CHARACTERISTICS
fSW_RANGE
fSW_ACCY
EXT_SYNCPW
EXT_SYNCDRIFT
Switching Frequency Range
Switching Frequency Set-point
Accuracy
Minimum Pulse Width Required from
External SYNC Clock
Measured at 50% Amplitude
Drift Tolerance for External SYNC Clock External SYNC Clock equal to 500kHz
is not supported
150
ns
-10
+10
%
-100
+100
nA
0.8
V
LOGIC INPUT/OUTPUT CHARACTERISTICS
ILOGIC_BIAS
Bias Current at the Logic Input Pins
VLOGIC_IN_LOW
Logic Input Low Threshold Voltage
VLOGIC_IN_HIGH
Logic Input High Threshold Voltage
VLOGIC_OUT_LOW
Logic Output Low Threshold Voltage
2mA sinking
VLOGIC_OUT_HIGH
Logic Output High Threshold Voltage
2mA sourcing
DDC, EN, MGN, PG, SA, SCL, SDA,
SALRT, SYNC, UVLO, VMON, VSET
2.0
V
0.5
2.25
V
V
PMBus INTERFACE TIMING CHARACTERISTIC
fSMB
PMBus Operating Frequency
100
400
kHz
NOTES:
14. Compliance to datasheet limits is assured by one or more methods: Production test, characterization and/or design. Controller is independently
tested before module assembly.
15. VOUT measured at the termination of the VSENP and VSENN sense points.
16. The MAX load current is determined by the thermal “Derating Curves” on page 15, provide with this document.
17. “FS” stand for full scale of recommended maximum operation range.
18. “tSW” stands for time period of operation switching frequency.
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12
FN8670.2
January 14, 2015
ISL8272M
Typical Performance Curves
Efficiency Performance
Operating condition: TA = +25°C, no air flow. COUT = 1340µF. Typical values are used unless otherwise noted.
0.97
1.00
1.8V
0.95
0.85
1V
0.80
1.8V
1.2V
EFFICIENCY (%)
EFFICIENCY (%)
0.90
3.3V
2.5V
0.8V
0.75
0.93
0.91
0.89
0.70
0.87
0.65
0.85
300 350 400 450 500 550 600 650 700 750 800 850 900
0
5
10
15
20
25
30
IOUT (A)
35
40
45
50
1V
FIGURE 4. EFFICIENCY vs SWITCHING FREQUENCY AT VIN = 5V,
IOUT = 50A FOR VARIOUS OUTPUT VOLTAGES
0.98
0.95
0.96
0.90
0.94
2.5V
1.8V
EFFICIENCY (%)
1.00
0.85
5V
3.3V
1.2V
0.80
1V
0.75
0.8V
0.70
0.65
0
5
15
20
25
30
35
40
45
1.8V
5V
3.3V
0.90
0.88
0.8V
1V
1.2V
0.84
300 350 400 450 500 550 600 650 700 750 800 850 900
50
SWITCHING FREQUENCY (kHz)
IOUT (A)
FIGURE 6. EFFICIENCY vs SWITCHING FREQUENCY AT VIN = 9V,
IOUT = 50A FOR VARIOUS OUTPUT VOLTAGES
FIGURE 5. EFFICIENCY vs OUTPUT CURRENT AT VIN = 9V,
fSW = 300kHz FOR VARIOUS OUTPUT VOLTAGES
1.00
0.98
0.95
0.96
1.8V
2.5V
3.3V
5V
0.85
1.8V
2.5V
5V
3.3V
1.2V
0.80
1V
0.75
EFFICIENCY (%)
0.94
0.90
0.92
0.90
0.88
0.86
0.70
0.84
0.8V
0.65
2.5V
0.92
0.86
10
1.2V
SWITCHING FREQUENCY (kHz)
FIGURE 3. EFFICIENCY vs OUTPUT CURRENT AT VIN = 5V,
fSW = 300kHz FOR VARIOUS OUTPUT VOLTAGES
EFFICIENCY (%)
3.3V
0.95
0.8V
EFFICIENCY (%)
2.5V
0
5
10
15
20
25
30
IOUT (A)
35
40
45
FIGURE 7. EFFICIENCY vs OUTPUT CURRENT AT VIN = 12V,
fSW = 300kHz FOR VARIOUS OUTPUT VOLTAGES
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13
50
0.8V
1V
1.2V
0.82
300 350 400 450 500 550 600 650 700 750 800 850 900
SWITCHING FREQUENCY (kHz)
FIGURE 8. EFFICIENCY vs SWITCHING FREQUENCY AT VIN = 12V,
IOUT = 50A FOR VARIOUS OUTPUT VOLTAGES
FN8670.2
January 14, 2015
ISL8272M
Typical Performance Curves
(Continued)
Transient Response Performance Operating condition: VIN = 12V, fSW = 533kHz, IOUT = 0A/25A, IOUT slew rate > 100A/µs,
TA = +25°C, no air flow. Typical values are used unless otherwise noted.
FIGURE 9. 1V TRANSIENT RESPONSE. COUT = 8x100µF
CERAMIC + 4x470µF POSCAP
FIGURE 11. 2.5V TRANSIENT RESPONSE. COUT = 4x100µF
CERAMIC + 2x470µF POSCAP
FIGURE 10. 1.8V TRANSIENT RESPONSE. COUT = 6x100µF
CERAMIC + 2x470µF POSCAP
FIGURE 12. 3.3V TRANSIENT RESPONSE. COUT = 4x100µF
CERAMIC + 2x470µF POSCAP
FIGURE 13. 5V TRANSIENT RESPONSE. COUT = 4x100µF CERAMIC + 2x470µF POSCAP
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FN8670.2
January 14, 2015
ISL8272M
Typical Performance Curves
Derating Curves
(Continued)
All of the following curves were plotted at TJ = +115°C.
60
60
50
200LFM
40
400LFM
0LFM
30
20
LOAD CURRENT (A)
LOAD CURRENT (A)
50
10
0
40
400LFM
40
0LFM
30
20
50
60
70
80
90
TEMPERATURE (°C)
100
110
0
40
120
FIGURE 14. 5VIN TO 1VOUT, fSW = 300kHz
60
LOAD CURRENT (A)
200LFM
0LFM
30
20
110
120
200LFM
40
400LFM
0LFM
30
20
10
10
50
60
70
80
90
100
110
0
40
120
50
60
TEMPERATURE (°C)
80
90
100
110
120
FIGURE 17. 12VIN TO 1.8VOUT, fSW = 300kHz
60
50
50
200LFM
LOAD CURRENT (A)
60
40
70
TEMPERATURE (°C)
FIGURE 16. 5VIN TO 1.8VOUT, fSW = 300kHz
LOAD CURRENT (A)
100
50
400LFM
40
400LFM
0LFM
30
20
400LFM
40
0LFM
30
200LFM
20
10
10
0
40
70
80
90
TEMPERATURE (°C)
60
50
LOAD CURRENT (A)
50
FIGURE 15. 12VIN TO 1VOUT, fSW = 300kHz
60
0
40
200LFM
10
50
60
70
80
90
100
TEMPERATURE (°C)
FIGURE 18. 5VIN TO 2.5VOUT, fSW = 300kHz
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15
110
120
0
40
50
60
70
80
90
100
110
120
TEMPERATURE (°C)
FIGURE 19. 12VIN TO 2.5VOUT, fSW = 300kHz
FN8670.2
January 14, 2015
ISL8272M
Typical Performance Curves
Derating Curves
(Continued)
All of the following curves were plotted at TJ = +115°C. (Continued)
60
60
50
400LFM
200LFM
40
LOAD CURRENT (A)
LOAD CURRENT (A)
50
0LFM
30
20
10
0
40
400LFM
40
0LFM
30
200LFM
20
10
50
60
70
80
90
100
110
0
40
120
50
60
TEMPERATURE (°C)
70
80
90
100
110
120
TEMPERATURE (°C)
FIGURE 20. 5VIN TO 3.3VOUT, fSW = 300kHz
FIGURE 21. 12VIN TO 3.3VOUT, fSW = 533kHz
60
LOAD CURRENT (A)
50
400LFM
40
0LFM
30
200LFM
20
10
0
40
50
60
70
80
90
100
110
120
TEMPERATURE (°C)
FIGURE 22. 12VIN TO 5VOUT, fSW = 533kHz
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FN8670.2
January 14, 2015
ISL8272M
Functional Description
TABLE 3. OUTPUT VOLTAGE RESISTOR SETTINGS (Continued)
VOUT
(V)
RSET
(kΩ)
The ISL8272M provides a PMBus digital interface that enables
the user to configure all aspects of the module operation as well
as monitor the input and output parameters. The ISL8272M can
be used with any SMBus host device. In addition, the module is
compatible with PMBus™ Power System Management Protocol
Specification Parts I and II version 1.2. The ISL8272M accepts
most standard PMBus commands. When configuring the device
with PMBus commands, it is recommended that the enable pin is
tied to SGND.
2.20
90.9
2.30
100
2.50
110, or Connect to V25
2.80
121
3.00
133
3.30
147
4.00
162
The SMBus device address is the only parameter that must be
set by external pins. All other device parameters can be set with
PMBus commands.
5.00
178
SMBus Communications
Output Voltage Selection
The output voltage may be set to a voltage between 0.6V and 5V
provided that the input voltage is higher than the desired output
voltage by an amount sufficient to maintain regulation.
The VSET pin is used to set the output voltage to levels as shown
in Table 3. The RSET resistor is placed between the VSET pin and
SGND. A standard 1% resistor is required.
TABLE 3. OUTPUT VOLTAGE RESISTOR SETTINGS
VOUT
(V)
RSET
(kΩ)
0.60
10
0.65
11
0.70
12.1
0.75
13.3
0.80
14.7
0.85
16.2
0.90
17.8
0.95
19.6
1.00
21.5, or Connect to SGND
1.05
23.7
1.10
26.1
1.15
28.7
1.20
31.6, or OPEN
1.25
34.8
1.30
38.3
1.40
42.2
1.50
46.4
1.60
51.1
1.70
56.2
1.80
61.9
1.90
68.1
2.00
75
2.10
82.5
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The output voltage may also be set to any value between 0.6V and
5V using a PMBus command VOUT_COMMAND. This device
supports dynamic voltage scaling, by allowing change to the output
voltage set point during regulation. The voltage transition rate is
specified with the PMBus command VOUT_TRANSITION_RATE.
By Default, VOUT_MAX is set 110% higher than VOUT set by the pin
strap resistor, which can be changed to any value up to 5.5V with
PMBus Command VOUT_MAX.
Soft-Start/Stop Delay and Ramp Times
It may be necessary to set a delay from when an enable signal is
received until the output voltage starts to ramp to its target
value. In addition, the designer may wish to precisely set the time
required for VOUT to ramp to its target value after the delay
period has expired. These features may be used as part of an
overall in-rush current management strategy or to precisely
control how fast a load IC is turned on. The ISL8272M gives the
system designer several options for precisely and independently
controlling both the delay and ramp time periods. The soft-start
delay period begins when the EN pin is asserted and ends when
the delay time expires.
The soft-start delay and ramp up time can be programmed to
custom values with PMBus commands TON_DELAY and
TON_RISE. When the delay time is set to 0ms, the device begins
its ramp-up after the internal circuitry has initialized
(approximately 2ms). When the soft-start ramp period is set to
0ms, the output ramps up as quickly as the output load
capacitance and loop settings allow. It is generally
recommended to set the soft-start ramp to a value greater than
1ms to prevent inadvertent fault conditions due to excessive
in-rush current.
Similar to the soft-start delay and ramp up time, the delay and
ramp down time for soft-stop/off can be programmed with the
PMBus commands TOFF_DELAY and TOFF_FALL. In addition, the
module can be configured as “immediate off” with the command
ON_OFF_CONFIG, such that the FETs are turned off immediately
after the delay time expires.
In current sharing mode where multiple ISL8272M modules are
connected in parallel, ASCR is required to be disabled for the
ramp up with the USER_CONFIG command. Therefore, the
soft-start rise time is not equal to TON_RISE. It can be calculated
approximately by Equation 1.
FN8670.2
January 14, 2015
ISL8272M
TON_RISE
Rise Time (ms)  -------------------------------  330kHz  12V
V IN  f SW
(EQ. 1)
In current sharing mode, ASCR will be enabled automatically
upon power good assertion after the ramp completes. To avoid
premature ASCR turn on, it is recommended to increase
POWER_GOOD_DELAY if the rise time exceeds 10ms. In addition,
only “immediate off” is supported for current sharing.
The SS/UVLO pin can be used to program the soft start/stop
delay time and ramp time to some typical values as shown in
Table 4.
TABLE 4. SOFT START/STOP RESISTOR SETTINGS
Switching Frequency and PLL
The device’s switching frequency is set from 296kHz to 1067kHz
using the pin strap method (for standalone non-current sharing
module only) as shown in Table 5, or by using a PMBus command
FREQUENCY_SWITCH. The ISL8272M incorporates an internal
phase-locked loop (PLL) to clock the internal circuitry. The PLL
can be driven by an external clock source connected to the SYNC
pin. The incoming clock signal must be in the range of 300kHz to
1.33MHz and must be stable when the enable pin is asserted.
When using an external clock, the frequencies are not limited to
discrete values as when using the internal clock. The external
clock signal must not vary more than 10% from its initial value
and should have a minimum pulse width of 150ns. It is
recommended that when using an external clock, same
frequency should be set in the FREQUENCY_SWITCH command.
In case the external clock is lost, the module will automatically
switch to the internal clock. When using the internal oscillator,
the SYNC pin can be configured as a clock source as an external
sync to other modules. Refer to SYNC_CONFIG command on
page 47 for more information.
DELAY TIME
(ms)
RAMP TIME
(ms)
RSET
(kΩ)
5
2
19.6, or Connect to
SGND
10
2
21.5
5
5
23.7, or OPEN
10
5
26.1
20
5
28.7
fSW
(kHz)
RSET
(kΩ)
5
10
31.6
296
14.7, or Connect to SGND
10
10
34.8, or Connect to V25
320
16.2
20
10
38.3
364
17.8
400
19.6
421
21.5, or OPEN
471
23.7
533
26.1
5
2
42.2
10
2
46.4
5
5
51.1
10
5
56.2
20
5
61.9
TABLE 5. SWITCHING FREQUENCY RESISTOR SETTINGS
571
28.7
615
31.6, or Connect to V25
34.8
5
10
68.1
727
10
10
75
800
38.3
20
10
82.5
842
42.2
889
46.4
1067
51.1
Power-Good
The ISL8272M provides a Power-Good (PG) signal that indicates
the output voltage is within a specified tolerance of its target
level and no fault condition exists. By default, the PG pin asserts
if the output is within 10% of the target voltage. These limits and
the polarity of the pin may be changed with PMBus command
POWER_GOOD_ON.
A PG delay period is defined as the time from when all conditions
within the ISL8272M for asserting PG are met to when the PG pin
is actually asserted. This feature is commonly used instead of
using an external reset controller to control external digital logic.
A PG delay can be programmed with PMBus command
POWER_GOOD_DELAY.
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Loop Compensation
The module loop response is programmable via the PMBus
command ASCR_CONFIG or by using the pin strap method (ASCR
pin) according to Table 6,. The ISL8272M uses the ChargeMode™
control algorithm that responds to output current changes within
a single PWM switching cycle, achieving a smaller total output
voltage variation with less output capacitance than traditional
PWM controllers.
TABLE 6. ASCR RESISTOR SETTINGS
ASCR GAIN
ASCR RESIDUAL
RSET
(kΩ)
80
90
10
120
90
11, or Connect to SGND
160
90
12.1
200
90
13.3, or OPEN
FN8670.2
January 14, 2015
ISL8272M
TABLE 6. ASCR RESISTOR SETTINGS (Continued)
TABLE 7. UVLO RESISTOR SETTINGS
ASCR GAIN
ASCR RESIDUAL
RSET
(kΩ)
UVLO
(V)
RSET
(kΩ)
240
90
14.7
4.5
OPEN
280
90
16.2
4.5
Connect to V25
Connect to SGND
320
90
17.8
4.5
360
90
19.6
4.5
400
90
21.5
19.6, 21.5, 23.7, 26.1, 28.7, 31.6,
34.8, 38.3
10.8
450
90
23.7
42.2, 46.4, 51.1, 56.2, 61.9, 68.1,
75, 82.5,
500
90
26.1
550
90
28.7
600
90
31.6
700
90
34.8
800
90
38.3
80
100
42.2
120
100
46.4
SMBus Module Address Selection
Each module must have its own unique serial address to
distinguish between other devices on the bus. The module
address is set by connecting a resistor between the SA pin and
SGND. Table 8 lists the available module addresses.
TABLE 8. SMBus ADDRESS RESISTOR SELECTION
RSA
(kΩ)
SMBus
ADDRESS
160
100
51.1
10
19h
200
100
56.2
11
1Ah
240
100
61.9
12.1
1Bh
280
100
68.1
13.3
1Ch
1Dh
320
100
75
14.7
360
100
82.5
16.2
1Eh
17.8
1Fh
19.6
20h
400
100
90.9
450
100
100
500
100
110, or Connect to V25
550
100
600
100
21.5
21h
23.7
22h
121
26.1
23h
133
28.7
24h
25h
700
100
147
31.6
800
100
162
34.8, or connect to SGND
26h
38.3
27h
Input Undervoltage Lockout (UVLO)
42.2, or Open
28h
The input undervoltage lockout (UVLO) prevents the ISL8272M
from operating when the input falls below a preset threshold,
indicating the input supply is out of its specified range. The UVLO
threshold (VUVLO) can be set between 4.18V and 16V by using a
PMBus command VIN_UV_FAULT_LIMIT. Using the pin strap
method (SS/UVLO pin) as shown in Table 7, allows to set the
VUVLO to two typical values.
46.4
29h
51.1
2Ah
56.2
2Bh
Fault response to an input undervoltage fault can be programmed
with PMBus command VIN_UV_FAULT_RESPONSE. If the input
undervoltage fault retry is enabled, the module will shut down
immediately once the input voltage falls below VUVLO and then
check the input voltage every 70ms. If the input voltage rises
above the input undervoltage warning level, the module will
restart. The input undervoltage warning is 1.05*VUVLO by default
and can be programmed with the PMBus command
VIN_UV_WARN_LIMIT.
90.9
30h
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61.9
2Ch
68.1
2Dh
75
2Eh
82.5
2Fh
100
31h
110
32h
121
33h
133
34h
147
35h
162
36h
178
37h
FN8670.2
January 14, 2015
ISL8272M
Output Overvoltage Protection
The ISL8272M offers an internal output overvoltage protection
circuit that can be used to protect sensitive load circuitry from
being subjected to a voltage higher than its prescribed limits. A
hardware comparator is used to compare the actual output
voltage (seen at the VSENP, VSENN pins) to a threshold set to
15% higher than the target output voltage (the default setting).
Fault threshold can be programmed to a desired level with
PMBus command VOUT_OV_FAULT_LIMIT. If the VSENP voltage
exceeds this threshold, module will initiate an immediate
shutdown without retry. 70ms continuous retry can be enabled
with the PMBus command VOUT_OV_FAULT_RESPONSE.
Internal to module, two 22Ω resistors are populated from VOUT to
VSENP and SGND to VSENN to protect from overvoltage
conditions in case of open at voltage sensing pins and
differential remote sense traces due to assembly error. As long
as differential remote sense traces have low resistance, VOUT
regulation accuracy is not sacrificed.
Output Prebias Protection
An output prebias condition exists when an externally applied
voltage is present on a power supply’s output before the power
supply’s control IC is enabled. Certain applications require that
the converter not be allowed to sink current during start-up if a
prebias condition exists at the output. The ISL8272M provides
prebias protection by sampling the output voltage prior to
initiating an output ramp.
If a prebias voltage lower than the target voltage exists after the
preconfigured delay period has expired, the target voltage is set
to match the existing prebias voltage and both drivers are
enabled. The output voltage is then ramped to the final
regulation value at the preconfigured ramp rate.
The actual time the output takes to ramp from the prebias
voltage to the target voltage varies, depending on the prebias
voltage, however, the total time elapsed from when the delay
period expires to when the output reaches its target value will
match the preconfigured ramp time (see Figure 23).
VOUT
DESIRED OUTPUT
VOLTAGE
PREBIAS
VOLTAGE
TIME
TONDELAY
TONRISE
VPREBIAS < VTARGET
VOUT
PREBIAS
VOLTAGE
DESIRED OUTPUT
VOLTAGE
If a prebias voltage is higher than the target voltage after the
preconfigured delay period has expired, the target voltage is set
to match the existing prebias voltage and both drivers are
enabled with a PWM duty cycle that would ideally create the
prebias voltage.
Once the preconfigured soft-start ramp period has expired, the
PG pin is asserted (assuming the prebias voltage is not higher
than the overvoltage limit). The PWM then adjusts its duty cycle
to match the original target voltage and the output ramps down
to the preconfigured output voltage.
If a prebias voltage is higher than the overvoltage limit, the
device does not initiate a turn-on sequence and declares an
overvoltage fault condition. The device then responds based on
the output overvoltage fault response setting programmed with
PMBus command VOUT_OV_FAULT_RESPONSE.
Output Overcurrent Protection
The ISL8272M can protect the power supply from damage if the
output is shorted to ground or if an overload condition is imposed
on the output. Average output overcurrent fault threshold can be
programmed with PMBus command IOUT_OC_FAULT_LIMIT.
Module automatically programs peak inductor current fault
threshold, by calculating inductor ripple current by reading input
voltage, switching frequency and VOUT_COMMAND. When peak
inductor current crosses peak inductor current fault threshold for
three successive switching cycles it will initiate an immediate
shutdown.
The default response from an overcurrent fault is an immediate
shutdown without retry. 70ms continuous retry can be enabled
with the PMBus command MFR_IOUT_OC_FAULT_RESPONSE. It
is required to enable the output undervoltage fault retry with the
PMBus command VOUT_UV_FAULT_RESPONSE command
simultaneously if the overcurrent fault retry is enabled.
Thermal Overload Protection
The ISL8272M includes a thermal sensor that continuously
measures the internal temperature of the module and shuts
down the controller when the temperature exceeds the preset
limit. The default temperature limit is set to +125°C in the
factory, but can be changed with PMBus command
OT_FAULT_LIMIT.
The default response from an over-temperature fault is an
immediate shutdown without retry. Retry settings can be
programmed with PMBus command OT_FAULT_RESPONSE.
Hysteresis is implemented with the over-temperature fault retry.
If retry is enabled, the module will shut down immediately upon
an over-temperature fault event and then check the temperature
every 70ms. If the temperature falls below the over-temperature
warning level, the module will restart. The over-temperature
warning is +105°by default and programmable with the PMBus
command OT_WARN_LIMIT.
TIME
TONDELAY
TONRISE
VPREBIAS > VTARGET
FIGURE 23. OUTPUT RESPONSES TO PREBIAS VOLTAGES
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FN8670.2
January 14, 2015
ISL8272M
The Digital-DC™ Communications (DDC) bus is used to
communicate between Intersil digital power modules and digital
controllers. This dedicated bus provides the communication
channel between devices for features such as current sharing,
sequencing and fault spreading. The DDC pin on all Digital-DC™
devices in an application should be connected together. A pull-up
resistor is required on the DDC bus in order to guarantee the rise
time as shown in Equation 2:
(EQ. 2)
Rise Time = R PU C LOAD  1s
Where RPU is the DDC bus pull-up resistance and CLOAD is the
bus loading. The pull-up resistor may be tied to an external 3.3V
or 5V supply as long as this voltage is present prior to or during
device power-up. In principle, each device connected to the DDC
bus presents approximately 10pF of capacitive loading and each
inch of FR4 PCB trace introduces approximately 2pF. The ideal
design uses a central pull-up resistor that is well-matched to the
total load capacitance.
be a good trade-off between output load regulation and dynamic
current sharing.
V OUT
V OUT
---------------------------------  0.005  Droop  ---------------------------------  0.01 5
I LOAD  MAX 
I LOAD  MAX 
(EQ. 3)
Upon system start-up, the module with the lowest device position
as selected in DDC_CONFIG is defined as the reference module.
The remaining modules are members. The reference module
broadcasts its current over the DDC bus. The members use the
reference current information to trim their voltages (VMEMBER) to
balance the current loading of each module in the system.
VREFERENCE
-R
VOUT
Digital-DC™ Bus
VMEMBER
-R
Active Current Sharing
Paralleling multiple ISL8272M modules can be used to increase
the output current capability of a single power rail. By connecting
the DDC and SYNC pins of each module together and configuring
the modules as a current sharing rail, the units will share the
current equally within a few percent.
Figure 24 illustrates a typical connection for two modules.
VIN
3.3V TO 5V
ISL8272M
I REFERENCE
FIGURE 25. ACTIVE CURRENT SHARING
The relation between reference and member current and voltage
is given by Equation 4:
COUT
SYNC
I OUT
Figure 25 shows that, for load lines with identical slopes, the
member voltage is increased towards the reference voltage
which closes the gap between the inductor currents.
CIN
DDC
I MEMBER
V MEMBER = V OUT + R   I REFERENCE – I MEMBER 
where R is the value of the droop resistance.
CIN
DDC
ISL8272M
VOUT
COUT
SYNC
FIGURE 24. CURRENT SHARING GROUP
The ISL8272M uses a DDC bus based digital current sharing
technique to balance the steady state module output current by
aligning the load lines of member modules to a reference
module.
When multiple ISL8272M modules are connected for current
sharing, a non-zero active droop resistance must be set to add
artificial resistance in the output voltage path to control the slope
of the load line curve, calibrating out the physical parasitic
mismatches due to power train components and PCB layout. The
active droop resistance can be programmed with the PMBus
command VOUT_DROOP based on Equation 3. Typically, higher
droop value offers a more accurate dynamic current sharing at
the sacrifice of output load regulation. 1% droop at full load will
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(EQ. 4)
The DDC_CONFIG command is used to configure the module for
active current sharing. The default setting is a standalone non
current sharing module.
For fault configuration, it is required to enable the fault spreading
mode in the current sharing rail with the PMBus command
DDC_GROUP. Broadcast operation must be enabled with the
DDC_GROUP command to allow start up/shut down and
margining operations. It is optional to enable VOUT broadcast in
the DDC_GROUP command to allow VOUT set point change
dynamically during operation.
In multiple-module current sharing configuration, it is required to
synchronize all modules to the same switching clock by tying the
SYNC pins together. The clock source can be selected either from
one module or from an external clock with the SYNC_CONFIG
command. The phase offset of current sharing modules is
automatically set according to the device positions and number
of devices specified in the DDC_CONFIG command.
Pin strap method is offered for the current sharing configuration
with the CS pin. Table 9 lists the current sharing pin strap
settings.
FN8670.2
January 14, 2015
ISL8272M
TABLE 9. CURRENT SHARING RESISTOR SETTINGS
CLOCK
CONFIGURATION
DEVICE POSITION
- NUMBER OF
DEVICES
DROOP
(mV/A)
RSET
(kΩ)
Output internal
1-2
0.1
10
External
2-2
0.1
11
Output internal
1-2
0.15
12.1
External
2-2
0.15
13.3
Output internal
1-2
0.2
14.7
increments with the PMBus command INTERLEAVE. The internal
two phases of the module always maintain a phase difference
of 180°.
Fault Spreading
Digital-DC modules and devices can be configured to broadcast a
fault event over the DDC bus to the other devices in the group
with PMBus command DDC_GROUP. When a nondestructive fault
occurs, the device shuts down and broadcasts the fault event
over the DDC bus. The other devices on the DDC bus shut down
simultaneously, if configured to do so and attempt to restart.
External
2-2
0.2
16.2
Output Sequencing
Output internal
1-2
0.25
17.8
External
2-2
0.25
19.6
Output internal
1-2
0.3
21.5
External
2-2
0.3
23.7
Output internal
1-3
0.07
26.1
External
2-3
0.07
28.7
External
3-3
0.07
31.6
Output internal
1-3
0.1
34.8
A group of Digital-DC modules or devices may be configured to
power-up in a predetermined sequence. This feature is especially
useful when powering advanced processors (FPGAs and ASICs)
that require one supply to reach its operating voltage prior to
another supply reaching its operating voltage in order to avoid
latch-up. Multi-device sequencing can be achieved by configuring
each device with PMBus command SEQUENCE. Multiple device
sequencing is configured by issuing PMBus commands to assign
the preceding device in the sequencing chain as well as the
device that follows in the sequencing chain.
External
2-3
0.1
38.3
External
3-3
0.1
42.2
Output internal
1-3
0.13
46.4
External
2-3
0.13
51.1
External
3-3
0.13
56.2
Monitoring Via SMBus
Output internal
1-3
0.16
61.9
External
2-3
0.16
68.1
A system controller can monitor a wide variety of different
ISL8272M system parameters with PMBus commands:
External
3-3
0.16
75
Output internal
1-3
0.2
82.5
External
2-3
0.2
90.9
• READ_IOUT
External
3-3
0.2
100
• READ_INTERNAL_TEMP
Internal only
1-1
0
Connect to SGND
(for immediate
off)
Internal only
1-1
0
OPEN
(for soft off)
Phase Spreading
When multiple point-of-load converters share a common DC
input supply, it is desirable to adjust the clock phase offset of
each device, such that not all devices start to switch
simultaneously. Setting each converter to start its switching cycle
at a different point in time, can dramatically reduce input
capacitance requirements and efficiency losses. Since the peak
current drawn from the input supply is effectively spread out over
a period of time, the peak current drawn at any given moment is
reduced and the power losses proportional to the IRMS2 are
reduced dramatically.
The Enable pins of all devices in a sequencing group must be tied
together and driven high to initiate a sequenced turn-on of the
group. Enable must be driven low to initiate a sequenced turnoff
of the group. It is recommend to enable fault spreading with the
PMBus command DDC_GROUP within a sequencing group.
• READ_VIN
• READ_VOUT
• READ_DUTY_CYCLE
• READ_FREQEUNCY
• READ_VMON
Snapshot Parameter Capture
The ISL8272M offers a special feature to capture parametric data
and some fault status following a fault. Detail description is
provided in “PMBus Commands Description” on page 29 under
PMBus command SNAPSHOT and SNAPSHOT_CONTROL.
Nonvolatile Memory
The ISL8272M has internal nonvolatile memory where user
configurations are stored. Integrated security measures ensure
that the user can only restore the module to a level that has been
made available to them. During the initialization process, the
ISL8272M checks for stored values contained in its internal
nonvolatile memory.
To enable phase spreading, all converters must be synchronized
to the same switching clock. The phase offset of each device
may also be set to any value between 0° and 360° in 22.5°
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ISL8272M
Modules are shipped with factory defaults configuration and
most settings can be overwritten with PMBus Commands and
can be stored in nonvolatile memory with PMBus command
STORE_USER_ALL.
COUT
VOUT
COUT
PGND
PGND
Layout Guide
To achieve stable operation, low losses and good thermal
performance some layout considerations are necessary
(Figure 26).
• Establish separate SGND plane and PGND planes, then
connect SGND to PGND plane on the middle layer and
underneath PAD6 with a single point connection. For SGND
and PGND pin connections, such as small pins H16, J16, M5
and M17..., use multiple vias for each pin to connect to inner
SGND or PGND layer.
• Place enough ceramic capacitors between VIN and PGND,
VOUT and PGND and bypass capacitors between VDD, VDRV
and the ground plane, as close to the module as possible to
minimize high frequency noise. It is very critical to place the
output ceramic capacitors as close to the center of the two
VOUT pads as possible, to create a low impedance path for the
high frequency inductor ripple current.
• Use large copper areas for power path (VIN, PGND, VOUT) to
minimize conduction loss and thermal stress. Also, use
multiple vias to connect the power planes in different layers. It
is recommended to enlarge the PAD11, 15 and put more vias
on these pads. The ceramic caps CIN can be put on the bottom
layer under these two pads.
• Connect remote sensed traces to the regulation point to
achieve a tight output voltage regulation and keep them in
parallel. Route a trace from VSENN and VSENP to the point of
load where the tight output voltage is desired. Avoid routing
any sensitive signal traces, such as the VSENN, VSENP sensing
point near the SW pins.
• The SW1, 2 pads are noisy pads, but they are beneficial for
thermal dissipations. If the noise issue is critical for the
applications, it is recommended to use top layer only for SW
pads. For better thermal performance, use multiple vias on
these pads to connect into SW inner and bottom layer.
However, it should be very careful to put limited SW planes in
any layer. The SW planes should avoid the sensing signals and
should be surrounded by PGND layer to avoid the noise
coupling.
• For pins SWD1 (L3) and SWD2 (P10), it is recommended to
connect to related SW1, 2 pads with short loop wires. The wire
width should be more than 20 mils.
SGND
PGND
PGND
VSEN- VSEN+
Kelvin Connections
VIN
VIN
CIN
CIN
PGND
FIGURE 26. RECOMMENDED LAYOUT
Thermal Considerations
Experimental power loss curves along with θJA from thermal
modeling analysis can be used to evaluate the thermal
consideration for the module. The derating curves are derived
from the maximum power allowed while maintaining the
temperature below the maximum junction temperature of
+125°C. In actual application, other heat sources and design
margin should be considered.
Package Description
The structure of the ISL8272M belongs to the High Density Array
No-lead package (HDA). This kind of package has advantages,
such as good thermal and electrical conductivity, low weight and
small size. The HDA package is applicable for surface mounting
technology and is being more readily used in the industry. The
ISL8272M contains several types of devices, including resistors,
capacitors, inductors and control ICs. The ISL8272M is a copper
lead-frame based package with exposed copper thermal pads,
which have good electrical and thermal conductivity. The copper
lead frame and multi component assembly is overmolded with
polymer mold compound to protect these devices.
The package outline and typical PCB layout pattern design and
typical stencil pattern design are shown on pages 53, 54, 55. The
module has a small size of 18mmx23mmx7.5mm.
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ISL8272M
PCB Layout Pattern Design
Thermal Vias
A grid of 1.0mm to 1.2mm pitch thermal vias, which drops down
and connects to buried copper plane(s), should be placed under the
thermal land. The vias should be about 0.3mm to 0.33mm in
diameter with the barrel plated to about 1.0 ounce copper.
Although adding more vias (by decreasing via pitch) will improve
the thermal performance, diminishing returns will be seen as more
and more vias are added. Simply use as many vias as practical for
the thermal land size and your board design rules allow.
300
PEAK TEMPERATURE ~+245°C;
TYPICALLY 60s-150s ABOVE +217°C
KEEP LESS THAN 30s WITHIN 5°C OF PEAK TEMP.
250
TEMPERATURE (°C)
The bottom of ISL8272M is a lead-frame footprint, which is
attached to the PCB by surface mounting process. The PCB
layout pattern is shown on page 55. The PCB layout pattern is
essentially 1:1 with the HDA exposed pad and I/O termination
dimensions. The thermal lands on the PCB layout should match
1:1 with the package exposed die pads.
200
SLOW RAMP (3°C/s MAX)
AND SOAK FROM +150°C
TO +200°C FOR 60s~180s
150
100
RAMP RATE 1.5°C FROM +70°C TO +90°C
50
0
0
100
150
200
250
300
350
DURATION (s)
FIGURE 27. TYPICAL REFLOW PROFILE
Stencil Pattern Design
Reflowed solder joints on the perimeter I/O lands should have
about a 50µm to 75µm (2mil to 3mil) standoff height. The solder
paste stencil design is the first step in developing optimized,
reliable solder joins. Stencil aperture size to land size ratio should
typically be 1:1. The aperture width may be reduced slightly to help
prevent solder bridging between adjacent I/O lands. To reduce
solder paste volume on the larger thermal lands, it is
recommended that an array of smaller apertures be used instead
of one large aperture. It is recommended that the stencil printing
area cover 50% to 80% of the PCB layout pattern. A typical solder
stencil pattern is shown on page 54. The gap width between pad to
pad is 0.6mm. The user should consider the symmetry of the
whole stencil pattern when designing its pads. A laser cut,
stainless steel stencil with electropolished trapezoidal walls is
recommended. Electropolishing “smooths” the aperture walls
resulting in reduced surface friction and better paste release which
reduces voids. Using a Trapezoidal Section Aperture (TSA) also
promotes paste release and forms a “brick like” paste deposit that
assists in firm component placement. A 0.1mm to 0.15mm stencil
thickness is recommended for this large pitch (1.3mm) HDA.
Reflow Parameters
Due to the low mount height of the HDA, “No Clean” Type 3 solder
paste per ANSI/J-STD-005 is recommended. Nitrogen purge is
also recommended during reflow. A system board reflow profile
depends on the thermal mass of the entire populated board, so it
is not practical to define a specific soldering profile just for the
HDA. The profile given in Figure 27 is provided as a guideline, to
be customized for varying manufacturing practices and
applications.
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ISL8272M
PMBus Command Summary
COMMAND
CODE
COMMAND
NAME
DESCRIPTION
TYPE
DATA
FORMAT
DEFAULT
VALUE
DEFAULT
SETTING
PAGE
01h
OPERATION
Sets Enable, Disable and VOUT
Margin modes.
R/W BYTE
BIT
02h
ON_OFF_CONFIG
Configures the EN pin and PMBus
commands to turn the unit
ON/OFF
R/W BYTE
BIT
03h
CLEAR_FAULTS
Clears fault indications.
SEND BYTE
29
15h
STORE_USER_ALL
Stores all PMBus values written
since last restore at user level.
SEND BYTE
29
16h
RESTORE_USER_ALL
Restores PMBus settings that were
stored using STORE_USER_ALL.
SEND BYTE
30
20h
VOUT_MODE
Preset to defined data format of
VOUT commands.
READ BYTE
BIT
21h
VOUT_COMMAND
Sets the nominal value of the
output voltage.
R/W WORD
L16u
23h
VOUT_CAL_OFFSET
Applies a fixed offset voltage to the
VOUT_COMMAND.
R/W WORD
L16s
24h
VOUT_MAX
Sets the maximum possible value
of VOUT. 110% of pin strap VOUT.
R/W WORD
25h
VOUT_MARGIN_HIGH
Sets the value of the VOUT during a
margin high.
26h
VOUT_MARGIN_LOW
27h
29
16h
29
Linear Mode,
Exponent = -13
30
Pin Strap
30
0V
30
L16u
1.1*VOUT
Pin Strap
30
R/W WORD
L16u
1.05*VOUT
Pin Strap
31
Sets the value of the VOUT during a
margin low.
R/W WORD
L16u
0.95*VOUT
Pin Strap
31
VOUT_TRANSITION_RATE
Sets the transition rate during
margin or other change of VOUT.
R/W WORD
L11
1V/ms
31
28h
VOUT_DROOP
Sets the loadline (V/I Slope)
resistance for the rail.
R/W WORD
L11
Pin Strap
31
33h
FREQUENCY_SWITCH
Sets the switching frequency.
R/W WORD
L11
Pin Strap
31
37h
INTERLEAVE
Configures a phase offset between
devices sharing a SYNC clock.
R/W WORD
BIT
0000h
38h
IOUT_CAL_GAIN
Sense resistance for inductor DCR
current sensing.
R/W WORD
L11
B370h
0.86mΩ
32
39h
IOUT_CAL_OFFSET
Sets the current-sense offset.
R/W WORD
L11
0000h
0A
32
40h
VOUT_OV_FAULT_LIMIT
Sets the VOUT overvoltage fault
threshold.
R/W WORD
L16u
1.15*VOUT
Pin Strap
32
41h
VOUT_OV_FAULT_RESPONSE
Configures the VOUT overvoltage
fault response.
R/W BYTE
BIT
Disable and
No Retry
32
42h
VOUT_OV_WARN_LIMIT
Sets the VOUT overvoltage warn
threshold.
R/W WORD
L16u
1.10*VOUT
Pin Strap
33
43h
VOUT_UV_WARN_LIMIT
Sets the VOUT undervoltage warn
threshold.
R/W WORD
L16u
0.9 * VOUT
Pin Strap
33
44h
VOUT_UV_FAULT_LIMIT
Sets the VOUT undervoltage fault
threshold.
R/W WORD
L16u
0.85*VOUT
Pin Strap
33
45h
VOUT_UV_FAULT_RESPONSE
Configures the VOUT undervoltage
fault response.
R/W BYTE
BIT
80h
Disable and
No Retry
33
46h
IOUT_OC_FAULT_LIMIT
Sets the IOUT average overcurrent
fault threshold.
R/W WORD
L11
E3C0h
60A
33
4Bh
IOUT_UC_FAULT_LIMIT
Sets the IOUT average
undercurrent fault threshold.
R/W WORD
L11
E440h
-60A
34
4Fh
OT_FAULT_LIMIT
Sets the over-temperature fault
threshold.
R/W WORD
L11
EBE8h
+125°C
34
50h
OT_FAULT_RESPONSE
Configures the over-temperature
fault response.
R/W BYTE
BIT
80h
Disable and
No Retry
34
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13h
Hardware Enable,
Soft Off
0000h
BA00h
80h
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PMBus Command Summary (Continued)
COMMAND
CODE
COMMAND
NAME
DESCRIPTION
TYPE
DATA
FORMAT
DEFAULT
VALUE
DEFAULT
SETTING
PAGE
51h
OT_WARN_LIMIT
Sets the over-temperature warning
limit.
R/W WORD
L11
EB48h
+105°C
34
52h
UT_WARN_LIMIT
Sets the under-temperature
warning limit.
R/W WORD
L11
DC40h
-30°C
34
53h
UT_FAULT_LIMIT
Sets the under-temperature fault
threshold.
R/W WORD
L11
E580h
-40°C
35
54h
UT_FAULT_RESPONSE
Configures the under-temperature
fault response.
R/W BYTE
BIT
80h
Disable and
No Retry
35
55h
VIN_OV_FAULT_LIMIT
Sets the VIN overvoltage fault
threshold.
R/W WORD
L11
D380h
14V
35
56h
VIN_OV_FAULT_RESPONSE
Configures the VIN overvoltage
fault response.
R/W BYTE
BIT
80h
Disable and
No Retry
35
57h
VIN_OV_WARN_LIMIT
Sets the input overvoltage warning
limit.
R/W WORD
L11
D353h
13.3V
36
58h
VIN_UV_WARN_LIMIT
Sets the input undervoltage
warning limit.
R/W WORD
L11
1.05*VIN
UV Fault Limit
36
59h
VIN_UV_FAULT_LIMIT
Sets the VIN undervoltage fault
threshold.
R/W WORD
L11
Pin Strap
36
5Ah
VIN_UV_FAULT_RESPONSE
Configures the VIN undervoltage
fault response.
R/W BYTE
BIT
Disable and
No Retry
36
5Eh
POWER_GOOD_ON
Sets the voltage threshold for
Power-Good indication.
R/W WORD
L16u
0.9*VOUT
Pin Strap
36
60h
TON_DELAY
Sets the delay time from ENABLE
to start of VOUT rise.
R/W WORD
L11
Pin Strap
37
61h
TON_RISE
Sets the rise time of VOUT after
ENABLE and TON_DELAY.
R/W WORD
L11
Pin Strap
37
64h
TOFF_DELAY
Sets the delay time from DISABLE
to start of VOUT fall.
R/W WORD
L11
Pin Strap
37
65h
TOFF_FALL
Sets the fall time for VOUT after
DISABLE and TOFF_DELAY.
R/W WORD
L11
Pin Strap
37
78h
STATUS_BYTE
Returns an abbreviated status for
fast reads.
READ BYTE
BIT
00h
No Faults
38
79h
STATUS_WORD
Returns information with a
summary of the units's fault
condition.
READ WORD
BIT
0000h
No Faults
38
7Ah
STATUS_VOUT
Returns the VOUT specific status.
READ BYTE
BIT
00h
No Faults
39
80h
7Bh
STATUS_IOUT
Returns the IOUT specific status.
READ BYTE
BIT
00h
No Faults
39
7Ch
STATUS_INPUT
Returns specific status specific to
the input.
READ BYTE
BIT
00h
No Faults
39
7Dh
STATUS_TEMPERATURE
Returns the temperature specific
status.
READ BYTE
BIT
00h
No Faults
40
7Eh
STATUS_CML
Returns the Communication, Logic
and Memory specific status.
READ BYTE
BIT
00h
No Faults
40
80h
STATUS_MFR_SPECIFIC
Returns the VMON and External
Sync clock specific status.
READ BYTE
BIT
00h
No Faults
40
88h
READ_VIN
Returns the input voltage reading.
READ WORD
L11
41
8Bh
READ_VOUT
Returns the output voltage
reading.
READ WORD
L16u
41
8Ch
READ_IOUT
Returns the output current
reading.
READ WORD
L11
41
8Dh
READ_INTERNAL_TEMP
Returns the temperature reading
internal to the device.
READ WORD
L11
41
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PMBus Command Summary (Continued)
COMMAND
CODE
COMMAND
NAME
DESCRIPTION
TYPE
DATA
FORMAT
DEFAULT
VALUE
DEFAULT
SETTING
PAGE
94h
READ_DUTY_CYCLE
Returns the duty cycle reading
during the ENABLE state.
READ WORD
L11
41
95h
READ_FREQUENCY
Returns the measured operating
switch frequency.
READ WORD
L11
41
96h
READ_IOUT_0
Returns phase 1 current reading.
READ WORD
L11
41
97h
READ_IOUT_1
Returns phase 2 current reading.
READ WORD
L11
99h
MFR_ID
Sets a user defined identification.
R/W BLOCK
ASC
Null
42
42
9Ah
MFR_MODEL
Sets a user defined model.
R/W BLOCK
ASC
Null
42
9Bh
MFR_REVISION
Sets a user defined revision.
R/W BLOCK
ASC
Null
42
9Ch
MFR_LOCATION
Sets a user defined location
identifier.
R/W BLOCK
ASC
Null
42
9Dh
MFR_DATE
Sets a user defined date.
R/W BLOCK
ASC
Null
43
9Eh
MFR_SERIAL
Sets a user defined serialized
identifier.
R/W BLOCK
ASC
Null
43
A8H
LEGACY_FAULT_GROUP
Sets rail IDs of legacy devices for
fault spreading
R/W BLOCK
BIT
B0h
USER_DATA_00
Sets a user defined data.
R/W BLOCK
ASC
D0h
ISENSE_CONFIG
Configures ISENSE related
features.
R/W BYTE
BIT
D1h
USER_CONFIG
Configures several user-level
features.
R/W BYTE
D3h
DDC_CONFIG
Configures the DDC bus.
D4h
POWER_GOOD_DELAY
00000000h No rail ID
specified
43
Null
43
256ns Blanking
Time, Mid Range
44
BIT
Pin Strap (ASCR
on/off for start
up)
44
R/W WORD
BIT
Pin Strap (set
based on PMBus
address and CS)
45
Sets the delay between VOUT > PG
threshold and asserting the PG
pin.
R/W WORD
L11
3ms
45
Pin Strap
45
Prequel and
Sequel Disabled
46
05h
C300h
DFh
ASCR_CONFIG
Configures ASCR control loop.
R/W BLOCK
CUS
E0h
SEQUENCE
Identifies the Rail DDC ID to
perform multi-rail sequencing.
R/W WORD
BIT
E2h
DDC_GROUP
Sets rail DDC IDs to obey faults
and margining spreading
information.
R/W BLOCK
BIT
Pin Strap (set
based on CS)
46
E4h
DEVICE_ID
Returns the 16-byte (character)
device identifier string.
READ BLOCK
ASC
Reads Device
Version
47
E5h
MFR_IOUT_OC_FAULT_RESPONSE Configures the IOUT overcurrent
fault response.
R/W BYTE
BIT
80h
Disable and
No Retry
47
E6h
MFR_IOUT_UC_FAULT_RESPONSE Configures the IOUT undercurrent
fault response.
R/W BYTE
BIT
80h
Disable and
No Retry
47
E9h
SYNC_CONFIG
Configures the Sync pin.
R/W BYTE
BIT
Pin Strap (set
based on CS)
47
EAh
SNAPSHOT
Returns 32-byte read-back of
parametric and status values.
READ BLOCK
BIT
EBh
BLANK_PARAMS
Returns recently changed
parameter values.
READ BLOCK
BIT
F3h
SNAPSHOT_CONTROL
Snapshot feature control
command.
R/W BYTE
BIT
F4h
RESTORE_FACTORY
Restores device to the factory
default values.
SEND BYTE
F5h
MFR_VMON_OV_FAULT_LIMIT
Returns the VMON overvoltage
threshold.
READ WORD
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27
0000h
48
FF...FFh
48
48
49
L11
CB00h
6V
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ISL8272M
PMBus Command Summary (Continued)
COMMAND
CODE
COMMAND
NAME
DESCRIPTION
TYPE
DATA
FORMAT
DEFAULT
VALUE
CA00h
DEFAULT
SETTING
4V
PAGE
F6h
MFR_VMON_UV_FAULT_LIMIT
Returns the VMON undervoltage
threshold.
READ WORD
L11
49
F7h
MFR_READ_VMON
Returns the VMON voltage
reading.
READ WORD
L11
F8h
VMON_OV_FAULT_RESPONSE
Returns the VMON overvoltage
response.
READ BYTE
BIT
80h
Disable and
No Retry
49
F9h
VMON_UV_FAULT_RESPONSE
Returns the VMON undervoltage
response.
READ BYTE
BIT
80h
Disable and No
Retry
49
49
PMBus™ Data Formats
Linear-11 (L11)
L11 data format uses 5-bit two’s compliment exponent (N) and 11-bit two’s compliment mantissa (Y) to represent real world decimal
value (X).
Data Byte High
Data Byte Low
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Exponent (N)
Mantissa (Y)
Relation between real world decimal value (X), N and Y is: X = Y·2N
Linear-16 Unsigned (L16u)
L16u data format uses a fixed exponent (hard-coded to N = -13h) and a 16-bit unsigned integer mantissa (Y) to represent real world
decimal value (X). Relation between real world decimal value (X), N and Y is: X = Y·2-13
Linear-16 Signed (L16s)
L16s data format uses a fixed exponent (hard-coded to N = -13h) and a 16-bit two’s compliment mantissa (Y) to represent real world
decimal value (X).
Relation between real world decimal value (X), N and Y is: X = Y·2-13
Bit Field (BIT)
Breakdown of Bit Field is provided in “PMBus Commands Description” on page 29.
Custom (CUS)
Breakdown of Custom data format is provided in “PMBus Commands Description” on page 29. A combination of Bit Field and integer
are common type of Custom data format.
ASCII (ASC)
A variable length string of text characters uses ASCII data format.
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PMBus Commands Description
OPERATION (01h)
Definition: Sets Enable, Disable and VOUT Margin settings. Data values of OPERATION that force margin high or low only take effect
when the MGN pin is left open (i.e., in the NOMINAL margin state).
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value:
Units: N/A
SETTINGS
ACTIONS
04h
Immediate off (no sequencing)
44h
Soft off (with sequencing)
84h
On - Nominal
94h
On - Margin low
A4h
On - Margin high
ON_OFF_CONFIG (02h)
Definition: Configures the interpretation and coordination of the OPERATION command and the ENABLE pin (EN).
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 16h (Device starts from ENABLE pin with soft off)
Units: N/A
SETTINGS
ACTIONS
16h
Device starts from ENABLE pin with soft off.
17h
Device starts from ENABLE pin with immediate off.
1Ah
Device starts from OPERATION command with soft off.
1Bh
Device starts from OPERATION command with immediate off.
CLEAR_FAULTS (03h)
Definition: Clears all fault bits in all registers and releases the SALRT pin (if asserted) simultaneously. If a fault condition still exists, the
bit will reassert immediately. This command will not restart a device if it has shut down, it will only clear the faults.
Data Length in Bytes: 0 Byte
Data Format: N/A
Type: Write only
Default Value: N/A
Units: N/A
Reference: N/A
STORE_USER_ALL (15h)
Definition: Stores all PMBus settings from the operating memory to the nonvolatile USER store memory. To clear the USER store,
perform a RESTORE_FACTORY then STORE_USER_ALL. To add to the USER store, perform a RESTORE_USER_ALL, write commands to
be added, then STORE_USER_ALL. This command can be used during device operation, but the device will be unresponsive for 20ms
while storing values.
Data Length in Bytes: 0
Data Format: N/A
Type: Write only
Default Value: N/A
Units: N/A
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RESTORE_USER_ALL (16h)
Definition: Restores all PMBus settings from the USER store memory to the operating memory. Command performed at power-up.
Security level is changed to Level 1 following this command. This command can be used during device operation, but the device will be
unresponsive for 20ms while storing values.
Data Length in Bytes: 0
Data Format: N/A
Type: Write only
Default Value: N/A
Units: N/A
VOUT_MODE (20h)
Definition: Reports the VOUT mode and provides the exponent used in calculating several VOUT settings. Fixed with linear mode with
default exponent (N) = -13
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: 13h (Linear Mode, N = -13)
Units: N/A
VOUT_COMMAND (21h)
Definition: This command sets or reports the target output voltage. This command cannot set a value higher than either VOUT_MAX or
110% of the pin strap VOUT setting.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: Pin strap setting
Units: Volts
Range: 0V to VOUT_MAX
VOUT_CAL_OFFSET (23h)
Definition: The VOUT_CAL_OFFSET command is used to apply a fixed offset voltage to the output voltage command value. This
command is typically used by the user to calibrate a device in the application circuit.
Data Length in Bytes: 2
Data Format: L16s
Type: R/W
Default Value: 0000h
Units: Volts
VOUT_MAX (24h)
Definition: The VOUT_ MAX command sets an upper limit on the output voltage the unit can command regardless of any other
commands or combinations. The intent of this command is to provide a safeguard against a user accidentally setting the output
voltage to a possibly destructive level rather than to be the primary output overprotection. Default value can be changed via PMBus.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 1.10xVOUT_COMMAND pin strap setting
Units: Volts
Range: 0V to 5.5V
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ISL8272M
VOUT_MARGIN_HIGH (25h)
Definition: Sets the value of the VOUT during a margin high. This VOUT_MARGIN_HIGH command loads the unit with the voltage to
which the output is to be changed when the OPERATION command or MGN pin is set to “Margin High”.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default value: 1.05 x VOUT_COMMAND pin strap setting
Units: V
Range: 0V to VOUT_MAX
VOUT_MARGIN_LOW (26h)
Definition: Sets the value of the VOUT during a margin low. This VOUT_MARGIN_LOW command loads the unit with the voltage to which
the output is to be changed when the OPERATION command or MGN pin is set to “Margin Low”.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default value: 0.95 x VOUT_COMMAND pin strap setting
Units: V
Range: 0V to VOUT_MAX
VOUT_TRANSITION_RATE (27h)
Definition: This command sets the rate at which the output should change voltage when the device receives the VOUT_COMMAND or an
OPERATION command (Margin High, Margin Low) that causes the output voltage to change. The maximum possible positive value of
the two data bytes indicates that the device should make the transition as quickly as possible.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default value: BA00h (1.0 V/ms)
Units: V/ms
Range: 0.1 to 4V/ms
VOUT_DROOP (28h)
Definition: The VOUT_DROOP sets the effective load line (V/I slope) for the rail in which the device is used. It is the rate, in mV/A at
which the output voltage decreases (or increases) with increasing (or decreasing) output current for use with Adaptive Voltage
Positioning schemes or multi-module current sharing. In current sharing configuration, VOUT_DROOP set in each module stands for the
droop seen by the load.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default value: Pin strap setting
Units: mV/A
Range: 0 to 40mV/A
FREQUENCY_SWITCH (33h)
Definition: Sets the switching frequency of the device. Initial default value is defined by a pin strap and this value can be overridden by
writing this command via PMBus. If an external SYNC is utilized, this value should be set as close as possible to the external clock value.
The output must be disabled when writing this command.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: Pin strap setting
Units: kHz
Range: 300kHz to 1066kHz
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ISL8272M
INTERLEAVE (37h)
Definition: Configures the phase offset of a device that is sharing a common SYNC clock with other devices. The phase offset of each
device can be set to any value between 0° and 360° in 22.5° increments. The internal two phases of the module always maintain a
phase difference of 180°.
Data Length in Bytes: 2
Data Format: BIT
Type: R/W
Default Value: 0000h
Units: N/A
BITS
PURPOSE
VALUE
15:4
Reserved
0
3:0
Position in Group
0 to 15
DESCRIPTION
Reserved
Sets position of the device's rail within the group.
IOUT_CAL_GAIN (38h)
Definition: Sets the effective impedance across the current sense circuit for use in calculating output current at +25°C.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: B370h (0.86mΩ)
Units: mΩ
IOUT_CAL_OFFSET (39h)
Definition: Used to null out any offsets in the output current sensing circuit and to compensate for delayed measurements of current
ramp due to Isense blanking time.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: 0000h (0A)
Units: A
VOUT_OV_FAULT_LIMIT (40h)
Definition: Sets the VOUT overvoltage fault threshold.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 1.15xVOUT_COMMAND pin strap setting
Units: V
Range: 0V to VOUT_MAX
VOUT_OV_FAULT_RESPONSE (41h)
Definition: Configures the VOUT overvoltage fault response. Note that the device cannot be set to ignore this fault mode.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable and no retry)
Units: N/A
SETTINGS
ACTIONS
80h
Disable with no retry.
BFh
Disable and continuous retry with 70ms delay.
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ISL8272M
VOUT_OV_WARN_LIMIT (42h)
Definition: Sets the VOUT overvoltage warning threshold. Power-good signal is pulled low when output voltage goes higher than this
threshold.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 1.10xVOUT_COMMAND pin strap setting
Units: V
Range: 0V to VOUT_MAX
VOUT_UV_WARN_LIMIT (43h)
Definition: Sets the VOUT undervoltage warning threshold. Power-good signal is pulled low when output voltage goes lower than this
threshold.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 0.90xVOUT_COMMAND pin strap setting
Units: V
Range: 0V to VOUT_MAX
VOUT_UV_FAULT_LIMIT (44h)
Definition: Sets the VOUT undervoltage fault threshold. This fault is masked during ramp or when disabled.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 0.85xVOUT_COMMAND pin strap setting
Units: V
Range: 0V to VOUT_MAX
VOUT_UV_FAULT_RESPONSE (45h)
Definition: Configures the VOUT undervoltage fault response.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable, no retry)
Units: N/A
SETTINGS
ACTIONS
80h
Disable with no retry.
BFh
Disable and continuous retry with 70ms delay.
IOUT_OC_FAULT_LIMIT (46h)
Definition: Sets the IOUT average overcurrent fault threshold. Device will automatically calculate peak inductor overcurrent fault limit
for each phase based on the equation: IOUT(PEAK OC LIMIT) = (0.5*IOUT_OC_FAULT_LIMIT+0.5*IRIPPLE(P-P))*120%. A hard bound of
42A is applied to the peak overcurrent fault limit per phase.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: E3C0h (60A)
Units: A
Range: -100 to 100A
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ISL8272M
IOUT_UC_FAULT_LIMIT (4Bh)
Definition: Sets the IOUT average undercurrent fault threshold. Device will automatically calculate valley inductor undercurrent fault limit
for each phase based on the equation: IOUT(VALLEY UC LIMIT) = (0.5*IOUT_UC_FAULT_LIMIT-0.5*IRIPPLE(P-P))*120%. A hard bound of 42A is applied to the valley undercurrent fault limit per phase.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: -1xIOUT_OC_FAULT_LIMIT
Units: A
Range: -100 to 100A
OT_FAULT_LIMIT (4Fh)
Definition: The OT_FAULT_LIMIT command sets the temperature at which the device should indicate an over-temperature fault. Note
that the temperature must drop below OT_WARN_LIMIT to clear this fault.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: EBE8h (+125˚C)
Units: Celsius
Range: 0°C to +175°C
OT_FAULT_RESPONSE (50h)
Definition: The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an over-temperature fault.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Fault Value: 80h (Disable and no retry)
Units: N/A
SETTINGS
ACTIONS
80h
Disable with no retry.
BFh
Disable and continuous retry with 70ms delay.
OT_WARN_LIMIT (51h)
Definition: The OT_WARN_LIMIT command sets the temperature at which the device should indicate an over-temperature warning
alarm. In response to the OT_WARN_LIMIT being exceeded, the device: Sets the TEMPERATURE bit in STATUS_WORD, Sets the
OT_WARNING bit in STATUS_TEMPERATURE and notifies the host.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: EB48h (+105°C)
Units: Celsius
Range: 0°C to +175°C
UT_WARN_LIMIT (52h)
Definition: The UT_WARN_LIMIT command set the temperature at which the device should indicate an under-temperature warning
alarm. In response to the UT_WARN_LIMIT being exceeded, the device: Sets the TEMPERATURE bit in STATUS_WORD, Sets the
UT_WARNING bit in STATUS_TEMPERATURE and notifies the host.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: DC40h (-30°C)
Units: Celsius
Range: -55°C to +25°C
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ISL8272M
UT_FAULT_LIMIT (53h)
Definition: The UT_FAULT_LIMIT command sets the temperature, in degrees Celsius, of the unit where it should indicate an
under-temperature fault. Note that the temperature must rise above UT_WARN_LIMIT to clear this fault.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: E580h (-40°C)
Units: Celsius
Range: -55°C to +25°C
UT_FAULT_RESPONSE (54h)
Definition: Configures the under-temperature fault response as defined by the following table. The delay time is the time between
restart attempts.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable, no retry)
Units: N/A
SETTINGS
ACTIONS
80h
Disable with no retry.
BFh
Disable and continuous retry with 70ms delay.
VIN_OV_FAULT_LIMIT (55h)
Definition: Sets the VIN overvoltage fault threshold.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: D380h (14V)
Units: V
Range: 0V to 16V
VIN_OV_FAULT_RESPONSE (56h)
Definition: Configures the VIN overvoltage fault response as defined by the following table. The delay time is the time between restart
attempts.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable and no retry)
Units: N/A
SETTINGS
ACTIONS
80h
Disable with no retry.
BFh
Disable and continuous retry with 70ms delay.
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ISL8272M
VIN_OV_WARN_LIMIT (57h)
Definition: Sets the VIN overvoltage warning threshold. In response to the OV_WARN_LIMIT being exceeded, the device: Sets the NONE
OF THE ABOVE and INPUT bits in STATUS_WORD, Sets the VIN_OV_WARNING bit in STATUS_INPUT and notifies the host.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Protectable: Yes
Default Value: D353h (13.3V)
Units: V
Range: 0V to 16V
VIN_UV_WARN_LIMIT (58h)
Definition: Sets the VIN undervoltage warning threshold. If a VIN_UV_FAULT occurs, the input voltage must rise above
VIN_UV_WARN_LIMIT to clear the fault, which provides hysteresis to the fault threshold. In response to the UV_WARN_LIMIT being
exceeded, the device: Sets the NONE OF THE ABOVE and INPUT bits in STATUS_WORD, Sets the VIN_UV_WARNING bit in STATUS_INPUT
and notifies the host.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: 1.05 x VIN_UV_FAULT_LIMIT pin strap setting
Units: V
Range: 0V to 12V
VIN_UV_FAULT_LIMIT (59h)
Definition: Sets the VIN undervoltage fault threshold.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: Pin strap setting
Units: V
Range: 0V to 12V
VIN_UV_FAULT_RESPONSE (5Ah)
Definition: Configures the VIN undervoltage fault response as defined by the following table. The delay time is the time between restart
attempts.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable and no retry)
Units: N/A
SETTINGS
ACTIONS
80h
Disable with no retry
BFh
Disable and continuous retry with 70ms delay
POWER_GOOD_ON (5Eh)
Definition: Sets the voltage threshold for Power-good indication. Power-good asserts with a delay specified in POWER_GOOD_DELAY
after the output voltage exceeds POWER_GOOD_ON and deasserts when the output voltage is less than VOUT_UV_WARN_LIMIT.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 0.9xVOUT_COMMAND pin strap setting
Units: V
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ISL8272M
TON_DELAY (60h)
Definition: Sets the delay time from when the device is enabled to the start of VOUT rise.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: Pin strap setting
Units: ms
Range: 0 to 500ms
TON_RISE (61h)
Definition: Sets the rise time of VOUT after ENABLE and TON_DELAY. In multi-module current sharing configuration where ASCR is
disabled for start up, the rise time of VOUT can be approximately calculated by Equation 1.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: Pin strap setting
Units: ms
Range: 0 to 200ms
TOFF_DELAY (64h)
Definition: Sets the delay time from DISABLE to start of VOUT fall.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: Pin strap setting
Units: ms
Range: 0 to 500ms
TOFF_FALL (65h)
Definition: Sets the soft-off fall time for VOUT after DISABLE and TOFF_DELAY.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: Pin strap setting
Units: ms
Range: 0 to 200ms
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FN8670.2
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ISL8272M
STATUS_BYTE (78h)
Definition: The STATUS_BYTE command returns one byte of information with a summary of the most critical faults.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: 00h
Units: N/A
BIT NUMBER
STATUS BIT NAME
MEANING
7
BUSY
6
OFF
5
VOUT_OV_FAULT
An output overvoltage fault has occurred.
4
IOUT_OC_FAULT
An output overcurrent fault has occurred.
3
VIN_UV_FAULT
An input undervoltage fault has occurred.
2
TEMPERATURE
A temperature fault or warning has occurred.
1
CML
0
NONE OF THE ABOVE
A fault was declared because the device was busy and unable to respond.
This bit is asserted if the unit is not providing power to the output, regardless of
the reason, including simply not being enabled.
A communications, memory or logic fault has occurred.
A fault or warning not listed in bits 7:1 has occurred.
STATUS_WORD (79h)
Definition: The STATUS_WORD command returns two bytes of information with a summary of the unit's fault condition. Based on the
information in these bytes, the host can get more information by reading the appropriate status registers. The low byte of the
STATUS_WORD is the same register as the STATUS_BYTE (78h) command.
Data Length in Bytes: 2
Data Format: BIT
Type: Read-only
Default Value: 0000h
Units: N/A
BIT NUMBER
STATUS BIT NAME
15
VOUT
14
IOUT/POUT
13
INPUT
12
MFG_SPECIFIC
11
POWER_GOOD#
10
FANS
9
OTHER
8
UNKNOWN
7
BUSY
6
OFF
5
VOUT_OV_FAULT
An output overvoltage fault has occurred.
4
IOUT_OC_FAULT
An output overcurrent fault has occurred.
3
VIN_UV_FAULT
An input undervoltage fault has occurred.
2
TEMPERATURE
A temperature fault or warning has occurred.
1
CML
0
NONE OF THE ABOVE
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MEANING
An output voltage fault or warning has occurred.
An output current or output power fault or warning has occurred.
An input voltage, input current, or input power fault or warning has occurred.
A manufacturer specific fault or warning has occurred.
The POWER_GOOD signal, if present, is negated.
A fan or airflow fault or warning has occurred.
A bit in STATUS_OTHER is set.
A fault type not given in bits 15:1 of the STATUS_WORD has been detected.
A fault was declared because the device was busy and unable to respond.
This bit is asserted if the unit is not providing power to the output, regardless of
the reason, including simply not being enabled.
A communications, memory or logic fault has occurred.
A fault or warning not listed in bits 7:1 has occurred.
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STATUS_VOUT (7Ah)
Definition: The STATUS_VOUT command returns one data byte with the status of the output voltage.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: 00h
Units: N/A
BIT NUMBER
STATUS BIT NAME
MEANING
7
VOUT_OV_FAULT
6
VOUT_OV_WARNING
Indicates an output overvoltage fault.
Indicates an output overvoltage warning.
5
VOUT_UV_WARNING
Indicates an output undervoltage warning.
4
VOUT_UV_FAULT
3:0
N/A
Indicates an output undervoltage fault.
These bits are not used.
STATUS_IOUT (7Bh)
Definition: The STATUS_IOUT command returns one data byte with the status of the output current.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: 00h
Units: N/A
BIT NUMBER
STATUS BIT NAME
MEANING
7
IOUT_OC_FAULT
6
IOUT_OC_LV_FAULT
An output overcurrent and low voltage fault has occurred.
An output overcurrent fault has occurred.
5
IOUT_OC_WARNING
An output overcurrent warning has occurred.
4
IOUT_UC_FAULT
3:0
N/A
An output undercurrent fault has occurred.
These bits are not used.
STATUS_INPUT (7Ch)
Definition: The STATUS_INPUT command returns input voltage and input current status information.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: 00h
Units: N/A
BIT NUMBER
STATUS BIT NAME
7
VIN_OV_FAULT
6
VIN_OV_WARNING
5
VIN_UV_WARNING
4
VIN_UV_FAULT
3:0
N/A
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MEANING
An input overvoltage fault has occurred.
An input overvoltage warning has occurred.
An input undervoltage warning has occurred.
An input undervoltage fault has occurred.
These bits are not used.
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STATUS_TEMP (7Dh)
Definition: The STATUS_TEMP command returns one byte of information with a summary of any temperature related faults or warnings.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: 00h
Units: N/A
BIT NUMBER
STATUS BIT NAME
MEANING
7
OT_FAULT
6
OT_WARNING
An over-temperature warning has occurred.
An over-temperature fault has occurred.
5
UT_WARNING
An under-temperature warning has occurred.
4
UT_FAULT
3:0
N/A
An under-temperature fault has occurred.
These bits are not used.
STATUS_CML (7Eh)
Definition: The STATUS_CML command returns one byte of information with a summary of any Communications, Logic and/or Memory
errors.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: 00h
Units: N/A
BIT NUMBER
MEANING
7
Invalid or unsupported PMBus command was received.
6
The PMBus command was sent with invalid or unsupported data.
5
packet error was detected in the PMBus command.
4:2
Not Used
1
A PMBus command tried to write to a read-only or protected command, or a communication fault other than the ones listed in
this table has occurred.
0
Not Used
STATUS_MFR_SPECIFIC (80h)
Definition: The STATUS_MFR_SPECIFIC command returns one byte of information providing the status of the device's voltage
monitoring and clock synchronization faults. VMON OV/UV warnings are set at ±10% of the VMON_FAULT commands.
Data Length in Bytes: 1
Data Format: BIT
Type: Read only
Default value: 00h
Units: N/A
BIT NUMBER
FIELD NAME
MEANING
7:6
Reserved
5
VMON UV Warning
The voltage on the VMON pin has dropped 10% below the level set by
VMON_UV_FAULT_LIMIT.
4
VMON OV Warning
The voltage on the VMON pin has risen 10% above the level set by
VMON_OV_FAULT_LIMIT.
3
External Switching Period Fault
Loss of external clock synchronization has occurred.
2
Reserved
1
VMON UV Fault
The voltage on the VMON pin has dropped below the level set by
VMON_UV_FAULT_LIMIT.
0
VMON OV Fault
The voltage on the VMON pin has risen above the level set by
VMON_OV_FAULT_LIMIT.
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FN8670.2
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ISL8272M
READ_VIN (88h)
Definition: Returns the input voltage reading.
Data Length in Bytes: 2
Data Format: L11
Type: Read-only
Units: V
READ_VOUT (8Bh)
Definition: Returns the output voltage reading.
Data Length in Bytes: 2
Data Format: L16u
Type: Read-only
Units: V
READ_IOUT (8Ch)
Definition: Returns the output current reading.
Data Length in Bytes: 2
Data Format: L11
Type: Read-only
Default Value: N/A
Units: A
READ_INTERNAL_TEMP (8Dh)
Definition: Returns the controller junction temperature reading from internal temperature sensor.
Data Length in Bytes: 2
Data Format: L11
Type: Read-only
Units: °C
READ_DUTY_CYCLE (94h)
Definition: Reports the actual duty cycle of the converter during the enable state.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Units: %
READ_FREQUENCY (95h)
Definition: Reports the actual switching frequency of the converter during the enable state.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Units: kHz
READ_IOUT_0 (96h)
Definition: Returns the Phase 1 current reading.
Data Length in Bytes: 2
Data Format: L11
Type: Read-only
Default Value: N/A
Units: A
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ISL8272M
READ_IOUT_1 (97h)
Definition: Returns the Phase 2 current reading.
Data Length in Bytes: 2
Data Format: L11
Type: Read-only
Default Value: N/A
Units: A
MFR_ID (99h)
Definition: MFR_ID sets user defined identification. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,
MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This
limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this
command then perform a STORE/RESTORE.
Data Length in Bytes: user defined
Data Format: ASCII
Type: Block R/W
Default Value: null
Units: N/A
MFR_MODEL (9Ah)
Definition: MFR_MODEL sets a user defined model. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,
MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This
limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this
command then perform a STORE/RESTORE.
Data Length in Bytes: user defined
Data Format: ASC
Type: Block R/W
Default Value: null
Units: N/A
MFR_REVISION (9Bh)
Definition: MFR_REVISION sets a user defined revision. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,
MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This
limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this
command then perform a STORE/RESTORE.
Data Length in Bytes: user defined
Data Format: ASC
Type: Block R/W
Default Value: null
Units: N/A
MFR_LOCATION (9Ch)
Definition: MFR_LOCATION sets a user defined location identifier. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,
MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This
limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this
command then perform a STORE/RESTORE.
Data Length in Bytes: User defined
Data Format: ASC
Type: Block R/W
Default Value: null
Units: N/A
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ISL8272M
MFR_DATE (9Dh)
Definition: MFR_DATE sets a user defined date. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION, MFR_LOCATION,
MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This limitation includes
multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this command then
perform a STORE/RESTORE.
Data Length in Bytes: User defined
Data Format: ASC
Type: Block R/W
Default Value: null
Units: N/A
Reference: N/A
MFR_SERIAL (9Eh)
Definition: MFR_SERIAL sets a user defined serialized identifier. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,
MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This
limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this
command then perform a STORE/RESTORE.
Data Length in Bytes: User defined
Data Format: ASC
Type: Block R/W
Default Value: null
Units: N/A
LEGACY_FAULT_GROUP (A8h)
Definition: This command sets which rail DDC IDs should be listened to for fault spreading with legacy devices. The data sent is a
4-byte, 32-bit, bit vector where every bit represents a rail’s DDC ID. A bit set to 1 indicates a device DDC ID to which the configured
device will respond upon receiving a fault spreading event. In this vector, bit 0 of byte 0 corresponds to the rail with DDC ID 0. Following
through, Bit 7 of byte 3 corresponds to the rail with DDC ID 31.
Data Length in Bytes: 4
Data Format: BIT
Type: R/W
Default Value: 00000000h
USER_DATA_00 (B0h)
Definition: USER_DATA_00 sets a user defined data. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,
MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This
limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this
command then perform a STORE/RESTORE.
Data Length in Bytes: User defined
Data Format: ASCII
Type: Block R/W
Default Value: null
Units: N/A
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43
FN8670.2
January 14, 2015
ISL8272M
ISENSE_CONFIG (D0h)
Definition: Configures current sense circuitry.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 05h
Units: N/A
BIT
FIELD NAME
VALUE
7:4
Reserved
000
3:2
Current Sense
Blanking Time
1:0
Current Sense Range
SETTING
DESCRIPTION
00
192ns
Sets the blanking time current sense blanking time.
01
256ns
10
412ns
11
640ns
00
Low Range
±25mV
01
Mid Range
±35mV
10
High Range
±50mV
11
Not Used
USER_CONFIG (D1h)
Definition: Configures several user-level features. This command overrides the CONFIG pin settings.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: Pin strap setting
Units: N/A
BIT
7
FIELD NAME
ASCR on for Start up
VALUE
SETTING
0
Disabled
1
Enabled
6:5
Reserved
0
4:3
Ramp-Up and
Ramp-Down Minimum
Duty Cycle
00
0.39%
01
0.78%
2
1
0
Minimum Duty Cycle
Control
Power-Good Pin
Configuration
Reserved
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DESCRIPTION
ASCR is disabled for start up. Use this for current sharing mode.
ASCR is enabled for start up. Use this for stand alone mode.
Reserved
10
1.17%
11
1.56%
0
Disable
1
Enable
0
Open Drain
1
Push-Pull
Sets the minimum duty-cycle during start-up and shutdown ramp.
Control for minimum duty cycle.
0 = PG is open drain output.
1 = PG is push-pull output.
0
44
FN8670.2
January 14, 2015
ISL8272M
DDC_CONFIG (D3h)
Definition: Configures DDC addressing and current sharing. With pin strap for stand alone configuration, the DDC rail ID is set according
to the SMBus address. With pin strap for multi-module current sharing, the DDC rail ID is set according to the number of devices. Device
position and number of devices in the rail can be programmed as needed.
Data Length in Bytes: 2
Data Format: BIT
Type: R/W
Default Value: Pin strap setting
Units: N/A
BIT
FIELD NAME
15:13
Device Position
12:8
Rail ID
VALUE
SETTING
DESCRIPTION
0, 1, 2, 3
Sets the device position in a current sharing rail. 0-Position 1;
1-Position 2; 2-Position 3; 3-Position 4
0 to 31 (00 to 1Fh)
7:3
Reserved
2:0
Number of Devices in
Rail
0
Configures DDC rail ID
Reserved
Reserved
1, 3, 5, 7
Identifies the number of devices in a current sharing rail. 1-standalone;
3-two devices; 5-three devices; 7-four devices
POWER_GOOD_DELAY (D4h)
Definition: Sets the delay applied between the output exceeding the PG threshold (POWER_GOOD_ON) and asserting the PG pin. The
delay time can range from 0ms up to 500s, in steps of 125ns. A 1ms minimum configured value is recommended to apply proper
de-bounce to this signal.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: 3ms
Units: ms
Range: 0 to 5s
ASCR_CONFIG (DFh)
Definition: Allows user configuration of ASCR settings. ASCR Gain is analogous to bandwidth, ASCR Residual is analogous to damping.
To improve load transient response performance, increase ASCR Gain. To lower transient response overshoot, increase ASCR Residual.
Increasing ASCR gain can result in increased PWM jitter and should be evaluated in the application circuit. Excessive ASCR gain can
lead to excessive output voltage ripple. Increasing ASCR Residual to improve transient response damping can result in slower recovery
times, but will not affect the peak output voltage deviation. Typical ASCR Gain settings range from 50 to 1000 and ASCR Residual
settings range from 10 to 100.
Data Length in Bytes: 4
Data Format: CUS
Type: R/W
Default Value: Pin strap setting
BIT
31:25
24
PURPOSE
DATA Format
Unused
ASCR Enable
BIT
VALUE
DESCRIPTION
0000000h
Unused
1
Enable
0
Disable
23:16
ASCR Residual Setting
Integer
ASCR residual
15:0
ASCR Gain Setting
Integer
ASCR gain
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45
FN8670.2
January 14, 2015
ISL8272M
SEQUENCE (E0h)
Definition: Identifies the Rail DDC ID of the prequel and sequel rails when performing multi-rail sequencing. The device will enable its
output when its EN or OPERATION enable states, as defined by ON_OFF_CONFIG, is set and the prequel device has issued a Power-Good
event on the DDC bus. The device will disable its output (using the programmed delay values) when the sequel device has issued a
Power-Down event on the DDC bus.
The data field is a two-byte value. The most-significant byte contains the 5-bit Rail DDC ID of the prequel device. The least-significant
byte contains the 5-bit Rail DDC ID of the sequel device. The most significant bit of each byte contains the enable of the prequel or
sequel mode. This command overrides the corresponding sequence configuration set by the CONFIG pin settings.
Data Length in Bytes: 2
Data Format: BIT
Type: R/W
Default Value: 0000h (Prequel and Sequel disabled)
BIT
15
FIELD NAME
Prequel Enable
14:13
Reserved
12:8
Prequel Rail DDC ID
7
Sequel Enable
6:5
Reserved
4:0
Sequel Rail DDC ID
VALUE
SETTING
DESCRIPTION
0
Disable
Disable, no prequel preceding this rail.
1
Enable
Enable, prequel to this rail is defined by bits 12:8.
0
Reserved
0-31
DDC ID
Set to the DDC ID of the prequel rail.
Reserved
0
Disable
Disable, no sequel following this rail.
1
Enable
Enable, sequel to this rail is defined by bits 4:0.
0
Reserved
0-31
DDC ID
Reserved
Set to the DDC ID of the sequel rail.
DDC_GROUP (E2h)
Definition: This command configures fault spreading group ID and enable, broadcast OPERATION group ID and enable and broadcast
VOUT_COMMAND group ID and enable.
Data Length in Bytes: 3
Data Format: BIT
Type: R/W
Default Value: Pin strap setting (Ignore BROADCAST VOUT_COMMAND, OPERATION and fault for stand alone operation. Enable
BROADCAST VOUT_COMMAND, OPERATION and fault for current sharing).
BITS
23:22
PURPOSE
Reserved
21
BROADCAST_VOUT_COMMAND Response
20:16
BROADCAST_VOUT_COMMAND Group ID
15:14
Reserved
13
12:8
7:6
BROADCAST_OPERATION Response
BROADCAST_OPERATION Group ID
Reserved
5
POWER_FAIL Response
4:0
POWER_FAIL group ID
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46
VALUE
DESCRIPTION
0
Reserved
1
Responds to BROADCAST_VOUT_COMMAND with same Group ID.
0
Ignores BROADCAST_VOUT_COMMAND.
0-31d
Group ID sent as data for broadcast BROADCAST_VOUT_COMMAND events.
0
Reserved
1
Responds to BROADCAST_OPERATION with same Group ID.
0
Ignores BROADCAST_OPERATION.
0-31d
Group ID sent as data for broadcast BROADCAST_OPERATION events.
0
Reserved
1
Responds to POWER_FAIL events with same Group ID by shutting down
immediately.
0
Responds to POWER_FAIL events with same Group ID with sequenced shutdown.
0-31d
Group ID sent as data for broadcast POWER_FAIL events.
FN8670.2
January 14, 2015
ISL8272M
DEVICE_ID (E4h)
Definition: Returns the 16-byte (character) device identifier string.
Data Length in Bytes: 16
Data Format: ASCII
Type: Block Read
Default Value: Part number/Die revision/Firmware revision
MFR_IOUT_OC_FAULT_RESPONSE (E5h)
Definition: Configures the IOUT overcurrent fault response as defined by the following table. The command format is the same as the
PMBus standard fault responses except that it sets the overcurrent status bit in STATUS_IOUT.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable and no retry)
Units: N/A
SETTINGS
ACTIONS
80h
Disable with no retry.
BFh
Disable and continuous retry with 70ms delay.
MFR_IOUT_UC_FAULT_RESPONSE (E6h)
Definition: Configures the IOUT undercurrent fault response as defined by the following table. The command format is the same as the
PMBus standard fault responses except that it sets the undercurrent status bit in STATUS_IOUT.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable and no retry)
Units: N/A
SETTINGS
ACTIONS
80h
Disable with no retry.
BFh
Disable and continuous retry with 70ms delay.
SYNC_CONFIG (E9h)
Definition: This command is used to set options for SYNC output configurations.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: Pin strap setting
SETTINGS
ACTIONS
00h
Use Internal clock. Clock frequency is set by pin strap or PMBus command.
02h
Use internal clock and output internal clock.
04h
Use external clock.
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47
FN8670.2
January 14, 2015
ISL8272M
SNAPSHOT (EAh)
Definition: The SNAPSHOT command is a 32-byte read-back of parametric and status values. It allows monitoring and status data to be
stored to flash following a fault condition. In case of a fault, last updated values are stored to the flash memory. When SNAPSHOT
STATUS bit is set stored, device will no longer automatically capture parametric and status values following fault till stored data are
erased. Use SNAPSHOT_CONTROL command to erase store data and clear the status bit before next ramp up. Data erased is not
allowed when module is enabled.
Data Length in Bytes: 32
Data Format: Bit field
Type: Block Read
BYTE NUMBER
31:23
VALUE
PMBUS COMMAND
FORMAT
Reserved
Reserved
00h
22
Flash Memory Status Byte
FF - Not Stored
00 - Stored
N/A
BIT
21
Manufacturer Specific Status Byte
STATUS_MFR_SPECIFIC (80h)
Byte
20
CML Status Byte
STATUS_CML (7Eh)
Byte
19
Temperature Status Byte
STATUS_TEMPERATURE (7Dh)
Byte
18
Input Status Byte
STATUS_INPUT (7Ch)
Byte
17
IOUT Status Byte
STATUS_IOUT (7Bh)
Byte
16
VOUT Status Byte
STATUS_VOUT (7Ah)
Byte
15:14
Switching Frequency
READ_FREQUENCY (95h)
L11
13:12
Reserved
Reserved
00h
11:10
Internal Temperature
READ_INTERNAL_TEMP (8Dh)
L11
9:8
Duty Cycle
READ_DUTY_CYCLE (94h)
L11
7:6
Highest Measured Output Current
N/A
L11
5:4
Output Current
READ_IOUT (8Ch)
L11
3:2
Output Voltage
READ_VOUT (8Bh)
L16u
1:0
Input Voltage
READ_VIN (88h)
L11
BLANK_PARAMS (EBh)
Definition: Returns a 16-byte string indicating which parameter values were either retrieved by the last RESTORE operation or have
been written since that time. Reading BLANK_PARAMS immediately after a restore operation allows the user to determine which
parameters are stored in that store. A one indicates the parameter is not present in the store and has not been written since the
RESTORE operation.
Data Length in Bytes: 16
Data Format: BIT
Type: Block Read
Default Value: FF…FFh
SNAPSHOT_CONTROL (F3h)
Definition: Writing a 01h will cause the device to copy the current SNAPSHOT values from NVRAM to the 32-byte SNAPSHOT command
parameter. Writing a 02h will cause the device to write the current SNAPSHOT values to NVRAM, 03h will erase all SNAPSHOT values
from NVRAM. Write (02h) and Erase (03h) may only be used when the device is disabled. All other values will be ignored.
Data Length in Bytes: 1
Data Format: Bit field
Type: R/W byte
VALUE
DESCRIPTION
01h
Read SNAPSHOT values from NV RAM
02h
Write SNAPSHOT values to NV RAM
03h
Erase SNAPSHOT values stored in NV RAM.
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48
FN8670.2
January 14, 2015
ISL8272M
RESTORE_FACTORY (F4h)
Definition: Restores the device to the hard-coded Factory default values and pin strap definitions. The device retains the DEFAULT and
USER stores for restoring. Security level is changed to Level 1 following this command.
Data Length in Bytes: 0
Data Format: N/A
Type: Write only
Default Value: N/A
Units: N/A
MFR_VMON_OV_FAULT_LIMIT (F5h)
Definition: Reads the VMON OV fault threshold.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Default Value: CB00h (6V)
Units: V
Range: 4V to 6V
MFR_VMON_UV_FAULT_LIMIT (F6h)
Definition: Reads the VMON UV fault threshold
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Default Value: CA00h (4V)
Units: V
Range: 4V to 6V
MFR_READ_VMON (F7h)
Definition: Reads the VMON voltage.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Default Value: N/A
Units: V
Range: 4V to 6V
VMON_OV_FAULT_RESPONSE (F8h)
Definition: Reads the VMON OV fault response
Data Length in Bytes: 1
Data Format: BIT
Type: Read only
Default Value: 80h (Disable and no retry)
Units:
VMON_UV_FAULT_RESPONSE (F9h)
Definition: Reads the VMON UV fault response, which follows VIN_UV_FAULT_RESPONSE
Data Length in Bytes: 1
Data Format: BIT
Type: Read only
Default Value: 80h (Disable and no retry)
Units: V
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49
FN8670.2
January 14, 2015
ISL8272M
Firmware Revision History
TABLE 10. ISL8272M NOMENCLATURE GUIDE
FIRMWARE REVISION CODE
CHANGE DESCRIPTION
ISL8272-000-FC01
NOTE
Initial Release
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
January 14, 2015
FN8670.2
“Electrical Specifications” on page 10 under VOUT_ACCY and VOUT_READ_ERR: Updated unit value from “% FS”
to “%VOUT”.
Updated “Switching Frequency and PLL” on page 18.
September 17, 2014
FN8670.1
Removed the words “in forced CCM Mode” from 2nd paragraph on page 1, which read “The ISL8272M operated
in forced CCM Mode with the ChargeMode™ control architecture,...
September 12, 2014
FN8670.0
Initial Release.
About Intersil
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address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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Submit Document Feedback
50
FN8670.2
January 14, 2015
Submit Document Feedback
Package Outline Drawing
Y58.18x23
58 I/O 18mmx23mmx7.5mm CUSTOM HDA MODULE
Rev 0, 8/14
18.00
A
DATUM A
B
18 17 16 1514 13 12 1110 9 8 7 6 5 4 3 2 1
51
TERMINAL #A1
INDEX AREA
(9x11.5)
12.00
23.00
0.40 REF
DATUM B
ISL8272M
0.10 C 2X
0.10 M C A B
22.60 ± 0.15
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
PIN A1 INDICATOR
C = 0.35
SEE DETAIL A
16.00
0.10 C 2X
17.20
TOP VIEW
0.10
M C AB
BOTTOM VIEW
7.50 MAX
0.10 C
2
0.20 REF
1.00
0.20 REF
SEATING PLANE
0.08 C
C
MAX 0.025
SIDE VIEW
NOTES:
FN8670.2
January 14, 2015
1.
All dimensions are in millimeters.
2.
Represents the basic land grid pitch.
3.
These 42 I/Os are centered in a fixed row and column matrix
at 1.0mm pitch BSC.
4.
Dimensioning and tolerancing per ASME Y14.5-2009.
5.
Tolerance for exposed PAD edge location dimension on
page 3 is ±0.1mm.
3
42 x 0.60 ± 0.05
42 x 0.60 ± 0.05
0.10 C A B
3
0.05 C
1.00
TERMINAL TIP
DETAIL A
2
8.20
8.80
6.80
7.20
7.80
5.80
6.20
4.20
4.80
5.20
3.20
3.80
2.20
2.80
0.50
1.20
1.80
0.80
0.20
2.80
2.20
1.80
1.20
0.50
0.20
0.80
4.20
3.80
3.20
6.20
5.20
4.80
1.00 (2X)
5.80
8.80
8.00 (2X)
7.20
7.80
Submit Document Feedback
8.40 (2X)
11.30
11.30
1.60 (2X)
52
4.80 (2X)
8.70
2.60
9.70
9.30
9.10
9.70 9.30
9.10
7.70
6.70
6.50 6.30
5.50 5.70
4.70 5.30
4.30
3.70
3.30
2.70
2.00 2.30
1.70
1.30
0.70
0.30
0.30
0.70
1.30
1.70
2.30
2.70 2.90
3.30
4.00
7.70
6.70 7.30
6.30 6.50
5.70 5.50
5.30
4.70
6.00
6.00 6.30
7.30
4.40
3.50 (2X)
4.60
2.30
1.30
1.60 (2X)
3.40
3.60
2.20
1.10
1.10 (2X)
4.40
0.00
1.00
2.30
5.00 (2X)
8.10
8.10
9.30
9.30
2.00 (2X)
1.60 (2X)
9.70
11.30
SIZE DETAILS FOR THE 16 EXPOSED PADS
TERMINAL AND PAD EDGE DETAILS
BOTTOM VIEW
8.60
6.00
6.40 6.50
5.20
4.40
3.60
2.40
2.00
1.80
1.20 0.80
0.20
0.40 0.00
4.60
3.00
2.60
0.60
3.80
6.40
8.60
5.60
5.40
6.20
7.40
7.00
7.20
5.60
2.20
6.60
11.30
4.00 (2X)
1.40 (2X)
2.90
4.00
0.80 (2X)
5.30 (2X)
0.70
5.10
4.20
2.10 (2X)
2.00
1.30
8.50
9.70
ISL8272M
1.00 (2X)
4.30
3.70
FN8670.2
January 14, 2015
8.90
9.73
1.57
2.17
2.77
3.37
3.97
4.57
5.16
5.74
6.20
6.37
8.03
1.09
1.71
2.30
2.86
3.44
4.01
4.59
5.17
5.77
6.30
6.97
7.59
8.21
10.50
8.44
9.00
7.37
8.00
7.16
7.00
6.00
6.00
4.50
5.00
3.75
4.00
3.10
3.00
2.00
1.00
1.00
0.00
1.00
0.00
1.65
2.00
1.00
3.53
3.53
4.55
6.56
6.56
7.54
7.54
8.46
8.46
9.34
9.34
10.73
FN8670.2
January 14, 2015
STENCIL OPENING CENTER POSITION (FOR REFERENCE)
3.00
4.55
6.91
7.99
8.90
9.76
10.50 10.74
ISL8272M
6.93
0.50
2.60
0.79
4.90
1.41
8.97
7.30
6.24
5.18
4.12
0.50
0.71
1.00
1.57
2.43
3.06
1.95
1.00
3.50
.
2.50
4.50
5.50
7.30
6.70
8.30
C = 0.35mm
2.03
53
8.12
7.31
6.49
5.68
5.28
4.87
4.43
3.68
2.88
8.30
6.70
5.50
0.95
1.50
2.00
2.50
3.29
3.50
4.13
4.50
0.50
2.00
1.50
3.06
4.12
5.18
6.24
7.10
8.20
Submit Document Feedback
8.18
7.50
6.82
6.08
5.63
5.03
4.48
3.83
3.23
2.80
2.63
Stencil opening center position
10.50
8.97
7.37
7.16
7.00
5.90
4.90
3.75
2.60
Stencil opening edge
9.85
9.29
8.72
8.10
6.65
6.60
6.29
5.40
5.13
4.72
4.25
3.73
3.10
2.10
2.15
4.00
4.95
6.45
7.13
11.15
9.00
9.70
8.25
7.73
7.72
6.53
5.72
5.29
4.40
3.88
3.25
2.48
1.15
3.05
4.15
6.15
6.98
7.40
7.95
8.65
8.98
9.30
9.70
10.15
54
4.05
3.60
3.35
3.00
7.55
8.10
8.50
8.83
9.15
9.85
10.30
11.15
Submit Document Feedback
8.65
7.92
7.79
7.77
7.75
7.23
6.97
6.55
6.16
5.85
5.60
5.35
5.25
4.95
4.80
4.55
8.70
8.45
7.90
7.75
7.10
7.64
7.55
7.08
6.82
6.65
6.40
6.01
5.75
5.40
5.20
4.65
4.20
4.15
4.00
3.45
3.20
2.85
6.30
5.22
4.22
3.79
3.52
2.79
2.55
2.25 2.40
2.15
1.65 1.80
2.22
1.33
1.35
1.48
1.93
2.08
2.40
2.55
2.79
3.00
3.08
3.15
3.60
3.75
4.20
4.23
4.35
4.80
5.38
5.40
5.95
6.10
6.15
6.60
6.85
7.20
7.82
1.15
0.60
0.55
0.30
0.35
0.70
0.85
1.06
1.21
0.15
0.30
0.60
1.22
1.55
1.60
1.79
2.46
1.80
1.95
2.10
2.50
2.65
2.94
2.79
3.23
3.65
3.80
3.52
3.79
4.38
4.45
4.95
4.58
4.78
5.22
4.79
4.73
4.58
3.67
3.22
2.61
2.60
2.46
1.79
1.55
1.40
1.30
1.22
0.79
0.22
0.22
0.79
1.40
2.22
2.61
3.22
3.67
4.21
5.53
5.55
6.00
5.78
5.79
6.50
6.75
6.69
7.10
7.35
7.90
7.97
8.45
4.73
5.63
6.30
6.84
7.75
8.70
11.15
9.70
8.29
8.10
7.73
6.72
6.60
5.72
5.28
4.40
3.72
3.29
3.10
2.29
1.29
0.29
0.29
0.72
1.72
2.72
4.15
6.15
7.38
7.95
8.45
8.83
9.20
9.85
9.85
9.00
8.25
7.88
6.65
6.29
5.40
4.29
4.25
3.25
2.72
2.10
0.72
1.29
2.29
3.29
4.95
6.45
6.98
7.53
8.10
8.60
8.98
9.70
11.15
FN8670.2
January 14, 2015
STENCIL OPENING EDGE POSITION (FOR REFERENCE)
ISL8272M
1.03 1.18
6.84
6.79
6.69
6.22
5.79
5.63
7.80
8.80
6.20
7.20
5.20
5.80
4.20
4.80
3.20
3.80
.2.20
.
2.80
0.50
0.20
0.80
0.80
0.20
0.50
1.20
1.80
1.80
1.20
3.20
2.80
2.20
4.80
4.20
3.80
5.80
5.20
6.20
8.20
8.80
7.80
7.20
Submit Document Feedback
6.80
PCB layout pattern
11.30
11.30
55
9.70
9.30
9.10
9.70
9.30
9.10
7.70
6.70
6.50 6.30
5.70
5.50
5.30
4.70
4.30
3.70
2.00
1.30
0.70
0.00
1.00
2.30
2.90
4.00
5.10
5.10
6.00
6.00
8.10
8.10
8.50
8.50
9.30
9.30
9.70
9.70
FN8670.2
January 14, 2015
PCB LAND PATTERN (FOR REFERENCE)
8.60
6.60
7.00
5.40
4.60
3.80
3.00
2.60
0.80
0.20
1.20
0.00
0.40
1.80
2.00
2.40
3.60
4.40
5.20
6.40
8.60
6.00
11.30
6.50
11.30
ISL8272M
7.70
7.30
6.70
6.30 6.50
5.70
5.50
5.30
4.70
4.30
3.70
3.30
2.70
2.30
2.00
1.70
1.30
0.70
0.30
0.30
0.70
1.30
1.70
2.30
2.90 2.70
3.30
4.00
7.30
6.30
8.70