ISL8273M Datasheet

DATASHEET
80A Single Channel Digital PMBus Step-Down Power
Module
ISL8273M
Features
The ISL8273M is a complete PMBus enabled DC/DC single
channel step-down advance power supply capable of delivering
up to 80A of current and optimized for high power density
applications. For higher output current, up to four ISL8273Ms
can be paralleled to supply up to 320A in a multiphase current
sharing configuration.
• Complete digital power supply
Operating over an input voltage range of 4.5V to 14V, the
ISL8273M offers adjustable output voltages down to 0.6V and
achieves up to 93% conversion efficiencies. A unique
ChargeMode™ control architecture provides a single clock cycle
response to an output load step and can support switching
frequencies up to 1MHz. The power module integrates all power
and most passive components and only requires a few external
components to operate. A set of optional external resistors allows
the user to easily configure the device for standard operation. For
advanced configurations, a standard PMBus interface addresses
such things as sequencing and fault management, as well as
real-time full telemetry and point-of-load monitoring. Additionally,
an on-board nonvolatile memory can store the desired custom
configuration and settings.
A fully customizable voltage, current and temperature
protection scheme insures safe operation for the ISL8273M
under abnormal operating conditions. The device is also
supported by the PowerNavigator™ software, a full digital
power train development environment.
• 80A single channel output current
- 4.5V to 14V single rail input voltage
- Up to 93% efficiency
- Up to 320A/4 parallel modules capable solution
- Multiphase and current sharing operations (180°/22.5°
steps)
• Programmable output voltage
- 0.6V to 2.5V output voltage settings
- ±1% accuracy over line/load/temperature
• ChargeMode™ control loop architecture
- 296kHz to 1.06MHz fixed switching frequency operations
- No compensation required
- Fast single clock cycle transient response
• PMBus interface and/or pin-strap mode
- Fully programmable through PMBus
- Pin-strap mode for standard settings
- Real-time telemetry for VIN, VOUT, IOUT, temperature, duty
cycle and fSW
• Advanced soft-start/stop, sequencing and margining
• On-board nonvolatile memory
The ISL8273M is available in a low profile compact
18mmx23mmx7.5mm fully encapsulated thermally enhanced
HDA package.
• Complete over/undervoltage, current and temperature
protections with fault logging
Applications
• Thermally enhanced 18mmx23mmx7.5mm HDA package
• PowerNavigator™ supported
• Server, telecom, storage and datacom
Related Literature
• Industrial/ATE and networking equipment
• UG036, “ISL8273MEVAL1Z Evaluation Board User Guide”
• General purpose power for ASIC, FPGA, DSP and memory
VIN
VIN
CIN
ENABLE
VSENP
EN
PG
VR5
10µF 10µF
m
23
m
m
VR
ISL8273M
VCC
VDRV1
VR55
SCL
SDA
2x10µF
SALRT
VMON
SGND
6.65k
18m
COUT
VSENN
VR6
VDRV
100k
VOUT
VOUT
VDD
7.5mm
PMBUS
INTERFACE
PGND
NOTE: Figure 1 represents a typical implementation of the ISL8273M. For PMBus
operation, it is recommended to tie the enable pin (EN) to SGND.
FIGURE 1. 80A APPLICATION CIRCUIT
September 10, 2015
FN8704.1
1
FIGURE 2. A SMALL PACKAGE FOR HIGH POWER DENSITY
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015. All Rights Reserved
Intersil (and design), ChargeMode, PowerNavigator and Digital-DC are trademarks owned by Intersil Corporation
or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
ISL8273M
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
ISL8273M Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Application Circuit - Single Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Application Circuit - Three Module Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Efficiency Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Transient Response Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Derating Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMBus Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-Start, Stop Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Undervoltage Lockout (UVLO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMBus Module Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Prebias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital-DC™ Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Active Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitoring Via SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Snapshot Parameter Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nonvolatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
16
16
17
17
17
18
18
19
19
19
20
20
20
21
21
21
22
22
22
Layout Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB Layout Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stencil Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reflow Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
23
23
23
23
23
PMBus Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PMBus™ Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PMBus Commands Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Firmware Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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2
FN8704.1
September 10, 2015
ISL8273M
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
ISL8273MAIRZ
ISL8273M
-40 to +85
58 LD 18x23 HDA Module
ISL8273MEVAL1Z
Single-Module Evaluation Board (see UG036, “ISL8273MEVAL1Z Evaluation Board User Guide”)
PKG.
DWG. #
Y58.18x23
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISL8273M. For more information on MSL, please see tech brief TB363.
Pin Configuration
ISL8273M
(58 LD HDA)
TOP VIEW
1
2
3
4
A
TEST
D
E
9
10 11 12 13 14 15 16 17 18
SA
VMON
CS
PAD2
VOUT
MGN
SCL
SALRT SDA
EN
TEST
PAD6
VSENN VSENP
P
R
T
U
PGND
ASCR V25
SGND
VDD
L
N
PGND
TEST
TEST
K
M
TEST
TEST
SYNC
PG
DDC
PAD7
J
8
VOUT
VSET
SS/UVLO
PGND
PGND
PAD5
H
7
PAD4
PAD3
C
G
6
PAD1
B
F
5
VR SWD1
VCC
VR6 SGND
VR55
PAD8
SGND
PGND
VR5
PGND
PGND VDRV
VDRV1
DCM
VIN
PAD9
PAD10
VIN
PGND
SGND
SWD2
VDRV
VDRV1
DCM
PAD11
PAD12
VIN
PGND
SGND
V
W
PGND
SW1
Y
AA
AB
AC
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3
PGND
SW2
PAD15
PAD13
PAD14
PAD16
FN8704.1
September 10, 2015
ISL8273M
Pin Descriptions
PIN
NUMBER
PIN
NAME
TYPE
PAD1, PAD2
VOUT
PWR
Power supply output voltage. Output voltage from 0.6V to 2.5V. Tie these two pins together to achieve a single
output. For higher output voltage, refer to the derating curves starting on page 15 to set the maximum output
current from these pads.
PAD3, PAD4,
PAD5, PAD7,
PAD10,
PAD12,
PAD13, PAD15
PGND
PWR
Power ground. Refer to the “Layout Guide” on page 22 for the PGND pad connections and I/O capacitor placement.
PAD6
SGND
PWR
Signal ground. Refer to “Layout Guide” on page 22 for the SGND pad connections.
PAD8, PAD9,
PAD11
VIN
PWR
Input power supply voltage to power the module. Input voltage range from 4.5V to 14V.
PAD14
SW1
PWR
PAD16
SW2
Switching node pads. The SW pads are used to dissipate the heat and provide the good thermal performance. Refer
to “Layout Guide” on page 22 for the SW pad connections.
C6
VSET
I
Output voltage selection pin. Used to set VOUT set point and VOUT max.
C7
CS
I
Current sharing configuration pin. Used to program current sharing configurations such as SYNC selection, phase
spreading and VOUT droop.
C8
MGN
I
External VOUT margin control pin. Active high (>2V) sets VOUT margin high; active low (<0.8V) sets VOUT margin low;
high impedance (floating) sets VOUT to normal voltage. Factory default range for margining is nominal VOUT ±5%.
When using PMBus to control margin command, leave this pin as no connection.
C9
VMON
I
Driver voltage monitoring. Use this pin to monitor VDRV through an external 16:1 resistor divider.
C10
SA
I
Serial address selection pin. Used to assign unique address for each individual device or to enable certain
management features.
C11
SALRT
O
Serial alert. Connect to external host if desired. SALRT is asserted low upon a warning or a fault event and
deasserted when warning or fault is cleared. A pull-up resistor is required.
C12
SDA
I/O
Serial data. Connect to external host and/or to other Digital-DC™ devices. A pull-up resistor is required.
C13
SCL
I/O
Serial clock. Connect to external host and/or to other Digital-DC™ devices. A pull-up resistor is required.
D4
SS/
UVLO
I
Soft-start/stop and undervoltage lockout selection pin. Used to set turn on/off delay and ramp time as well as input
UVLO threshold levels.
D5
PG
O
Power-good output. Power-good output can be an open drain that requires a pull-up resistor or push-pull output that
can drive a logic input.
D13
SYNC
I/O
Clock synchronization input. Used to set the frequency of the internal switch clock, to sync to an external clock or to
output internal clock. If external synchronization is used, the external clock must be active before enable.
E14
EN
I
E4
DDC
I/O
C5, D14, E15,
F4, F15, G4
TEST
-
Test pins. Do not connect these pins.
G14
ASCR
I
ChargeMode™ control ASCR parameters selection pin. Used to set ASCR gain and residual values.
G15
V25
PWR
H3
VSENN
I
Differential output voltage sense feedback. Connect to negative output regulation point.
H4
VSENP
I
Differential output voltage sense feedback. Connect to positive output regulation point.
H16, J16, K16,
M14
SGND
PWR
Signal grounds. Using multiple vias to connect the SGND pins to the internal SGND layer.
K14
VDD
PWR
Input supply voltage for controller. Connect VDD pad to VIN supply.
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DESCRIPTION
Enable pin. Logic high to enable the module output.
A Digital-DC bus. This dedicated bus provides the communication between devices for features such as sequencing,
fault spreading and current sharing. The DDC pin on all Digital-DC devices should be connected together. A pull-up
resistor is required.
Internal 2.5V reference used to power internal circuitry. No external capacitor required for this pin. Not
recommended to power external circuit.
4
FN8704.1
September 10, 2015
ISL8273M
Pin Descriptions
(Continued)
PIN
NUMBER
PIN
NAME
TYPE
DESCRIPTION
L2
VR
PWR
Internal LDO bias pin. Tie VR to VR55 directly with a short loop trace. Not recommended to power external circuit.
L3
SWD1
PWR
Switching node driving pins. Directly connect to the SW1 and SW2 pads with short loop wires.
P11
SWD2
L14
VR5
PWR
Internal 5V reference used to power internal circuitry. Place a 10µF decoupling capacitor for this pin. Maximum
external loading current is 5mA.
M1
VCC
PWR
Internal LDO output. Connect VCC to VDRV for internal LDO driving.
M5, M17, N5
PGND
PWR
Power grounds. Using multiple vias to connect the PGND pins to the internal PGND layer.
M10
VR55
PWR
Internal 5.5V bias voltage for internal LDO use only. Tie VR55 pin directly to the VR pin. Not recommended to power
external circuit.
M13
VR6
PWR
Internal 6V reference used to power internal circuitry. Place a 10µF decoupling capacitor for this pin. Not
recommended to power external circuit.
N6, N16
VDRV
PWR
Power supply for internal FET drivers. Connect a 10μF bypass capacitor to each of these pins. These pins can be
driven by the internal LDO through VCC pin or by the external power supply directly. Keep the driving voltage between
4.5V and 5.5V. For 5V input application, use external supply or connect this pin to VIN.
R8, R17
VDRV1
I
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Bias pin of the internal FET drivers. Always tie to VDRV.
5
FN8704.1
September 10, 2015
ISL8273M
VDRV1
VDRV
VCC
VIN
VR
VR55
V25
VR5
VR6
VDD
ISL8273M Internal Block Diagram
LDO
LDOs
0.15µH
VOUT
OV/UV
CURRENT SHARE
INTERLEAVE
OT/UT
OC/UC
POWER
MANAGEMENT
SEQUENCE
FAULT SPREADING
MARGINING
PGND
VDRV1
SS
SNAPSHOT
SWD2
SW2
LOGIC
ASCR
CS
VSET
SS/UVLO
EN
PG
MGN
DDC
VDRV
VIN
FILTER
SYNC
OUT
PWM2
SYNC
PLL
D-PWM
PWM1
ChargeModeTM
CONTROL
SUPERVISOR
VIN
VDRV
NVM
SWD1
SW1
ADC
CSA
VDRV1
ADC
0.15µH
LOGIC
PROTECTION
VOUT
CSA
ADC
PGND
VSA
VDD
ADC
INTERNAL
TEMP SENSOR
SCL
SDA
SALRT
PMBus/I2C
INTERFACE
100 :
SA
VSENP
VSENN
SGND
100 :
FIGURE 3. INTERNAL BLOCK DIAGRAM
PGND
SGND
VMON
DIGITAL CONTROLLER
FIGURE 3. INTERNAL BLOCK DIAGRAM
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September 10, 2015
DDC
DDC
SCL
SCL
SDA
SDA
PG
R10
R11
R12
MGN
R9
VR55
VR
SALRT
470µF
BULK
SWD1
6x47µF
CERAMIC
SW1
VIN
12V
C1
C2
SWD2
C3
VDD
SW2
10µF
ISL8273M
VR5
10µF
10µF
C4
C5
4x470µF
POSCAP
10x100µF
CERAMIC
VR6
VOUT
VOUT
1V 80A
VDRV
VCC
10µF
10µF
VCC
C8
C7
VDRV1
PGND
6.65k:
SGND
VMON
R6
VSENN
C6
VSENP
R5
100k:
FN8704.1
September 10, 2015
NOTES:
3. R2 and R3 are not required if the PMBus host already has I2C pull-up resistors.
4. Only one R4 per DDC bus is required when multiple modules share the same DDC bus.
5. R7 thru R12 can be selected according to the tables for the pin-strap resistor setting in this document.
If the PMBus configuration is chosen to overwrite the pin-strap configuration, R8 thru R12 can be non-populated.
6. V25, VR and VR55 do not need external capacitors. V25 can be no connection.
FIGURE 4. TYPICAL APPLICATION CIRCUIT - SINGLE MODULE
C9
ISL8273M
VIN
R8
CS
R7
R4
SALRT
PG
Note 5
ASCR
R3
10k:
SYNC
R2
10k:
SS/UVLO
7
R1
10k:
VSET
10k:
EN
Note 3 Note 3 Note 4
VAUX OR VCC 3.3V TO 5V
SHOULD BE ACTIVE BEFORE
ENABLE
EN
MGN
PIN STRAP RESISTORS
(OPTIONAL)
SA
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Typical Application Circuit - Single Module
ISL8273M
Typical Application Circuit - Three Module Current Sharing
EN
PG1
PG
R9
R10 R11
CS
SCL
ASCR
DDC
SCL
VSET
DDC
SDA
VIN
12V
R8
R4
SS/UVLO
R3
SA
R2
MGN
R7
R1
EN
SMBus Address= 0x2A
VAUX OR VCC 3.3V TO 5V
SHOULD BE ACTIVE BEFORE ENABLE 4.7k: 4.7k: 4.7k: 4.7k:
51.1k:
MGN
PIN STRAP RESISTORS
(OPTIONAL)
VR55
SDA
VR
SALRT
SALRT
SYNC
SYNC
2x470µF
BULK
4x47μF
CERAMIC
C1
C2
SWD1
SW1
VIN
C3
SWD2
VDD
SW2
10µF
ISL8273M
VR5
10µF 10µF
C4
4x100µF
CERAMIC
VR6
C5
12x100μF
CERAMIC
12x470μF
POSCAP
VOUT
VDRV
VCC
C8
VSENN
MGN
EN
PG2
PG
SGND
VMON
R6
6.65k:
EN
VDRV1
VSENP
C7
MGN
C6
PGND
VCC1 10µF 10µF
R5
100k:
VOUT
1V 240A
C23
C24
PIN STRAP RESISTORS
(OPTIONAL)
SMBus Address = 0x2B
56.2k:
SCL
CS
ASCR
VSET
DDC
SS/UVLO
R15 R16 R17 R18
SA
R14
VR55
SDA
VR
SALRT
4x47µF
CERAMIC
C9
SWD1
SYNC
SW1
VIN
C10
SWD2
VDD
SW2
10µF
ISL8273M
VR5
10µF 10µF
4x100µF
CERAMIC
VR6
C12
C11
VOUT
VDRV
VCC
C15
VSENN
EN
PG3
PG
SGND
VMON
R13
6.65k:
MGN
VDRV1
EN
C14
VSENP
C13
MGN
R12
100k:
PGND
VCC2 10µF 10µF
PIN STRAP RESISTORS
(OPTIONAL)
SMBus Address = 0x2C
61.9k:
SCL
CS
ASCR
VSET
SA
DDC
SS/UVLO
R22 R23 R24 R25
R21
VR55
SDA
VR
SALRT
SWD1
SYNC
4x47µF
CERAMIC
C16
SW1
VIN
C17
SWD2
VDD
SW2
10µF
ISL8273M
VR5
10µF 10µF
C18
4x100µF
CERAMIC
VR6
C19
VOUT
VDRV
VCC
VSENN
VMON
R20
6.65k:
C22
VDRV1
VSENP
C21
PGND
C20
SGND
VCC3 10µF 10µF
R19
100k:
FIGURE 4. TYPICAL APPLICATION CIRCUIT - THREE MODULE CURRENT SHARING
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ISL8273M
TABLE 1. ISL8273M DESIGN GUIDE MATRIX AND OUTPUT VOLTAGE RESPONSE
VIN
(V)
VOUT
(V)
CIN (BULK)
(µF)
(Note 7)
CIN
(CERAMIC)
(µF)
COUT
(BULK)
(µF)
COUT
(CERAMIC)
(µF)
ASCR GAIN
(Note 8)
ASCR
RESIDUAL
(Note 8)
VOUT
DEVIATION
(mV)
RECOVERY
TIME
(µs)
LOAD STEP
(A)
(Note 9)
FREQ.
(kHz)
5
1
1x470
6x47
6x470
12x100
140
90
80
25
0 to 40
300
5
1
1x470
4x47
4x470
8x100
220
90
95
20
0 to 40
571
5
1.5
1x470
6x47
6x470
14x100
110
90
82
35
0 to 40
300
5
1.5
1x470
4x47
4x470
10x100
240
90
85
20
0 to 40
571
12
1
1x470
8x47
6x470
14x100
140
90
80
30
0 to 40
300
12
1
1x470
6x47
4x470
10x100
240
90
82
20
0 to 40
571
12
1.5
1x470
8x47
6x470
12x100
140
90
85
35
0 to 40
364
12
1.5
1x470
6x47
4x470
10x100
220
90
85
30
0 to 40
571
12
2.5
1x470
8x47
4x470
8x100
180
90
105
45
0 to 40
571
12
2.5
1x470
6x47
3x470
6x100
220
90
110
40
0 to 40
800
NOTES:
7. CIN bulk capacitor is optional only for energy buffer from the long input power supply cable.
8. ASCR gain and residual are selected to ensure phase margin higher than 60° and gain margin higher than 6dB at ambient room temperature and
full load (80A).
9. Output voltage response is tested with load step slew rate higher than 100A/µs.
TABLE 2. RECOMMENDED INPUT/OUTPUT CAPACITOR
VENDORS
VALUE
PART NUMBER
MURATA, Input Ceramic
47µF, 16V, 1210
GRM32ER61C476ME15L
MURATA, Input Ceramic
22µF, 16V, 1210
GRM32ER61E226KE15L
TAIYO YUDEN, Input Ceramic
47µF, 16V, 1210
EMK325BJ476MM-T
TAIYO YUDEN, Input Ceramic
22µF, 25V, 1210
TMK325BJ226MM-T
MURATA, Output Ceramic
100µF, 6.3V, 1210
GRM32ER60J107M
TDK, Output Ceramic
100µF, 6.3V, 1210
C3225X5R0J107M
AVX, Output Ceramic
100µF, 6.3V, 1210
12106D107MAT2A
SANYO POSCAP, Output Bulk
470µF, 4V
4TPE470MCL
SANYO POSCAP, Output Bulk
470µF, 6.3V
6TPF470MAH
PANASONIC, Input Bulk
150µF, 16V
16TQC150MYF
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ISL8273M
Absolute Maximum Ratings
Thermal Information
Input Supply Voltage, VIN Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 17V
Input Supply Voltage for Controller, VDD Pin . . . . . . . . . . . . . . -0.3V to 17V
MOSFET Switch Node Voltage, SW1/2, SWD1/2 . . . . . . . . . . . -0.3V to 17V
MOSFET Driver Supply Voltage, VDRV, VDRV1 Pin . . . . . . . . . -0.3V to 6.0V
Output Voltage, VOUT pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 6.0V
Internal Reference Supply Voltage, VR6 Pin . . . . . . . . . . . . . . -0.3V to 6.6V
Internal Reference Supply Voltage, VR, VR5, VR55 Pin. . . . . -0.3V to 6.5V
Internal Reference Supply Voltage, V25 Pin . . . . . . . . . . . . . . . . -0.3V to 3V
Logic I/O Voltage for DDC, EN, MGN, PG, ASCR, CS
SA, SCL, SDA, SALRT, SYNC, SS/UVLO, VMON, VSET . . . . . -0.3V to 6.0V
Analog Input Voltages
VSENP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
VSENN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . . 750V
Latch-up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
58 LD HDA Package (Notes 10, 11). . . . . .
5.3
1.1
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see Figure 27
Recommended Operating Conditions
Input Supply Voltage Range, VIN . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 14V
Input Supply Voltage Range for Controller, VDD . . . . . . . . . . . 4.5V to 14V
Output Voltage Range, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6V to 2.5V
Output Current Range, IOUT(DC) (Note 14). . . . . . . . . . . . . . . . . . . 0A to 80A
Operating Junction Temperature Range, TJ. . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
10. JA is measured in free air with the module mounted on an 8-layer evaluation board 4.7x4.8inch in size with 2oz Cu on all layers and multiple via
interconnects as specified in the ISL8273MEVAL1Z evaluation board user guide.
11. For JC, the “case temp” location is the center of the package underside.
Electrical Specifications
VIN = VDD= 12V, fSW = 533kHz, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 12)
TYP
MAX
(Note 12)
UNIT
40
50
mA
6.1
6.6
V
INPUT AND SUPPLY CHARACTERISTICS
IDD
Input Supply Current for Controller
VR6
6V Internal Reference Supply Voltage
VR5
5V Internal Reference Supply
V25
2.5V Internal Reference Supply
Vcc
Internal LDO Output Voltage
IVCC
Internal LDO Output Current
VDD_READ_RES
Input Supply Voltage for Controller
Read Back Resolution
VDD_READ_ERR
Input Supply Voltage for Controller
Read Back Total Error (Note 15)
VIN = VDD = 12V, VOUT = 0V, module not
enabled
5.5
IVR5 <5mA
4.5
5.2
5.5
V
2.25
2.5
2.75
V
5.3
VIN = VDD = 12V, VCC connected to
VDRV, module enabled
V
50
PMBus Read
mA
±20
mV
±2
% FS
OUTPUT CHARACTERISTICS
Output Voltage Adjustment Range
VIN > VOUT + 1.8V
VOUT_RES
Output Voltage Set-point Range
Configured using PMBus
VOUT_ACCY
Output Voltage Set-point Accuracy
(Notes 13, 15)
Includes line, load and temperature
(-20°C ≤ TA ≤ +85°C)
VOUT_RANGE
VOUT_READ_RES
Output Voltage Read Back Resolution
VOUT_READ_ERR
Output Voltage Read Back Total Error
(Note 15)
PMBus read
Output Ripple Voltage
VOUT = 1V, COUT = 6 x 470µF
POSCAP + 12 x 100µF CERAMIC
VOUT_RIPPLE
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10
0.54
2.75
±0.025
-1
%
+1
±0.15
-2
% FS
% FS
+2
8
V
% FS
mV
FN8704.1
September 10, 2015
ISL8273M
Electrical Specifications
VIN = VDD= 12V, fSW = 533kHz, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
IOUT_READ_RES
Output Current Read Back Resolution
IOUT_RANGE
IOUT_READ_ERR
TEST CONDITIONS
MIN
(Note 12)
TYP
0.087
Output Current Range (Note 14)
Output Current Read Back Total Error
MAX
(Note 12)
A
80
PMBus read at max load. VOUT = 1V
UNIT
±3
A
A
SOFT-START AND SEQUENCING
tON_DELAY
tON_DELAY_ACCY
Delay Time from Enable to VOUT Rise
Configured using PMBus
tON_DELAY Accuracy
Output Voltage Ramp-up Time
Configured using PMBus. Single module
standalone
tON_RISE_ACCY
Output Voltage Ramp-up Time
Accuracy
Single module standalone
Delay Time from Disable to VOUT Fall
Configured using PMBus
tOFF_DELAY_ACCY
tOFF_FALL
5000
±2
tON_RISE
tOFF_DELAY
2
0.5
ms
100
±250
2
tOFF_DELAY Accuracy
ms
µs
5000
±2
ms
ms
Output Voltage Fall Time
Configured using PMBus. Single module
standalone
Output Voltage Fall Time Accuracy
Single module standalone
Power-good Delay
Configured using PMBus
0
5000
ms
TSENSE_RANGE
Temperature Sense Range
Configurable via PMBus
-50
150
C
INT_TEMPACCY
Internal Temperature Sensor Accuracy
Tested at +100°C
-5
+5
C
VDD Undervoltage Threshold Range
Measured internally
4.18
16
V
tON_FALL_ACCY
0.5
ms
100
±250
ms
µs
POWER-GOOD
VPG_DELAY
TEMPERATURE SENSE
FAULT PROTECTION
VDD_UVLO_RANGE
VDD_UVLO_ACCY
VDD Undervoltage Threshold Accuracy
(Note 15)
±2
%FS
VDD_UVLO_DELAY
VDD Undervoltage Response Time
10
µs
VOUT_OV_RANGE
VOUT Overvoltage Threshold Range
1.15VOUT
V
Factory default
Configured using PMBus
VOUT_UV_RANGE
VOUT Undervoltage Threshold Range
Factory default
Configured using PMBus
VOUT_OV/UV_ACCY
VOUT OV/UV Threshold Accuracy
(Note 13)
VOUT_OV/UV_DELAY
VOUT OV/UV Response Time
ILIMIT_ACCY
ILIMIT_DELAY
TJUNCTION
TJUNCTION_HYS
Output Current Limit Set-point
Accuracy (Note 15)
Output Current Fault Response Time
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11
VOUT_MAX
0.85VOUT
V
V
0
0.95VOUT
V
-2
+2
%
Tested at IOUT_OC_FAULT_LIMIT = 80A
Factory default
Over-temperature Protection Threshold Factory default
(Controller Junction Temperature)
Configured using PMBus
Thermal Protection Hysteresis
1.05VOUT
10
µs
±10
% FS
3
tSW
(Note 16)
125
C
-40
125
15
C
C
FN8704.1
September 10, 2015
ISL8273M
Electrical Specifications
VIN = VDD= 12V, fSW = 533kHz, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MAX
(Note 12)
UNIT
296
1067
kHz
-5
+5
%
MIN
(Note 12)
TYP
OSCILLATOR AND SWITCHING CHARACTERISTICS
fSW_RANGE
fSW_ACCY
EXT_SYNCPW
EXT_SYNCDRIFT
Switching Frequency Range
Switching Frequency Set-point
Accuracy
Minimum Pulse Width Required from
External SYNC Clock
Measured at 50% Amplitude
Drift Tolerance for External SYNC Clock External SYNC Clock equal to 500kHz
is not supported
150
ns
-10
+10
%
-100
+100
nA
0.8
V
LOGIC INPUT/OUTPUT CHARACTERISTICS
ILOGIC_BIAS
Bias Current at the Logic Input Pins
VLOGIC_IN_LOW
Logic Input Low Threshold Voltage
VLOGIC_IN_HIGH
Logic Input High Threshold Voltage
VLOGIC_OUT_LOW
Logic Output Low Threshold Voltage
2mA sinking
VLOGIC_OUT_HIGH
Logic Output High Threshold Voltage
2mA sourcing
DDC, EN, MGN, PG, SA, SCL, SDA,
SALRT, SYNC, UVLO, VMON, VSET
2.0
V
0.5
2.25
V
V
PMBus INTERFACE TIMING CHARACTERISTIC
fSMB
PMBus Operating Frequency
100
400
kHz
NOTES:
12. Compliance to datasheet limits is assured by one or more methods: Production test, characterization and/or design. Controller is independently
tested before module assembly.
13. VOUT measured at the termination of the VSENP and VSENN sense points.
14. The MAX load current is determined by the thermal “Derating Curves” on page 15,
15. “FS” stands for full scale of recommended maximum operation range.
16. “tSW” stands for time period of operation switching frequency.
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ISL8273M
Typical Performance Curves
Efficiency Performance
are used unless otherwise noted.
Operating condition: TA = +25°C, no air flow. COUT = 6 x 470µF POSCAP + 12 x 100µF CERAMIC. Typical values
100
93
1.2V
92
95
1.5V
1.8V
90
85
1V
0.8V
1.2V
1.5V
90
EFFICIENCY (%)
EFFICIENCY (%)
91
1.8V
80
89
88
87
86
75
85
70
0
10
20
30
40
50
LOAD CURRENT (A)
60
70
80
FIGURE 5. EFFICIENCY vs OUTPUT CURRENT AT VIN = 5V,
fSW = 300kHz FOR VARIOUS OUTPUT VOLTAGES
100
94
95
92
EFFICIENCY (%)
85
2.5V
1.8V
1.5V
1.2V
530kHz
1V
300kHz 346kHz 346kHz
300kHz
80
75
0.8V
300kHz
0
10
20
30
40
50
60
70
350
400
90
90
85
2.5V
1.8V
1.5V
1.2V
346kHz 530kHz
300kHz 346kHz
0.8V
300kHz
10
20
30
40
50
60
70
80
FIGURE 9. EFFICIENCY vs OUTPUT CURRENT AT VIN = 12V, FOR
VARIOUS OUTPUT VOLTAGES
13
2.5V
0.8V
350
1V
400
1.2V
450
500
550
600
650
700
1.5V
2.5V
1.8V
88
86
84
82
LOAD CURRENT (A)
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EFFICIENCY (%)
EFFICIENCY (%)
92
0
1.8V
FIGURE 8. EFFICIENCY vs SWITCHING FREQUENCY AT VIN = 9V,
IOUT = 70A FOR VARIOUS OUTPUT VOLTAGES
95
65
700
FREQUENCY (kHz)
94
70
650
86
100
75
600
88
82
300
80
FIGURE 7. EFFICIENCY vs OUTPUT CURRENT AT VIN = 9V, FOR
VARIOUS OUTPUT VOLTAGES
1V
300kHz
450
500
550
FREQUENCY (kHz)
1.5V
LOAD CURRENT (A)
80
1V
90
84
70
65
0.8V
FIGURE 6. EFFICIENCY vs SWITCHING FREQUENCY AT VIN = 5V,
IOUT = 70A FOR VARIOUS OUTPUT VOLTAGES
90
EFFICIENCY (%)
84
300
80
300
0.8V
350
1V
400
1.2V
450
500
550
600
650
700
FREQUENCY (kHz)
FIGURE 10. EFFICIENCY vs SWITCHING FREQUENCY AT VIN = 12V,
IOUT = 70A FOR VARIOUS OUTPUT VOLTAGES
FN8704.1
September 10, 2015
ISL8273M
Typical Performance Curves
Transient Response Performance
values are used unless otherwise noted.
(Continued)
Operating conditions: IOUT = 0A/40A, IOUT slew rate > 100A/µs, TA = +25°C, 0LFM. Typical
ASCR GAIN = 220
RESIDUAL = 90
ASCR GAIN = 240
RESIDUAL = 90
VOUT (50mV/DIV)
VOUT (100mV/DIV)
IOUT (20A/DIV)
IOUT (20A/DIV)
50µs/DIV
50µs/DIV
FIGURE 11. 5VIN TO 1VOUT TRANSIENT RESPONSE, fSW = 571kHz,
COUT = 8x100µF CERAMIC + 4x470µF POSCAP
FIGURE 12. 5VIN TO 1.5VOUT TRANSIENT RESPONSE, fSW = 571kHz,
COUT = 10x100µF CERAMIC + 4x470µF POSCAP
ADCR GAIN = 140
RESIDUAL = 90
ADCR GAIN = 240
RESIDUAL = 90
VOUT (50mV/DIV)
VOUT (50mV/DIV)
IOUT (20A/DIV)
IOUT (20A/DIV)
50µs/DIV
50µs/DIV
FIGURE 13. 12VIN TO 1VOUT TRANSIENT RESPONSE, fSW = 300kHz,
COUT = 14x100µF CERAMIC + 6x470µF POSCAP
FIGURE 14. 12VIN TO 1VOUT TRANSIENT RESPONSE, fSW = 571kHz,
COUT = 10x100µF CERAMIC + 4x470µF POSCAP
ADCR GAIN = 220
RESIDUAL = 90
ADCR GAIN = 220
RESIDUAL = 90
VOUT (100mV/DIV)
VOUT (100mV/DIV)
IOUT (20A/DIV)
IOUT (20A/DIV)
50µs/DIV
FIGURE 15. 12VIN TO 1.5VOUT TRANSIENT RESPONSE,
fSW = 571kHz, COUT = 10x100µF CERAMIC + 4x470µF
POSCAP
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50µs/DIV
FIGURE 16. 12VIN TO 2.5VOUT TRANSIENT RESPONSE,
fSW = 800kHz, COUT = 6x100µF CERAMIC + 3x470µF
POSCAP
FN8704.1
September 10, 2015
ISL8273M
Typical Performance Curves
Derating Curves
(Continued)
All of the following curves were plotted at TJ = +120°C.
90
90
80
400LFM
70
LOAD CURRENT (A)
LOAD CURRENT (A)
80
0LFM
60
50
200LFM
40
30
20
10
0
25
50
30
20
10
35
45
55
65
75
85
95 105
AMBIENT TEMPERATURE (°C)
115
0
25
125
80
80
400LFM
LOAD CURRENT (A)
LOAD CURRENT (A)
90
70
0LFM
60
50
35
45
55
65
75
85
95 105
AMBIENT TEMPERATURE (°C)
115
125
115
125
115
125
FIGURE 18. 12VIN TO 1VOUT, fSW = 300kHz
200LFM
40
30
20
10
70
400LFM
0LFM
60
50
200LFM
40
30
20
10
35
45
55
65
75
85
95 105
AMBIENT TEMPERATURE (°C)
115
0
25
125
FIGURE 19. 5VIN TO 1.5VOUT, fSW = 300kHz
90
90
80
80
70
400LFM
60
0LFM
50
200LFM
40
35
45
55
65
75
85
95 105
AMBIENT TEMPERATURE (°C)
FIGURE 20. 12VIN TO 1.5VOUT, fSW = 364kHz
LOAD CURRENT (A)
LOAD CURRENT (A)
200LFM
40
90
30
20
10
0
25
0LFM
60
FIGURE 17. 5VIN TO 1VOUT, fSW = 300kHz
0
25
400LFM
70
70
400LFM
60
0LFM
50
200LFM
40
30
20
10
35
45
55
65
75
85
95
105
AMBIENT TEMPERATURE (°C)
FIGURE 21. 5VIN TO 2.5VOUT, fSW = 364kHz
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115
125
0
25
35
45
55
65
75
85
95
105
AMBIENT TEMPERATURE (°C)
FIGURE 22. 12VIN TO 2.5VOUT, fSW = 533kHz
FN8704.1
September 10, 2015
ISL8273M
Functional Description
TABLE 3. OUTPUT VOLTAGE RESISTOR SETTINGS (Continued)
SMBus Communications
The ISL8273M provides a PMBus digital interface that enables
the user to configure all aspects of the module operation as well
as monitor the input and output parameters. The ISL8273M can
be used with any SMBus host device. In addition, the module is
compatible with PMBus™ Power System Management Protocol
Specification Parts I and II version 1.2. The ISL8273M accepts
most standard PMBus commands. When configuring the device
using PMBus commands, it is recommended that the enable pin
is tied to SGND.
The SMBus device address is the only parameter that must be
set by the external pins. All other device parameters can be set
using PMBus commands.
The ISL8273M can operate without the PMBus in pin-strap mode
with configurations programmed by pin-strap resistors, such as
output voltage, switching frequency, device SMBus address, input
UVLO, soft-start/stop and current sharing.
Output Voltage Selection
The output voltage may be set to a voltage between 0.6V and
2.5V provided that the input voltage is higher than the desired
output voltage by an amount sufficient to maintain regulation.
The VSET pin is used to set the output voltage to levels as shown
in Table 3. The RSET resistor is placed between the VSET pin and
SGND. A standard 1% resistor is required.
TABLE 3. OUTPUT VOLTAGE RESISTOR SETTINGS
VOUT
(V)
RSET
(kΩ)
0.60
10
0.65
11
0.70
12.1
0.75
13.3
0.80
14.7
0.85
16.2
0.90
17.8
0.95
19.6
1.00
21.5, or Connect to SGND
1.05
23.7
1.10
26.1
1.15
28.7
1.20
31.6, or OPEN
1.25
34.8
1.30
38.3
1.40
42.2
1.50
46.4
1.60
51.1
1.70
56.2
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VOUT
(V)
RSET
(kΩ)
1.80
61.9
1.90
68.1
2.00
75
2.10
82.5
2.20
90.9
2.30
100
2.50
110, or Connect to V25
The output voltage may also be set to any value between 0.6V and
2.5V using the PMBus command VOUT_COMMAND. This device
supports dynamic voltage scaling, by allowing change to the output
voltage set point during regulation. The voltage transition rate is
specified by the PMBus command VOUT_TRANSITION_RATE.
By Default, VOUT_MAX is set to 110% of VOUT set by the pin-strap
resistor, which can be changed to any value up to 2.75V by the
PMBus Command VOUT_MAX.
Soft-Start, Stop Delay and Ramp Times
The ISL8273M follows an internal start-up procedure after power
is applied to the VDD pin. The module requires approximately
60ms to 70ms to check for specific values stored in its internal
memory and programmed by pin-strap resistors. Once this
process is completed, the device is ready to accept commands
via the PMBus interface and the module is ready to be enabled. If
the module is to be synchronized to an external clock source, the
clock frequency must be stable prior to asserting the EN pin.
It may be necessary to set a delay from when an enable signal is
received until the output voltage starts to ramp to its target
value. In addition, the designer may wish to precisely set the time
required for VOUT to ramp to its target value after the delay
period has expired. These features may be used as part of an
overall inrush current management strategy or to precisely
control how fast a load IC is turned on. The ISL8273M gives the
system designer several options for precisely and independently
controlling both the delay and ramp time periods. The soft-start
delay period begins when the EN pin is asserted and ends when
the delay time expires.
The soft-start delay and ramp-up time can be programmed to
custom values using the PMBus commands TON_DELAY and
TON_RISE. When the delay time is set to 0ms, the device begins
its ramp-up after the internal circuitry has initialized
(approximately 2ms). When the soft-start ramp period is set to
0ms, the output ramps up as quickly as the output load
capacitance and loop settings allow. It is generally
recommended to set the soft-start ramp to a value greater than
1ms to prevent inadvertent fault conditions due to excessive
inrush current.
Similar to the soft-start delay and ramp-up time, the delay and
ramp down time for soft-stop/off can be programmed using the
PMBus commands TOFF_DELAY and TOFF_FALL. In addition, the
module can be configured as “immediate off” using the
FN8704.1
September 10, 2015
ISL8273M
command ON_OFF_CONFIG, such that the internal MOSFETs are
turned off immediately after the delay time expires.
A PG delay can be programmed using the PMBus command
POWER_GOOD_DELAY.
In the current sharing mode where multiple ISL8273M modules
are connected in parallel, ASCR is required to be disabled for the
ramp-up with the USER_CONFIG command. Therefore, the
soft-start rise time is not equal to TON_RISE. It can be calculated
approximately by Equation 1.
Switching Frequency and PLL
TON_RISE
Rise Time (ms)  -------------------------------  330kHz  12V
V IN  f SW
(EQ. 1)
Also in the current sharing mode, ASCR will be enabled
automatically upon power-good assertion after the ramp
completes. To avoid premature ASCR turn on, it is recommended
to increase POWER_GOOD_DELAY if the rise time exceeds 10ms.
In addition, only “immediate off” is supported for current sharing.
In the current sharing mode, if module self enable is used (VIN
power-up), a minimum TON_DELAY of 15ms is recommended.
The device’s switching frequency is set from 296kHz to 1067kHz
using the pin-strap method (for stand-alone noncurrent sharing
module only) as shown in Table 5, or by using the PMBus
command FREQUENCY_SWITCH. The ISL8273M incorporates an
internal Phase-locked Loop (PLL) to clock the internal circuitry.
The PLL can be driven by an external clock source connected to
the SYNC pin. It is recommended that when using an external
clock, same frequency should be set in the FREQUENCY_SWITCH
command. In case the external clock is lost, the module will
automatically switch to the internal clock. When using the
internal oscillator, the SYNC pin can be configured as a clock
source and as external sync to other modules. Refer to
SYNC_CONFIG command on page 46 for more information.
TABLE 5. SWITCHING FREQUENCY RESISTOR SETTINGS
The SS/UVLO pin can be used to program the soft-start/stop
delay time and ramp time to some typical values as shown in
Table 4.
TABLE 4. SOFT-START/STOP RESISTOR SETTINGS
fSW
(kHz)
RSET
(kΩ)
296
14.7, or Connect to SGND
320
16.2
DELAY TIME
(ms)
RAMP TIME
(ms)
RSET
(kΩ)
364
17.8
400
19.6
5
2
19.6, or Connect to
SGND
421
21.5, or OPEN
471
23.7
10
2
21.5
533
26.1
5
5
23.7, or OPEN
571
28.7
615
31.6, or Connect to V25
727
34.8
10
5
26.1
20
5
28.7
5
10
31.6
10
10
34.8, or Connect to V25
20
10
38.3
5
2
42.2
10
2
46.4
Loop Compensation
5
5
51.1
10
5
56.2
20
5
61.9
5
10
68.1
The module loop response is programmable via the PMBus
command ASCR_CONFIG or by using the pin-strap method (ASCR
pin) according to Table 6. The ISL8273M uses the ChargeMode™
control algorithm that responds to the output current changes
within a single PWM switching cycle, achieving a smaller total
output voltage variation with less output capacitance than
traditional PWM controllers.
10
10
75
20
10
82.5
Power-Good
The ISL8273M provides a Power-good (PG) signal that indicates
the output voltage is within a specified tolerance of its target
level and no fault condition exists. By default, the PG pin asserts
if the output is within 10% of the target voltage. This limit may be
changed using the PMBus command POWER_GOOD_ON.
A PG delay period is defined as the time from when all conditions
within the ISL8273M for asserting PG are met to when the PG pin
is actually asserted. This feature is commonly used instead of
using an external reset controller to control external digital logic.
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800
38.3
842
42.2
889
46.4
1067
51.1
TABLE 6. ASCR RESISTOR SETTINGS
ASCR GAIN
ASCR RESIDUAL
RSET
(kΩ)
80
90
10
120
90
11, or Connect to SGND
160
90
12.1
200
90
13.3, or OPEN
240
90
14.7
280
90
16.2
FN8704.1
September 10, 2015
ISL8273M
TABLE 6. ASCR RESISTOR SETTINGS (Continued)
TABLE 7. UVLO RESISTOR SETTINGS
ASCR GAIN
ASCR RESIDUAL
RSET
(kΩ)
UVLO
(V)
RSET
(kΩ)
320
90
17.8
4.5
OPEN
360
90
19.6
4.5
Connect to V25
Connect to SGND
400
90
21.5
4.5
450
90
23.7
4.5
500
90
26.1
19.6, 21.5, 23.7, 26.1, 28.7, 31.6,
34.8, 38.3
10.8
550
90
28.7
42.2, 46.4, 51.1, 56.2, 61.9, 68.1,
75, 82.5
600
90
31.6
700
90
34.8
800
90
38.3
80
100
42.2
120
100
46.4
160
100
51.1
200
100
56.2
SMBus Module Address Selection
Each module must have its own unique serial address to
distinguish between other devices on the bus. The module
address is set by connecting a resistor between pins SA and
SGND. Table 8 lists the available module addresses.
TABLE 8. SMBus ADDRESS RESISTOR SELECTION
RSA
(kΩ)
SMBus
ADDRESS
240
100
61.9
10
19h
280
100
68.1
11
1Ah
320
100
75
12.1
1Bh
360
100
82.5
13.3
1Ch
1Dh
400
100
90.9
14.7
450
100
100
16.2
1Eh
17.8
1Fh
19.6
20h
500
100
110, or Connect to V25
550
100
121
600
100
133
700
100
800
100
21.5
21h
23.7
22h
147
26.1
23h
162
28.7
24h
31.6
25h
34.8, or connect to SGND
26h
38.3
27h
Input Undervoltage Lockout (UVLO)
The input Undervoltage Lockout (UVLO) prevents the ISL8273M
from operating when the input falls below a preset threshold,
indicating the input supply is out of its specified range. The UVLO
threshold (VUVLO) can be set between 4.18V and 16V by using the
PMBus command VIN_UV_FAULT_LIMIT. Using the pin-strap
method (SS/UVLO pin) as shown in Table 7 allows to set the
VUVLO to two typical values.
A fault response to an input undervoltage fault can be programmed
by the PMBus command VIN_UV_FAULT_RESPONSE. If the input
undervoltage fault retry is enabled, the module will shut down
immediately once the input voltage falls below VUVLO and then
continuously checks the input voltage after a retry delay time, which
can be configured from 35ms to 280ms. If the input voltage rises
above the input undervoltage warning level, the module will restart.
The input undervoltage warning is 1.05*VUVLO by default and can
be programmed by the PMBus command VIN_UV_WARN_LIMIT.
Note that fault retry is not supported in current sharing
configuration.
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42.2, or Open
28h
46.4
29h
51.1
2Ah
56.2
2Bh
61.9
2Ch
68.1
2Dh
75
2Eh
82.5
2Fh
90.9
30h
100
31h
110
32h
121
33h
133
34h
147
35h
162
36h
178
37h
FN8704.1
September 10, 2015
ISL8273M
Output Overvoltage Protection
The ISL8273M offers an internal output overvoltage protection
circuit that can be used to protect sensitive load circuitry from
being subjected to a voltage higher than its prescribed limits. A
hardware comparator is used to compare the actual output
voltage (seen at pins VSENP, VSENN) to a threshold set to 15%
higher than the target output voltage (default setting). Fault
threshold can be programmed to a desired level by PMBus
command VOUT_OV_FAULT_LIMIT. If the VSENP - VSENN voltage
exceeds this threshold, the module will initiate an immediate
shutdown without retry. Continuous retry can be enabled using
the PMBus command VOUT_OV_FAULT_RESPONSE. The retry
delay time can be configured from 35ms to 280ms. Note that
fault retry is not supported in current sharing configuration.
Internal to module, two 100Ω resistors are populated from VOUT
to VSENP and SGND to VSENN to protect the module from
overvoltage conditions in case of open at the voltage sensing
pins and differential remote sense traces due to assembly error.
As long as differential remote sense traces have low resistance,
VOUT regulation accuracy is not compromised.
Output Prebias Protection
VOUT
DESIRED OUTPUT
VOLTAGE
PREBIAS
VOLTAGE
TIME
TONDELAY
TONRISE
VPREBIAS < VTARGET
VOUT
PREBIAS
VOLTAGE
DESIRED OUTPUT
VOLTAGE
TIME
TONDELAY
TONRISE
VPREBIAS > VTARGET
An output prebias condition exists when an externally applied
voltage is present on a power supply’s output before the power
supply’s control IC is enabled. Certain applications require that
the converter not be allowed to sink current during start-up if a
prebias condition exists at the output. The ISL8273M provides
prebias protection by sampling the output voltage prior to
initiating an output ramp.
If a prebias voltage is higher than the target voltage after the
preconfigured delay period has expired, the target voltage is set
to match the existing prebias voltage. Thus, both drivers are
enabled with a PWM duty cycle that would ideally create the
prebias voltage.
If a prebias voltage lower than the target voltage exists after the
preconfigured delay period has expired, the target voltage is set
to match the existing prebias voltage and both drivers are
enabled. The output voltage is then ramped to the final
regulation value at the preconfigured ramp rate.
Once the preconfigured soft-start ramp period has expired, the
PG pin is asserted (assuming the prebias voltage is not higher
than the overvoltage limit). The PWM then adjusts its duty cycle
to match the original target voltage and the output ramps down
to the preconfigured output voltage.
The actual time the output takes to ramp from the prebias
voltage to the target voltage varies, depending on the prebias
voltage. However, the total time elapsed from when the delay
period expires to when the output reaches its target value will
match the preconfigured ramp time (see Figure 23).
If a prebias voltage is higher than the overvoltage limit, the
device does not initiate a turn-on sequence and declares an
overvoltage fault condition. The device then responds based on
the output overvoltage fault response setting programmed by the
PMBus command VOUT_OV_FAULT_RESPONSE.
FIGURE 23. OUTPUT RESPONSES TO PREBIAS VOLTAGES
Output Overcurrent Protection
The ISL8273M is protected from damage if the output is shorted
to ground or if an overload condition is imposed on the output.
Average output overcurrent fault threshold can be programmed
by the PMBus command IOUT_OC_FAULT_LIMIT. The module
automatically programs the peak inductor current fault
threshold, by calculating inductor ripple current based on input
voltage, switching frequency and VOUT_COMMAND. When the
peak inductor current crosses the peak inductor current fault
threshold for three successive switching cycles, the module will
initiate an immediate shutdown.
The default response from an overcurrent fault is an immediate
shutdown without retry. A continuous retry can be enabled using
the PMBus command MFR_IOUT_OC_FAULT_RESPONSE. Note
that fault retry is not supported in current sharing configuration.
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September 10, 2015
ISL8273M
Thermal Overload Protection
Figure 24 illustrates a typical connection for two modules.
The ISL8273M includes a thermal sensor that continuously
measures the internal temperature of the module and shuts
down the controller when the temperature exceeds the preset
limit. The factory default temperature limit is set to +125°C, that
can be changed using the PMBus command OT_FAULT_LIMIT.
The default response from an over-temperature fault is an
immediate shutdown without retry. Retry settings can be
programmed using the PMBus command OT_FAULT_RESPONSE.
Hysteresis is implemented with the over-temperature fault retry.
If a retry is enabled, the module will shut down immediately upon
an over-temperature fault event and then continuously checks
the temperature after a retry delay time, which can be configured
from 35ms to 280ms. If the temperature falls below the
over-temperature warning level, the module will restart. The
over-temperature warning is +105°C by default and
programmable using the PMBus command OT_WARN_LIMIT.
Note that fault retry is not supported in current sharing
configuration.
Digital-DC™ Bus
The Digital-DC™ Communications (DDC) bus is used to
communicate between Intersil’s digital power modules and
digital controllers. The DDC bus provides the communication
channel between devices for features such as current sharing,
sequencing and fault spreading. The DDC pin on all Digital-DC™
devices in an application should be connected together. A pull-up
resistor is required on the DDC bus in order to guarantee the rise
time as shown in Equation 2:
Rise Time = R PU C LOAD  1s
(EQ. 2)
Where RPU is the DDC bus pull-up resistance and CLOAD is the
bus loading. The pull-up resistor may be tied to an external 3.3V
or 5V supply as long as this voltage is present prior to or during
the device power-up. In principle, each device connected to the
DDC bus represents approximately 10pF of capacitive loading,
and each inch of FR4 PCB trace introduces approximately 2pF.
The ideal design uses a central pull-up resistor that is
well-matched to the total load capacitance.
Active Current Sharing
Paralleling multiple ISL8273M modules can be used to increase
the output current capability of a single power rail. By connecting
the DDC and SYNC pins of each module together and configuring
the modules as a current sharing rail, the units will share the
current equally within a few percent.
VIN
3.3V TO 5V
CIN
DDC ISL8273M
COUT
SYNC
CIN
DDC ISL8273M
VOUT
COUT
SYNC
FIGURE 24. CURRENT SHARING GROUP
The ISL8273M uses a DDC bus based digital current sharing
technique to balance the steady-state module output current by
aligning the load lines of member modules to a reference
module.
When multiple ISL8273M modules are connected for current
sharing, a non-zero active droop resistance must be set to add
artificial resistance in the output voltage path to control the slope
of the load line curve, calibrating out the physical parasitic
mismatches due to the power train components and PCB layout.
The active droop resistance can be programmed using the
PMBus command VOUT_DROOP based on Equation 3. Typically,
a higher droop value offers a more accurate dynamic current
sharing at the expense of the output load regulation. 1% droop at
full load will be a good trade-off between output load regulation
and dynamic current sharing.
V OUT
V OUT
---------------------------------  0.005  Droop  ---------------------------------  0.01 5
I LOAD  MAX 
I LOAD  MAX 
(EQ. 3)
Upon system start-up, the module with the lowest device position
as selected in the DDC_CONFIG is defined as the reference
module. The remaining modules are members. The reference
module broadcasts its current over the DDC bus. The members
use the reference current information to trim their voltages
(VMEMBER) to balance the current loading of each module in the
system.
VREFERENCE
VOUT
-R
VMEMBER
-R
I MEMBER
I OUT
I REFERENCE
FIGURE 25. ACTIVE CURRENT SHARING
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September 10, 2015
ISL8273M
Figure 25 shows that for load lines with identical slopes, the
member voltage is increased towards the reference voltage,
which closes the gap between the inductor currents.
The relation between reference and member currents and
voltage is given by Equation 4:
V MEMBER = V OUT + R   I REFERENCE – I MEMBER 
(EQ. 4)
Where R is the value of the droop resistance.
The DDC_CONFIG command is used to configure the module for
active current sharing. The default setting is a stand-alone
noncurrent sharing module.
For the fault configuration, it is required to enable the fault
spreading mode in the current sharing rail with the PMBus
command DDC_GROUP. Broadcast operation must be enabled
using the DDC_GROUP command to allow start-up/shutdown
and margining operations. It is optional to enable the VOUT
broadcast in the DDC_GROUP command to allow VOUT set point
to change dynamically during operation.
In multiple-module current sharing configuration, it is required to
synchronize all modules to the same switching clock by tying the
SYNC pins together. The clock source can be selected either from
one module or from an external clock using the SYNC_CONFIG
command. The phase offset of current sharing modules is
automatically set according to the device positions and number
of devices specified in the DDC_CONFIG command.
The pin-strap method is offered for the current sharing
configuration with the CS pin. Table 9 lists the current sharing
pin-strap settings.
TABLE 9. CURRENT SHARING RESISTOR SETTINGS
TABLE 9. CURRENT SHARING RESISTOR SETTINGS (Continued)
DEVICE POSITION
- NUMBER OF
DEVICES
DROOP
(mV/A)
RSET
(kΩ)
External
2-3
0.09
51.1
External
3-3
0.09
56.2
Output internal
1-3
0.11
61.9
External
2-3
0.11
68.1
External
3-3
0.11
75
Output internal
1-3
0.14
82.5
External
2-3
0.14
90.9
External
3-3
0.14
100
Internal only
1-1
0
Connect to SGND
(for immediate
off)
Internal only
1-1
0
OPEN
(for soft-off)
CLOCK
CONFIGURATION
NOTE: Fault retry is not supported in current sharing configuration.
Phase Spreading
When multiple point-of-load converters share a common DC
input supply, it is desirable to adjust the clock phase offset of
each device, such that not all devices start to switch
simultaneously. Setting each converter to start its switching cycle
at a different point in time can dramatically reduce input
capacitance requirements and efficiency losses. Since the peak
current drawn from the input supply is effectively spread out over
a period of time, the peak current drawn at any given moment is
reduced, and the power losses proportional to the IRMS2 are
reduced dramatically.
DEVICE POSITION
- NUMBER OF
DEVICES
DROOP
(mV/A)
RSET
(kΩ)
Output internal
1-2
0.07
10
External
2-2
0.07
11
Output internal
1-2
0.1
12.1
External
2-2
0.1
13.3
To enable phase spreading, all converters must be synchronized
to the same switching clock. The phase offset of each device
may also be set to any value between 0° and 360° in 22.5°
increments with the PMBus command INTERLEAVE. The internal
two phases of the module always maintain a phase difference
of 180°.
Output internal
1-2
0.13
14.7
Fault Spreading
External
2-2
0.13
16.2
Output internal
1-2
0.17
17.8
External
2-2
0.17
19.6
Output internal
1-2
0.21
21.5
External
2-2
0.21
23.7
Digital-DC modules and devices can be configured to broadcast a
fault event over the DDC bus to the other devices in the group
using the PMBus command DDC_GROUP. When a nondestructive
fault occurs, the device shuts down and broadcasts the fault
event over the DDC bus. The other devices on the DDC bus shut
down simultaneously, if configured to do so.
Output internal
1-3
0.05
26.1
External
2-3
0.05
28.7
External
3-3
0.05
31.6
Output internal
1-3
0.07
34.8
External
2-3
0.07
38.3
External
3-3
0.07
42.2
Output internal
1-3
0.09
46.4
CLOCK
CONFIGURATION
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Note that fault retry is not supported in multiple modules with
fault spreading enabled, such as current sharing configuration.
Output Sequencing
A group of Digital-DC modules or devices may be configured to
power up in a predetermined sequence. This feature is especially
useful when powering advanced processors (FPGAs and ASICs)
that require one supply to reach its operating voltage prior to
another supply reaching it in order to avoid latch-up. Multidevice
sequencing can be achieved by configuring each device with the
FN8704.1
September 10, 2015
ISL8273M
PMBus command SEQUENCE. Multiple device sequencing is
configured by issuing PMBus commands to assign the preceding
device in the sequencing chain as well as the device that follows
the sequence.
The Enable pins of all devices in a sequencing group must be tied
together and driven high to initiate a sequenced turn-on of the
group. The enable must be driven low to initiate a sequenced
turnoff of the group. It is recommended to enable fault spreading
with the PMBus command DDC_GROUP within a sequencing
group.
Monitoring Via SMBus
The ISL8273M can monitor a wide variety of different system
parameters using the PMBus commands:
• READ_VIN
output ceramic capacitors close to the VOUT pads and in the
direction of the load current path in order to create a low
impedance path for the high frequency inductor ripple current.
• Use large copper areas for power path (VIN, PGND, VOUT) to
minimize conduction loss and thermal stress. Also, use
multiple vias to connect the power planes in different layers. It
is recommended to enlarge PAD11 and 15 to also place more
vias on them. The ceramic capacitors CIN can be placed on the
bottom layer under these two pads.
• Connect remote sensing traces to the regulation point to
achieve a tight output voltage regulation and place the two
traces in parallel. Route a trace from VSENN and VSENP to the
point of load where the tight output voltage is desired. Avoid
routing any sensitive signal traces, such as the VSENN, VSENP
sensing lines near the SW pins.
• PAD14 and 16 (SW1 and SW2) are noisy pads, but they are
beneficial for thermal dissipation. If the noise issue is critical
for the applications, it is recommended to use only the top
layer for the SW pads. For better thermal performance, use
multiple vias on these pads to connect into the SW inner and
bottom layers. However, caution must be taken when placing a
limited area of SW planes in any layer. The SW planes should
avoid the sensing signals and should be surrounded by the
PGND layer to avoid the noise coupling.
• READ_VOUT
• READ_IOUT
• READ_INTERNAL_TEMP
• READ_DUTY_CYCLE
• READ_FREQEUNCY
• READ_VMON
Snapshot Parameter Capture
The ISL8273M offers a special feature to capture parametric data
and fault status following a fault. Detailed description is provided
in the “PMBus Commands Description” on page 28 under PMBus
command SNAPSHOT and SNAPSHOT_CONTROL.
• For pins SWD1 (L3) and SWD2 (P10), it is recommended to
connect to the related SW1 and SW2 pads with short loop
wires. The wire width should be more than 20mils.
COUT
VOUT
COUT
PGND
PGND
Nonvolatile Memory
The ISL8273M has internal nonvolatile memory where user
configurations are stored. Integrated security measures ensure
that the user can only restore the module to a level that has been
made available to them. During the initialization process, the
ISL8273M checks for stored values contained in its internal
nonvolatile memory.
Modules are shipped with factory defaults configuration and
most settings can be overwritten by PMBus Commands and can
be stored in nonvolatile memory by PMBus command
STORE_USER_ALL.
Kelvin Connections
VIN
To achieve stable operation, low losses and good thermal
performance some layout considerations are necessary
(Figure 26).
CIN
• Place enough ceramic capacitors between VIN and PGND,
VOUT and PGND and bypass capacitors between VDD, VDRV
and the ground plane, as close to the module as possible to
minimize high frequency noise. It is very critical to place the
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PGND
VSEN- VSEN+
Layout Guide
• Establish separate SGND plane and PGND planes, then
connect SGND to PGND plane on a middle layer and
underneath PAD6 with a single point connection. For SGND
and PGND pin connections, such as small pins H16, J16, M5
and M17..., use multiple vias for each pin to connect to inner
SGND or PGND layer.
SGND
PGND
VIN
CIN
PGND
FIGURE 26. RECOMMENDED LAYOUT
Thermal Considerations
Experimental power loss curves along with θJA from thermal
modeling analysis can be used to evaluate the thermal
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September 10, 2015
ISL8273M
Package Description
The structure of the ISL8273M belongs to the High Density Array
no-lead package (HDA). This kind of package has advantages,
such as good thermal and electrical conductivity, low weight and
small size. The HDA package is applicable for surface mounting
technology and is being more readily used in the industry. The
ISL8273M contains several types of devices, including resistors,
capacitors, inductors and control ICs. The ISL8273M is a copper
leadframe based package with exposed copper thermal pads,
which have good electrical and thermal conductivity. The copper
leadframe and multicomponent assembly is overmolded with a
polymer mold compound to protect these devices.
The package outline and typical PCB layout pattern design and
typical stencil pattern design are shown on pages 52, 53 and 54.
The module has a small size of 18mmx 23mmx7.5mm.
PCB Layout Pattern Design
The bottom of ISL8273M is a leadframe footprint, which is
attached to the PCB by surface mounting process. The PCB
layout pattern is shown on page 54. The PCB layout pattern is
essentially 1:1 with the HDA exposed pad and I/O termination
dimensions. The thermal lands on the PCB layout should match
1:1 with the package exposed die pads.
Thermal Vias
walls resulting in reduced surface friction and better paste
release, which reduces voids. Using a Trapezoidal Section
Aperture (TSA) also promotes paste release and forms a “brick
like” paste deposit that assists in firm component placement. A
0.1mm to 0.15mm stencil thickness is recommended for this
large pitch (1.3mm) HDA.
Reflow Parameters
Due to the low mount height of the HDA, “No-Clean” Type 3
solder paste per ANSI/J-STD-005 is recommended. A nitrogen
purge is also recommended during reflow. A system board reflow
profile depends on the thermal mass of the entire populated
board, so it is not practical to define a specific soldering profile
just for the HDA. The profile given in Figure 27 is provided as a
guideline, which can be customized for varying manufacturing
practices and applications.
300
PEAK TEMPERATURE ~+245°C;
TYPICALLY 60s-150s ABOVE +217°C
KEEP LESS THAN 30s WITHIN 5°C OF PEAK TEMP.
250
TEMPERATURE (°C)
consideration for the module. The derating curves are derived
from the maximum power allowed while maintaining the
temperature below the maximum junction temperature of
+120°C. The derating curves are derived based on tests of the
ISL8273MEVAL1Z evaluation board, which is an 8-layer board
4.7x4.8inch in size with 2oz Cu on all layers and multiple via
interconnects. In the actual application, other heat sources and
design margins should be considered.
200
SLOW RAMP (3°C/s MAX)
AND SOAK FROM +150°C
TO +200°C FOR 60s~180s
150
100
RAMP RATE 1.5°C FROM +70°C TO +90°C
50
0
0
100
150
200
250
300
350
DURATION (s)
FIGURE 27. TYPICAL REFLOW PROFILE
A grid of 1.0mm to 1.2mm pitch thermal vias, which drops down
and connects to buried copper plane(s), should be placed under the
thermal land. The vias should be about 0.3mm to 0.33mm in
diameter with the barrel plated to about 1.0 oz. of copper. Although
adding more vias (by decreasing via pitch) will improve the thermal
performance, diminishing returns will be seen as the number of
vias is increased. Simply use as many vias as practical for the
thermal land size and your board design rules will allow.
Stencil Pattern Design
Reflowed solder joints on the perimeter I/O lands should have
about a 50µm to 75µm (2mil to 3mil) standoff height. The solder
paste stencil design is the first step in developing optimized,
reliable solder joins. Stencil aperture size to land size ratio should
typically be 1:1. The aperture width may be reduced slightly to
help prevent solder bridging between adjacent I/O lands. To
reduce solder paste volume on the larger thermal lands, it is
recommended that an array of smaller apertures be used
instead of one large aperture. It is recommended that the stencil
printing area cover 50% to 80% of the PCB layout pattern. A
typical solder stencil pattern is shown on page 53. The gap width
between pad to pad is 0.6mm. The user should consider the
symmetry of the whole stencil pattern when designing its pads. A
laser cut, stainless steel stencil with electropolished trapezoidal
walls is recommended. Electropolishing “smooths” the aperture
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FN8704.1
September 10, 2015
ISL8273M
PMBus Command Summary
COMMAND
CODE
COMMAND
NAME
DESCRIPTION
TYPE
DATA
FORMAT
DEFAULT
VALUE
DEFAULT
SETTING
PAGE
01h
OPERATION
Sets Enable, Disable and VOUT
Margin modes.
R/W BYTE
BIT
02h
ON_OFF_CONFIG
Configures the EN pin and PMBus
commands to turn the unit
ON/OFF
R/W BYTE
BIT
03h
CLEAR_FAULTS
Clears fault indications.
SEND BYTE
28
15h
STORE_USER_ALL
Stores all PMBus values written
since last restore at user level.
SEND BYTE
28
16h
RESTORE_USER_ALL
Restores PMBus settings that were
stored using STORE_USER_ALL.
SEND BYTE
29
20h
VOUT_MODE
Preset to defined data format of
VOUT commands.
READ BYTE
BIT
21h
VOUT_COMMAND
Sets the nominal value of the
output voltage.
R/W WORD
L16u
23h
VOUT_CAL_OFFSET
Applies a fixed offset voltage to the
VOUT_COMMAND.
R/W WORD
L16s
24h
VOUT_MAX
Sets the maximum possible value
of VOUT. 110% of pin-strap VOUT.
R/W WORD
25h
VOUT_MARGIN_HIGH
Sets the value of the VOUT during a
margin high.
26h
VOUT_MARGIN_LOW
27h
28
16h
28
Linear Mode,
Exponent = -13
29
Pin-strap
29
0V
29
L16u
1.1*VOUT
Pin-strap
29
R/W WORD
L16u
1.05*VOUT
Pin-strap
29
Sets the value of the VOUT during a
margin low.
R/W WORD
L16u
0.95*VOUT
Pin-strap
30
VOUT_TRANSITION_RATE
Sets the transition rate during
margin or other change of VOUT.
R/W WORD
L11
1V/ms
30
28h
VOUT_DROOP
Sets the loadline (V/I Slope)
resistance for the rail.
R/W WORD
L11
Pin-strap
30
33h
FREQUENCY_SWITCH
Sets the switching frequency.
R/W WORD
L11
Pin-strap
30
37h
INTERLEAVE
Configures a phase offset between
devices sharing a SYNC clock.
R/W WORD
BIT
0000h
38h
IOUT_CAL_GAIN
Sense resistance for inductor DCR
current sensing.
R/W WORD
L11
B370h
0.86mΩ
39h
IOUT_CAL_OFFSET
Sets the current-sense offset.
R/W WORD
L11
0000h
0A
31
40h
VOUT_OV_FAULT_LIMIT
Sets the VOUT overvoltage fault
threshold.
R/W WORD
L16u
1.15*VOUT
Pin-strap
31
41h
VOUT_OV_FAULT_RESPONSE
Configures the VOUT overvoltage
fault response.
R/W BYTE
BIT
Disable and
No Retry
31
42h
VOUT_OV_WARN_LIMIT
Sets the VOUT overvoltage warn
threshold.
R/W WORD
L16u
1.10*VOUT
Pin-strap
31
43h
VOUT_UV_WARN_LIMIT
Sets the VOUT undervoltage warn
threshold.
R/W WORD
L16u
0.9*VOUT
Pin-strap
32
44h
VOUT_UV_FAULT_LIMIT
Sets the VOUT undervoltage fault
threshold.
R/W WORD
L16u
0.85*VOUT
Pin-strap
32
45h
VOUT_UV_FAULT_RESPONSE
Configures the VOUT undervoltage
fault response.
R/W BYTE
BIT
80h
Disable and
No Retry
32
46h
IOUT_OC_FAULT_LIMIT
Sets the IOUT average overcurrent
fault threshold.
R/W WORD
L11
EAD0h
90A
32
4Bh
IOUT_UC_FAULT_LIMIT
Sets the IOUT average
undercurrent fault threshold.
R/W WORD
L11
E4E0h
-50A
32
4Fh
OT_FAULT_LIMIT
Sets the over-temperature fault
threshold.
R/W WORD
L11
EBE8h
+125°C
33
50h
OT_FAULT_RESPONSE
Configures the over-temperature
fault response.
R/W BYTE
BIT
80h
Disable and
No Retry
33
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13h
Hardware Enable,
Soft Off
0000h
BA00h
80h
30
31
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ISL8273M
PMBus Command Summary (Continued)
COMMAND
CODE
COMMAND
NAME
DESCRIPTION
TYPE
DATA
FORMAT
DEFAULT
VALUE
DEFAULT
SETTING
PAGE
51h
OT_WARN_LIMIT
Sets the over-temperature warning
limit.
R/W WORD
L11
EB48h
+105°C
33
52h
UT_WARN_LIMIT
Sets the under-temperature
warning limit.
R/W WORD
L11
DC40h
-30°C
33
53h
UT_FAULT_LIMIT
Sets the under-temperature fault
threshold.
R/W WORD
L11
E580h
-40°C
34
54h
UT_FAULT_RESPONSE
Configures the under-temperature
fault response.
R/W BYTE
BIT
80h
Disable and
No Retry
34
55h
VIN_OV_FAULT_LIMIT
Sets the VIN overvoltage fault
threshold.
R/W WORD
L11
D380h
14V
34
56h
VIN_OV_FAULT_RESPONSE
Configures the VIN overvoltage
fault response.
R/W BYTE
BIT
80h
Disable and
No Retry
34
57h
VIN_OV_WARN_LIMIT
Sets the input overvoltage warning
limit.
R/W WORD
L11
D353h
13.3V
35
58h
VIN_UV_WARN_LIMIT
Sets the input undervoltage
warning limit.
R/W WORD
L11
1.05*VIN
UV Fault Limit
35
59h
VIN_UV_FAULT_LIMIT
Sets the VIN undervoltage fault
threshold.
R/W WORD
L11
Pin-strap
35
5Ah
VIN_UV_FAULT_RESPONSE
Configures the VIN undervoltage
fault response.
R/W BYTE
BIT
Disable and
No Retry
35
5Eh
POWER_GOOD_ON
Sets the voltage threshold for
Power-good indication.
R/W WORD
L16u
0.9*VOUT
Pin-strap
36
60h
TON_DELAY
Sets the delay time from ENABLE
to start of VOUT rise.
R/W WORD
L11
Pin-strap
36
61h
TON_RISE
Sets the rise time of VOUT after
ENABLE and TON_DELAY.
R/W WORD
L11
Pin-strap
36
64h
TOFF_DELAY
Sets the delay time from DISABLE
to start of VOUT fall.
R/W WORD
L11
Pin-strap
36
65h
TOFF_FALL
Sets the fall time for VOUT after
DISABLE and TOFF_DELAY.
R/W WORD
L11
Pin-strap
36
78h
STATUS_BYTE
Returns an abbreviated status for
fast reads.
READ BYTE
BIT
00h
No Faults
37
79h
STATUS_WORD
Returns information with a
summary of the units's fault
condition.
READ WORD
BIT
0000h
No Faults
37
7Ah
STATUS_VOUT
Returns the VOUT specific status.
READ BYTE
BIT
00h
No Faults
38
80h
7Bh
STATUS_IOUT
Returns the IOUT specific status.
READ BYTE
BIT
00h
No Faults
38
7Ch
STATUS_INPUT
Returns specific status specific to
the input.
READ BYTE
BIT
00h
No Faults
38
7Dh
STATUS_TEMP
Returns the temperature specific
status.
READ BYTE
BIT
00h
No Faults
39
7Eh
STATUS_CML
Returns the communication, logic
and memory specific status.
READ BYTE
BIT
00h
No Faults
39
80h
STATUS_MFR_SPECIFIC
Returns the VMON and external
sync clock specific status.
READ BYTE
BIT
00h
No Faults
39
88h
READ_VIN
Returns the input voltage reading.
READ WORD
L11
40
8Bh
READ_VOUT
Returns the output voltage
reading.
READ WORD
L16u
40
8Ch
READ_IOUT
Returns the output current
reading.
READ WORD
L11
40
8Dh
READ_INTERNAL_TEMP
Returns the temperature reading
internal to the device.
READ WORD
L11
40
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FN8704.1
September 10, 2015
ISL8273M
PMBus Command Summary (Continued)
COMMAND
CODE
COMMAND
NAME
DESCRIPTION
TYPE
DATA
FORMAT
DEFAULT
VALUE
DEFAULT
SETTING
PAGE
94h
READ_DUTY_CYCLE
Returns the duty cycle reading
during the ENABLE state.
READ WORD
L11
40
95h
READ_FREQUENCY
Returns the measured operating
switch frequency.
READ WORD
L11
40
96h
READ_IOUT_0
Returns phase 1 current reading.
READ WORD
L11
40
97h
READ_IOUT_1
Returns phase 2 current reading.
READ WORD
L11
99h
MFR_ID
Sets a user defined identification.
R/W BLOCK
ASC
Null
40
41
9Ah
MFR_MODEL
Sets a user defined model.
R/W BLOCK
ASC
Null
41
9Bh
MFR_REVISION
Sets a user defined revision.
R/W BLOCK
ASC
Null
41
9Ch
MFR_LOCATION
Sets a user defined location
identifier.
R/W BLOCK
ASC
Null
41
9Dh
MFR_DATE
Sets a user defined date.
R/W BLOCK
ASC
Null
41
9Eh
MFR_SERIAL
Sets a user defined serialized
identifier.
R/W BLOCK
ASC
Null
42
A8H
LEGACY_FAULT_GROUP
Sets rail IDs of legacy devices for
fault spreading
R/W BLOCK
BIT
B0h
USER_DATA_00
Sets a user defined data.
R/W BLOCK
ASC
D0h
ISENSE_CONFIG
Configures ISENSE related
features.
R/W BYTE
BIT
D1h
USER_CONFIG
Configures several user-level
features.
R/W BYTE
D3h
DDC_CONFIG
Configures the DDC bus.
D4h
POWER_GOOD_DELAY
00000000h No rail ID
specified
42
Null
42
256ns Blanking
Time, High Range
42
BIT
Pin-strap (ASCR
on/off for
start-up)
43
R/W WORD
BIT
Pin-strap (set
based on PMBus
address and CS)
43
Sets the delay between VOUT > PG
threshold and asserting the PG
pin.
R/W WORD
L11
3ms
43
Pin-strap
44
Prequel and
Sequel Disabled
44
06h
C300h
DFh
ASCR_CONFIG
Configures ASCR control loop.
R/W BLOCK
CUS
E0h
SEQUENCE
Identifies the Rail DDC ID to
perform multi-rail sequencing.
R/W WORD
BIT
E2h
DDC_GROUP
Sets rail DDC IDs to obey faults
and margining spreading
information.
R/W BLOCK
BIT
Pin-strap (set
based on CS)
45
E4h
DEVICE_ID
Returns the 16-byte (character)
device identifier string.
READ BLOCK
ASC
Reads Device
Version
45
E5h
MFR_IOUT_OC_FAULT_RESPONSE Configures the IOUT overcurrent
fault response.
R/W BYTE
BIT
80h
Disable and
No Retry
45
E6h
MFR_IOUT_UC_FAULT_RESPONSE Configures the IOUT undercurrent
fault response.
R/W BYTE
BIT
80h
Disable and
No Retry
46
E9h
SYNC_CONFIG
Configures the SYNC pin.
R/W BYTE
BIT
Pin-strap (set
based on CS)
46
EAh
SNAPSHOT
Returns 32-byte read-back of
parametric and status values.
READ BLOCK
BIT
EBh
BLANK_PARAMS
Returns recently changed
parameter values.
READ BLOCK
BIT
F3h
SNAPSHOT_CONTROL
Snapshot feature control
command.
R/W BYTE
BIT
F4h
RESTORE_FACTORY
Restores device to the factory
default values.
SEND BYTE
F5h
MFR_VMON_OV_FAULT_LIMIT
Returns the VMON overvoltage
threshold.
READ WORD
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0000h
47
FF...FFh
47
47
48
L11
CB00h
6V
48
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September 10, 2015
ISL8273M
PMBus Command Summary (Continued)
COMMAND
CODE
COMMAND
NAME
DESCRIPTION
TYPE
DATA
FORMAT
DEFAULT
VALUE
CA00h
DEFAULT
SETTING
4V
PAGE
F6h
MFR_VMON_UV_FAULT_LIMIT
Returns the VMON undervoltage
threshold.
READ WORD
L11
48
F7h
MFR_READ_VMON
Returns the VMON voltage
reading.
READ WORD
L11
F8h
VMON_OV_FAULT_RESPONSE
Returns the VMON overvoltage
response.
READ BYTE
BIT
80h
Disable and
No Retry
48
F9h
VMON_UV_FAULT_RESPONSE
Returns the VMON undervoltage
response.
READ BYTE
BIT
80h
Disable and No
Retry
48
48
PMBus™ Data Formats
Linear-11 (L11)
L11 data format uses 5-bit two’s compliment exponent (N) and 11-bit two’s compliment mantissa (Y) to represent real world decimal
value (X).
Data Byte High
Data Byte Low
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Exponent (N)
Mantissa (Y)
Relation between real world decimal value (X), N and Y is: X = Y·2N
Linear-16 Unsigned (L16u)
L16u data format uses a fixed exponent (hard-coded to N = -13h) and a 16-bit unsigned integer mantissa (Y) to represent real world
decimal value (X). Relation between real world decimal value (X), N and Y is: X = Y·2-13
Linear-16 Signed (L16s)
L16s data format uses a fixed exponent (hard-coded to N = -13h) and a 16-bit two’s compliment mantissa (Y) to represent real world
decimal value (X).
Relation between real world decimal value (X), N and Y is: X = Y·2-13
Bit Field (BIT)
Breakdown of Bit Field for each command is provided in “PMBus Commands Description” on page 28.
Custom (CUS)
Breakdown of Custom data format for each command is provided in “PMBus Commands Description” on page 28. A combination of Bit
Field and integer are common type of Custom data format.
ASCII (ASC)
A variable length string of text characters uses ASCII data format.
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September 10, 2015
ISL8273M
PMBus Commands Description
OPERATION (01h)
Definition: Sets Enable, Disable and VOUT Margin settings. Data values of OPERATION that force margin high or low only take effect
when the MGN pin is left open (i.e., in the NOMINAL margin state).
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value:
Units: N/A
SETTINGS
ACTIONS
04h
Immediate off (no sequencing)
44h
Soft off (with sequencing)
84h
On - Nominal
94h
On - Margin low
A4h
On - Margin high
ON_OFF_CONFIG (02h)
Definition: Configures the interpretation and coordination of the OPERATION command and the ENABLE pin (EN).
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 16h (Device starts from ENABLE pin with soft-off)
Units: N/A
SETTINGS
ACTIONS
16h
Device starts from ENABLE pin with soft off.
17h
Device starts from ENABLE pin with immediate off.
1Ah
Device starts from OPERATION command with soft off.
1Bh
Device starts from OPERATION command with immediate off.
CLEAR_FAULTS (03h)
Definition: Clears all fault bits in all registers and releases the SALRT pin (if asserted) simultaneously. If a fault condition still exists, the
bit will reassert immediately. This command will not restart a device if it has shut down, it will only clear the faults.
Data Length in Bytes: 0 Byte
Data Format: N/A
Type: Send byte
Default Value: N/A
Units: N/A
Reference: N/A
STORE_USER_ALL (15h)
Definition: Stores all PMBus settings from the operating memory to the nonvolatile USER store memory. To clear the USER store,
perform a RESTORE_FACTORY then STORE_USER_ALL. To add to the USER store, perform a RESTORE_USER_ALL, write commands to
be added, then STORE_USER_ALL. This command can be used during device operation, but the device will be unresponsive for 20ms
while storing values.
Data Length in Bytes: 0
Data Format: N/A
Type: Send byte
Default Value: N/A
Units: N/A
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RESTORE_USER_ALL (16h)
Definition: Restores all PMBus settings from the USER store memory to the operating memory. Command performed at power-up.
Security level is changed to Level 1 following this command. This command can be used during device operation, but the device will be
unresponsive for 20ms while storing values.
Data Length in Bytes: 0
Data Format: N/A
Type: Send byte
Default Value: N/A
Units: N/A
VOUT_MODE (20h)
Definition: Reports the VOUT mode and provides the exponent used in calculating several VOUT settings. Fixed with linear mode with
default exponent (N) = -13
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: 13h (Linear Mode, N = -13)
Units: N/A
VOUT_COMMAND (21h)
Definition: This command sets or reports the target output voltage. This command cannot set a value higher than VOUT_MAX.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: Pin-strap setting
Units: Volts
Range: 0V to VOUT_MAX
VOUT_CAL_OFFSET (23h)
Definition: The VOUT_CAL_OFFSET command is used to apply a fixed offset voltage to the output voltage command value. This
command is typically used by the user to calibrate a device in the application circuit.
Data Length in Bytes: 2
Data Format: L16s
Type: R/W
Default Value: 0000h
Units: Volts
VOUT_MAX (24h)
Definition: The VOUT_ MAX command sets an upper limit on the output voltage the unit can command regardless of any other
commands or combinations. The intent of this command is to provide a safeguard against a user accidentally setting the output
voltage to a possibly destructive level rather than to be the primary output overprotection. Default value can be changed via PMBus.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 1.10xVOUT_COMMAND pin-strap setting
Units: Volts
Range: 0V to 5.5V
VOUT_MARGIN_HIGH (25h)
Definition: Sets the value of the VOUT during a margin high. This VOUT_MARGIN_HIGH command loads the unit with the voltage to
which the output is to be changed when the OPERATION command or MGN pin is set to “Margin High”.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default value: 1.05 x VOUT_COMMAND pin-strap setting
Units: V
Range: 0V to VOUT_MAX
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VOUT_MARGIN_LOW (26h)
Definition: Sets the value of the VOUT during a margin low. This VOUT_MARGIN_LOW command loads the unit with the voltage to which
the output is to be changed when the OPERATION command or MGN pin is set to “Margin Low”.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default value: 0.95 x VOUT_COMMAND pin-strap setting
Units: V
Range: 0V to VOUT_MAX
VOUT_TRANSITION_RATE (27h)
Definition: This command sets the rate at which the output should change voltage when the device receives the VOUT_COMMAND or an
OPERATION command (Margin High, Margin Low) that causes the output voltage to change. The maximum possible positive value of
the two data bytes indicates that the device should make the transition as quickly as possible.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default value: BA00h (1V/ms)
Units: V/ms
Range: 0.1 to 4V/ms
VOUT_DROOP (28h)
Definition: The VOUT_DROOP sets the effective load line (V/I slope) for the rail in which the device is used. It is the rate, in mV/A at
which the output voltage decreases (or increases) with increasing (or decreasing) output current for use with adaptive voltage
positioning schemes or multi-module current sharing. In current sharing configuration, VOUT_DROOP set in each module stands for the
droop seen by the load.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default value: Pin-strap setting
Units: mV/A
Range: 0 to 40mV/A
FREQUENCY_SWITCH (33h)
Definition: Sets the switching frequency of the device. Initial default value is defined by a pin-strap and this value can be overridden by
writing this command via the PMBus. If an external SYNC is utilized, this value should be set as close as possible to the external clock
value. The output must be disabled when writing this command.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: Pin-strap setting
Units: kHz
Range: 300kHz to 1066kHz
INTERLEAVE (37h)
Definition: Configures the phase offset of a device that is sharing a common SYNC clock with other devices. The phase offset of each
device can be set to any value between 0° and 360° in 22.5° increments. The internal two phases of the module always maintains a
phase difference of 180°.
Data Length in Bytes: 2
Data Format: BIT
Type: R/W
Default Value: 0000h
Units: N/A
BITS
PURPOSE
VALUE
15:4
Reserved
0
3:0
Position in Group
0 to 15
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DESCRIPTION
Reserved
Sets position of the device's rail within the group.
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IOUT_CAL_GAIN (38h)
Definition: Sets the effective impedance across the current sense circuit for use in calculating output current at +25°C.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: B370h (0.86mΩ)
Units: mΩ
IOUT_CAL_OFFSET (39h)
Definition: Used to null out any offsets in the output current sensing circuit for each phase, and to compensate for delayed
measurements of current ramp due to Isense blanking time.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: 0000h (0A)
Units: A
VOUT_OV_FAULT_LIMIT (40h)
Definition: Sets the VOUT overvoltage fault threshold.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 1.15xVOUT_COMMAND pin-strap setting
Units: V
Range: 0V to VOUT_MAX
VOUT_OV_FAULT_RESPONSE (41h)
Definition: Configures the VOUT overvoltage fault response. Note that the device cannot be set to ignore this fault mode.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable and no retry)
Units: N/A
BIT
FIELD NAME
7:6
Reserved
VALUE
DESCRIPTION
10
000
001-110
5:3
Retry Setting
2:0
Retry Delay
111
000-111
No retry. The output remains disabled until the fault is cleared.
Not used.
Attempts to restart continuously, without checking if the fault is still present, until it is
commanded OFF (by the CONTROL pin or OPERATION command), bias power is removed,
or another fault condition causes the unit to shut down.
Retry delay time = (Value + 1)*35ms. Sets the time between retries in 35ms
VOUT_OV_WARN_LIMIT (42h)
Definition: Sets the VOUT overvoltage warning threshold. Power-good signal is pulled low when output voltage goes higher than this
threshold.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 1.10xVOUT_COMMAND pin-strap setting
Units: V
Range: 0V to VOUT_MAX
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VOUT_UV_WARN_LIMIT (43h)
Definition: Sets the VOUT undervoltage warning threshold. Power-good signal is pulled low when the output voltage goes lower than this
threshold.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 0.90xVOUT_COMMAND pin-strap setting
Units: V
Range: 0V to VOUT_MAX
VOUT_UV_FAULT_LIMIT (44h)
Definition: Sets the VOUT undervoltage fault threshold. This fault is masked during ramp or when disabled.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 0.85xVOUT_COMMAND pin-strap setting
Units: V
Range: 0V to VOUT_MAX
VOUT_UV_FAULT_RESPONSE (45h)
Definition: Configures the VOUT undervoltage fault response.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable, no retry)
Units: N/A
BIT
FIELD NAME
VALUE
7:6
Reserved
10
000
001-110
5:3
Retry Setting
2:0
Retry Delay
DESCRIPTION
No retry. The output remains disabled until the fault is cleared.
Not used.
111
Attempts to restart continuously, without checking if the fault is still present, until it is
commanded OFF (by the CONTROL pin or OPERATION command), bias power is removed,
or another fault condition causes the unit to shut down.
000-111
Retry delay time = (Value + 1)*35ms. Sets the time between retries in 35ms increments.
Range is 35ms to 280ms.
IOUT_OC_FAULT_LIMIT (46h)
Definition: Sets the IOUT average overcurrent fault threshold. Device will automatically calculate peak inductor overcurrent fault limit
for each phase based on the equation: IOUT(PEAK OC LIMIT) = (0.5*IOUT_OC_FAULT_LIMIT+0.5*IRIPPLE(P-P))*125%. A hard bound of
60A is applied to the peak overcurrent fault limit per phase.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: EAD0h (90A)
Units: A
Range: -100A to 100A
IOUT_UC_FAULT_LIMIT (4Bh)
Definition: Sets the IOUT average undercurrent fault threshold. Device will automatically calculate valley inductor undercurrent fault limit
for each phase based on the equation: IOUT(VALLEY UC LIMIT) = (0.5*IOUT_UC_FAULT_LIMIT-0.5*IRIPPLE(P-P))*125%. A hard bound of
-55A is applied to the valley undercurrent fault limit per phase.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: E4E0h (-50A)
Units: A
Range: -100A to 100A
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OT_FAULT_LIMIT (4Fh)
Definition: The OT_FAULT_LIMIT command sets the temperature at which the device should indicate an over-temperature fault. Note
that the temperature must drop below OT_WARN_LIMIT to clear this fault.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: EBE8h (+125˚C)
Units: Celsius
Range: 0°C to +175°C
OT_FAULT_RESPONSE (50h)
Definition: The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an over-temperature fault.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Fault Value: 80h (Disable and no retry)
Units: N/A
BIT
FIELD NAME
7:6
Reserved
VALUE
DESCRIPTION
10
000
001-110
5:3
Retry Setting
2:0
Retry Delay
No retry. The output remains disabled until the fault is cleared.
Not used.
111
Attempts to restart continuously, without checking if the fault is still present, until it is
commanded OFF (by the CONTROL pin or OPERATION command), bias power is removed,
or another fault condition causes the unit to shut down.
000-111
Retry delay time = (Value + 1)*35ms. Sets the time between retries in 35ms increments.
Range is 35ms to 280ms.
OT_WARN_LIMIT (51h)
Definition: The OT_WARN_LIMIT command sets the temperature at which the device should indicate an over-temperature warning
alarm. In response to the OT_WARN_LIMIT being exceeded, the device: sets the TEMPERATURE bit in STATUS_WORD, sets the
OT_WARNING bit in STATUS_TEMPERATURE and notifies the host.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: EB48h (+105°C)
Units: Celsius
Range: 0°C to +175°C
UT_WARN_LIMIT (52h)
Definition: The UT_WARN_LIMIT command set the temperature at which the device should indicate an under-temperature warning
alarm. In response to the UT_WARN_LIMIT being exceeded, the device: sets the TEMPERATURE bit in STATUS_WORD, sets the
UT_WARNING bit in STATUS_TEMPERATURE and notifies the host.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: DC40h (-30°C)
Units: Celsius
Range: -55°C to +25°C
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UT_FAULT_LIMIT (53h)
Definition: The UT_FAULT_LIMIT command sets the temperature, in degrees Celsius, of the unit where it should indicate an
under-temperature fault. Note that the temperature must rise above UT_WARN_LIMIT to clear this fault.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: E580h (-40°C)
Units: Celsius
Range: -55°C to +25°C
UT_FAULT_RESPONSE (54h)
Definition: Configures the under-temperature fault response as defined by the following table. The delay time is the time between
restart attempts.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable, no retry)
Units: N/A
BIT
FIELD NAME
7:6
Reserved
VALUE
DESCRIPTION
10
000
001-110
5:3
Retry Setting
2:0
Retry Delay
No retry. The output remains disabled until the fault is cleared.
Not used.
111
Attempts to restart continuously, without checking if the fault is still present, until it is
commanded OFF (by the CONTROL pin or OPERATION command), bias power is removed,
or another fault condition causes the unit to shut down.
000-111
Retry delay time = (Value + 1)*35ms. Sets the time between retries in 35ms increments.
Range is 35ms to 280ms.
VIN_OV_FAULT_LIMIT (55h)
Definition: Sets the VIN overvoltage fault threshold.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: D380h (14V)
Units: V
Range: 0V to 16V
VIN_OV_FAULT_RESPONSE (56h)
Definition: Configures the VIN overvoltage fault response as defined by the following table. The delay time is the time between restart
attempts.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable and no retry)
Units: N/A
BIT
FIELD NAME
VALUE
7:6
Reserved
10
000
001-110
DESCRIPTION
No retry. The output remains disabled until the fault is cleared.
Not used.
5:3
Retry Setting
111
Attempts to restart continuously, without checking if the fault is still present, until it is
commanded OFF (by the CONTROL pin or OPERATION command), bias power is removed,
or another fault condition causes the unit to shut down.
2:0
Retry Delay
000-111
Retry delay time = (Value + 1)*35ms. Sets the time between retries in 35ms increments.
Range is 35ms to 280ms.
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VIN_OV_WARN_LIMIT (57h)
Definition: Sets the VIN overvoltage warning threshold. In response to the OV_WARN_LIMIT being exceeded, the device: Sets the NONE
OF THE ABOVE and INPUT bits in STATUS_WORD, Sets the VIN_OV_WARNING bit in STATUS_INPUT and notifies the host.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Protectable: Yes
Default Value: D353h (13.3V)
Units: V
Range: 0V to 16V
VIN_UV_WARN_LIMIT (58h)
Definition: Sets the VIN undervoltage warning threshold. If a VIN_UV_FAULT occurs, the input voltage must rise above
VIN_UV_WARN_LIMIT to clear the fault, which provides hysteresis to the fault threshold. In response to the UV_WARN_LIMIT being
exceeded, the device: Sets the NONE OF THE ABOVE and INPUT bits in STATUS_WORD, Sets the VIN_UV_WARNING bit in STATUS_INPUT,
and notifies the host.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: 1.05 x VIN_UV_FAULT_LIMIT pin-strap setting
Units: V
Range: 0V to 12V
VIN_UV_FAULT_LIMIT (59h)
Definition: Sets the VIN undervoltage fault threshold.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: Pin-strap setting
Units: V
Range: 0V to 12V
VIN_UV_FAULT_RESPONSE (5Ah)
Definition: Configures the VIN undervoltage fault response as defined by the following table. The delay time is the time between restart
attempts.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable and no retry)
Units: N/A
BIT
FIELD NAME
7:6
Reserved
VALUE
DESCRIPTION
10
000
001-110
No retry. The output remains disabled until the fault is cleared.
Not used.
5:3
Retry Setting
111
Attempts to restart continuously, without checking if the fault is still present, until it is
commanded OFF (by the CONTROL pin or OPERATION command), bias power is removed,
or another fault condition causes the unit to shut down.
2:0
Retry Delay
000-111
Retry delay time = (Value + 1)*35ms. Sets the time between retries in 35ms increments.
Range is 35ms to 280ms.
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POWER_GOOD_ON (5Eh)
Definition: Sets the voltage threshold for Power-good indication. Power-good asserts with a delay specified in POWER_GOOD_DELAY
after the output voltage exceeds POWER_GOOD_ON and deasserts when the output voltage is less than VOUT_UV_WARN_LIMIT. It is
recommended to set POWER_GOOD_ON higher than VOUT_UV_FAULT_LIMIT.
Data Length in Bytes: 2
Data Format: L16u
Type: R/W
Default Value: 0.9xVOUT_COMMAND pin-strap setting
Units: V
TON_DELAY (60h)
Definition: Sets the delay time from when the device is enabled to the start of VOUT rise.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: Pin-strap setting
Units: ms
Range: 0 to 256ms
TON_RISE (61h)
Definition: Sets the rise time of VOUT after ENABLE and TON_DELAY. In multi-module current sharing configuration where ASCR is
disabled for start up, the rise time of VOUT can be approximately calculated by Equation 1.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: Pin-strap setting
Units: ms
Range: 0 to 200ms
TOFF_DELAY (64h)
Definition: Sets the delay time from DISABLE to start of VOUT fall.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: Pin-strap setting
Units: ms
Range: 0 to 256ms
TOFF_FALL (65h)
Definition: Sets the soft-off fall time for VOUT after DISABLE and TOFF_DELAY.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: Pin-strap setting
Units: ms
Range: 0 to 200ms
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STATUS_BYTE (78h)
Definition: The STATUS_BYTE command returns one byte of information with a summary of the most critical faults.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: 00h
Units: N/A
BIT NUMBER
STATUS BIT NAME
MEANING
7
BUSY
6
OFF
5
VOUT_OV_FAULT
An output overvoltage fault has occurred.
4
IOUT_OC_FAULT
An output overcurrent fault has occurred.
3
VIN_UV_FAULT
An input undervoltage fault has occurred.
2
TEMPERATURE
A temperature fault or warning has occurred.
1
CML
0
NONE OF THE ABOVE
A fault was declared because the device was busy and unable to respond.
This bit is asserted if the unit is not providing power to the output, regardless of
the reason, including simply not being enabled.
A communications, memory or logic fault has occurred.
A fault or warning not listed in bits 7:1 has occurred.
STATUS_WORD (79h)
Definition: The STATUS_WORD command returns two bytes of information with a summary of the unit's fault condition. Based on the
information in these bytes, the host can get more information by reading the appropriate status registers. The low byte of the
STATUS_WORD is the same register as the STATUS_BYTE (78h) command.
Data Length in Bytes: 2
Data Format: BIT
Type: Read-only
Default Value: 0000h
Units: N/A
BIT NUMBER
STATUS BIT NAME
15
VOUT
14
IOUT/POUT
13
INPUT
12
MFG_SPECIFIC
11
POWER_GOOD#
10
FANS
9
OTHER
8
UNKNOWN
7
BUSY
6
OFF
5
VOUT_OV_FAULT
An output overvoltage fault has occurred.
4
IOUT_OC_FAULT
An output overcurrent fault has occurred.
3
VIN_UV_FAULT
An input undervoltage fault has occurred.
2
TEMPERATURE
A temperature fault or warning has occurred.
1
CML
0
NONE OF THE ABOVE
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MEANING
An output voltage fault or warning has occurred.
An output current or output power fault or warning has occurred.
An input voltage, input current, or input power fault or warning has occurred.
A manufacturer specific fault or warning has occurred.
The POWER_GOOD signal, if present, is negated.
A fan or airflow fault or warning has occurred.
A bit in STATUS_OTHER is set.
A fault type not given in bits 15:1 of the STATUS_WORD has been detected.
A fault was declared because the device was busy and unable to respond.
This bit is asserted if the unit is not providing power to the output, regardless of
the reason, including simply not being enabled.
A communications, memory or logic fault has occurred.
A fault or warning not listed in bits 7:1 has occurred.
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STATUS_VOUT (7Ah)
Definition: The STATUS_VOUT command returns one data byte with the status of the output voltage.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: 00h
Units: N/A
BIT NUMBER
STATUS BIT NAME
7
VOUT_OV_FAULT
MEANING
6
VOUT_OV_WARNING
Indicates an output overvoltage warning.
5
VOUT_UV_WARNING
Indicates an output undervoltage warning.
4
VOUT_UV_FAULT
3:0
N/A
Indicates an output overvoltage fault.
Indicates an output undervoltage fault.
These bits are not used.
STATUS_IOUT (7Bh)
Definition: The STATUS_IOUT command returns one data byte with the status of the output current.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: 00h
Units: N/A
BIT NUMBER
STATUS BIT NAME
7
IOUT_OC_FAULT
MEANING
An output overcurrent fault has occurred.
6
IOUT_OC_LV_FAULT
An output overcurrent and low voltage fault has occurred.
5
IOUT_OC_WARNING
An output overcurrent warning has occurred.
4
IOUT_UC_FAULT
3:0
N/A
An output undercurrent fault has occurred.
These bits are not used.
STATUS_INPUT (7Ch)
Definition: The STATUS_INPUT command returns the input voltage and input current status information.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: 00h
Units: N/A
BIT NUMBER
STATUS BIT NAME
7
VIN_OV_FAULT
6
VIN_OV_WARNING
5
VIN_UV_WARNING
4
VIN_UV_FAULT
3:0
N/A
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MEANING
An input overvoltage fault has occurred.
An input overvoltage warning has occurred.
An input undervoltage warning has occurred.
An input undervoltage fault has occurred.
These bits are not used.
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STATUS_TEMP (7Dh)
Definition: The STATUS_TEMP command returns one byte of information with a summary of any temperature related faults or warnings.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: 00h
Units: N/A
BIT NUMBER
STATUS BIT NAME
7
OT_FAULT
MEANING
6
OT_WARNING
An over-temperature warning has occurred.
5
UT_WARNING
An under-temperature warning has occurred.
4
UT_FAULT
3:0
N/A
An over-temperature fault has occurred.
An under-temperature fault has occurred.
These bits are not used.
STATUS_CML (7Eh)
Definition: The STATUS_CML command returns one byte of information with a summary of any communications, logic and/or memory
errors.
Data Length in Bytes: 1
Data Format: BIT
Type: Read-only
Default Value: 00h
Units: N/A
BIT NUMBER
7
MEANING
Invalid or unsupported PMBus command was received.
6
The PMBus command was sent with invalid or unsupported data.
5
Packet error was detected in the PMBus command.
4:2
Not used
1
A PMBus command tried to write to a read-only or protected command, or a communication fault other than the ones listed in
this table has occurred.
0
Not used
STATUS_MFR_SPECIFIC (80h)
Definition: The STATUS_MFR_SPECIFIC command returns one byte of information providing the status of the device's voltage
monitoring and clock synchronization faults. VMON OV/UV warnings are set at ±10% of the VMON_FAULT commands.
Data Length in Bytes: 1
Data Format: BIT
Type: Read only
Default value: 00h
Units: N/A
BIT NUMBER
7:6
FIELD NAME
MEANING
Reserved
5
VMON UV Warning
The voltage on the VMON pin has dropped 10% below the level set by
VMON_UV_FAULT_LIMIT.
4
VMON OV Warning
The voltage on the VMON pin has risen 10% above the level set by
VMON_OV_FAULT_LIMIT.
3
External Switching Period Fault
Loss of external clock synchronization has occurred.
2
Reserved
1
VMON UV Fault
The voltage on the VMON pin has dropped below the level set by
VMON_UV_FAULT_LIMIT.
0
VMON OV Fault
The voltage on the VMON pin has risen above the level set by
VMON_OV_FAULT_LIMIT.
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READ_VIN (88h)
Definition: Returns the input voltage reading.
Data Length in Bytes: 2
Data Format: L11
Type: Read-only
Units: V
READ_VOUT (8Bh)
Definition: Returns the output voltage reading.
Data Length in Bytes: 2
Data Format: L16u
Type: Read-only
Units: V
READ_IOUT (8Ch)
Definition: Returns the output current reading.
Data Length in Bytes: 2
Data Format: L11
Type: Read-only
Default Value: N/A
Units: A
READ_INTERNAL_TEMP (8Dh)
Definition: Returns the controller junction temperature reading from internal temperature sensor.
Data Length in Bytes: 2
Data Format: L11
Type: Read-only
Units: °C
READ_DUTY_CYCLE (94h)
Definition: Reports the actual duty cycle of the converter during the enable state.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Units: %
READ_FREQUENCY (95h)
Definition: Reports the actual switching frequency of the converter during the enable state.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Units: kHz
READ_IOUT_0 (96h)
Definition: Returns the Phase 1 current reading.
Data Length in Bytes: 2
Data Format: L11
Type: Read-only
Default Value: N/A
Units: A
READ_IOUT_1 (97h)
Definition: Returns the Phase 2 current reading.
Data Length in Bytes: 2
Data Format: L11
Type: Read-only
Default Value: N/A
Units: A
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MFR_ID (99h)
Definition: MFR_ID sets user defined identification. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,
MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This
limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this
command then perform a STORE/RESTORE.
Data Length in Bytes: user defined
Data Format: ASC
Type: Block R/W
Default Value: null
Units: N/A
MFR_MODEL (9Ah)
Definition: MFR_MODEL sets a user defined model. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,
MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This
limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this
command then perform a STORE/RESTORE.
Data Length in Bytes: user defined
Data Format: ASC
Type: Block R/W
Default Value: null
Units: N/A
MFR_REVISION (9Bh)
Definition: MFR_REVISION sets a user defined revision. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,
MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This
limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this
command then perform a STORE/RESTORE.
Data Length in Bytes: user defined
Data Format: ASC
Type: Block R/W
Default Value: null
Units: N/A
MFR_LOCATION (9Ch)
Definition: MFR_LOCATION sets a user defined location identifier. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,
MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This
limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this
command then perform a STORE/RESTORE.
Data Length in Bytes: user defined
Data Format: ASC
Type: Block R/W
Default Value: null
Units: N/A
MFR_DATE (9Dh)
Definition: MFR_DATE sets a user defined date. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION, MFR_LOCATION,
MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This limitation includes
multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this command then
perform a STORE/RESTORE.
Data Length in Bytes: user defined
Data Format: ASC
Type: Block R/W
Default Value: null
Units: N/A
Reference: N/A
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MFR_SERIAL (9Eh)
Definition: MFR_SERIAL sets a user defined serialized identifier. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,
MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This
limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this
command then perform a STORE/RESTORE.
Data Length in Bytes: user defined
Data Format: ASC
Type: Block R/W
Default Value: null
Units: N/A
LEGACY_FAULT_GROUP (A8h)
Definition: This command sets which rail DDC IDs should be listened to for fault spreading with legacy devices. The data sent is a
4-byte, 32-bit, bit vector where every bit represents a rail’s DDC ID. A bit set to 1 indicates a device DDC ID to which the configured
device will respond upon receiving a fault spreading event. In this vector, Bit 0 of byte 0 corresponds to the rail with DDC ID 0. Following
through, Bit 7 of byte 3 corresponds to the rail with DDC ID 31.
Data Length in Bytes: 4
Data Format: BIT
Type: Block R/W
Default Value: 00000000h (No rail ID specified)
USER_DATA_00 (B0h)
Definition: USER_DATA_00 sets a user defined data. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,
MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 characters. This
limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this
command then perform a STORE/RESTORE.
Data Length in Bytes: user defined
Data Format: ASC
Type: Block R/W
Default Value: null
Units: N/A
ISENSE_CONFIG (D0h)
Definition: Configures current sense circuitry.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 06h (256ns current sense blanking time, current sense high range)
Units: N/A
BIT
FIELD NAME
7:4
Reserved
3:2
Current Sense
Blanking Time
1:0
VALUE
DESCRIPTION
00
192ns
Sets the blanking time current sense blanking time.
01
256ns
10
412ns
0000
Current Sense Range
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SETTING
42
11
640ns
00
Low Range
±25mV
01
Mid Range
±35mV
10
High Range
±50mV
11
Not Used
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USER_CONFIG (D1h)
Definition: Configures several user-level features. This command overrides the pin-strap settings.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: Pin-strap setting for ASCR on for Start up; ramp-up and ramp-down minimum duty cycle 0.39%; minimum duty cycle
control enabled; PG is open-drain output.
Units: N/A
BIT
7
FIELD NAME
VALUE
SETTING
0
Disabled
ASCR is disabled for start up. Use this for current sharing mode.
1
Enabled
ASCR is enabled for start up. Use this for stand alone mode.
ASCR on for Start up
6:5
Reserved
0
4:3
Ramp-up and
Ramp-down Minimum
Duty Cycle
00
0.39%
01
0.78%
10
1.17%
Reserved
11
1.56%
2
Minimum Duty Cycle
Control
0
Disable
1
Enable
1
Power-good Pin
Configuration
0
Open Drain
1
Push-Pull
Reserved
0
0
DESCRIPTION
Sets the minimum duty-cycle during start-up and shutdown ramp.
Control for minimum duty cycle.
0 = PG is open-drain output.
1 = PG is push-pull output.
DDC_CONFIG (D3h)
Definition: Configures DDC addressing and current sharing. With pin-strap for stand alone configuration, the DDC rail ID is set according
to the SMBus address. With pin-strap for multi-module current sharing, the DDC rail ID is set according to the number of devices. Device
position and number of devices in the rail can be programmed as needed.
Data Length in Bytes: 2
Data Format: BIT
Type: R/W
Default Value: Pin-strap setting
Units: N/A
BIT
15:13
12:8
FIELD NAME
VALUE
Device Position
0, 1, 2, 3
Rail ID
7:3
Reserved
2:0
Number of Devices in
Rail
SETTING
Sets the device position in a current sharing rail. 0-Position 1;
1-Position 2; 2-Position 3; 3-Position 4
0 to 31 (00 to 1Fh)
0
1, 3, 5, 7
DESCRIPTION
Configures DDC rail ID
Reserved
Reserved
Identifies the number of devices in a current sharing rail. 1-stand-alone;
3-two devices; 5-three devices; 7-four devices
POWER_GOOD_DELAY (D4h)
Definition: Sets the delay applied between the output exceeding the PG threshold (POWER_GOOD_ON) and asserting the PG pin. The
delay time can range from 0ms up to 500s, in steps of 125ns. A 1ms minimum configured value is recommended to apply proper
debounce to this signal.
Data Length in Bytes: 2
Data Format: L11
Type: R/W
Default Value: C300h, 3ms
Units: ms
Range: 0 to 5s
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ASCR_CONFIG (DFh)
Definition: Allows user configuration of ASCR settings. ASCR gain is analogous to bandwidth, ASCR residual is analogous to damping.
To improve load transient response performance, increase ASCR gain. To lower transient response overshoot, increase ASCR residual.
Increasing ASCR gain can result in increased PWM jitter and should be evaluated in the application circuit. Excessive ASCR gain can
lead to excessive output voltage ripple. Increasing ASCR residual to improve transient response damping can result in slower recovery
times, but will not affect the peak output voltage deviation. Typical ASCR gain settings range from 50 to 1000, and ASCR residual
settings range from 10 to 100.
Data Length in Bytes: 4
Data Format: CUS
Type: R/W
Default Value: Pin-strap setting
BIT
31:25
24
PURPOSE
DATA Format
Unused
ASCR Enable
BIT
VALUE
DESCRIPTION
0000000h
Unused
1
Enable
0
Disable
23:16
ASCR Residual Setting
Integer
ASCR residual
15:0
ASCR Gain Setting
Integer
ASCR gain
SEQUENCE (E0h)
Definition: Identifies the Rail DDC ID of the prequel and sequel rails when performing multi-rail sequencing. The device will enable its
output when its EN or OPERATION enable states, as defined by ON_OFF_CONFIG, is set and the prequel device has issued a Power-good
event on the DDC bus. The device will disable its output (using the programmed delay values) when the sequel device has issued a
Power-down event on the DDC bus.
The data field is a two-byte value. The most significant byte contains the 5-bit Rail DDC ID of the prequel device. The least-significant
byte contains the 5-bit Rail DDC ID of the sequel device. The most significant bit of each byte contains the enable of the prequel or
sequel mode. This command overrides the corresponding sequence configuration set by the CONFIG pin settings.
Data Length in Bytes: 2
Data Format: BIT
Type: R/W
Default Value: 0000h (Prequel and Sequel disabled)
BIT
15
FIELD NAME
Prequel Enable
14:13
Reserved
12:8
Prequel Rail DDC ID
7
Sequel Enable
6:5
Reserved
4:0
Sequel Rail DDC ID
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VALUE
SETTING
0
Disable
Disable, no prequel preceding this rail.
DESCRIPTION
1
Enable
Enable, prequel to this rail is defined by bits 12:8.
0
Reserved
Reserved
0-31
DDC ID
Set to the DDC ID of the prequel rail.
0
Disable
Disable, no sequel following this rail.
1
Enable
Enable, sequel to this rail is defined by bits 4:0.
0
Reserved
0-31
DDC ID
Reserved
Set to the DDC ID of the sequel rail.
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ISL8273M
DDC_GROUP (E2h)
Definition: This command configures fault spreading group ID and enable, broadcast OPERATION group ID and enable and broadcast
VOUT_COMMAND group ID and enable.
Data Length in Bytes: 3
Data Format: BIT
Type: Block R/W
Default Value: Pin-strap setting (Ignore BROADCAST VOUT_COMMAND, OPERATION and fault for stand-alone operation. Enable
BROADCAST VOUT_COMMAND, OPERATION and fault for current sharing)
BITS
23:22
21
20:16
15:14
PURPOSE
VALUE
DESCRIPTION
Reserved
0
Reserved
BROADCAST_VOUT_COMMAND Response
1
Responds to BROADCAST_VOUT_COMMAND with same Group ID.
0
Ignores BROADCAST_VOUT_COMMAND.
BROADCAST_VOUT_COMMAND Group ID
0-31d
Group ID sent as data for broadcast BROADCAST_VOUT_COMMAND events.
Reserved
0
Reserved
13
BROADCAST_OPERATION Response
1
Responds to BROADCAST_OPERATION with same Group ID.
0
Ignores BROADCAST_OPERATION.
12:8
BROADCAST_OPERATION Group ID
0-31d
7:6
Reserved
0
Reserved
POWER_FAIL Response
1
Responds to POWER_FAIL events with same Group ID by shutting down
immediately.
0
Responds to POWER_FAIL events with same Group ID with sequenced shutdown.
5
4:0
Group ID sent as data for broadcast BROADCAST_OPERATION events.
POWER_FAIL group ID
0-31d
Group ID sent as data for broadcast POWER_FAIL events.
DEVICE_ID (E4h)
Definition: Returns the 16-byte (character) device identifier string.
Data Length in Bytes: 16
Data Format: ASC
Type: Block Read
Default Value: Part number/Die revision/Firmware revision
MFR_IOUT_OC_FAULT_RESPONSE (E5h)
Definition: Configures the IOUT overcurrent fault response as defined by the following table. The command format is the same as the
PMBus standard fault responses except that it sets the overcurrent status bit in STATUS_IOUT.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable, and no retry)
Units: N/A
BIT
FIELD NAME
7:6
Reserved
VALUE
DESCRIPTION
10
000
001-110
No retry. The output remains disabled until the fault is cleared.
Not used.
5:3
Retry Setting
111
Attempts to restart continuously, without checking if the fault is still present, until it is
commanded OFF (by the CONTROL pin or OPERATION command), bias power is removed,
or another fault condition causes the unit to shut down.
2:0
Retry Delay
000-111
Retry delay time = (Value + 1)*35ms. Sets the time between retries in 35ms increments.
Range is 35ms to 280ms.
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MFR_IOUT_UC_FAULT_RESPONSE (E6h)
Definition: Configures the IOUT undercurrent fault response as defined by the following table. The command format is the same as the
PMBus standard fault responses except that it sets the undercurrent status bit in STATUS_IOUT.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: 80h (Disable and no retry)
Units: N/A
BIT
FIELD NAME
VALUE
7:6
Reserved
10
000
001-110
DESCRIPTION
No retry. The output remains disabled until the fault is cleared.
Not used.
5:3
Retry Setting
111
Attempts to restart continuously, without checking if the fault is still present, until it is
commanded OFF (by the CONTROL pin or OPERATION command), bias power is removed,
or another fault condition causes the unit to shut down.
2:0
Retry Delay
000-111
Retry delay time = (Value + 1)*35ms. Sets the time between retries in 35ms increments.
Range is 35ms to 280ms.
SYNC_CONFIG (E9h)
Definition: This command is used to set options for SYNC output configurations.
Data Length in Bytes: 1
Data Format: BIT
Type: R/W
Default Value: Pin-strap setting
SETTINGS
ACTIONS
00h
Use Internal clock. Clock frequency is set by pin-strap or PMBus command.
02h
Use internal clock and output internal clock.
04h
Use external clock.
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SNAPSHOT (EAh)
Definition: The SNAPSHOT command is a 32-byte read-back of parametric and status values. It allows monitoring and status data to be
stored to flash following a fault condition. In case of a fault, last updated values are stored to the flash memory. When SNAPSHOT
STATUS bit is set stored, device will no longer automatically capture parametric and status values following fault till stored data are
erased. Use SNAPSHOT_CONTROL command to erase store data and clear the status bit before next ramp up. Data erased is not
allowed when module is enabled.
Data Length in Bytes: 32
Data Format: Bit field
Type: Block Read
BYTE NUMBER
31:23
VALUE
PMBUS COMMAND
FORMAT
Reserved
Reserved
00h
22
Flash Memory Status Byte
FF - Not Stored
00 - Stored
N/A
BIT
21
Manufacturer Specific Status Byte
STATUS_MFR_SPECIFIC (80h)
Byte
20
CML Status Byte
STATUS_CML (7Eh)
Byte
19
Temperature Status Byte
STATUS_TEMPERATURE (7Dh)
Byte
18
Input Status Byte
STATUS_INPUT (7Ch)
Byte
17
IOUT Status Byte
STATUS_IOUT (7Bh)
Byte
16
VOUT Status Byte
STATUS_VOUT (7Ah)
Byte
15:14
Switching Frequency
READ_FREQUENCY (95h)
L11
13:12
Reserved
Reserved
00h
11:10
Internal Temperature
READ_INTERNAL_TEMP (8Dh)
L11
9:8
Duty Cycle
READ_DUTY_CYCLE (94h)
L11
7:6
Highest Measured Output Current
N/A
L11
5:4
Output Current
READ_IOUT (8Ch)
L11
3:2
Output Voltage
READ_VOUT (8Bh)
L16u
1:0
Input Voltage
READ_VIN (88h)
L11
BLANK_PARAMS (EBh)
Definition: Returns a 16-byte string indicating which parameter values were either retrieved by the last RESTORE operation or have
been written since that time. Reading BLANK_PARAMS immediately after a restore operation allows the user to determine which
parameters are stored in that store. A one indicates the parameter is not present in the store and has not been written since the
RESTORE operation.
Data Length in Bytes: 16
Data Format: BIT
Type: Block Read
Default Value: FF…FFh
SNAPSHOT_CONTROL (F3h)
Definition: Writing a 01h will cause the device to copy the current Snapshot values from NVRAM to the 32-byte Snapshot command
parameter. Writing a 02h will cause the device to write the current Snapshot values to NVRAM, 03h will erase all Snapshot values from
NVRAM. Write (02h) and Erase (03h) may only be used when the device is disabled. All other values will be ignored.
Data Length in Bytes: 1
Data Format: Bit field
Type: R/W byte
VALUE
DESCRIPTION
01h
Read Snapshot values from NV RAM
02h
Write Snapshot values to NV RAM
03h
Erase Snapshot values stored in NV RAM.
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RESTORE_FACTORY (F4h)
Definition: Restores the device to the hard coded factory default values and pin-strap definitions. The device retains the DEFAULT and
USER stores for restoring. Security level is changed to Level 1 following this command.
Data Length in Bytes: 0
Data Format: N/A
Type: Send byte
Default Value: N/A
Units: N/A
MFR_VMON_OV_FAULT_LIMIT (F5h)
Definition: Reads the VMON OV fault threshold.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Default Value: CB00h (6V)
Units: V
Range: 4V to 6V
MFR_VMON_UV_FAULT_LIMIT (F6h)
Definition: Reads the VMON UV fault threshold
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Default Value: CA00h (4V)
Units: V
Range: 4V to 6V
MFR_READ_VMON (F7h)
Definition: Reads the VMON voltage.
Data Length in Bytes: 2
Data Format: L11
Type: Read only
Default Value: N/A
Units: V
Range: 4V to 6V
VMON_OV_FAULT_RESPONSE (F8h)
Definition: Reads the VMON OV fault response
Data Length in Bytes: 1
Data Format: BIT
Type: Read only
Default Value: 80h (Disable and no retry)
Units: N/A
VMON_UV_FAULT_RESPONSE (F9h)
Definition: Reads the VMON UV fault response, which is a direct copy of VIN_UV_FAULT_RESPONSE
Data Length in Bytes: 1
Data Format: BIT
Type: Read only
Default Value: 80h (Disable and no retry)
Units: V
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ISL8273M
Datasheet Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
September 10, 2015
FN8704.1
-Updated text on page 1.
-Added a paragraph under “Soft-Start, Stop Delay and Ramp Times” on page 16 to explain the internal start-up
procedure after power is applied to the VDD pin.
-Updated command description for VOUT_COMMAND, “This command cannot set a value higher than
VOUT_MAX.”
-Updated the range for commands TON_DELAY and TOFF_DELAY on page 36 to “0ms to 256ms”.
June 11, 2015
FN8704.0
Initial Release
Firmware Revision History
TABLE 10. ISL8273M NOMENCLATURE GUIDE
FIRMWARE REVISION CODE
CHANGE DESCRIPTION
ISL8273-000-FC01
NOTE
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN8704.1
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Package Outline Drawing
Y58.18x23
58 I/O 18mmx23mmx7.5mm CUSTOM HDA MODULE
Rev 0, 8/14
18.00
A
DATUM A
B
18 17 16 1514 13 12 1110 9 8 7 6 5 4 3 2 1
TERMINAL #A1
INDEX AREA
(9x11.5)
50
12.00
23.00
0.40 REF
DATUM B
ISL8273M
0.10 C 2X
0.10 M C A B
22.60 ± 0.15
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
PIN A1 INDICATOR
C = 0.35
SEE DETAIL A
16.00
0.10 C 2X
17.20
TOP VIEW
0.10
M C AB
BOTTOM VIEW
7.50 MAX
0.10 C
2
0.20 REF
1.00
0.20 REF
SEATING PLANE
0.08 C
C
MAX 0.025
SIDE VIEW
NOTES:
FN8704.1
September 10, 2015
1.
All dimensions are in millimeters.
2.
Represents the basic land grid pitch.
3.
These 42 I/Os are centered in a fixed row and column matrix
at 1.0mm pitch BSC.
4.
Dimensioning and tolerancing per ASME Y14.5-2009.
5.
Tolerance for exposed PAD edge location dimension on
page 3 is ±0.1mm.
3
42 x 0.60 ± 0.05
42 x 0.60 ± 0.05
0.10 C A B
3
0.05 C
1.00
TERMINAL TIP
DETAIL A
2
8.20
8.80
6.80
7.20
7.80
5.80
6.20
4.20
4.80
5.20
3.20
3.80
2.20
2.80
0.50
1.20
1.80
0.80
0.20
2.80
2.20
1.80
1.20
0.50
0.20
0.80
4.20
3.80
3.20
6.20
5.20
4.80
1.00 (2X)
5.80
8.80
8.00 (2X)
7.20
7.80
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8.40 (2X)
11.30
11.30
1.60 (2X)
51
4.80 (2X)
8.70
2.60
9.70
9.30
9.10
9.70 9.30
9.10
7.70
6.70
6.50 6.30
5.50 5.70
4.70 5.30
4.30
3.70
3.30
2.70
2.00 2.30
1.70
1.30
0.70
0.30
0.30
0.70
1.30
1.70
2.30
2.70 2.90
3.30
4.00
7.70
6.70 7.30
6.30 6.50
5.70 5.50
5.30
4.70
6.00
6.00 6.30
7.30
4.40
3.50 (2X)
4.60
2.30
1.30
1.60 (2X)
3.40
3.60
2.20
1.10
1.10 (2X)
4.40
0.00
1.00
2.30
5.00 (2X)
8.10
8.10
9.30
9.30
2.00 (2X)
1.60 (2X)
9.70
11.30
SIZE DETAILS FOR THE 16 EXPOSED PADS
TERMINAL AND PAD EDGE DETAILS
FN8704.1
September 10, 2015
BOTTOM VIEW
8.60
6.00
6.40 6.50
5.20
4.40
3.60
2.40
2.00
1.80
1.20 0.80
0.20
0.40 0.00
4.60
3.00
2.60
0.60
3.80
6.40
8.60
5.60
5.40
6.20
7.40
7.00
7.20
5.60
2.20
6.60
11.30
4.00 (2X)
1.40 (2X)
2.90
4.00
0.80 (2X)
5.30 (2X)
0.70
5.10
4.20
2.10 (2X)
2.00
1.30
8.50
9.70
ISL8273M
1.00 (2X)
4.30
3.70
8.90
9.73
1.57
2.17
2.77
3.37
3.97
4.57
5.16
5.74
6.20
6.37
8.03
1.09
1.71
2.30
2.86
3.44
4.01
4.59
5.17
5.77
6.30
6.97
7.59
8.21
10.50
8.44
9.00
7.37
8.00
7.16
7.00
6.00
6.00
4.50
5.00
3.75
4.00
3.10
3.00
2.00
1.00
1.00
0.00
1.00
0.00
1.65
2.00
1.00
3.53
3.53
4.55
6.56
6.56
7.54
7.54
8.46
8.46
9.34
9.34
10.73
FN8704.1
September 10, 2015
STENCIL OPENING CENTER POSITION (FOR REFERENCE)
3.00
4.55
6.91
7.99
8.90
9.76
10.50 10.74
ISL8273M
6.93
0.50
2.60
0.79
4.90
1.41
8.97
7.30
6.24
5.18
4.12
0.50
0.71
1.00
1.57
2.43
3.06
1.95
1.00
3.50
.
2.50
4.50
5.50
7.30
6.70
8.30
C = 0.35mm
2.03
52
8.12
7.31
6.49
5.68
5.28
4.87
4.43
3.68
2.88
8.30
6.70
5.50
0.95
1.50
2.00
2.50
3.29
3.50
4.13
4.50
0.50
2.00
1.50
3.06
4.12
5.18
6.24
7.10
8.20
Submit Document Feedback
8.18
7.50
6.82
6.08
5.63
5.03
4.48
3.83
3.23
2.80
2.63
Stencil opening center position
10.50
8.97
7.37
7.16
7.00
5.90
4.90
3.75
2.60
Stencil opening edge
9.85
9.29
8.72
8.10
6.65
6.60
6.29
5.40
5.13
4.72
4.25
3.73
3.10
2.10
2.15
4.00
4.95
6.45
7.13
11.15
9.00
9.70
8.25
7.73
7.72
6.53
5.72
5.29
4.40
3.88
3.25
2.48
1.15
3.05
4.15
6.15
6.98
7.40
7.95
8.65
8.98
9.30
9.70
10.15
53
4.05
3.60
3.35
3.00
7.55
8.10
8.50
8.83
9.15
9.85
10.30
11.15
Submit Document Feedback
8.65
7.92
7.79
7.77
7.75
7.23
6.97
6.55
6.16
5.85
5.60
5.35
5.25
4.95
4.80
4.55
8.70
8.45
7.90
7.75
7.10
7.64
7.55
7.08
6.82
6.65
6.40
6.01
5.75
5.40
5.20
4.65
4.20
4.15
4.00
3.45
3.20
2.85
6.30
5.22
4.22
3.79
3.52
2.79
2.55
2.25 2.40
2.15
1.65 1.80
2.22
1.33
1.35
1.48
1.93
2.08
2.40
2.55
2.79
3.00
3.08
3.15
3.60
3.75
4.20
4.23
4.35
4.80
5.38
5.40
5.95
6.10
6.15
6.60
6.85
7.20
7.82
1.15
0.60
0.55
0.30
0.35
0.70
0.85
1.06
1.21
0.15
0.30
0.60
1.22
1.55
1.60
1.79
2.46
1.80
1.95
2.10
2.50
2.65
2.94
2.79
3.23
3.65
3.80
3.52
3.79
4.38
4.45
4.95
4.58
4.78
5.22
4.79
4.73
4.58
3.67
3.22
2.61
2.60
2.46
1.79
1.55
1.40
1.30
1.22
0.79
0.22
0.22
0.79
1.40
2.22
2.61
3.22
3.67
4.21
5.53
5.55
6.00
5.78
5.79
6.50
6.75
6.69
7.10
7.35
7.90
7.97
8.45
4.73
5.63
6.30
6.84
7.75
8.70
11.15
9.70
8.29
8.10
7.73
6.72
6.60
5.72
5.28
4.40
3.72
3.29
3.10
2.29
1.29
0.29
0.29
0.72
1.72
2.72
4.15
6.15
7.38
7.95
8.45
8.83
9.20
9.85
9.85
9.00
8.25
7.88
6.65
6.29
5.40
4.29
4.25
3.25
2.72
2.10
0.72
1.29
2.29
3.29
4.95
6.45
6.98
7.53
8.10
8.60
8.98
9.70
11.15
FN8704.1
September 10, 2015
STENCIL OPENING EDGE POSITION (FOR REFERENCE)
ISL8273M
1.03 1.18
6.84
6.79
6.69
6.22
5.79
5.63
7.80
8.80
6.20
7.20
5.20
5.80
4.20
4.80
3.20
3.80
.2.20
.
2.80
0.50
0.20
0.80
0.80
0.20
0.50
1.20
1.80
1.80
1.20
3.20
2.80
2.20
4.80
4.20
3.80
5.80
5.20
6.20
8.20
8.80
7.80
7.20
Submit Document Feedback
6.80
PCB layout pattern
11.30
11.30
54
9.70
9.30
9.10
9.70
9.30
9.10
7.70
6.70
6.50 6.30
5.70
5.50
5.30
4.70
4.30
3.70
2.00
1.30
0.70
0.00
1.00
2.30
2.90
4.00
5.10
5.10
6.00
6.00
8.10
8.10
8.50
8.50
9.30
9.30
9.70
9.70
PCB LAND PATTERN (FOR REFERENCE)
8.60
6.60
7.00
5.40
4.60
3.80
3.00
2.60
0.80
0.20
1.20
0.00
0.40
1.80
2.00
2.40
3.60
4.40
5.20
6.40
FN8704.1
September 10, 2015
8.60
6.00
11.30
6.50
11.30
ISL8273M
7.70
7.30
6.70
6.30 6.50
5.70
5.50
5.30
4.70
4.30
3.70
3.30
2.70
2.30
2.00
1.70
1.30
0.70
0.30
0.30
0.70
1.30
1.70
2.30
2.90 2.70
3.30
4.00
7.30
6.30
8.70