User Guide 037 ISL71841SEHEV1Z Evaluation Board User Guide Description Key Features The ISL71841SEH is a radiation hardened, 32-channel high ESD protected multiplexer that is fabricated using Intersil’s proprietary P6SOI (Silicon On Insulator) process technology to mitigate single-event effects and total ionizing dose. It operates with a dual supply voltage ranging from ±10.8V to ±16.5V. This evaluation board is designed to provide easy access to the capabilities of the part. • Jumper selectable input source for each input The evaluation board has a set of toggle switches, which provides a convenient way to address all 32 channels without the need for extra supplies. There’s also a BNC input available that will allow you to drive the address pins with a signal generator. Specifications This board has been configured and optimized for the following operating conditions: • Toggle switches to conveniently select 1 of 32 channels • BNC input for dynamic addressing • Multiple loading options with jumpers on VOUT • Convenient power connection • On-board enable switch References ISL71841SEH Datasheet Ordering Information PART NUMBER ISL71841SEHEV1Z DESCRIPTION Evaluation board for the ISL71841SEH • V+ = +10.8V to +16.5V • V- = -10.8V to -16.5V • VREF = 4.5V to 5.5V EVALUATION BOARD ISL71841SEH IN01 IN02 IN03 . . . OUT ADC IN32 SIGNAL GENERATOR INPUT 5 ADDRESS VREF EN BUS WIR E A0 A1 A2 A3 A4 FIGURE 1. ISL71841SEHEV1Z BLOCK DIAGRAM June 16, 2015 UG037.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. User Guide 037 ISL71841SEHEV1Z Evaluation Board FIGURE 2. TOP SIDE FIGURE 3. BOTTOM SIDE Submit Document Feedback 2 UG037.0 June 16, 2015 User Guide 037 Operating Range PCB Layout Guidelines This board has power supply inputs for V+, V- and VREF. There’s no requirements for sequencing on these supplies, but it is recommended that the supplies come up relatively at the same time. In-line resistors are provided to V+ and V- with decoupling capacitors close to the part for V+, V- and VREF. The in-line resistors are 100Ω but can be changed by the user for additional power supply filtering or to limit the rise time of the supply voltages. The ISL71841SEHEV1Z PCB layout has been optimized for ease of testing. When incorporating the ISL71841SEH into a system there are a few guidelines that can ensure optimal electrical and noise performance. The voltage ranges for V+ is +10.8V to +16.5V and the range for V- is -10.8V to -16.5V. VREF ranges from 4.5V to 5.5V. The ISL71841SEH is a rail-to-rail mux and should be able to accommodate any input signal with a voltage level between or equal to the supplies voltages. VREF is used to set the decoder logic levels. • It is recommended to decouple the power supply pins (V+, Vand VREF) for power supply filtering. If the traces to the supply lines are long, it is recommended to use a larger 1µF capacitor at the point of entry for the supply and a smaller capacitor, like a 0.1µF, close to the part to reduce high frequency perturbations. Submit Document Feedback 3 • Analog circuits can conduct noise through paths that connect it to the “outside world”. These paths include the V+, V-, VREF, input to any switch and the output. It is important to make sure these paths are kept away from known noise sources. UG037.0 June 16, 2015 SP2 SP3 OUT D OUT V1 D V2 TP17 TP9 J21 J18 R3 DNP C6 TP10 100PF C5 VOUT SP1 1UF J1 C1 J20 TP1 1UF Submit Document Feedback ISL71841SEHEV1Z Circuit Schematic V1 D D D J2 1 D D V2 IN IN D 2 3 1 2 3 1 J29 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 TP2 1 44 45 46 47 43 IN29 IN30 IN31 IN20 IN19 IN2 IN18 IN1 1 35 1 34 33 1 32 31 1 1 1 V+ D 10K TP16 J22 1 1 EN 2 2 A4 3 3 J24 A3 4 4 J25 A2 5 5 A1 6 6 A0 7 7 GND 8 8 J23 UG037.0 June 16, 2015 EN 1 SW6 DRAWN BY: D D D D 49.9K D D 3 A4 SW5 1 3 A3 1 SW4 3 A2 SW3 1 3 A1 SW2 3 3 A0 1 1 J27 TP8 D J28 J26 1UF C4 IN R9 A0 J19 SW1 C3 1UF OUT J44 10K TP15 VREF J43 R8 A1 D TP7 J42 VREF R7 TP14 TP4 D J41 10K R10 1UF C2 10K A2 TP6 J40 R6 A3 OUT J39 R5 TP13 V- J38 10K TP12 OUT 10 J37 R4 A4 V+ R2 J36 10K TP11 TP5 J35 VREF EN 10 J34 IN IN TP3 J33 V- IN R1 J32 36 V- GND IN17 1 30 3 18 ISL71841SEH IN3 EN_B 3 2 IN32 IN4 17 2 48 15 29 J17 1 IN21 28 1 IN23 IN22 IN5 NC J16 NC 3 37 IN6 NC 2 38 IN7 1 J31 40 IN24 14 16 41 39 13 27 J15 1 1 3 NC 2 U1 IN8 1 42 IN25 12 A4 J14 1 IN26 IN9 26 3 IN10 25 2 IN27 V+ J13 1 11 2 3 IN28 IN11 19 J12 1 10 OUT 2 9 J11 1 1 IN12 A3 3 8 3 2 7 NC 3 A2 2 24 3 4 2 1 5 3 IN16 3 2 J30 User Guide 037 2 23 J10 1 3 IN15 J9 1 2 A1 J8 1 1 A0 1 1 3 22 J7 3 2 6 J6 1 2 IN13 J5 1 IN14 1 VREF J4 21 4 D 20 J3 1 D D TIM KLEMANN ENGINEER: FIGURE 4. ISL71841SEHEV1Z SCHEMATIC DATE: 11/11/2013 DRAWING TITLE ISL71841SEH 32CH ANALOG MULTIP User Guide 037 Bill of Materials ITEM QTY REFERENCE DESIGNATOR VALUE TOL (%) RATING TYPE PCB FOOTPRINT MANUFACTURER PART NUMBER 1 1 C6 100pF 5% 100V X7R 0805 AVX 08051C101JAT4A 2 3 SP1-SP3 - - - - CONN TEKTRONIX 131-4353-00 3 17 TP1-TP17 - - - - THOLE KEYSTONE 1514-2 4 1 J28 - - - - CONN AMPHENOL 31-5329-52RFX 5 1 J19 - - - - IN-LINE Generic CONN-1X8 6 5 C1-C5 1µF 10% 50V X7R 0805 MURATA GRM21BR71H105KA12L 7 6 SW1-SW6 - - - - SPST C&K GT12MSCBETR 8 1 R3 DNP 1% DNP - 0805 GENERIC H2506-DNP-DNP-1 9 6 R4-R9 10k 1% 1/10W - 0603 GENERIC H2511-01002-1/10W1 10 1 R10 49.9k 1% 1/16W - 0603 GENERIC H2511-04992-1/16W1 11 2 R1, R2 10 1% 1/10W - 0805 GENERIC H2512-00100-1/10W1 12 1 U1 - - - - CQFP INTERSIL ISL71841SEHF/PROTO 13 32 J2-J17, J29-J44 - - - - THOLE GENERIC JUMPER-3-100 14 10 J1, J18, J20-J27 - - - - THOLE GENERIC JUMPER2_100 MANUFACTURER Board Layout - 4 Layers FIGURE 5. SILKSCREEN TOP Submit Document Feedback 5 UG037.0 June 16, 2015 User Guide 037 Board Layout - 4 Layers (Continued) FIGURE 6. TOP LAYER FIGURE 7. PCB – INNER LAYER 1 (TOP VIEW) Submit Document Feedback 6 UG037.0 June 16, 2015 User Guide 037 Board Layout - 4 Layers (Continued) FIGURE 8. PCB – INNER LAYER 2 (TOP VIEW) FIGURE 9. PCB – BOTTOM LAYER (TOP VIEW) Submit Document Feedback 7 UG037.0 June 16, 2015 User Guide 037 Board Layout - 4 Layers (Continued) FIGURE 10. SILKSCREEN BOTTOM Typical Performance Curves Unless otherwise noted: V+ = +15V, V- = -15V, VREF = 5.0V, TA = +25°C 600 600 400 500 +125°C +125°C +25°C rDS(ON) (Ω) rDS(ON) (Ω) 500 300 200 100 0 -15 +25°C 300 200 100 -55°C -10 400 -55°C -5.0 0 5.0 SWITCH INPUT VOLTAGE (V) 10 15 FIGURE 11. rDS(ON) vs SWITCH INPUT VOLTAGE (V± = ±12.0V) Submit Document Feedback 8 0 -20 -15 -10 -5.0 0 5.0 10 15 20 SWITCH INPUT VOLTAGE (V) FIGURE 12. rDS(ON) vs SWITCH INPUT VOLTAGE (V± = ±15.0V) UG037.0 June 16, 2015 User Guide 037 Typical Performance Curves Unless otherwise noted: V+ = +15V, V- = -15V, VREF = 5.0V, TA = +25°C (Continued) 5V/DIV 5V/DIV 1V/DIV 2V/DIV tADDLH = 211.199ns tADDHL = 561.469ns tDISABLE = 202.207ns 500ns/DIV FIGURE 13. TYPICAL ADDRESS TO OUTPUT DELAY (V± = ±15V, +25°C) tENABLE = 352.379ns 500ns/DIV FIGURE 14. TYPICAL ENABLE TO OUTPUT DELAY (V± = ±15V, +25°C) 120 2V/DIV 1V/DIV OFF ISOLATION (dB) 100 80 60 40 20 0 10 tBBM = 73.425ns 200ns/DIV FIGURE 15. TYPICAL BREAK BEFORE MAKE DELAY (V± = 15V, +25°C) 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 16. OFF ISOLATION (V± = ±15V, +25°C) Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the document is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 9 UG037.0 June 16, 2015