User Guide 028 ISL71840SEHEV1Z Evaluation Board User Guide Description Key Features The ISL71840SEH is a radiation hardened, 16-channel high ESD protected multiplexer that is fabricated using Intersil’s proprietary P6SOI (Silicon On Insulator) process technology to mitigate single-event effects and total ionizing dose. It operates with a dual supply voltage ranging from ±10.8V to ±16.5V. “This evaluation board is designed to provide easy access to the capabilities of the part.” • Jumper selectable input source for each input • DIP switch to conveniently select 1 of 16 channels • BNC input for dynamic addressing • Multiple loading options with jumpers on VOUT • Convenient power connection • On-board enable switch The evaluation board has a DIP switch, which provides a convenient way to address all 16 channels without the need for extra supplies. There’s also a BNC input available that will allow you to drive the address pins with a signal generator. References ISL71840SEH Datasheet Specifications Ordering Information This board has been configured and optimized for the following operating conditions: PART NUMBER ISL71840SEHEV1Z DESCRIPTION Evaluation board for the ISL71840SEH • V+ = +10.8V to +16.5V • V- = -10.8V to -16.5V • VREF = 4.5V to 5.5V EVALUATION BOARD ISL71840SEH IN01 IN02 IN03 . . . OUT ADC IN16 SIGNAL GENERAT OR INPUT 4 VREF ADDRESS EN BUS WIRE A0 A1 A2 A3 FIGURE 1. ISL71840SEHEV1Z BLOCK DIAGRAM April 16, 2015 UG028.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. User Guide 028 ISL71840SEHEV1Z Evaluation Board FIGURE 2. TOP SIDE FIGURE 3. BOTTOM SIDE Power Supplies PCB Layout Guidelines This board has power supply inputs for V+, V- and VREF. There’s no requirements for sequencing on these supplies, but it is recommended that the supplies come up relatively at the same time. In-line resistors are provided to V+ and V- with decoupling capacitors close to the part for V+, V- and VREF. The in-line resistors are 100Ω but can be changed by the user for additional power supply filtering or to limit the rise time of the supply voltages. The ISL71840SEHEV1Z PCB layout has been optimized for ease of testing. When incorporating the ISL71840SEH into a system there are a few guidelines that can ensure optimal electrical and noise performance. The voltage ranges for V+ is +10.8V to +16.5V and the range for V- is -10.8V to -16.5V. VREF ranges from 4.5V to 5.5V. The ISL71840SEH is a rail-to-rail mux and should be able to accommodate any input signal with a voltage level between or equal to the supplies voltages. VREF is used to set the decoder logic levels. • It is recommended to decouple the power supply pins (V+, Vand VREF) for power supply filtering. If the traces to the supply lines are long, it is recommended to use a larger 1µF capacitor at the point of entry for the supply and a smaller capacitor, like a 0.1µF, close to the part to reduce high frequency perturbations. Submit Document Feedback 2 • Analog circuits can conduct noise through paths that connect it to the “outside world”. These paths include the V+, V-, VREF, input to any switch and the output. It is important to make sure these paths are kept away from known noise sources. UG028.0 April 16, 2015 SP3 +V P11 1 2 3 D 1 1 J6 J7 2 2 3 3 13 27 3 P3 IN 4 IN 5 IN 6 IN 7 IN 8 IN 9 IN 10 VREF R5 GND P8 IN 11 IN 12 D IN 13 IN 14 DECODER/ IN 15 D D DRIVER IN 16 IN VREF LEVEL SHIFT -V SUPPLY R6 R7 R8 R9 R10 10K 10K 10K 10K 10K OUT D 1 J10 2 P4 3 D GND 1 1 1 1 2 J12 2 J13 2 J14 2 J15 2 J16 2 D 3 3 3 P5 -V 1 12 EN 2 11 A3 3 10 A2 4 9 A1 5 8 A0 6 7 78B06S 10 P13 C2 R2 J18 P14 P15 P16 A3 A2 A1 EN P18 A0 GND 1UF OUT P17 J20 D J21 J22 J23 D BNC1 3 P6 3 D GND D 3 DRAWN BY: TIM KLEMANN 49.9 1 J11 R11 1 VREF SW1 12 3 P7 IN 3 GND C3 2 28 IN 2 1UF 1 J9 2 OUT IN 1 D DATE: DATE: UPDATED BY: DATE: FIGURE 4. ISL71840SEHEV1Z SCHEMATIC ENGINEER: DATE: KIRAN BERNARD 09/20/2013 RELEASED BY: TITLE: ISL71840SEH EVALUATION BOARD User Guide 028 1 J8 DNP 1UF 19 20 21 22 23 24 25 26 11 10 9 8 7 6 5 4 3 D 1 J26 J5 2 D +V SUPPLY D R4 1 1UF U1 D DNP 3 GND P10 J4 D J25 D J3 C6 C5 P12 1 C4 3 C1 100PF 2 SP1 GND ISL71840SEHVF 3 VOUT P2 J24 2 J17 GND A3 1 J2 10 3 A2 J19 2 R1 A1 1 P9 J1 A0 D P1 V2 D 17 16 15 14 18 V1 EN SP2 1UF Submit Document Feedback ISL71840SEHEV1Z Circuit Schematic UG028.0 April 16, 2015 User Guide 028 Bill of Materials REFERENCE ITEM QTY DESIGNATOR VALUE TOL (%) RATING TYPE PCB FOOTPRINT MANUFACTURER MANUFACTURER PART NUMBER 1 1 C4 100pF 5 50V X7R 0805 PANASONIC ECU-V1H101JCG 2 5 C1, C2, C3, C5, C6 1µF 10 25V X7R 0805 AVX 3 2 R4, R5 DNP 1 DNP 0805 GENERIC 4 2 R1, R2 10Ω 1 1/10W 0805 VENKEL CR0805-8W-10R0FT 5 5 R6, R7, R8, R9, R10 10KΩ 1 1/10W 0805 VENKEL CR0805-8W-1002FT(Pb-free) 6 1 R11 49.9Ω 1 1/10W 0805 ROHM 7 3 SP1-SP3 CONN TEKTRONIX 131-4353-00 8 18 P1-P18 THOLE KEYSTONE 1514-2 9 1 BNC1 CONN AMPHENOL 31-5329-51RFX 10 1 SW1 DIP GRAYHILL 78B06S 11 1 U1 28CDFP INTERSIL ISL71840SEH/PROTO 12 16 J1-J16 THOLE BERG/FCI 68000-236HLF 13 10 J17-J26 BERG/FCI 69190-202HLF 14 4 Bottom four corners 3M 08053C105KAT2A MCR10EZHF49R9 SJ-5003SPBL Board Layout - 4 Layers FIGURE 5. SILKSCREEN TOP Submit Document Feedback 4 UG028.0 April 16, 2015 User Guide 028 Board Layout - 4 Layers (Continued) FIGURE 6. TOP LAYER FIGURE 7. PCB – INNER LAYER 1 (TOP VIEW) Submit Document Feedback 5 UG028.0 April 16, 2015 User Guide 028 Board Layout - 4 Layers (Continued) FIGURE 8. PCB – INNER LAYER 2 (TOP VIEW) FIGURE 9. PCB – BOTTOM LAYER (TOP VIEW) Submit Document Feedback 6 UG028.0 April 16, 2015 User Guide 028 Board Layout - 4 Layers (Continued) FIGURE 10. SILKSCREEN BOTTOM Typical Performance Curves Unless otherwise noted: V+ = +15V, V- = -15V, VREF = 5.0V, TA = +25°C 600 600 400 500 +125°C +125°C +25°C rDS(ON) (Ω) rDS(ON) (Ω) 500 300 200 100 0 -15 +25°C 300 200 100 -55°C -10 400 -55°C -5.0 0 5.0 SWITCH INPUT VOLTAGE (V) 10 15 FIGURE 11. rDS(ON) vs SWITCH INPUT VOLTAGE (V± = ±12.0V) Submit Document Feedback 7 0 -20 -15 -10 -5.0 0 5.0 10 15 20 SWITCH INPUT VOLTAGE (V) FIGURE 12. rDS(ON) vs SWITCH INPUT VOLTAGE (V± = ±15.0V) UG028.0 April 16, 2015 User Guide 028 Typical Performance Curves Unless otherwise noted: V+ = +15V, V- = -15V, VREF = 5.0V, TA = +25°C (Continued) 5V/DIV 5V/DIV 1V/DIV 2V/DIV tADDLH = 211.199ns tADDHL = 561.469ns tDISABLE = 202.207ns 500ns/DIV FIGURE 13. TYPICAL ADDRESS TO OUTPUT DELAY (V± = ±15V, +25°C) tENABLE = 352.379ns 500ns/DIV FIGURE 14. TYPICAL ENABLE TO OUTPUT DELAY (V± = ±15V, +25°C) 120 2V/DIV 1V/DIV OFF ISOLATION (dB) 100 80 60 40 20 0 10 tBBM = 73.425ns 200ns/DIV FIGURE 15. TYPICAL BREAK BEFORE MAKE DELAY (V± = 15V, +25°C) 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 16. OFF ISOLATION (V± = ±15V, +25°C) Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the document is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 8 UG028.0 April 16, 2015