ISL78600 Data Short

DATASHEET
To request the full datasheet, please visit www.intersil.com/products/isl78600
Multi-Cell Li-Ion Battery Manager
ISL78600
Features
The ISL78600 Li-ion battery manager IC supervises up to 12
series connected cells. The part provides accurate monitoring,
cell balancing and extensive system diagnostics functions. Three
cell balancing modes are incorporated: Manual Balance mode,
Timed Balance mode, and Auto Balance mode. The auto balance
mode terminates balancing functions when a charge transfer
value specified by the host microcontroller has been met.
• Up to 12-cell voltage monitors, support Li-ion CoO2, Li-ion
Mn2O4, and Li-ion FePO4 chemistries
The ISL78600 communicates to a host microcontroller via an SPI
interface and to other ISL78600 devices using a robust,
proprietary, two-wire Daisy Chain system.
• Cell voltage scan rate of 19.5µs per cell (234µs to scan
12 cells)
The ISL78600 is offered in a 64 Ld TQFP package and is
specified for operation at a temperature range of -40°C to
+105°C.
• Cell voltage measurement accuracy ±2.5mV
• 13-bit cell voltage measurement
• Pack voltage measurement accuracy ±100mV
• 14-bit pack voltage and temperature measurements
• Internal and external temperature monitoring
• Up to four external temperature inputs
• Robust Daisy Chain communications system
• Integrated system diagnostics for all key internal functions
Applications
• Hybrid Electric Vehicle (HEV), Plug-in Hybrid Electric Vehicle
(PHEV) and Electric Vehicle (EV) battery packs
• Electric motorcycle battery packs
• Backup battery and energy storage systems requiring high
accuracy management and monitoring
• Hardwired and communications based fault notification
• Integrated watchdog shuts down device if communication is
lost
• 7µA shutdown current: Enable = VSS
• 2Mbps SPI
• Portable and semiportable equipment
TO OTHER DEVICES (OPTIONAL)
ISL78600
ISL78600
VG2 VG2
VG1 VG1
DHi2
DLo2
DHi2
DHi1
DLo2
DLo1
SCLK
DOUT
DIN
CS
DATA READY
HOST
MICRO
FAULT
EN
VG1
VG1
MONITOR BOARD (Master or Stand-alone)
VG2
MONITOR BOARD (Daisy Chain - Optional)
FIGURE 1. TYPICAL APPLICATION
January 20, 2015
FN7672.6
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC. 2012-2015. All Rights Reserved
Intersil is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL78600
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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2
FN7672.6
January 20, 2015
ISL78600
Ordering Information
PART NUMBER
(Notes 1, 2, 3, 4)
PART
MARKING
TRIM VOLTAGE, VNOM
(V)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
3.3
-40 to +105
64 Ld TQFP
ISL78600ANZ
ISL78600ANZ
ISL78600/601EVAL1Z
Evaluation Board for ISL78600
PKG.
DWG. #
Q64.10x10D
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For more information on handling and processing moisture sensitive devices, please see Techbrief TB363.
4. For other trim options, please contact Intersil Automotive Marketing.
Pin Configuration
VC10
CB11
VC11
CB12
VC12
VBAT
VBAT
NC
DHi2
DLo2
NC
SCLK/DHi1
CS/DLo1
NC
DIN/NC
DOUT/NC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
ISL78600
(64 LD 10x10 TQFP)
TOP VIEW
VC4
12
37
DNC
CB4
13
36
V3P3
VC3
14
35
V2P5
CB3
15
34
VCC
VC2
16
33
REF
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3
32
BASE
VDDEXT
38
31
DNC
11
NC
39
CB5
30
VC5
29
COMMS SELECT 2
ExT4
40
10
TEMPREG
9
28
CB6
27
COMMS SELECT 1
NC
COMMS RATE 1
41
ExT3
42
8
26
7
VC6
25
CB7
NC
COMMS RATE 0
ExT2
DGND
43
24
44
6
ExT1
5
VC7
23
CB8
22
FAULT
NC
45
VSS
4
21
VC8
20
DATA READY
VC0
EN
46
VSS
47
3
19
2
CB9
18
VC9
VC1
DNC
CB1
48
17
1
CB2
CB10
FN7672.6
January 20, 2015
ISL78600
Pin Descriptions
SYMBOL
VC0, VC1, VC2, VC3, VC4,
VC5, VC6, VC7, VC8, VC9,
VC10, VC11, VC12
PIN NUMBER
DESCRIPTION
20, 18, 16, Battery cell voltage inputs. VCn connects to the positive terminal of CELLn and the negative terminal of
14, 12, 10, 8, CELLn+1. (VC12 connects only to the positive terminal of CELL12 and VC0 only connects with the negative
6, 4, 2, 64, terminal of CELL1.)
62, 60
19, 17, 15, Cell Balancing FET control outputs. Each output controls an external FET which provides a current path
CB1, CB2, CB3, CB4, CB5,
CB6, CB7, CB8, CB9, CB10, 13, 11, 9, 7, around the cell for balancing.
5, 3, 1, 63, 61
CB11, CB12
VBAT
58, 59
Main IC Supply pins. Connect to the most positive terminal in the battery string.
VSS
21, 22
Ground. These pins connect to the most negative terminal in the battery string.
ExT1, ExT2, ExT3, ExT4
24, 26, 28,
30
External temperature monitor or general purpose inputs. The temperature inputs are intended for use with
external resistor networks using NTC type thermistor sense elements but may also be used as general
purpose analog inputs at the user’s discretion. 0V to 2.5V input range.
TEMPREG
29
Temperature monitor voltage regulator output. This is a switched 2.5V output which supplies a reference
voltage to external NTC thermistor circuits to provide ratiometric ADC inputs for temperature
measurement.
VDDEXT
32
External V3P3 supply input/output. Connected to the V3P3 pin via a switch, this pin may be used to power
external circuits from the V3P3 supply. The switch is open when the ISL78600 is placed in Sleep mode.
REF
33
2.5V voltage reference decoupling pin. Connect a 2.0µF to 2.5µF X7R capacitor to VSS. Do not connect any
additional external load to this pin.
VCC
34
Analog supply voltage input. Connect to V3P3 via a 33Ω resistor. Connect a 1µF capacitor to ground.
V2P5
35
Internal 2.5V digital supply decoupling pin. Connect a 1µF capacitor to DGND.
V3P3
36
3.3V digital supply voltage input. Connect the emitter of the external NPN regulator transistor to this pin.
Connect a 1µF capacitor to DGND.
BASE
38
DNC
37, 39, 48
Regulator control pin. Connect the external NPN transistor’s base. Do not let this pin float.
COMMS SELECT 1
41
Communications port 1 mode select pin. Connect via a 1kΩ resistor to V3P3 for Daisy Chain
communications on port 1 or to DGND for SPI operation on port 1.
COMMS SELECT 2
40
Communications port 2 mode select pin. Connect via a 1kΩ resistor to V3P3 to enable port 2 or to DGND
to disable this port.
COMMS RATE 0,
COMMS RATE 1
43, 42
Daisy Chain communications data rate setting. Connect via a 1kΩ resistor to DGND (‘0’) or to V3P3 (‘1’) to
select between various communication data rates.
Do not connect. Leave pins floating.
DGND
44
Digital Ground.
FAULT
45
Logic fault output. Asserted low if a fault condition exists.
DATA READY
46
SPI data ready. Asserted low when the device is ready to transmit data to the host microcontroller.
EN
47
Enable input. Tie to V3P3 to enable the part. Tie to DGND to disable (all IC functions are turned off).
DOUT/NC
49
Serial Data Output (SPI) or NC (Daisy Chain). 0V to 3.3V push-pull output.
DIN/NC
50
Serial Data Input (SPI) or
NC (Daisy Chain). 0V to 3.3V input.
CS/DLo1
52
Chip-Select, active low 3.3V input (SPI) or Daisy Chain port 1 Lo connection.
SCLK/DHi1
53
Serial-Clock Input (SPI) or Daisy Chain port 1 Hi connection.
DHi2
56
Daisy Chain port 2 Hi connection.
DLo2
55
NC
23, 25, 27,
31, 51, 54,
57
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4
Daisy Chain port 2 Lo connection.
No internal connection.
FN7672.6
January 20, 2015
ISL78600
Block Diagram
DHI 2
DLO 2
CONTROL LOGIC AND COMMUNICATIONS
VBAT
VC12
CB12
VC11
CB11
VC10
CB10
VC9
INPUT BUFFER/LEVEL SHIFT AND FAULT DETECTION
CB9
CB8
VC7
CB7
VC6
CB6
VC5
CB5
VC4
SPI
COMMS
CS/DLO 1
DIN
DOUT
DATA READY
COMMS RATE 1
COMMS RATE 0
COMMS SELECT 2
COMMS SELECT 1
DGND
FAULT
EN
BASE
VREG
V3P3
VDDEXT
V2P5
V2P5
VCC
VREF
MUX
CB4
DAISY
CHAIN
AND
REF
VC MUX
VC8
SCLK/DHI 1
VC3
ADC
CB3
TEMPREG
VC2
TEMP MUX
IC TEMP
VC1
CB1
VC0
ExT1
ExT2
ExT3
ExT4
VSS
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REFERENCE
CB2
5
FN7672.6
January 20, 2015
ISL78600
Absolute Maximum Ratings
Thermal Information
Unless otherwise specified. With respect to VSS.
Thermal Resistance (Typical)
θJA(C/W)
θJC(C/W)
64 Ld TQFP Package (Notes 5, 6) . . . . . . .
49
9
Max Continuous Package Power Dissipation . . . . . . . . . . . . . . . . . .400mW
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Max Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . Refer to JEDEC J STD 020D
DIN, SCLK, CS, DOUT, DATA READY, COMMS SELECT n, ExTn,
TEMPREG, REF, V3P3, VCC, FAULT, COMMS RATE n,
BASE, EN, VDDEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.2V to 4.1V
V2P5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 2.9V
VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 63V
Dhi1, DLo1, DHi2, DLo2 . . . . . . . . . . . . . . . . . . . . . . .-0.5V to (VBAT + 0.5V)
VC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +9.0V
VC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +18V
VC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +18V
VC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +27V
VC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +27V
VC5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +36V
VC6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +36V
VC7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +45V
VC8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +45V
VC9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +54V
VC10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +63V
VC11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +63V
VC12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +63V
VCn (for n = 0 to 12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VBAT +0.5V
CBn (for n = 1 to 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VBAT +0.5V
CBn (for n = 1 to 9) . . . . . . . . . . . . . . . . . . . . . . . . V(VCn-1) -0.5V to V(VCn-1) +9V
CBn (for n = 10 to 12). . . . . . . . . . . . . . . . . . . . . . . . . V(VCn) -9V to V(VCn) +0.5V
Current into VCn, VBAT, VSS (Latch-up Test) . . . . . . . . . . . . . . . . . . ±100mA
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 2kV
Capacitive Discharge Model (Tested per JESD22-C101D). . . . . . . . 500V
Latch-up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Recommended Operating Conditions
TA, Ambient Temperature Range . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V to 60V
VBAT (Daisy Chain Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V to 60V
VCn (for n = 1 to 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . .V(VCn-1) to V(VCn-1) + 5V
VC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.1V to 0.1V
CBn (for n = 1 to 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V(VCn-1) to V(VCn-1) + 9V
CBn (for n = 10 to 12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V(VCn) -9V to V(VCn)
DIN, SCLK, CS, COMMS SELECT 1, COMMS SELECT 2, V3P3, VCC,
COMMS RATE 0, COMMS RATE 1, EN. . . . . . . . . . . . . . . . . . . . . . .0V to 3.6V
ExT1, ExT2, ExT3, ExT4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 2.5V
NOTE: DOUT, DATA READY, and FAULT are digital outputs and should not
be driven from external sources. V2P5, REF, TEMPREG and BASE are
analog outputs and should not be driven from external sources.
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. For JC, the “case temp” location is taken at the package top center.
Electrical Specifications
PARAMETER
VBAT = 6 to 60V, TA = -20°C to +60°C, unless otherwise specified.
SYMBOL
Power-Up Condition Threshold
VPOR
Power-Up Condition Hysteresis
VPORhys
TEST CONDITIONS
VBAT voltage (rising)
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
4.8
5.1
5.6
V
400
mV
Initial Power-Up Delay
tPOR
Time after VPOR condition
VREF from 0V to 0.95 x VREF(nom) (EN tied to V3P3)
Device can now communicate
27.125
ms
Enable Pin Power-Up Delay
tPUD
Delay after EN = 1 to VREF from
0V to 0.95 x VREF(nom)
(VBAT = 39.6V) - Device can now communicate
27.125
ms
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6
FN7672.6
January 20, 2015
ISL78600
Electrical Specifications
VBAT = 6 to 60V, TA = -20°C to +60°C, unless otherwise specified. (Continued)
PARAMETER
SYMBOL
VBAT Supply Current
IVBAT
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
Non Daisy Chain configuration. Device enabled. No communications, ADC, measurement, balancing
or open wire detection activity.
6V
7
35
80
µA
39.6V
0
64
241
µA
60V
0
90
250
µA
-40°C to +105°C (Note 9)
0
280
µA
IVBATMASTER Daisy Chain configuration – master device. Enabled. No communications, ADC, measurement,
balancing or open wire detection activity.
6V
400
530
660
µA
39.6V
500
680
900
µA
60V
550
750
1000
µA
-40°C to +105°C (Note 9)
1150
Peak current when Daisy Chain transmitting
IVBATMID
18
Daisy Chain configuration – MIDDLE stack device. Enabled. No communications, ADC,
measurement, balancing or open wire detection activity.
6V
700
1020
1210
µA
39.6V
900
1250
1560
µA
60V
1000
1400
1700
µA
-40°C to +105°C (Note 9)
1850
Peak current when Daisy Chain transmitting
IVBATTOP
18
6V
400
530
660
µA
39.6V
500
680
900
µA
60V
550
750
1000
µA
-40°C to +105°C (Note 9)
IVBATSLEEP1 Sleep mode (EN = 1, Daisy Chain configuration)
(Note 9)
6V
1150
18
18
23
µA
39.6V
18
23
29
µA
60V
20
25
30
µA
41
µA
16
µA
70
µA
IVBATSLEEP2 Sleep mode (EN = 1, Stand-alone, non-Daisy Chain)
(Note 9)
-40°C to +105°C
3.5
8
3
IVBATSHDN Shutdown. device “off” (EN = 0) (Daisy Chain and Non-Daisy Chain configurations)
(Note 9)
6V
1.5
7
15.5
39.6V
µA
3
7
18
60V
5
7
23
µA
-40°C to +105°C
1
77
µA
8
µA
17
µA
IVBATΔSLEEP EN = 1, Daisy Chain Sleep Mode configuration. VBAT
(Note 9) current difference between any two devices operating
at the same temperature and supply voltage.
-40°C to +105°C
7
µA
mA
14
-40°C to +105°C
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µA
mA
Daisy Chain configuration – top device. Enabled. No communications, ADC, measurement,
balancing or open wire detection activity.
Peak Current when Daisy Chain transmitting
VBAT Supply Current Tracking. Sleep Mode.
µA
mA
0
0
4
µA
FN7672.6
January 20, 2015
ISL78600
Electrical Specifications
VBAT = 6 to 60V, TA = -20°C to +60°C, unless otherwise specified. (Continued)
PARAMETER
SYMBOL
VBAT Incremental Supply Current, Balancing
IVBATBAL
TEST CONDITIONS
All balancing circuits on. Incremental current:
Add to nonbalancing VBAT current. VBAT = 39.6V
-40°C to +105°C (Note 9)
V3P3 Regulator Voltage (Normal)
V3P3N
EN = 1, Load current range 0 to 5mA. VBAT = 39.6V
-40°C to +105°C (Note 9)
V3P3 Regulator Voltage (Sleep)
V3P3S
EN = 1, Load current range. No load. (SLEEP).
VBAT = 39.6V
-40°C to +105°C (Note 9)
V3P3 Regulator Control Current
IBASE
Current sourced from BASE output. VBAT = 6V
-40°C to +105°C (Note 9)
V3P3 Supply Current
IV3P3
Device Enabled
No measurement activity, Normal Mode
-40°C to +105°C (Note 9)
VREF Reference Voltage
VREF
VDDEXT Switch Resistance
RVDDEXT
IVCC
TYP
MAX
(Note 7)
UNITS
250
300
350
µA
200
300
400
µA
3.25
3.35
3.45
V
3.5
V
2.95
V
3.05
V
3.2
2.45
Switch “On” resistance, VBAT = 39.6V
Device enabled (EN = 1). Stand-Alone or Daisy
Configuration. No ADC or Daisy Chain communications
active.
-40°C to +105°C (Note 9)
1
Device enabled (EN = 1). Sleep mode. VBAT = 39.6V
IVCCSHDN
Device disabled (EN = 0). Shutdown mode.
1.5
mA
1
0.8
mA
1
0.8
1.2
mA
1.3
mA
2.5
8
12
5
2.0
3.25
2.0
V
17
Ω
22
Ω
4.5
mA
5.0
mA
6.0
IVCCACTIVE1 Device enabled (EN = 1). Stand-Alone or Daisy
Configuration. Average current during 16ms Scan
Continuous operation. VBAT = 39.6V
IVCCSLEEP
2.7
2.4
EN = 1, No Load, Normal Mode
-40°C to +105°C (Note 9)
VCC Supply Current
MIN
(Note 7)
mA
2.4
0
1.2
-40°C to +105°C (Note 9)
µA
4.1
µA
9.0
µA
5
V
MEASUREMENT SPECIFICATIONS
Cell Voltage Input Measurement Range
Cell Monitor Voltage Resolution
VCELL
VCELLRES
ISL78600 Initial Cell Monitor Voltage Error
(Note 10)
VNOM = nominal calibration voltage.
Note: Cell measurement accuracy figures
assume a fixed 1kΩ resistor is placed in
series with each VCn pin (n = 0 to 12).
VCELL
VC(n) - VC(n-1). For Design Reference.
[VC(n)-VC(n-1)] LSB step size (13-bit signed number), 5V
full scale value
mV
-2.5
2.5
VCELL = VNOM - 0.7V < VCELL < VNOM + 0.7V
-3.5
3.5
mV
VCELL = 4.95
-10
10
mV
VCELL = 0.5
-15
15
mV
VCELL = VNOM - 0.7V < VCELL < VNOM + 0.7V
-40°C to +85°C (Note 9)
-9.5
9.0
mV
-26.5
26.5
mV
-11
11
mV
-26.5
26.5
mV
-18
18
mV
-37
37
mV
VCELL = 4.95, -40°C to +85°C (Note 9)
-40°C to +105°C (Note 9)
VCELL = 0.5, -40°C to +85°C (Note 9)
-40°C to +105°C (Note 9)
8
0.61
VCELL = VNOM - 0.3V < VCELL < VNOM + 0.3V
-40°C to +105°C (Note 9)
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mV
FN7672.6
January 20, 2015
ISL78600
Electrical Specifications
VBAT = 6 to 60V, TA = -20°C to +60°C, unless otherwise specified. (Continued)
PARAMETER
MIN
(Note 7)
TYP
VC0 ≥ 0.5 and VC0 ≤ 4.0V
-1.5
-1
VC0 > 4.0V
-1.75
SYMBOL
Cell Input Current.
IVCELL
Note: Cell accuracy figures assume a fixed
1kΩ resistor is placed in series with each
VCn pin (n = 0 to 12)
TEST CONDITIONS
MAX
(Note 7)
UNITS
VC0 Input
-0.5
µA
-0.5
µA
-2.0
-1
-0.5
µA
VCn - VC(n-1) ≥ 0.5 and VCn-VC(n-1) ≤ 4.0V
-2.7
-2
-1.3
µA
VCn - VC(n-1) > 4.0V
-2.85
-1.0
µA
-40°C to +105°C (Note 9)
-3.0
-2
-0.84
µA
VCn - VC(n-1) ≥ 0.5 and VCn-VC(n-1) ≤ 4.0V
-0.6
0
0.71
µA
VCn - VC(n-1) > 4.0V
-0.8
1.15
µA
-40°C to +105°C (Note 9)
VC1, VC2, VC3 Inputs
VC4 Input
-40°C to +105°C (Note 9)
- 0.84
0
1.31
µA
VCn - VC(n-1) < 2.6V
0.5
2
2.7
µA
VCn - VC(n-1) ≥ 2.6V and VCn-VC(n-1) ≤ 4.0V
1.32
2
2.89
µA
VCn - VC(n-1) > 4.0V
1.16
2
3.33
µA
-40°C to +105°C (Note 9)
0.5
2
3.43
µA
VC12 - VC11 ≥ 0.5 and VC12-VC11 ≤ 4.0V
0.37
1
1.85
µA
VC12 - VC11 > 4.0V
0.19
2.3
µA
-40°C to +105°C (Note 9)
0.15
2.47
µA
VC5, VC6, VC7, VC8, VC9, VC10, VC11 Inputs
VC12 Input
VBAT Monitor Voltage Resolution
VBATRES
Initial VBAT monitor Voltage Error
(Note 10)
VBAT
ADC resolution referred to input (VBAT) level. 14-bit
unsigned number. Full scale value = 79.67V.
1
4.863
mV
Measured at VBAT = 36V to 43.2V
-100
100
mV
Measured at VBAT = 31.2V to 48V
-125
125
mV
Measured at VBAT = 31.2V to 59.4V
-250
250
mV
Measured at VBAT = 6V to 59.4V
-320
332
mV
Measured at VBAT = 6V to 59.4V
-40°C to +105°C (Note 9)
-490
490
mV
External Temperature Monitoring Regulator
VTEMP
Voltage on TEMPREG output. (0 to 2mA load)
2.475
2.5
2.525
V
External Temperature Output Impedance
RTEMP
Output Impedance at TEMPREG pin. (Note 9)
0
0.1
0.2
Ω
Effective ExTn input voltage range. For design
reference. This is the input voltage range that does not
trigger an open input condition.
0
2344
mV
External Temperature Input Range
VEXT
External Temperature Input Pull-up
REXTTEMP Pull-up resistor to VTEMPREG applied to each input
during measurement
External Temperature Input Offset
VEXTOFF
External Temperature Input INL
VEXTINL
VBAT = 39.6V
VBAT = 39.6V, -40°C to +105°C (Note 9)
External Temperature Input Gain Error
VEXTG
(Note 9)
Error at 2.5V input
-40°C to +105°C (Note 9)
Internal Temperature Monitor Error
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VINTMON
9
10
-7.0
MΩ
7.0
mV
-10
10
mV
-0.65
0.65
mV
-7.5
11
mV
-13.4
19.3
mV
±10
°C
FN7672.6
January 20, 2015
ISL78600
Electrical Specifications
VBAT = 6 to 60V, TA = -20°C to +60°C, unless otherwise specified. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
Internal Temperature Monitor Resolution
TINTRES
Output resolution (LSB/°C). 14-bit number.
31.9
LSB/°C
Internal Temperature Monitor Output
TINT25
Output count at +25°C
9180
Decimal
Balance stops and auto scan stops.
Temperature rising or Falling.
150
°C
OVER-TEMPERATURE PROTECTION SPECIFICATIONS
Internal Temperature Limit Threshold
TINTSD
External Temperature Limit Threshold
TXT
Corresponding to 0V (min) and VTEMPREG (max)
External temperature input voltages higher than 15/16
VTEMPREG are registered as open input faults.
0
16383
Decimal
Undervoltage Threshold
VUV
Programmable. Corresponding to 0V (min) and 5V
(max)
0
8191
Decimal
Overvoltage Threshold
VOV
Programmable. Corresponding to 0V (min) and 5V
(max)
0
8191
Decimal
V3P3 Power-good Window
V3PH
3.3V power-good window high threshold. VBAT = 39.6V
3.99
V
4.05
V
2.64
2.71
V
2.8
V
2.7
2.766
V
2.77
V
2.08
V
2.14
V
3.9
V
4.0
V
2.8
V
FAULT DETECTION SYSTEM SPECIFICATIONS
-40°C to +105°C (Note 9)
V3PL
3.3V power-good window low threshold. VBAT = 39.6V
V2PH
2.5V power-good window high threshold. VBAT = 39.6V
-40°C to +105°C (Note 9)
V2P5 Power-good Window
-40°C to +105°C (Note 9)
VCC Power-good Window
V2PL
(Note 9)
2.5V power-good window low threshold. VBAT = 39.6V
VVCCH
VCC power-good window high threshold. VBAT = 39.6V
-40°C to +105°C
-40°C to +105°C (Note 9)
VVCCL
VCC power-good window low threshold. VBAT = 39.6V
VRPH
VREF power-good window high threshold. VBAT = 39.6V
-40°C to +105°C (Note 9)
VREF Power-good Window
-40°C to +105°C (Note 9)
VRPL
VREF power-good window low threshold. VBAT = 39.6V
VREF Reference Accuracy Test
VRACC
VREF value calculated using stored coefficients.
VBAT = 39.6V
Voltage Reference Check Timeout
tVREF
Oscillator Check Timeout
Oscillator Check Filter Time
-40°C to +105°C (Note 9)
3.79
3.89
3.7
2.57
2.5
2.62
2.616
1.96
2.02
1.90
3.6
3.74
3.6
2.6
2.7
2.55
2.525
2.7
2.525
2.15
2.30
2.0
2.85
V
2.9
V
2.9
V
2.465
V
2.5
V
2.500
V
Time to check voltage reference value from power-on,
enable or wakeup
20
ms
tOSC
Time to check main oscillator frequency from
power-on, enable or wakeup
20
ms
tOSCF
Minimum duration of fault required for detection
100
ms
CELL OPEN WIRE DETECTION
Open Wire Current
IOW
ISCN bit = 0; VBAT = 39.6V
0.125
0.15
0.185
mA
ISCN bit = 1; VBAT = 39.6V
0.85
1.0
1.15
mA
Open Wire Detection Time
tOW
Open wire current source “on” time
Open VC0 Detection Threshold
VVC0
CELL1 negative terminal (with respect to VSS)
VBAT = 39.6V (Note 9)
1.2
1.5
1.8
V
Open VC1 Detection Threshold
VVC1
CELL1 positive terminal (with respect to VSS)
VBAT = 39.6V (Note 9)
0.6
0.7
0.8
V
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FN7672.6
January 20, 2015
ISL78600
Electrical Specifications
VBAT = 6 to 60V, TA = -20°C to +60°C, unless otherwise specified. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
Primary Detection Threshold, VC2 to VC12
VVC2_12P
V(VC(n - 1))-V(VCn), n = 2 to 12
VBAT = 39.6V (Note 9)
Secondary Detection Threshold, VC2 to
VC12
VVC2_12S
Via ADC. VC2 to VC12 only
VBAT = 39.6V (Note 9)
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
-2
-1.5
0
V
-100
-30
50
mV
Open VBAT Fault Detection Threshold
VVBO
VC12 - VBAT
200
mV
Open VSS Fault Detection Threshold
VVSSO
VSS - VC0
250
mV
Cell Sample Time Start
Time to sample the first cell (CELL12) following CS
going High. Scan voltages command
65
71.5
µs
Cell Sample Time Duration
Time to scan all 12 cells
(sample of CELL12 to sample of CELL1) scan voltages
command.
233
257
µs
Scan Voltages Processing Time
Time from start of scan to registers loaded to DATA
READY going low
770
847
µs
Scan Temperatures Processing Time
Time from start of scan to registers loaded to DATA
READY going low
2690
2959
µs
Scan Mixed Processing Time
Time from start of scan to registers loaded to DATA
READY going low
830
913
µs
Scan Wires Processing Time
Time from start of scan to registers loaded to DATA
READY going low
59.4
65.3
ms
Scan All Processing Time
Time from start of scan to registers loaded to DATA
READY going low
63.2
69.5
ms
Measure Cell Voltage Processing Time
Time from start of measurement to register(s) loaded
to DATA READY going low
180
198
µs
Measure VBAT Voltage Processing Time
Time from start of measurement to register(s) loaded
to DATA READY going low
130
143
µs
Measure Internal Temperature Processing
Time
Time from start of measurement to register(s) loaded
to DATA READY going low
110
121
µs
Measure External Temperature Input
Processing Time
Time from start of measurement to register(s) loaded
to DATA READY going low
2520
2772
µs
Measure Secondary Voltage Reference
Time
Time from start of measurement to register(s) loaded
to DATA READY going low
2520
2772
µs
MEASUREMENT FUNCTION TIMING (Note 8)
CELL BALANCE OUTPUT SPECIFICATIONS
Cell Balance Pin Output Impedance
RCBL
CBn output off impedance
between CB(n) to VC(n-1): cells 1 to 9, and
between CB(n) to VC(n): cells 10 to 12
3
4
5
MΩ
Cell Balance Output Current
ICBH1
CBn output on. (CB1-CB9); VBAT = 39.6V;
device sinking current
-28
-25
-21
μA
ICBH2
CBn output on. (CB10-CB12); VBAT = 39.6V;
device sourcing current
21
25
28
μA
ICBSD
EN = GND. VBAT = 39.6V
-500
10
700
nA
CBn Output on;
External 320kΩ between VCn and CBn
(n = 10 to 12) and between CBn and VCn-1
(n = 1 to 9)
7.04
8.0
8.96
V
ICB = 100µA
8.94
Cell Balance Output Leakage in Shutdown
External Cell Balance FET Gate Voltage
Internal Cell Balance Output Clamp
VGS
VCBCL
V
LOGIC INPUTS: SCLK, CS, DIN
Low Level Input Voltage
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11
0.8
V
FN7672.6
January 20, 2015
ISL78600
Electrical Specifications
VBAT = 6 to 60V, TA = -20°C to +60°C, unless otherwise specified. (Continued)
PARAMETER
SYMBOL
High Level Input Voltage
TEST CONDITIONS
VIH
Input Hysteresis
VHYS
Input Current
IIN
Input Capacitance (Note 9)
CIN
MIN
(Note 7)
TYP
MAX
(Note 7)
1.75
(Note 9)
0V < VIN < V3P3
UNITS
V
100
mV
-1
+1
µA
10
pF
0.3*V3P3
V
LOGIC INPUTS: EN, COMMS SELECT1, COMMS SELECT2, COMMS RATE 0, COMMS RATE 1
Low Level Input Voltage
VIL
High Level Input Voltage
VIH
Input Hysteresis
VHYS
Input Current
IIN
Input Capacitance (Note 9)
CIN
(Note 9)
0V < VIN < V3P3
0.7*V3P3
V
0.05*V3P3
V
-1
+1
µA
10
pF
LOGIC OUTPUTS: DOUT, FAULT, DATA READY
Low Level Output Voltage
High Level Output Voltage
VOL1
At 3mA sink current
0
0.4
V
VOL2
At 6mA sink current
0
0.6
V
VOH1
At 3mA source current
V3P3 – 0.4
V3P3
V
VOH2
At 6mA source current
V3P3 – 0.6
V3P3
V
2
MHz
200
ns
SPI INTERFACE TIMING - See Figures 1 and 2.
SCLK Clock Frequency
fSCLK
Pulse Width of Input Spikes Suppressed
50
tIN1
Enable Lead Time
tLEAD
Chip select low to ready to receive clock data
200
ns
Clock High Time
tHIGH
(Note 9)
200
ns
Clock Low Time
tLOW
(Note 9)
200
ns
tLAG
Last data read clock edge to Chip Select high (Note 9)
250
ns
Minimum high time for CS between bytes
200
ns
Enable Lag Time
CHIP SELECT High Time
tCS:WAIT
Slave Access Time
tA
Chip Select low to DOUT active. (Note 9)
200
ns
Data Valid Time
tV
Clock low to DOUT valid
350
ns
240
ns
Data Output Hold Time (Note 9)
tHO
Data hold time after falling edge of SCLK
DOUT Disable Time
tDIS
DOUT disabled following rising edge of CS (Note 9)
Data Setup Time
tSU
Data input valid prior to rising edge of SCLK
100
ns
Data Input Hold Time
tHI
Data input to remain valid following rising edge of SCLK
80
ns
100
DATA READY Start Delay Time
tDR:ST
Chip select high to DATA READY low. (Note 9)
DATA READY Stop Delay Time
tDR:SP
Chip select high to DATA READY high. (Note 9)
DATA READY High Time
tDR:WAIT
SPI Communications Timeout
tSPI:TO
Time between bytes. (Note 9)
Time the CS remains high before SPI communications
time out - requiring the start of a new command
0
ns
ns
750
0.6
ns
µs
100
µs
DOUT Rise Time
tR
Up to 50pF load
30
ns
DOUT Fall Time
tF
Up to 50pF load
30
ns
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FN7672.6
January 20, 2015
ISL78600
Electrical Specifications
VBAT = 6 to 60V, TA = -20°C to +60°C, unless otherwise specified. (Continued)
PARAMETER
SYMBOL
MIN
(Note 7)
TEST CONDITIONS
TYP
MAX
(Note 7)
UNITS
DAISY CHAIN COMMUNICATIONS INTERFACE: DHi1, DLo1, DHi2, DLo2
Daisy Chain Clock Frequency
Comms Rate (0, 1) = 11
450
500
550
kHz
Comms Rate (0, 1) = 10
225
250
275
kHz
Comms Rate (0, 1) = 01
112.5
125
137.5
kHz
Comms Rate (0, 1) = 00
56.25
62.5
68.75
kHz
VBAT/2
Common Mode Reference Voltage
V
NOTES:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
8. Scan and Measurement start times are synchronised by the receiver to the falling edge of the 24th clock pulse (Daisy Chain systems) or to the falling edge
of the 16th clock pulse (non-Daisy Chain, single device systems) of the Scan or Measure command. Clock pulses are at the SCLK pin for Master and
Stand-alone devices, and at the DHi/DLo1 pins for middle and top Daisy Chain devices. Maximum values are based on characterization of the internal clock
and are not 100% tested.
9. These MIN and/or MAX values are based on characterization data and are not 100% tested.
10. Stresses may be induced in the ISL78600 during soldering or other high temperature events that affect measurement accuracy. Initial accuracy does
not include effects due to this. See Figure 4B for cell reading accuracy obtained after soldering to Intersil evaluation boards. When soldering the
ISL78600 to a customized circuit board with a layout or construction significantly differing from the Intersil evaluation board, design verification tests
should be applied to determine drift due to soldering and over lifetime.
Timing Diagrams
CS
(FROM µC)
tSPI:TO
tLEAD
tHIGH
tLOW
tCS:WAIT
tLAG
SCLK
(FROM µC)
tA
tV
tF
tDIS
tHO
DOUT
(TO µC)
tSU
tR
tHI
DIN
(FROM µC)
CLOCK DATA INTO
ISL78600
CLOCK DATA OUT OF
ISL78600
FIGURE 1. SPI FULL DUPLEX (4-WIRE) INTERFACE TIMING
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FN7672.6
January 20, 2015
ISL78600
CS
(FROM µC)
tCS:WAIT
tSPI:TO
tDR:ST
tDR:WAIT
tDR:SP
DATA READY
(TO µC)
SCLK
(FROM µC)
tA
DOUT
(TO µC)
CLOCK DATA OUT OF
ISL78600
SIGNALS ON DIN IGNORED
WHILE DATA READY IS LOW
DIN
(FROM µC)
CLOCK DATA INTO
ISL78600
FIGURE 2. SPI HALF DUPLEX (3-WIRE) INTERFACE TIMING
20
40
15
30
READING ERROR (mV)
READING ERROR (mV)
Typical Performance Curves
10
5
0
-5
-10
-15
-20
20
10
0
-10
-20
-30
-40
0
1
2
3
4
5
CELL VOLTAGE (V)
FIGURE 3A. CELL VOLTAGE READING ERROR FROM -20°C TO +60°C
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14
-50
0
1
2
3
4
5
CELL VOLTAGE (V)
FIGURE 3B. CELL VOLTAGE READING ERROR FROM -40°C to +105°C
FN7672.6
January 20, 2015
ISL78600
Typical Performance Curves
(Continued)
35
PERCENTAGE OF CELLS (%)
PERCENTAGE OF CELLS (%)
50
40
30
20
10
0
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0
30
25
20
15
10
5
0
0.5 1.0 1.5 2.0 2.5 3.0
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
READING ERROR (mV)
READING ERROR (mV)
FIGURE 4B. CELL READING ERROR FROM 114 EVALUATION
BOARDS AT 3.3V, +25°C HISTOGRAM
FIGURE 4A. INITIAL CELL VOLTAGE ACCURACY AT 3.3V, +25°C
HISTOGRAM
600
400
400
READING ERROR (mV)
READING ERROR (mV)
300
200
100
0
-100
-200
0
-200
-400
-300
-400
200
0
10
20
30
40
50
-600
60
0
10
PACK VOLTAGE (V)
40
50
60
FIGURE 5B. PACK VOLTAGE READING ERROR FROM -40°C TO +105°C
4
NORMALIZED VARIATIONS (%)
35
30
PERCENTAGE (%)
30
PACK VOLTAGE (V)
FIGURE 5A. PACK VOLTAGE READING ERROR FROM -20°C TO +60°C
25
20
15
10
5
0
20
-50
-40
-30
-20
-10
0
10
20
30
40
50
READING ERROR (mV)
FIGURE 6. INITIAL PACK VOLTAGE ACCURACY AT 39.6V, +25°C
HISTOGRAM
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15
-20°C
3
2
-40°C
1
0
+105°C
+85°C
-1
-2
+60°C
-3
+25°C
-4
-5
0
10
20
30
40
50
60
PACK VOLTAGE (V)
FIGURE 7. IC TEMPERATURE ERROR vs PACK VOLTAGE
FN7672.6
January 20, 2015
ISL78600
Typical Performance Curves
(Continued)
0.5
1.00
0.50
0.3
BGVREF ACCURACY (mV)
BGVREF ACCURACY (mV)
0.4
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.50
-1.00
-1.50
-2.00
-2.50
-0.4
-0.5
0.00
6
15
24
33
42
51
-3.00
60
-40
-20
0
VBAT (V)
20
40
60
80
100
TEMPERATURE ( °C )
FIGURE 8. VOLTAGE REFERENCE CHECK FUNCTION vs PACK
VOLTAGE (AT +25°C)
FIGURE 9. VOLTAGE REFERENCE CHECK FUNCTION vs
TEMPERATURE (VBAT = 39.6)
0
25.60
-0.05
BALANCE CURRENT (µA)
VREF SHIFT (mV)
-0.10
-0.15
-0.20
-0.25
-0.30
-0.35
-0.40
25.55
25.50
25.45
-0.45
-0.50
0
100
200
300
400
500
600
700
800
25.40
900 1000
HOURS AT +125°C
FIGURE 10. VREF SHIFT OVER HTOL
10
20
30
40
PACK VOLTAGE (V)
50
60
FIGURE 11. BALANCE CURRENT vs PACK VOLTAGE
25.6
157
VCELL = 3.3V
156
25.4
25.0
24.8
24.6
154
153
152
151
24.4
24.2
-40
VCELL = 3.3V
155
25.2
IOPWI (µA)
BALANCE CURRENT (µA)
0
150
-20
0
20
40
60
80
TEMPERATURE (°C)
FIGURE 12. BALANCE CURRENT vs TEMPERATURE
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100
149
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
FIGURE 13. OPEN WIRE TEST CURRENT vs TEMPERATURE
(150µA SETTING)
FN7672.6
January 20, 2015
ISL78600
Typical Performance Curves
(Continued)
970
158.0
VCELL = 3.3V
965
IOPWI (µA)
IOPWI (µA)
157.5
960
955
157.0
950
156.5
945
940
-40
-20
0
20
40
60
80
156.0
100
0
10
20
TEMPERATURE (°C)
50
60
0.4
1000
0.2
ERROR (%)
950
IOPWI (µA)
40
FIGURE 15. OPEN WIRE TEST CURRENT vs PACK VOLTAGE
(150µA SETTING)
FIGURE 14. OPEN WIRE TEST CURRENT vs TEMPERATURE
(1mA SETTING)
900
850
800
30
PACK VOLTAGE (V)
0
-0.2
-0.4
0
10
20
30
40
PACK VOLTAGE (V)
50
-0.6
2.7
60
2.9
3.1
3.3
3.5
3.7
VCC (V)
FIGURE 16. OPEN WIRE TEST CURRENT vs PACK VOLTAGE
(1mA SETTING)
FIGURE 17. 4MHz OSCILLATOR ERROR vs VCC
1
1
0
0
-2
ERROR (%)
ERROR (%)
-1
-3
-4
-1
-2
-3
-5
-4
-6
-7
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 18. 4MHz OSCILLATOR ERROR vs TEMPERATURE
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17
-5
-40
-20
0
20
40
60
TEMPERATURE (°C)
80
100
120
FIGURE 19. 32kHz OSCILLATOR ERROR vs TEMPERATURE
FN7672.6
January 20, 2015
ISL78600
Typical Performance Curves
(Continued)
0.4
19
17
0.2
VBAT = 60V
0
IVBAT (µA)
ERROR (%)
15
-0.2
13
VBAT = 39.6V
11
VBAT = 6V
9
-0.4
7
-0.6
2.7
2.9
3.1
3.3
3.5
5
-60
3.7
-40
-20
FIGURE 20. 32kHz OSCILLATOR ERROR vs VCC
60
80
100
120
33
VBAT = 60V (MASTER)
31
29
29
27
27
IVBAT (µA)
31
25
23
21
VBAT = 39.6V (MASTER)
19
15
-60
-40
-20
0
20
40
60
VBAT = 60V (TOP)
VBAT = 39.6V (TOP)
25
23
21
80
100
VBAT = 6V (TOP)
19
VBAT = 6V (MASTER)
17
17
15
-60
120
-40
-20
TEMPERATURE ( °C )
0
20
40
60
80
100
120
TEMPERATURE ( °C )
FIGURE 21B. PACK VOLTAGE SLEEP CURRENT vs TEMPERATURE AT
6V, 39.6V, 60V (DAISY CHAIN MODE)
FIGURE 21C. PACK VOLTAGE SLEEP CURRENT vs TEMPERATURE AT
6V, 39.6V, 60V (DAISY CHAIN MODE)
35
120
33
VBAT = 60V
100
31
VBAT = 39.6V (MID)
29
80
27
IVBAT (µA)
IVBAT (µA)
40
35
33
25
20
FIGURE 21A. PACK VOLTAGE SLEEP CURRENT vs TEMPERATURE AT
6V, 39.6V, 60V (STANDALONE MODE)
35
IVBAT (µA)
0
TEMPERATURE ( °C )
VCC (V)
VBAT = 60V (MID)
23
60
40
21
19
VBAT = 6V
20
17
15
-60
VBAT = 39.6V
VBAT = 6V (MID)
-40
-20
0
20
40
60
80
100
120
TEMPERATURE ( °C )
FIGURE 21D. PACK VOLTAGE SLEEP CURRENT vs TEMPERATURE AT
6V, 39.6V, 60V (DAISY CHAIN MODE)
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0
-60
-40
-20
0
20
40
60
80
100
120
TEMPERATURE ( °C )
FIGURE 22A. PACK VOLTAGE SUPPLY CURRENT vs TEMPERATURE AT
6V, 39.6V, 60V (STANDALONE MODE)
FN7672.6
January 20, 2015
ISL78600
Typical Performance Curves
(Continued)
1500
850
VBAT = 60V (TOP)
800
VBAT = 60V (MID)
1400
750
1300
IVBAT (µA)
IVBAT (µA)
700
650
VBAT = 39.6V (TOP)
600
550
1200
1000
500
VBAT = 6V (MID)
VBAT = 6V (TOP)
900
450
400
-60
-40
-20
0
20
40
60
TEMPERATURE ( °C )
80
100
800
-60
120
-40
-20
0
12
750
80
100
120
VBAT = 6V (STAND-ALONE)
11
IVBAT (µA)
700
650
VBAT = 39.6V (MASTER)
600
550
500
10
9
8
VBAT = 39.6V (STAND-ALONE)
7
VBAT = 6V (MASTER)
450
6
400
-60
5
-60
-40
-20
0
20
40
60
80
100
120
VBAT = 60V (STAND-ALONE)
-40
-20
0
20
40
60
80
TEMPERATURE ( °C )
TEMPERATURE ( °C )
FIGURE 22D. PACK VOLTAGE SUPPLY CURRENT vs TEMPERATURE AT
6V, 39.6V, 60V (DAISY CHAIN MASTER)
100
120
140
FIGURE 23A. PACK VOLTAGE SHUTDOWN CURRENT vs TEMPERATURE
(EN = 0) AT 6V, 39.6V, 60V
13
13
VBAT = 60V (MASTER)
12
12
11
11
10
10
IVBAT (µA)
IVBAT (µA)
60
13
VBAT = 60V (MASTER)
800
9
VBAT = 39.6V (MASTER)
VBAT = 60V (MID)
9
VBAT = 39.6V (MID)
8
7
7
VBAT = 6V (MASTER)
6
5
-60
40
FIGURE 22C. PACK VOLTAGE SUPPLY CURRENT vs TEMPERATURE AT
6V, 39.6V, 60V (DAISY CHAIN MIDDLE)
850
8
20
TEMPERATURE ( °C )
FIGURE 22B. PACK VOLTAGE SUPPLY CURRENT vs TEMPERATURE AT
6V, 39.6V, 60V (DAISY CHAIN TOP)
IVBAT (µA)
VBAT = 39.6V (MID)
1100
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
FIGURE 23B. VBAT SHUTDOWN CURRENT vs TEMPERATURE (EN = 0)
AT 6V, 39.6V, 60V
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VBAT = 6V (MID)
6
5
-60
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
FIGURE 23C. VBAT VOLTAGE SHUTDOWN CURRENT vs TEMPERATURE
(EN = 0) AT 6V, 39.6V, 60V
FN7672.6
January 20, 2015
ISL78600
Typical Performance Curves
(Continued)
13
3.50
3.45
12
VBAT = 60V (TOP)
3.40
3.35
10
9
IVCC (mA)
IVBAT (µA)
11
VBAT = 39.6V (TOP)
8
3.25
3.20
3.15
7
VBAT = 6V (TOP)
3.10
6
5
-60
3.30
3.05
-40
-20
0
20
40
60
80
3.00
-60
100 120 140
-40
-20
0
TEMPERATURE (°C)
FIGURE 23D. VBAT VOLTAGE SHUTDOWN CURRENT vs TEMPERATURE
(EN = 0) AT 6V, 39.6V, 60V
60
80
100
120
2.5
2.0
CELL INPUT CURRENT (µA)
1.05
SUPPLY CURRENT (mA)
40
FIGURE 24. VCC SUPPLY CURRENT vs TEMPERATURE AT 6V, 39.6V,
60V
1.06
1.04
39.6V
1.03
60V
1.02
6V
1.01
1.00
0.99
-40
20
TEMPERATURE ( °C )
VCELL = 3.3V
1.5
0
20
40
60
80
100
VC5
VC10
1.0
0
VC7
VC9
VC6
VC4
-0.5
-1.0
VC0
-1.5
-2.5
-40
VC3
-20
VC2
0
VC1
20
40
60
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 25. V3P3 SUPPLY CURRENT vs TEMPERATURE
VC8
VC12
0.5
-2.0
-20
VC11
80
100
120
FIGURE 26. CELL INPUT CURRENT vs TEMPERATURE
CELL INPUT CURRENT (µA)
2.5
2.0 VC11
VC10
VC9
1.5 VC8
VC7
1.0 VC6
VC5
0.5
VC12
VC4
0.0
-0.5
VC0
-1.0
-1.5
VC3
-2.0 VC2
VC1
-2.5
0
10
20
30
40
PACK VOLTAGE (V)
50
60
FIGURE 27. CELL INPUT CURRENT vs PACK VOLTAGE (+25°C)
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FN7672.6
January 20, 2015
ISL78600
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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FN7672.6
January 20, 2015
ISL78600
Package Outline Drawing
Q64.10x10D
64 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE
Rev 2, 9/12
12.00
4 5
10.00
D 3
12.00
A
10.00
4 5
B
0.50
3
4X
0.20 C A-B D
TOP VIEW
4X
11/13°
0.20 H A-B D
BOTTOM VIEW
1.20 MAX
0.05
/ / 0.10 C
C
SIDE VIEW
7
0.08
SEE DETAIL "A"
0° MIN.
H
3
0.08 M C A-B D
WITH LEAD FINISH
0.22 ±0.05
0.09/0.20
2
1.00 ±0.05
0.05/0.15
0.09/0.16
0.08
R. MIN.
0.20 MIN.
0.20 ±0.03
BASE METAL
DETAIL "A"
SCALE: NONE
0.25
0-7° GAUGE
PLANE
0.60 ±0.15
(1.00)
NOTES:
1. All dimensioning and tolerancing conform to ANSI Y14.5-1982.
2. Datum plane H located at mold parting line and coincident
with lead, where lead exits plastic body at bottom of parting line.
3. Datums A-B and D to be determined at centerline between
leads where leads exit plastic body at datum plane H.
4. Dimensions do not include mold protrusion. Allowable mold
protrusion is 0.254mm.
5. These dimensions to be determined at datum plane H.
6. Package top dimensions are smaller than bottom dimensions
and top of package will not overhang bottom of package.
7. Does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm total at maximum material
condition. Dambar cannot be located on the lower radius
or the foot.
8. Controlling dimension: millimeter.
9. This outline conforms to JEDEC publication 95 registration
MS-026, variation ACD.
10. Dimensions in ( ) are for reference only.
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FN7672.6
January 20, 2015