INTERSIL ISL94203EVAL1Z

3-to-8 Cell Li-ion Battery Pack Monitor
ISL94203
Features
The ISL94203 is a Li-ion battery monitor IC that supports from
3 to 8 series connected cells. It provides full battery monitoring
and pack control. The ISL94203 provides automatic shutdown
and recovery from out of bounds conditions and automatically
controls pack cell balancing.
• Eight cell voltage monitors support Li-ion CoO2, Li-ion
Mn2O4, and Li-ion FePO4 chemistries
• Stand-alone pack control - No microcontroller needed
• Multiple voltage protection options
(Each programmable to 4.8V; 12-bit digital value)
and selectable overcurrent protection levels
• Programmable detection/recovery times for overvoltage,
undervoltage, overcurrent, and short circuit conditions
The ISL94203 is highly configurable as a stand-alone unit, but
can be used with an external microcontroller, which
communicates to the IC through an I2C interface.
Applications
• Configuration/calibration registers maintained in EEPROM
• Open battery connect detection
• Power tools
• Integrated charge/discharge FET drive circuitry with built-in
charge pump supports high-side N-channel FETs
• Battery back-up systems
• E-bikes
• Cell balancing uses external FETs with internal state
machine or external microcontroller
• Enters low power states after periods of inactivity. Charge or
discharge current detection resumes normal scan rates
P+
LDMON
C2
C3
C1
DFET
CFET
VDD
PSD
CB8
VC7
FETSOFF
CB7
VC6
INT
RGO
CB6
VC5
CB5
VC4
CB4
VC3
CB3
VC2
CB2
VC1
GND
CHMON
VBATT
VC8
PCFET
CS2
43V
CS1
43V
CHRG
ISL94203
SD
EOC
SCL
SDA
TEMPO
CB1
VC0
xT1
xT2
VREF
VSS
ADDR
P-
FIGURE 1. TYPICAL APPLICATION DIAGRAM
December 5, 2012
FN7626.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL94203
Ordering Information
PART NUMBER
(Note 2)
PART
MARKING
QUANTITY
ISL94203IRTZ
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
Bulk quantity
94203 IRTZ
-40 to +85
48 Ld TQFN
L48.6x6
ISL94203IRTZ-T7 (Note 1)
1000/reel
94203 IRTZ
-40 to +85
48 Ld TQFN
L48.6x6
ISL94203IRTZ-T (Note 1)
4000/reel
94203 IRTZ
-40 to +85
48 Ld TQFN
L48.6x6
ISL94203EVAL1Z
One
Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL94203. For more information on MSL please see tech brief TB363.
Pin Configuration
VBATT
CSI1
CSI2
CFET
PCFET
VDD
DFET
C1
C2
C3
LDMON
CHMON
ISL94203
(48 LD TQFN)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
VC8
1
36 RGO
CB8
2
35 EOC
VC7
3
34 SD
CB7
4
33 FETSOFF
VC6
5
32 PSD
CB6
6
31 INT
PAD
VC5
7
30 DNC
CB5
8
29 VSS
VC4
9
28 VSS
CB4 10
27 SDAO
VC3
26 SDAI
11
CB3 12
2
13
14
15
16
17
18
19
20
21
22
23
24
VC2
CB2
VC1
CB1
VC0
VSS
VREF
XT1
XT2
TEMPO
DNC
ADDR
25 SCL
FN7626.2
December 5, 2012
ISL94203
Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
1, 3, 5, 7, 9,
11, 13, 15,
17
VC8, VC7,
VC6, VC5,
VC4, VC3,
VC2, VC1,
VC0
Battery cell n voltage input. This pin is used to monitor the voltage of this battery cell. The voltage is level shifted to a ground
reference and is monitored internally by an ADC converter. VCn connects to the positive terminal of a battery cell (CELLN)
and VC(n-1)the negative terminal of CELLN (VSS connects with the negative terminal of CELL1).
2, 4, 6, 8,
10, 12, 14,
16
CB8, CB7,
CB6, CB5,
CB4, CB3,
CB2, CB1
Cell balancing FET control output n. This internal drive circuit controls an external FET used to divert a portion of the current
around a cell while the cell is being charged or adds to the current pulled from a cell during discharge in order to perform a
cell voltage balancing operation. This function is generally used to reduce the voltage on an individual cell relative to other
cells in the pack. The cell balancing FETs are turned on or off by an internal cell balance state machine or an external
controller.
18, 28, 29
VSS
Ground. This pin connects to the most negative terminal in the battery string.
19
VREF
Voltage Reference Output. This output provides a 1.8V reference voltage for the internal circuitry and for the external
microcontroller.
20, 21
XT1, XT2
22
TEMPO
23, 30
DNC
24
ADDR
25
SCL
26, 27
Temperature monitor inputs. These pins input the voltage across two external thermistors used to determine the
temperature of the cells and or the power FET. When this input drops below the threshold, an external over-temperature
condition exists.
Temperature monitor output control. This pin outputs a voltage to be used in a divider that consists of a fixed resistor and
a thermistor. The thermistor is located in close proximity to the cells or the power FET. The TEMPO output is connected
internally to the VREF voltage through a PMOS switch only during a measurement of the temperature, otherwise the TEMPO
output is off.
Do Not Connect
Serial Address. This is an address input for an I2C communication link to allow for two cascaded devices on one bus.
Serial Clock. This is the clock input for an I2C communication link.
SDAI, SDAO Serial Data. These are the data lines for an I2C interface. When connected together they form the standard bi-directional
interface for the I2C bus. When separated, they can use separate level shifters for a cascaded operation.
31
INT
Interrupt. This pin goes active low, when there is an external µC connected to the ISL94203 and µC communication fails to
send a slave byte within a watchdog timer period. This is a CMOS type output.
32
PSD
Pack Shutdown. This pin goes active high, when any cell voltage reaches the OVLO threshold (OVLO flag). Optionally, PSD is
also set if there is a voltage differential between any two cells that is greater than a specified limit (CELLF flag), or if there
is an open wire condition. This pin can be used for blowing a fuse in the pack or as an interrupt to an external µC.
33
FETSOFF
34
SD
Shutdown. This output indicates that the ISL94203 detected any failure condition that would result in the DFET turning off.
This could be undervoltage, overcurrent, over- or under-temperature, etc. The SD pin also goes active if there is any charge
overcurrent condition. This is an open drain output.
35
EOC
End-of-Charge. This output indicates that the ISL94203 detected a fully charged condition. This is defined by any cell voltage
exceeding an EOC voltage (as defined by an EOC value in EEPROM).
36
RGO
Regulator Output. This is the 2.5V regulator output.
37
CHMON
Charge Monitor. This input monitors the charger connection. When the IC is in the sleep mode, connecting this pin to the
charger wakes up the device. When the IC recovers from a charge overcurrent condition, this pin is used to monitor that the
charger is removed prior to turning on the power FETs. In a single path configuration, this pin and the LDMON pin connect
together.
38
LDMON
Load Monitor. This pin monitors the load connection. When the IC is in the sleep mode, connecting this pin to a load wakes
up the device. When the IC recovers from a discharge overcurrent or short circuit condition, this pin is used to monitor that
the load is removed prior to turning on the power FETs. In a single path configuration, this pin and the CHMON pin connect
together.
39, 40, 41
C3, C2, C1
FETSOFF. This input allows an external microcontroller to turn off both Power FET and CB outputs.
Charge Pump Capacitor Pins. These external capacitors are used for the charge pump driving the power FETs.
3
FN7626.2
December 5, 2012
ISL94203
Pin Descriptions (Continued)
PIN
NUMBER
SYMBOL
DESCRIPTION
42
DFET
Discharge FET Control. The ISL94203 controls the gate of a discharge FET through this pin. The power FET is an N-Channel
device. The FET is turned on by the ISL94203 if all conditions are acceptable. The ISL94203 will turn off the FET in the event
of an out of bounds condition. The FET can be turned off by an external microcontroller by writing to the CFET control bit.
The CFET output is also turned off by the FETSOFF pin. The FET output cannot be turned on by an external microcontroller
if there are any out of bounds conditions.
43
VDD
IC Supply Pin. This pin provides the operating voltage for the IC circuitry.
44
PCFET
Precharge FET Control. The ISL94203 controls the gate of a precharge FET through this pin. The power FET is an N-Channel
device. The FET is turned on by the ISL94203 if all conditions are acceptable. The ISL94203 will turn off the FET in the event
of an out of bounds condition. The FET can be turned off by an external microcontroller by writing to the PCFET control bit.
The PCFET output is also turned off by the FETSOFF pin. The FET output cannot be turned on by an external microcontroller
if there are any out of bounds conditions. Either the PCFET or the CFET turn on, but not both.
45
CFET
Charge FET Control. The ISL94203 controls the gate of a charge FET through this pin. The power FET is an N-Channel device.
The FET is turned on by the ISL94203 if all conditions are acceptable. The ISL94203 will turn off the FET in the event of an
out of bounds condition. The FET can be turned off by an external microcontroller by writing to the CFET control bit. The CFET
output is also turned off by the FETSOFF pin. The FET output cannot be turned on by an external microcontroller if there are
any out of bounds conditions. Either the PCFET or the CFET turn on, but not both.
46, 47
CSI2, CSI1
48
VBATT
PAD
GND
Current Sense Inputs. These pins connect to the ISL94203 current sense circuit. There is an external resistance across
which the circuit operates. The sense resistor is typically in the range of 0.2mΩ to 5mΩ.
Battery pack voltage input. This pin is used to monitor the voltage of the battery stack. The voltage is internally divided by
32 and connected to an ADC converter through a MUX.
Thermal Pad. This pad should connect to ground.
4
FN7626.2
December 5, 2012
ISL94203
N-CHANNEL FETs
P+
PACK+
VDD
+16V
30kΩ
220nF
CHMON
LDMON
C2
C1
DFET
VDD
C3
O.C.
WAKEUP
RECOVERY CIRCUIT
FET CONTROLS/CHARGE PUMP
VBATT
1kΩ
POWER ON
RESET STATE
MACHINE
VC8
330kΩ
4.7nF
10kΩ
20kΩ 1kΩ
CB8
CB8:1
VC7
330kΩ
4.7nF
10kΩ
20kΩ 1kΩ
EOC
EOC/SD
ERROR CONDITIONS
(OV, UV, SLP STATE MACHINES)
VSS
SD
CB STATE
MACHINE
VSS
FETSOFF
CB7
PSD
VC6
330kΩ
4.7nF
10kΩ
20kΩ 1kΩ
INT
RAM
CB5
VC4
1kΩ
20kΩ 4.7nF
10kΩ
330kΩ
1kΩ
20kΩ 4.7nF
CB4
VC3
10kΩ
330kΩ
CB3
VC2
1kΩ
20kΩ 4.7nF
10kΩ
330kΩ
CB2
VC1
1kΩ
20kΩ 4.7nF
10kΩ
CB1
VC0
BAT-
MEMORY
MANAGER
OSC
TIMING
AND
CONTROL
SCAN STATE
MACHINE
SCAN STATE
CB STATE
OVERCURRENT STATE
EOC/SD/ERROR STATE
LDO
RGO
REG
RGO (OUT)
SDAO
SDAI
I2C
SCL
ADDR
TEMPO
WATCHDOG TIMER
TEMP
330kΩ
EEPROM
REGISTERS
14-BIT
ADC
MUX
10kΩ
330kΩ
TEMP/VOLTAGE
MONITOR ALU
MUX
VC5
20kΩ 4.7nF
MUX
CB6
INPUT BUFFER/LEVEL SHIFTER/OPEN WIRE DETECT
BAT+
CFET
CURRENT SENSE GAIN AMPLIFIER
x5/x50/x500 GAIN
OVERCURRENT STATE MACHINE
PCFET
CS2
CS1
VDD
+16V
TEMP
VB/16
RGO/2
xT2
xT2
xT1
xT1
iT
TGAIN
x1/x2
VREF
VREF
VSS
PACK-
P-
FIGURE 2. BLOCK DIAGRAM
5
FN7626.2
December 5, 2012
ISL94203
Table of Contents
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Symbol Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
External Temperature Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Change in FET Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Temperature Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Discharge Overcurrent/Short Circuit Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charge Overcurrent Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
17
18
18
19
19
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power Path Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pack Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Battery Cell Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power-Up Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Wake-up Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Low Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Typical Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Cell Fail Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Open Wire Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Current and Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Current Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent and Short Circuit Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent and Short Circuit Response (Discharge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Response (Charge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcontroller Overcurrent FET Control Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage, Temperature, and Current Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Voltage Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage Detection/Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage Detection/Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Monitoring/Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcontroller Read of Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
27
28
29
29
29
32
33
34
35
36
38
38
Microcontroller FET Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Cell Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Cell Balance in Cascade Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
µC Control of Cell Balance FETs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Cell Balance FET Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Power FET Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
General I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Higher Voltage Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Packs with Fewer than 8 Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6
FN7626.2
December 5, 2012
ISL94203
EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Serial Interface Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock and Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
45
45
45
45
46
48
Register Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Registers: Summary (EEPROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Registers: Summary (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Registers: Detailed (EEPROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Registers: Detailed (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
PC Board Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Circuit Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Simple Stand Alone. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7
FN7626.2
December 5, 2012
ISL94203
Absolute Maximum Ratings (Note 4)
Thermal Information
Power Supply Voltage, VDD . . . . . . . . . . . . . . . . . VSS - 0.5V to VSS + 45.0V
Cell Voltage (VC, VBATT)
VCn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VBATT + 0.5V
VCn - VSS (n = 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 45.0V
VCn - VSS (n = 6, 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 36.0V
VCn - VSS (n = 4, 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 27.0V
VCn - VSS (n = 2, 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 17.0V
VCn - VSS (n = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 7.0V
VCn - VSS (n = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 3.0V
VCn - VC(n-1) (n = 2 to 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-3.0V to 7.0V
VC1 - VC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 7.0V
Cell Balance Pin Voltages (VCB)
VCBn - VCn-1, n = 1 to 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 7.0V
VCn - VCBn, n = 6 to 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 7.0V
Terminal Voltage
ADDR, xT1, xT2, FETSOFF, PSD, INT . . . . . . . . . . . . . . -0.5 to VRGO +0.5V
SCL, SDAI, SDAO, EOC, SD. . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to 5.5V
CFET, PCFET, C1, C2, C3 . . . . . . . VDD - 0.5V to VDD + 15.5V (60V max)
DFET, CHMON, LDMON . . . . . . . . . . . . . . -0.5V to VDD+ 15.0V (60V max)
Current Sense Voltage
VBATT, CS1, CS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD +1.0V
VBATT - CS1, VBATT - CS2 . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +0.5V
CS1 - CS2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +0.5V
ESD Rating
Human Body Model (Tested per JESD22-A114E . . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A . . . . . . . . . . . . . . . . . . 100V
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
48 Ld QFN (Notes 5, 6) . . . . . . . . . . . . . . . .
28
0.75
Continuous Package Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . .400mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Operating Voltage:
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V to 36V
VCn-VC(n-1) Specified Range . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V to 4.3V
VCn-VC(n-1) Extended Range . . . . . . . . . . . . . . . . . . . . . . . . . 1.0V to 4.4V
VCn-VC(n-1) Maximum Range (any cell) . . . . . . . . . . . . . . . . 0.5V to 4.8V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. Devices are characterized, but not production tested, at Absolute Maximum Voltages.
5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VDD = 26.4V, TA = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply over
operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
Power-up Condition – Threshold
Rising
(Device becomes operational)
TEST CONDITION
MAX
(Note 7)
UNIT
VDD minimum voltage at which device
operation begins
(CFET turns on; CHMON = VDD)
6.0
V
VPORR2
CHMON minimum voltage at which device
operation begins
(CFET turns on; VDD > 6.0V)
VDD
V
3.0
V
VPORF
VDD minimum voltage device remains
operational (RGO turns off)
2.5V Regulated Voltage
VRGO
IRGO = 3mA
1.8V Reference Voltage
VREF
IVBATT
Input leakage current; NORMAL/IDLE/DOZE
VDD = 33.6V
Input leakage current; SLEEP/Power Down
VDD = 33.6V
8
TYP
VPORR1
Power-Down Condition – Threshold
Falling
VBATT Input Current - VBATT
MIN
(Note 7)
2.4
2.5
2.6
V
1.79
1.8
1.81
V
38
45
µA
1
µA
FN7626.2
December 5, 2012
ISL94203
Electrical Specifications
VDD = 26.4V, TA = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply over
operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
VDD Supply Current
Input Bias Current
TEST CONDITION
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
IVDD1
Device active (Normal Mode)
(No error conditions)
CFET, PCFET, DFET = OFF; VDD = 33.6V
310
370
µA
IVDD2
Device active (IDLE mode)
(No error conditions)
IDLE = 1
CFET, PCFET, DFET = OFF; VDD = 33.6V
215
275
µA
IVDD3
Device active (DOZE mode)
(No error conditions)
DOZE = 1
CFET, PCFET, DFET = OFF; VDD = 33.6V
210
265
µA
IVDD4
FET Drive Current
(IVDD increase when FETs are on NORMAL/IDLE/DOZE modes); VDD = 33.6V
215
IVDD5
Device active (SLEEP mode);
SLEEP = 1; VDD = 33.6V
0°C to +60°C
-40°C to +85°C
IVDD6
Power-Down
PDWN = 1; VDD = 33.6V
ICS1
VDD = VBATT = VCS1 = VCS2 = 33.6V
(Normal, Idle, Doze)
13
10
VDD = VBATT = VCS1 = VCS2 = 33.6V
(Sleep, Power-Down)
0°C to +60°C
-40°C to +85°C
ICS2
µA
30
50
µA
1
µA
15
µA
µA
1
3
VDD = VBATT = VCS1 = VCS2 = 33.6V
(Normal, Idle, Doze)
10
VDD = VBATT = VCS1 = VCS2 = 33.6V
(Sleep, Power Down)
0°C to +60°C
-40°C to +85°C
15
µA
1
3
µA
VCn Input Current
IVCN
Cell input leakage current
AO2:AO0 = 0000H
(NORMAL/IDLE/DOZE; Not sampling cells)
-1
1
µA
CBn Input Current
ICBN
Cell Balance pin leakage current
(No balance active)
-1
1
µA
-25
15
mV
TEMPERATURE MONITOR SPECIFICATIONS
External Temperature Accuracy
VXT1
Internal Temperature Monitor Output
(See “Temperature
Monitoring/Response” on page 36)
9
TINT25
VINTMON
External temperature monitoring error. ADC
voltage error when monitoring xT1 input.
TGain = 0; (xTn = 0.2V to 0.737V)
[iTB:iT0]10*1.8/4095/GAIN
GAIN = 2 (TGain bit = 0)
Temperature = 25°C
Change in
[iTB:iT0]10*1.8/4095/GAIN
GAIN = 2 (TGain bit = 0)
Temperature = -40°C to +85°C
0.276
V
1.0
mV/°C
FN7626.2
December 5, 2012
ISL94203
Electrical Specifications
VDD = 26.4V, TA = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply over
operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITION
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
CELL VOLTAGE MONITOR SPECIFICATIONS
Cell Monitor Voltage Accuracy
VADCR
Cell Monitor Voltage Accuracy
VADC
VBATT Voltage Accuracy
VBATT
Relative Cell Measurement Error
(Max absolute cell measurement error Min absolute cell measurement error)
VCn - VC(n-1) = 2.4V to 4.2V; 0°C to +60°C
VCn - VC(n-1) = 0.1V to 4.7V; 0°C to +60°C
VCn - VC(n-1) = 0.1V to 4.7V; -40°C to +85°C
3.0
10
15
30
mV
Absolute Cell Measurement Error
(Cell measurement error compared with
voltage at the cell)
VCn - VC(n-1) = 2.4V to 4.2V; 0°C to +60°C
VCn - VC(n-1) = 0.1V to 4.7V; 0°C to +60°C
VCn - VC(n-1) = 0.1V to 4.7V; -40°C to +85°C
-15
-20
-30
15
20
30
mV
VBATT - [VBB:VB0]10*32*1.8/4095;
0°C to +60°C
-40°C to +85°C
-200
-270
200
270
mV
CURRENT SENSE AMPLIFIER SPECIFICATIONS
Charge Current Threshold
VCCTH
Discharge Current Threshold
VDCTH
Current Sense Accuracy
-100
μV
VCS1-VCS2, DCHING indicates discharge
current; VCS1 = 26.4V
100
μV
VIA1
VIA1 = ([ISNSB:ISNS0]10*1.8/4095)/5;
CHING bit set
Gain = 5
VCS1 = 26.4V, VCS2 - VCS1 = + 100mV
97
102
107
mV
VIA2
VIA2 = ([ISNSB:ISNS0]10*1.8/4095)/5;
DCHING bit set
Gain = 5
VCS1 = 26.4V, VCS2 - VCS1 = - 100mV
-107
-102
-97
mV
VIA3
VIA3 = ([ISNSB:ISNS0]10*1.8/4095)/50;
CHING bit set
Gain = 50
VCS1 = 26.4V, VCS2 - VCS1 = + 10mV
8.0
10.0
12.0
mV
VIA4
VIA4 = ([ISNSB:ISNS0]10*1.8/4095)/50;
DCHING bit set
Gain = 50
VCS1 = 26.4V, VCS2 - VCS1 = - 10mV
-12.0
-10.0
-8.0
mV
VIA5
VIA3 = ([ISNSB:ISNS0]10*1.8/4095)/500;
CHING bit set
Gain = 500
VCS1 = 26.4V, VCS2 - VCS1 = + 1mV
0°C to +60°C
-40°C to +85°C
0.5
0.4
1.0
1.5
1.6
mV
VIA4 = ([ISNSB:ISNS0]10*1.8/4095)/500;
DCHING bit set.
Gain = 500
VCS1=26.4V, VCS2 - VCS1 = - 1mV
0°C to +60°C
-40°C to +85°C
-1.5
-1.6
-1.0
-0.5
-0.4
mV
VIA6
10
VCS1-VCS2, CHING indicates charge current
VCS1 = 26.4V
FN7626.2
December 5, 2012
ISL94203
Electrical Specifications
VDD = 26.4V, TA = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply over
operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
VOCD = 4mV [OCD2:0] = 0,0,0
2.6
4
5.4
mV
VOCD = 8mV [OCD2:0] = 0,0,1
6.4
8
9.6
mV
VOCD = 16mV [OCD2:0] = 0,1,0
12.8
16
19.2
mV
VOCD = 24mV [OCD2:0] = 0,1,1
20
25
30
mV
VOCD = 32mV [OCD2:0] = 1,0,0 (DEFAULT)
26.4
33
39.6
mV
VOCD = 48mV [OCD2:0] = 1,0,1
42.5
50
57.5
mV
VOCD = 64mV [OCD2:0] = 1,1,0
60.3
67
73.7
mV
VOCD = 96mV [OCD2:0] = 1,1,1
90
100
110
mV
TEST CONDITION
OVERCURRENT/SHORT CIRCUIT PROTECTION SPECIFICATIONS
Discharge Overcurrent Detection
Threshold
VOCD
160
ms
Discharge Overcurrent Detection Time
tOCDT
[OCDTA:OCDT0] = 0A0H (160ms) (DEFAULT)
Range:
0ms to 1023ms 1ms/step
0s to 1023s; 1s/step
Short Circuit Detection Threshold
VSCD
VSCD = 16mV [SCD2:0] = 0,0,0
10.4
16
21.6
mV
VSCD = 24mV [SCD2:0] = 0,0,1
18
24
30
mV
VSCD = 32mV [SCD2:0] = 0,1,0
26
33
40
mV
VSCD = 48mV [SCD2:0] = 0,1,1
42
49
56
mV
VSCD= 64mV [SCD2:0] = 1,0,0
60
67
74
mV
VSCD = 96mV [SCD2:0] = 1,0,1 (DEFAULT)
90
100
110
mV
VSCD =128mV [SCD2:0] = 1,1,0
127
134
141
mV
VSCD =256mV [SCD2:0] = 1,1,1
249
262
275
mV
200
µs
Short Circuit Current Detection Time
tSCT
[SCTA:SCT0] = 0C8H (200µs) (DEFAULT)
Range:
0µs to 1023µs; 1µs/step
0ms to 1023ms 1ms/step
Charge Overcurrent Detection
Threshold
VOCC
VOCC = 1mV [OCC2:0] = 0,0,0
0.2
1
2.1
mV
VOCC= 2mV [OCC2:0] = 0,0,1
0.7
2
3.3
mV
VOCC = 4mV [OCC2:0] = 0,1,0
2.8
4
5.2
mV
VOCC= 6mV [OCC2:0] = 0,1,1
4.5
6
7.5
mV
VOCC = 8mV [OCC2:0] = 1,0,0 (DEFAULT)
6.6
8
9.8
mV
VOCC= 12mV [OCC2:0] = 1,0,1
9.6
12
14.4
mV
VOCC = 16mV [OCC2:0] = 1,1,0
14.5
17
19.6
mV
VOCC= 24mV [OCC2:0] = 1,1,1
22.5
25
27.5
mV
Overcurrent Charge Detection Time
tOCCT
160
[OCCTA:OCCT0] = 0A0H (160ms) (DEFAULT)
Range:
0ms to 1023ms 1ms/step
0s to 1023s; 1s per step
ms
Charge Monitor Input Threshold
(Falling Edge)
VCHMON
µCCMON bit = “1”; CMON_EN bit = “1”
8.2
8.9
9.8
V
Load Monitor Input Threshold
(Rising Edge)
VLDMON
µCLMON bit = “1”; LMON_EN bit = “1”
0.45
0.6
0.75
V
Load Monitor Output Current
ILDMON
µCLMON bit = “1”; LMON_EN bit = “1”
11
62
µA
FN7626.2
December 5, 2012
ISL94203
Electrical Specifications
VDD = 26.4V, TA = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply over
operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITION
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
VOLTAGE PROTECTION SPECIFICATIONS
Overvoltage Lock-out Threshold
(Rising Edge - Any cell)
[VCn-VC(n-1)]
VOVLO
[OVLOB:OVLO0] = 0E80H (4.35V) (DEFAULT)
Range: 12-bit value (0V to 4.8V)
4.35
V
Overvoltage Lock-out Recovery
Threshold - All cells
VOVLOR
Falling edge
VOVR
V
Undervoltage Lock-out Threshold
(Falling Edge - Any Cell)
[VCn-VC(n-1)]
VUVLO
[UVLOB:UVLO0] = 0600H (1.8V) (DEFAULT)
Range: 12-bit value (0V to 4.8V)
1.8
V
Undervoltage Lock-out Recovery
Threshold - All Cells
VUVLOR
Rising edge
VUVR
V
Overvoltage Lock-out Detection Time
tOVLO
Normal Operating Mode
5 consecutive samples over the limit
(min = 160ms, max = 192ms)
176
ms
Undervoltage Lock-out Detection
Time
tUVLO
Normal Operating Mode
5 consecutive samples under the limit
(min = 160ms, max = 192ms)
176
ms
Overvoltage Threshold
(Rising Edge - Any Cell)
[VCn-VC(n-1)]
VOV
[OVLB:OVL0] = 0E2AH (4.25V) (DEFAULT)
Range: 12-bit value (0V to 4.8V)
4.25
V
Overvoltage Recovery Voltage
(Falling Edge - All cells)
[VCn-VC(n-1)]
VOVR
[OVRB:OVR0] = 0DD5H (4.15V) (DEFAULT)
Range: 12-bit value (0V to 4.8V)
4.15
V
Overvoltage Detection/Release Time
tOVT
[OVTA:OVT0] = 201H (1s) (DEFAULT) Range:
0ms to 1023ms; 1ms/step
0s to 1023s; 1s/step
1
s
Undervoltage Threshold
(Falling Edge - Any Cell)
[VCn-VC(n-1)]
VUV
[UVLB:UVL0] = 0900H (2.7V) (DEFAULT)
Range: 12-bit value (0V to 4.8V)
2.7
V
Undervoltage Recovery Voltage
(Rising Edge - All cells)
[VCn-VC(n-1)]
VUVR
[UVRB:UVR0] = 0A00H (3.0V) (DEFAULT)
Range: 12-bit value (0V to 4.8V)
3.0
V
Undervoltage Detection Time
tUVT
[UVTA:UVT0] = 201H (1s) (DEFAULT)
Range:
0ms to 1023ms; 1ms/step
0s to 1023s; 1s/step
1
s
Undervoltage Release Time
tUVTR
[UVTA:UVT0] = 201H (1s) + 2s (DEFAULT)
Range:
(0ms to 1023ms) + 2s; 1ms/step
(0s to 1023s) + 2s; 1s/step
3
s
Sleep Voltage Threshold
(Falling Edge - Any Cell)
[VCn-VC(n-1)]
VSLL
[SLLB:SLL0] = 06AAH (2.0V) (DEFAULT)
Range: 12-bit value (0V to 4.8V)
2.0
V
Sleep Detection Time
tSLT
[SLTA:SLT0] = 201H (1s) (DEFAULT) Range:
0ms to 1023ms; 1ms/step
0s to 1023s; 1s/step
1
s
Low Voltage Charge Threshold
(Falling Edge - Any Cell)
[VCn-VC(n-1)]
VLVCH
[LVCHB:LVCH0] = 07AAH (2.3V) (DEFAULT)
Range: 12-bit value (0V to 4.8V)
Pre-charge if any cell is below this voltage
2.3
V
Low Voltage Charge Threshold
Hysteresis
VLVCHH
117
mV
12
FN7626.2
December 5, 2012
ISL94203
Electrical Specifications
VDD = 26.4V, TA = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply over
operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
End of Charge Threshold
(Rising Edge - Any cell)
[VCn-VC(n-1)]
VEOC
End-of-Charge Threshold Hysteresis
VEOCH
TEST CONDITION
MIN
(Note 7)
[EOCSB:EOCS0] = 0E00H (4.2V) (DEFAULT)
Range: 12-bit value (0V to 4.8V)
TYP
MAX
(Note 7)
UNIT
4.2
V
117
mV
Sleep Mode Timer
tSMT
[MOD7:MOD0] = 0DH (off)
(DEFAULT)
Range:
0s to 255 minutes
90
min
Watchdog Timer
tWDT
[WDT4:WDT0] = 1FH (31s) (DEFAULT)
Range: 0s to 31s
31
s
TEMPERATURE PROTECTION SPECIFICATIONS
Internal Temperature Shutdown
Threshold
TITSD
[IOTSB:IOTS0] = 02D8H
115
°C
Internal Temperature Recovery
TITRCV
[IOTRB:IOTR0] = 027DH
95
°C
External Temperature Output Voltage
V TEMPO
Voltage output at TEMPO pin (during
temperature scan); ITEMPO = 1mA
External Temperature Limit Threshold
(Hot) - xT1 or xT2
Charge, Discharge,
Cell Balance
(see Figure 3)
TXTH
xTn Hot threshold. Voltage at V TEMPI,
xT1 or xT2 = 04B6H
TGain = 0
~+55°C; thermistor = 3.535k
Detected by COT, DOT, CBOT bits = 1
0.265
V
External Temperature Recovery
Threshold (Hot) - xT1 or xT2
Charge, Discharge,
Cell Balance
(see Figure 3)
TXTHR
xTn Hot Recovery Voltage at V TEMPI
xT1 or xT2 = 053EH
TGain = 0
(~+50°C; thermistor = 4.161k)
Detected by COT, DOT, CBOT bits = 0
0.295
V
2.3
2.45
2.6
V
External Temperature Limit Threshold
(Cold) - xT1 or xT2
Charge, Discharge,
Cell Balance
(see Figure 3)
TXTC
xTn Cold Threshold. Voltage at VTEMPI
xT1 or xT2 = 0BF2H
TGain = 0
(~ -10°C; thermistor = 42.5k)
Detected by CUT, DUT, CBUT bits
0.672
V
External Temperature Recovery
Threshold (Cold) - xT1 or xT2
Charge, Discharge,
Cell Balance
(see Figure 3)
TXTCH
xTn Cold Recovery Voltage at V TEMPI. xT1 or
xT2 = 0A93H
TGain = 0
(~5°C; thermistor = 22.02k)
Detected by CUT, DUT, CBUT bits
0.595
V
CELL BALANCE SPECIFICATIONS
Cell Balance FET Gate Drive Current
Cell Balance Max Voltage Threshold
(Rising Edge - Any cell)
[VCMAX]
VCBMX
Cell Balance Max Threshold
Hysteresis
VCBMXH
Cell Balance Min Voltage Threshold
(Falling Edge - Any cell)
[VCMIN]
VCBMN
Cell Balance Min Threshold Hysteresis
VCBMNH
13
VC1 to VC5 (current out of pin)
15
25
35
µA
VC6 to VC8 (current into pin)
15
25
35
µA
[CBVUB:CBVU0] = 0E00H (4.2V) (DEFAULT)
Range: 12-bit value (0V to 4.8V)
[CBVLB:CBVL0] = 0A00H (3.0V) (DEFAULT)
Range: 12-bit value (0V to 4.8V)
4.2
V
117
mV
3.0
V
117
mV
FN7626.2
December 5, 2012
ISL94203
Electrical Specifications
VDD = 26.4V, TA = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply over
operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
Cell Balance Max Voltage Delta
Threshold
(Rising Edge - Any Cell)
[VCn-VC(n-1)]
VCBDU
Cell Balance Max Voltage Delta
Threshold Hysteresis
VCBDUH
TEST CONDITION
MIN
(Note 7)
[CBDUB:CBD0] = 06AAH (2.0V) (DEFAULT)
Range: 12-bit value (0V to 4.8V)
TYP
MAX
(Note 7)
UNIT
2.0
V
117
mV
WAKE UP SPECIFICATIONS
Device CHMON Pin Voltage Threshold
(Wake on Charge)
(Rising Edge)
VWKUP1
CHMON pin rising edge
Device wakes up and sets SLEEP flag LOW
7.0
8.0
9.0
V
Device LDMON Pin Voltage Threshold
(Wake on Load)
(Falling Edge)
VWKUP2
LDMON pin falling edge
Device wakes up and sets SLEEP flag LOW.
0.15
0.4
0.7
V
OPEN WIRE SPECIFICATIONS
Open Wire Current
IOW
Open Wire Detection Threshold
1.0
mA
VOW1
VCn-VC(n-1); VCn is open. (n= 2, 3, 4, 5, 6, 7,
8). Open wire detection active on the VCn
input.
-0.3
V
VOW2
VC1-VC0; VC1 is open. Open wire detection
active on the VC1 input.
0.4
V
VOW3
VC0-VSS; VC0 is open. Open wire detection
active on the VC0 input.
1.25
V
FET CONTROL SPECIFICATIONS
DFET Gate Voltage
CFET Gate Voltage (ON)
PCFET Gate Voltage (ON)
VDFET1
(ON) 100µA load; VDD = 36V
47
52
57
V
VDFET2
(ON) 100µA load; VDD = 6V
8
9
10
V
VDFET3
(OFF)
VCFET1
(ON) 100µA load; VDD = 36V
47
52
57
V
VCFET2
(ON) 100µA load; VDD = 6V
8
9
10
V
VCFET3
(OFF)
VPFET1
(ON) 100µA load; VDD = 36V
47
52
57
V
VPFET2
(ON) 100µA load; VDD = 6V
8
9
10
V
VPFET3
(OFF)
0
V
VDD
V
VDD
V
FET Turn-Off Current (DFET)
IDF(OFF)
14
15
16
mA
FET Turn-Off Current (CFET)
ICF(OFF)
9
13
17
mA
FET Turn-Off Current (PCFET)
IPF(OFF)
9
13
17
mA
FETSOFF Rising Edge Threshold
VFO(IH)
FETSOFF rising edge threshold. Turn off FETs
1.8
V
FETSOFF Falling Edge Threshold
VFO(IL)
FETSOFF falling edge threshold. Turn on FETs
1.2
V
SERIAL INTERFACE CHARACTERISTICS (Note 8)
Input Buffer Low Voltage (SCL, SDA)
VIL
Voltage relative to VSS of the device
-0.3
VRGO x 0.3
V
Input Buffer High Voltage (SCL, SDAI,
SDAO)
VIH
Voltage relative to VSS of the device
VRGO x 0.7
VRGO + 0.1
V
VOL
IOL = 1mA
0.4
V
Output Buffer Low Voltage (SDA)
SDA and SCL Input Buffer Hysteresis
14
I2CHYST
Sleep bit = 0
0.05 x VRGO
V
FN7626.2
December 5, 2012
ISL94203
Electrical Specifications
VDD = 26.4V, TA = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply over
operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
SCL Clock Frequency
TEST CONDITION
MIN
(Note 7)
TYP
fSCL
MAX
(Note 7)
UNIT
400
kHz
Pulse Width Suppression Time at SDA
and SCL Inputs
tIN
Any pulse narrower than the max spec is
suppressed.
50
ns
SCL Falling Edge to SDA Output Data
Valid
tAA
From SCL falling crossing VIH (min), until SDA
exits the VIL (max) to VIH (min) window
0.9
µs
Time the Bus Must Be Free Before
Start of New Transmission
tBUF
SDA crossing VIH (min) during a STOP
condition to SDA crossing VIH (min) during the
following START condition
1.3
µs
Clock Low Time
tLOW
Measured at the VIL (max) crossing
1.3
µs
Clock High Time
tHIGH
Measured at the VIH (min) crossing
0.6
µs
Start Condition Setup Time
tSU:STA
SCL rising edge to SDA falling edge, both
crossing the VIH (min) level
0.6
µs
Start Condition Hold Time
tHD:STA
From SDA falling edge crossing VIL(max) to
SCL falling edge crossing VIH(min)
0.6
µs
Input Data Setup Time
tSU:DAT
From SDA exiting the VIL(max) to VIH(min)
window to SCL rising edge crossing VIL(min)
100
ns
Input Data Hold Time
tHD:DAT
From SCL falling edge crossing VIH (min) to
SDA entering the VIL (max) to VIH (min)
window
0
Stop Condition Setup Time
tSU:STO
From SCL rising edge crossing VIH (min) to
SDA rising edge crossing VIL(max)
0.6
µs
Stop Condition Hold Time
tHD:STO
From SDA rising edge to SCL falling edge.
Both crossing VIH (min)
0.6
µs
0
ns
0.9
µs
Data Output Hold Time
tDH
From SCL falling edge crossing VIL(max) until
SDA enters the VIL (max) to VIH (min) window
SDA and SCL Rise Time
tR
From VIL (max) to VIH (min)
300
ns
SDA and SCL Fall Time
tF
From VIH (min) to VIL(max)
300
ns
SDA and SCL Bus Pull-up Resistor- Off
Chip
ROUT
Input Leakage (SCL, SDA)
ILI
EEPROM Write Cycle Time
tWR
Maximum is determined by tR and tF
For CB = 400pF, max is 2kΩ ~ 2.5kΩ
For CB = 40pF, max is 15kΩ ~ 20kΩ
1
-10
+25°C
kΩ
10
µA
30
ms
NOTES:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Device MIN and/or MAX values are based on
temperature limits established by characterization and are not production tested.
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
15
FN7626.2
December 5, 2012
ISL94203
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
WAVEFORM
MUST BE
STEADY
WILL BE
STEADY
MA Y CHANGE
FROM LOW
TO HIGH
WILL CHANGE
FROM
LOW
TO HIGH
MA Y CHANGE
FROM HIGH
TO LOW
WILL CHANGE
FROM HIGH
TO LOW
INPUTS
OUTPUTS
DON’T CARE:
CHANGES
ALLOWED
CHANGING:
STATE NOT
KNOWN
N/A
CENTER LINE
IS HIGH
IMPEDANCE
Timing Diagrams
External Temperature Configuration
TEMPO PIN
22kΩ
22kΩ
xT1 PIN
DIGITAL TEMPERATURE VOLTAGE READING =
xTn * 2 (TGAIN BIT = 0)
xTn * 1 (TGAIN BIT = 1)
xT2 PIN
10kΩ
10kΩ
THERMISTORS: 10k, MuRata XH103F
FIGURE 3. EXTERNAL TEMPERATURE CONFIGURATION
Wake-up Timing
LDMON PIN
VWKUP2
<1µs
IN_SLEEP BIT
CAN GO TO
SLEEP
CAN GO TO SLEEP
CAN GO TO
SLEEP
CAN GO TO SLEEP
VWKUP1
CHMON PIN
<1µs
IN_SLEEP BIT
~140ms
DFET/CFET
FIGURE 4. WAKE-UP TIMING (FROM SLEEP)
16
FN7626.2
December 5, 2012
ISL94203
VWKUP1
CHMON PIN
~3s
256ms
LDMON CHECK
TURN ON FETS IF NO PACK FAULTS
DFET/CFET
RGO
~4ms
2
I C COMMUNICATION
FIGURE 5. POWER-UP TIMING (FROM POWER UP/SHUTDOWN)
Change in FET Control
SCL
BIT
3
SDA
BIT
2
BIT
1
BIT
0
BIT
1
ACK
BIT
0
ACK
DATA
~1µs or ~500µs IF BOTH FETS OFF
DFET/CFET TURN ON
tFTON
10%
~1µs
90%
tFTOFF
90%
10%
FIGURE 6. I2C FET CONTROL TIMING
VFO(OFF)
VFO(ON)
FETSOFF PIN
~1µs
~1µs
DFET/CFET TURN ON
FIGURE 7. FETSOFF FET CONTROL TIMING
17
FN7626.2
December 5, 2012
ISL94203
Automatic Temperature Scan
MONITOR TIME = 120µs
128ms
1024ms
2048ms
2.5V
TEMPO PIN
EXTERNAL
TEMPERATURE
OVER-TEMPERATURE
THRESHOLD
UNDER-TEMP
OVER-TEMP
xTn
xT2
xT2
xT1
MONITOR TEMPERATURE DURING THIS
TIME PERIOD
xT1
DELAY TIME = 20µs
DELAY TIME = 20µs
CBOT, DOT, COT BITs
FET SHUTDOWN OR CELL BALANCE TURN OFF
(IF ENABLED)
SEE FIGURE 3 FOR TEST CIRCUIT
FIGURE 8. AUTOMATIC TEMPERATURE SCAN
Serial Interface Timing Diagrams
BUS TIMING
tHIGH
tF
tLOW
tR
SCL
tSU:STA
tSU:DAT
tHD:STA
tHD:DAT
tSU:STO
SDA
(INPUT TIMING)
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
FIGURE 9. SERIAL INTERFACE BUS TIMING
18
FN7626.2
December 5, 2012
ISL94203
Discharge Overcurrent/Short Circuit Monitor
LOAD RELEASES DURING THIS TIME
256ms
VLDMON
3 sec
LDMON PIN
DETECTS 2 LDMON PULSES ABOVE THRESHOLD
VSC
VOCD
VDSENSE
tSCD
tSCD
tOCD
‘1’
‘0’
DOC BIT
‘1’
‘0’
DSC BIT
2.5V
SD
OUTPUT
µC REGISTER 1 READ
µC IS OPTIONAL
µC REGISTER 1 READ
LDMON DETECTS LOAD RELEASE
RESETS DOC, SCD BIT, TURNS ON FET
VDD+15V
LDMON DETECTS LOAD RELEASE
RESETS DOC, SCD BIT, TURNS ON FET
DFET
OUTPUT
ISL94203 TURNS ON DFET
(µCFET BIT = 0)
FIGURE 10. DISCHARGE/SHORT CIRCUIT MONITOR
Charge Overcurrent Monitor
(Assumes NO_OCCR bit is ‘0’)
CHARGER RELEASES
DETECTS 2 CHMON PULSES BELOW THRESHOLD
CHMON PIN
VCHMON
VCSENSE
VOCC
tOCC
COC BIT
‘1’
‘0’
2.5V
SD
OUTPUT
REGISTER 1 READ
VDD+15V
CHMON DETECTS CHARGER RELEASE
RESETS DOC, SCD BIT, TURNS ON FET
CFET
OUTPUT
ISL94203 TURNS ON CFET
(µCFET BIT = 0)
FIGURE 11. CHARGE OVERCURRENT MONITOR
19
FN7626.2
December 5, 2012
ISL94203
Functional Description
Power Path Connection
This IC is intended to be a stand-alone battery pack monitor, so it
provides monitor and protection functions without using an
external microcontroller.
Figure 12 shows the main power path connections for a single
charge/discharge path. Figure 13 shows the connection for
separate charge/discharge paths.
N-Channel FETs
The part locates the power control FETs on the high side with a
built-in charge pump for driving N-Channel FETs. The current
sense resistor is also on the high side.
CHG+
DISCHG+
PACK+
BAT+
• 14-bit ADC converter, with voltage readings trimmed and
saved as 12-bit results
4.7nF
• 1.8V voltage reference (0.8% accurate)
1kΩ
4.7nF
1kΩ
• 2.5V regulator, with the voltage maintained during sleep
4.7nF
• Automatic scan of the cell voltages; overvoltage, undervoltage,
and sleep voltage monitoring
• Current sense monitor with gain that provides the ability to
read the current sense voltage;
LDMON
DFET
VDD
VC8
VC7
FIGURE 12. SINGLE PATH FET DRIVE/POWER SUPPLY DETAIL
• Selectable overcurrent detection settings
8 Discharge overcurrent thresholds
8 Charge overcurrent thresholds
8 Short circuit thresholds
12-bit programmable discharge overcurrent delay time
12-bit programmable charge overcurrent delay time
12-bit programmable short circuit delay time
VBATT
CHMON
• Input level shifter to enable monitoring of battery stack
voltages
-
CS2
1kΩ
PCFET
CS1
The ISL94203 includes:
CFET
Power is minimized in all areas, with parts of the circuit powered
down a majority of the time, to extend battery life. At the same
time, the RGO output stays on, so that any connected
microcontroller can remain on most of the time.
The figures show Schottky diodes on the VDD pin. These are to
maintain the voltage on the VDD pin during high current
conditions or when the Charge FET is OFF. These are not needed
if VDD can be maintained within 0.5V of VBATT.
The CHMON pin connects to the pack pin that receives the charge
and the LDMON pin connects to the pack pin that drives the load.
For the single path application, these pins can tie together.
N-Channel FETs
BAT+
4.7nF
1kΩ
4.7nF
1kΩ
4.7nF
VBATT
CS2
LDMON
CHMON
CS1
1kΩ
VDD
DISCHG+
DFET
• EEPROM for storing operating parameters and a user area for
general purpose pack information
PCFET
CHG+
CFET
• Second external temperature sensor for use in monitoring the
pack or power FET temperatures
VC8
VC7
FIGURE 13. DUAL PATH FET DRIVE/POWER SUPPLY DETAIL
20
FN7626.2
December 5, 2012
ISL94203
Pack Configuration
Power-Up Operation
A register in EEPROM (CELLS) identifies the number of cells that
are supposed to be present, so the ISL94203 only scans these
cells. This register is also used for the cell balance operation. The
register contents are a 1:1 representation of the cells connected
to the pack. For example, in a 6 cell pack, the value in CELLS is
‘11100111’ (CFH) which indicates that cells 1, 2, 3, 6, 7, and 8
are connected. Also see Figure 14 on page 21.
When the ISL94203 first connects to the battery pack, it is
unknown which pins connect first or in what order. When the VDD
and VSS pins connect, the device enters the power-down state. It
remains in this state until a charger is connected. The device will
also power-up if the CHMON pin is connected to the VDD pin
through an outside resistor to simplify the PCB manufacture. It is
possible that the pack powers up automatically when the battery
stack is connected due to momentary conduction through the
power FET G-S and G-D capacitors.
Battery Cell Connections
Suggested connections for pack configurations varying from 3
cells to 8 cells are shown in Figure 14.
8 CELLS
Once the charger connects (or CHMON connects), the internal
power supply turns on. This powers up all internal supplies and
starts the state machine. If some cells are not connected, the
state machine recognizes this, either through the open wire test
(see “Typical Operating Conditions” on page 24) or because the
6 CELLS
7 CELLS
VC8
VC8
VC8
CB8
CB8
CB8
VC7
VC7
VC7
CB7
CB7
CB7
VC6
VC6
VC6
CB6
CB6
CB6
VC5
VC5
VC5
CB5
CB5
CB5
VC4
VC4
VC4
CB4
CB4
CB4
VC3
VC3
VC3
CB3
CB3
CB3
VC2
VC2
VC2
CB2
CB2
CB2
VC1
VC1
VC1
CB1
CB1
CB1
VC0
VSS
VC0
VSS
VC0
VSS
4 CELLS
5 CELLS
3 CELLS
VC8
VC8
VC8
CB8
CB8
CB8
VC7
VC7
VC7
CB7
CB7
CB7
VC6
VC6
VC6
CB6
CB6
CB6
VC5
VC5
VC5
CB5
CB5
CB5
VC4
VC4
VC4
CB4
CB4
CB4
VC3
VC3
VC3
CB3
CB3
CB3
VC2
VC2
VC2
CB2
CB2
CB2
VC1
VC1
VC1
CB1
CB1
CB1
VC0
VSS
VC0
VSS
VC0
VSS
NOTE: MULTIPLE CELLS CAN BE CONNECTED IN PARALLEL
FIGURE 14. BATTERY CONNECTION OPTIONS
21
FN7626.2
December 5, 2012
ISL94203
monitored cell voltage reads zero, when the “CELLS” register
indicates that there should be a voltage at that pin. If the cell
voltages do not read correctly, then the ISL94203 remains in the
POR loop until conditions are valid for power-up (It is for this
reason that the factory default for the device is 3 Cells. When
manufacturing the application board, cells 1, 2, and 8 must be
connected to power up. If other cells are connected it is OK, but
for the other cells to be monitored, the CELLS register needs to
be changed).
If the inputs all read good during this sequence, then the state
machine enters the normal monitor state. In the normal state, if
all cell voltages read good and there are no overcurrent or
temperature issues, and there is no load, the FETs turn on. To
determine if there is a load, the device does a load check. This
• DO A VOLTAGE SCAN.
operation waits for about three seconds and then must see no
load for two successive load monitor cycles (256ms apart).
During the POR operation, the RAM registers are all reset to
default conditions from values saved in the EEPROM.
When the cell voltages drop, the ISL94203 remains on if the VDD
voltage remains above 1V and the VRGO voltage is above 2.25V.
This is to maintain operation of the device in the event of a short
drop in cell voltage due to a pack short circuit condition. In the
event of a longer battery stack voltage drop, then the device will
return to a power-down condition if VDD drops below a POR
threshold of about 3.5V when VRGO is below 2.25V (see
Figures 15 and 16).
POWER-DOWN
STATE
• ONLY LOOK AT CELLS THAT ARE
SPECIFIED IN THE “CELL” REG.
• IF ALL CELL VOLTAGES AND TEMPS
ARE OK, DO A LOAD TEST.
• IF THERE ARE ANY ERRORS, KEEP
SCANNING VOLTAGES,
TEMPERATURES, AND LOAD AT
NORMAL SCAN RATES.
BATTERY STACK CONNECT
AND VDD > VPOR
CHARGER CONNECT
POWER ON RESET
FETS OFF, NO CURRENT SCAN.
SCAN ONLY VOLTAGES, TEMP, LOAD
VRGO < 1.2V
OR
(ANY CELL < VUVLO FOR 160ms AND
UVLOPD = 1)
ALL VOLTAGES OK
TEMP OK
NO LOAD
OR
PDWN BIT SET
NORMAL OPERATING
MODE
FIGURE 15. POWER ON RESET STATE MACHINE
WHILE RGO IS ABOVE 2.25V, VDD DROPPING BELOW
POR DOES NOT CAUSE A POWER-DOWN
6V
POR ~3.5V
POR SCAN
UVR
VDD
UV
LAST CELL CONNECTED
POR
(RESET
REGISTRS)
POWERED STATE
2.25V
RGO
3 sec
DFET
CHMON
LDMON
FIGURE 16. POWER-UP/POWER-DOWN/LOW VOLTAGE WAVEFORMS
22
FN7626.2
December 5, 2012
ISL94203
Wake-up Circuit
When in a sleep mode, the wake up circuit detects that the
output pin is pulled low (as might be the case when a load is
attached to the pack and the FETs are off) or pulled high (as
might be the case when the charger is connected and the FETs
are off).
The wake-up circuit does not draw significant continuous current
from the battery.
Low Power States
In order to minimize power consumption, most circuits are kept
off when not being used and items are sampled when possible.
There are five power states in the device (see Figure 17).
NORMAL MODE
This is the normal monitoring/scan mode. In this mode, the
device monitors the current continuously and scans the voltages
every 32ms. If balancing is called for, then the device activates
external balancing components. All necessary circuits are on and
unnecessary circuits are off.
During the scan, the ISL94203 draws more current as it activates
the input level shifter, the ADC, and data processing. Between
scans, circuits turn off to minimize power consumption.
IDLE MODE
If there is no current flowing for 0 to 15 minutes (set in the MOD
register), then the device enters the IDLE mode. In this mode,
voltage scanning slows to every 256ms per scan. The FETs and
the LDO remain on. In this mode, the device consumes less
current, because there is more time between scans.
When the ISL94203 detects any charge or discharge current, the
device exits the IDLE mode and returns to the NORMAL mode of
operation.
The device does not automatically enter the IDLE mode if the
µCSCAN bit is set to “1”, because the microcontroller is in charge
of performing the scan and controlling the operation.
Setting the IDLE bit to “1” forces the device to enter IDLE mode,
regardless of current flow. When a µC sets the IDLE bit, the
device remains in IDLE, regardless of the timer or the current.
Setting the Mode control bits to 0 allows the device to control the
mode.
DOZE MODE
While in IDLE mode, if there is no current flowing for another 0 to
16 minutes (same value as the idle timer), the device enters the
DOZE Mode, where cell voltage sampling occurs every 512ms.
The FETs and the LDO remain on. In this mode, the device
consumes less current than IDLE Mode, because there is more
time between scans.
When the ISL94203 detects any charge or discharge current, the
device exits DOZE mode and returns to the NORMAL mode.
The device does not automatically enter the IDLE mode if the
µCSCAN bit is set to “1”, because the microcontroller is in charge
of performing the scan and controlling the operation.
23
Setting the DOZE bit forces the device to enter the DOZE mode,
regardless of the current flow. When a microcontroller sets the
DOZE bit, the device remains in DOZE mode regardless of the
timer or the current. Setting the Mode control bits to 0 allows the
device to control the mode.
Note: Setting the IDLE/DOZE timer to 0 immediately forces the
device into the DOZE Mode when there is no current.
SLEEP MODE
The ISL94203 enters the SLEEP mode when the voltage on the
cells drops below the sleep voltage threshold for a period of time,
specified by the Sleep Delay Timer. To prevent the device from
entering the SLEEP mode by a low voltage on the cells, the Sleep
Voltage Level (SLL) register can be set to 0.
The device can also enter the SLEEP mode from the Doze mode,
if there has been no detected current for more than the duration
of the sleep mode timer (set in the MOD register). In this case,
the device remains in DOZE mode until there has been no current
for 0 to 240 minutes (with 16 minute steps).
The external microcontroller forces the ISL94203 to enter SLEEP
mode by writing to the SLEEP bit (Register 88H). Setting the
SLEEP bit forces the SLEEP mode, regardless of the current flow.
Note: If both IDLE/DOZE and SLEEP timers are set to 0, the
device immediately goes to sleep. To recover from this condition,
apply current to the device, or hold the LDMON pin low (or
CHMON pin high) and write non-zero values to the registers.
While in the SLEEP mode, everything is off except for the 2.5V
regulator and the wake up circuits. The device can be waken by
LDMON connection to a load or CHMON connection to a charger.
POWER-DOWN MODE
This mode occurs when the voltage on the pack is too low for
proper operation. This occurs when:
• VDD is less than the POR threshold and RGO < 2.25V. This
condition occurs if cells discharge over a long period of time.
• VDD is less than 1V and RGO > 2.25V. This condition can occur
during a short circuit with minimum capacity cells. The VDD
drops out, but the RGO cap maintains the logic supply.
• When any cell voltage is less than the UVLO threshold for more
than about 160ms (and UVLOPD = 1);
• If commanded by an external µC.
Recovering out of any low power state brings the ISL94203 into
the NORMAL operating mode.
EXCEPTIONS
There is one exception to the normal sequence of mode
management. When the microcontroller sets the µCSCAN bit, the
internal scan stops. This means that the device no longer looks
for the conditions required for sleep. The external microcontroller
needs to manage the modes of operation.
The lower device in a cascaded stack of ISL94203s does not
detect current. As such, the device will progress through the
power states to SLEEP regardless of the pack current. An external
µC needs to set the operating state to IDLE or DOZE to prevent
the lower device from going to sleep.
FN7626.2
December 5, 2012
ISL94203
{ANY CELL VOLTAGE LESS THAN UVLO
FOR 160ms AND UVLOPD = 1} OR
RGO < 1.2V OR
PDWN BIT SET TO “1”
POWER-DOWN STATE
POWER CONSUMPTION <1µA
FIRST POWER UP: VOLTAGE ON VDD RISES ABOVE
THE POR THRESHOLD.
ALREADY POWERED: A CHARGER WAKE UP SIGNAL.
NORMAL OPERATING
STATE
WAKE UP SIGNAL (EITHER
CHARGER OR LOAD)
POWER CONSUMPTION AVERAGE
450µA (2mA PEAKS)
NO CHARGE OR DISCHARGE CURRENT
DETECTED FOR 1-16 MIN OR IDLE BIT IS SET
IDLE STATE
ANY CELL VOLTAGE
DROPS BELOW SLEEP
THRESHOLD FOR
SLEEP DELAY TIME
WHEN THE DEVICE
DETECTS ANY CHARGE OR
DISCHARGE CURRENT,
OPERATION MOVES FROM
DOZE OR IDLE STATES
BACK TO THE NORMAL
OPERATING STATE
POWER CONSUMPTION AVERAGE
350µA MAX (2mA PEAKS)
NO CHARGE OR DISCHARGE CURRENT DETECTED
FOR 1 TO 16 MIN OR DOZE BIT IS SET
OR SLEEP BIT
IS SET
DOZE STATE
POWER CONSUMPTION AVERAGE
300µA (2mA PEAKS)
NO CHARGE OR DISCHARGE CURRENT DETECTED
FOR 32 TO 256 MIN OR SLEEP BIT IS SET
SLEEP STATE
POWER CONSUMPTION AVERAGE
15µA
FIGURE 17. ISL94203 POWER STATES
Typical Operating Conditions
TABLE 1. TYPICAL OPERATING CONDITIONS (Continued)
TABLE 1. TYPICAL OPERATING CONDITIONS
TYPICAL
UNITS
ADC Resolution
14
Bits
ADC Results Saved (and calibrated)
12
Bits
ADC Conversion Time
10
µs
FUNCTION
Overcurrent/Short Circuit Scan Time
Voltage Scan Time (Time per Cell) Includes
Settling Time
Continuous
125
µs
32
256
512
ms
Internal Over-temperature Turn-on/Turn off
Delay Time
128
ms
External Temperature Autoscan On Time;
TEMPO = 2.5V
0.2
ms
128
1024
2048
ms
140
ms
Voltage Protection Scan Rate
(Time between scans) Normal Mode;
IDLE Mode;
Doze Mode:
External Temperature Autoscan Off Time;
TEMPO = 0VNormal Mode
Idle Mode
Doze Mode
Wake Up Delay from Sleep. Time to Turn On
Power FETs Following Load or Charger
Connection. All Pack Conditions OK.
24
TYPICAL
UNITS
Wake Up Delay from shutdown or initial
power-up. Time to turn on power FETs
Following Charger Connection. All Pack
Conditions OK.
3
sec
Default Idle/Doze Mode Delay Times
10
min
Default Sleep Mode Delay Time
90
min
FUNCTION
Table 1 shows some typical device operating parameters.
Cell Fail Detection
The Cell Fail (CELLF) condition indicates that the difference
between the highest voltage cell and the lowest voltage cell
exceeds a programmed threshold (as specified in the CBDU
register). Once detected, the CELLF condition turns off the cell
balance FETs and the power FETs, but only if the µCFET bit = “0.”
Setting the µCFET bit = “1” prevents the power FETs from turning
off during a CELLF condition. The microcontroller is then
responsible for the power FET control.
An EEPROM bit, CFPSD, when set to “1”, enables the PSD
activation when the ISL94203 detects a Cell Fail condition. When
CELLF = “1” and CFPSD = “1”, the power FETs and cell balance
FETs turn off, PLUS the PSD output goes active. The pack
designer can use the PSD pin output to deactivate the pack by
blowing a fuse.
The CELLF function can be disabled by setting the CBDU value to
FFFH. In this case, the voltage differential can never exceed the
limit. However, disabling the cell fail condition also disables the
open wire detection (see “Open Wire Detection” on page 25).
FN7626.2
December 5, 2012
ISL94203
VCn0
CELL n
INTERNAL
2.5V SUPPLY
CONTROL LOGIC
VC4
CELL 4
VC3
CELL 3
VC2
NOTE: THE OPEN WIRE TEST IS
RUN ONLY IF THE DEVICE DETECTS
THE CELLF CONDITION, AND THEN
ONCE EVERY 32 VOLTAGE SCANS
WHILE A CELLF CONDITION
EXISTS. EACH CURRENT SOURCE
IS TURNED ON SEQUENTIALLY.
CELL 2
VC1
CELL 1
VC0
FIGURE 18. OPEN WIRE DETECTION
Open Wire Detection
There is a special open battery wire detection function on this
device. The most important reason for an open wire detection is
to turn off the power FETs if there is an open wire to prevent the
cells from being excessively charged or discharged.
Secondarily, the open wire function prevents the operation of cell
balancing when there is an open wire. There are two reasons for
this. First, if there is an open wire, cell balancing is compromised.
Second, when the cell balance turns on the external balancing
FET and there is an open wire, excessive voltage may appear on
the ISL94203 VCn input pins. Internal clamps and input series
resistors prevent damage as a result of short term exposure to
higher input voltages.
The open wire feature uses built in circuits to force short pulses
of current into or out of the input capacitors (see Figure 18).
When there is no open wire, the battery cell itself changes little in
response to the open wire test.
The open wire operation is disabled by setting a control bit
(DOWD) to “1”. When enabled (DOWD = “0”), the ISL94203
performs an open wire test when the CELLF condition exists and
then once every 32 voltage scans as long as the CELLF condition
remains. A CELLF condition is the first indication that there might
be an open wire.
In operation, the open wire circuit pulls (or pushes) 1mA of
current sequentially on each VCn input for a period of time. The
open wire on-time is programmable by a value in the OWT
register. The pulse duration is programmable between 1µs and
512ms. The default values for current and time are 1mA current
and 1ms duration. Note: In the absence of a battery cell, 1mA
25
input current, along with an external capacitor of 4.7nF, changes
the voltage of the input to the open wire threshold of -1.4V
(relative to the adjacent cell) within 30µs. With the cell present,
the voltage will have a negligible change.
Each input has a comparator that detects if the voltage on an
input drops more than 1.4V below the voltage of the cell below.
Exceptions are VC1 and VC0. For VC1, the circuit looks to see if
the voltage drops below 1V. For VC0, the circuit looks to see if the
voltage exceeds 1.4V. If any comparator trips, then the device
sets an OPEN error flag indicating an Open Wire failure and
disables cell balancing. See Figure 19 for sample timing.
With the open wire setting of 1mA, input resistors of 1kΩ create
a voltage drop of 1V. This voltage drop, combined with the body
diode clamp of the cell balance FET, provides the -1.4V needed to
detect an open wire. For this reason, and for the increased
protection, it is not recommended that smaller input series
resistors be used. For example, with a 100Ω input resistor, the
voltage across the input resistor drops only 0.1V. This will not
allow the input open wire detection hardware to trigger (although
the digital detection of open wire still works, the hardware
detection automatically turns off the open wire current).
Input resistors larger than 1kΩ may be desired to increase the
input filtering. This is allowed in the open wire test, by providing
an increase in the detection time (by changing the OWT value.)
However, increasing the input resistors can significantly affect
measurement accuracy. The ISL94203 has up to 2µA variation in
the input measurement current. This amounts to about 2mV
measurement error with 1k resistors (this error has been factory
calibrated out). However, 10kΩ resistors can result in up to 20mV
FN7626.2
December 5, 2012
ISL94203
measurement errors. To increase the input filtering, the preferred
method is to increase the size of the capacitors.
PACK VC5 OPEN WIRE
PACK OPEN WIRE CLEARED
PACK CELL IMBALANCE
CELLF THRESHOLD
VCMAX VCMIN
CBAL FETs TURN OFF
CELLF BIT
1s (NOTE 12)
NO OPEN WIRE SCANS
OPEN WIRE SCAN
~160ms (DEFAULT)
tOW
VC8 OW TEST
~1ms
VC7 OW TEST
VC6 OW TEST
VC5 OW TEST
VC4 OW TEST
VC3 OW TEST
VC2 OW TEST
VC1 OW TEST
VC6
VC5
VC4
DEFAULT = 20ms
(NOTE 9) 1V
32ms
~1.7V
(NOTE 10)
(NOTE 13)
VOLTAGE SCAN
OPEN BIT
VOLTAGE SCAN REPORTS THAT
VC5 = 0V AND VC6 = 4.8V
NOTES:
9. Voltage drop = 1mA * 1kΩ = 1V
10. Voltage = VF of CB5 Balance FET body diode + (1mA * 1kΩ)
11. OWPSD bit = 0
12. This time is 8s in IDLE and 16s in DOZE
13. This 32ms Scan rate increases to 256ms in IDLE and 512ms in DOZE
FIGURE 19. OPEN WIRE TEST TIMING
Depending on the selection of the input filter components, the
internal open wire comparators may not detect an open wire
condition. This might happen if the input resistor is small. In this
case, the body diode of the cell balance FET may clamp the input
before it reaches the open wire detection threshold. To overcome
this limitation, and provide a redundant open wire detection, at
the end of the open wire scan, all input voltages are converted to
digital values. If any digital value equals 0V (minimum) or 4.8V
(maximum), the device sets an OPEN error flag indicating an
Open Wire failure.
When an open wire condition occurs and the “open wire power
shut down” bit (OWPSD) is equal to “0”, the ISL94203 turns off
all power FETs and the cell balance FETs, but does not set the
PSD output. While in this condition, the device continues to
operate normally in all other ways (i.e. the cells are scanned and
the current monitored. As time passes, the device drops into
lower power modes).
26
When an open wire condition occurs and OWPSD = “1”, the OPEN
flag is set, the ISL94203 turns off all power FETs and the cell
balance FETs, and the ISL94203 sets the PSD output port active.
The device can automatically recover from an open wire
condition, because the open wire test is still functional, unless
the OWPSD bit equals 1 and the PSD pin blows a fuse in the
pack. If the open wire test finds that the open wire has been
cleared, then OPEN bit is reset and other tests determine
whether conditions allow the power FETs to turn back on.
The open wire test hardware has two limitations. First, it depends
on the CELLF indicator. If the Cell Balance Maximum Voltage
Delta (CBDU) value is set to high (FFFh for example), then the
device may never detect a CELLF condition. The second limitation
is that the open wire test does not happen immediately. First, a
scan must detect a CELLF condition. CELLF detection happens in
a maximum of 32ms (normal mode) or in a maximum of 256ms
(DOZE mode). Once CELLF is detected, the open wire test occurs
on the next scan, 32ms to 256ms later.
FN7626.2
December 5, 2012
ISL94203
Current and Voltage Monitoring
Current Sense
There are two main automatic processes in the ISL94203. The
first are the current monitor and overcurrent shutdown circuits.
The second are the voltage, temperature and current analog to
digital scan circuits.
The current sense element is on the high-side of the battery
pack.
Current Monitor
The current monitor is an analog detection circuit that tracks the
charge and discharge current and current direction. The current
monitor circuit is on all the time, except in sleep and power down
modes.
The current monitor compares the voltage across the sense
resistor to several different thresholds. These are short circuit
(discharge), overcurrent (discharge), and overcurrent (charge). If
the measured voltage exceeds the specified limit, for a specified
duration of time, the ISL94203 acts to protect the system, as
described in the following.
The current monitor also tracks the direction of the current. This
is a low level detection and indicates the presence of a charge or
discharge current. If either condition is detected, the ISL94203
sets an appropriate flag.
RSENSE
CS1
The current sense circuit has a gain x5, x50, or x500. The sense
amplifier allows a very wide range of currents to be monitored.
The gain settings allow a sense resistor in the range of 0.3mΩ to
5mΩ. A diagram of the current sense circuit is shown in
Figure 20.
There are two parts of the current sense circuit. The first part is a
digital current monitor circuit. This circuit allows the current to be
tracked by an external microcontroller or computer. The current
sense amplifier gain in this current measurement is set by the
[CG1:CG0] bits. The 14-bit offset adjusted ADC result of the
conversion of the voltage across the current sense resistor is
saved to RAM, as well is a 12-bit value that is used for threshold
comparisons. The offset adjustment is based on a “factory
calibration” value saved in EEPROM.
The digital readouts cover the input voltage ranges shown in
Table 2.
CS2
500Ω
5kΩ
50kΩ
+
CHARGE
OVERCURRENT
DETECT
AO2:0 = 9H
VOLTAGE SCAN
250kΩ
NOTE:
AGC SETS GAIN DURING
OVERCURRENT MONITORING.
CG BITS SELECT GAIN WHEN ADC
MEASURES CURRENT.
PROGRAMMABLE
DETECTION TIME
COC
250kΩ
[OCCTB:OCC0]
GAIN SELECT
PROGRAMMABLE
THRESHOLDS
[OCC2:OCC0]
CG1:0
14-BIT ADC OUTPUT
14-BIT
VALUE
DISCHARGE
OVERCURRENT
DETECT
AGC
RAM REGISTER
14-BIT
ADC
+
ADDRESS: [8Fh:8Eh]
MUX
PACK CURRENT
RAM REGISTER
DOC
[OCDTB:OCDT0]
ADDRESS: [ABh:AAh]
12-BIT
VALUE
PROGRAMMABLE
DETECTION TIME
12
+
-
DISCHARGE
SHORT CIRCUIT
DETECT
4
DIGITAL CAL EEPROM
DCHING
DIRECTION
DETECT +
[OCD2:OCD0]
PROGRAMMABLE
DETECTION TIME
DSC
[SCTB:SCT0]
CURRENT
CHING
AO3:AO0
VOLTAGE SELECT BITS
PROGRAMMABLE
THRESHOLDS
POLARITY
CONTROL
PROGRAMMABLE
THRESHOLDS
[DSC2:DSC0]
2ms FILTER
FIGURE 20. BLOCK DIAGRAM FOR OVERCURRENT DETECT AND CURRENT MONITORING
27
FN7626.2
December 5, 2012
ISL94203
TABLE 2. MAXIMUM CURRENT MEASUREMENT RANGE
GAIN
SETTING
VOLTAGE RANGE
(mV)
CURRENT RANGE
(RSENSE = 1mΩ)
5x
-250 to 250
50x
500x
TABLE 5. DISCHARGE SHORT CIRCUIT CURRENT THRESHOLD
VOLTAGES
EQUIVALENT CURRENT (A)
-250A to 250A
DSC
SETTING
THRESHOLD
(mV)
0.3mΩ
0.5mΩ
1mΩ
2mΩ
5mΩ
-25 to 25
-25A to 25A
000
16
53.3
32
16
8
3.2
-2.5 to 2.5
-2.5A to 2.5A
001
24
80
48
24
12
4.8
010
32
106.7
64
32
16
6.4
011
48
160
96
48
24
9.6
100
64
213.3
128
64
32
12.8
101
96
(Note)
192
96
48
19.2
110
128
(Note)
(Note)
128
64
25.6
111
256
(Note)
(Note)
Note
128
51.2
The second part is the analog current direction, overcurrent and
short circuit detect mechanisms. This circuit is on all the time.
During the operation of the overcurrent detection circuit, the
sense amplifier gain is automatically controlled.
For current direction detection, there is a 2ms digital delay for
getting into or out of either direction condition. This means that
charge current detection circuit needs to detect an uninterrupted
flow of current out of the pack for more than 2ms to indicate a
discharge condition. Then, the current detector needs to identify
that there is a charge current or no current for a continuous 2ms
to remove the discharge condition.
The overvoltage and short circuit detection thresholds are
programmable using values in the EEPROM. The discharge
overcurrent thresholds are shown in Table 3. The charge
overcurrent thresholds are shown in Table 4. The discharge short
circuit thresholds are shown in Table 5.
TABLE 3. DISCHARGE OVERCURRENT THRESHOLD VOLTAGES
0.8
1.6
00
0 to 1024µs
01
0 to 1024ms
10
0 to 1024s
11
0 to 1024 minutes
0.3mΩ
000
4
13.3
8
4
2
001
8
26.6
16
8
4
010
16
53.3
32
16
8
3.2
011
24
80
48
24
12
4.8
100
32
106.7
64
32
16
6.4
101
48
(Note)
96
48
24
9.6
110
64
(Note)
(Note)
64
32
12.8
111
96
(Note)
(Note)
(Note)
48
19.2
2mΩ
5mΩ
NOTE: These selections may not be reasonable due to sense resistor
power dissipation.
TABLE 4. CHARGE OVERCURRENT THRESHOLD VOLTAGES
EQUIVALENT CURRENT (A)
OCC
SETTING
THRESHOLD
(mV)
0.3mΩ
0.5mΩ
1mΩ
2mΩ
5mΩ
000
1
3.3
2
1
0.5
0.2
001
2
6.7
4
2
1
0.4
010
4
13.3
8
4
2
0.8
011
6
20
12
6
3
1.2
100
8
26.6
16
8
4
1.6
101
12
40
24
12
6
2.4
110
16
53.3
32
16
8
3.2
111
24
80
48
24
12
4.8
28
TABLE 6. CHARGE/DISCHARGE OVERCURRENT/SHORT CIRCUIT
DELAY TIMES
[OCCT9:0]
[OCDT9:0]
[SCT9:0]
DELAY (10-bit VALUE)
THRESHOLD
(mV)
1mΩ
The Charge and Discharge overcurrent conditions and the
Discharge Short circuit condition need to be continuous for a
period of time before an overcurrent condition is detected. These
times are set by individual 12-bit timers. The timers consist of a
10-bit timer value and a 2-bit scale value (see Table 6).
[OCCTB:A]
[OCDTB:A]
[SCTB:A]
SCALE VALUE
EQUIVALENT CURRENT (A)
OCD
SETTING
0.5mΩ
NOTE: These selections may not be reasonable due to sense resistor
power dissipation. Assumes short circuit FET turn off in 10ms or less.
Overcurrent and Short Circuit Detection
The ISL94203 continually monitors current by mirroring the
current across a current sense resistor (between the CS1 and
CS2 pins) to a resistor to ground.
• A discharge overcurrent condition exists when the voltage
across the external sense resistor exceeds the discharge
overcurrent threshold, set by the discharge overcurrent
threshold bits [OCD2:OCD0], for an overcurrent time delay, set
by the discharge overcurrent time out bits [OCDTB:OCDT0].
This condition sets the DOC bit high. The LD_PRSNT bit is also
set high at this time. If the µCFET bit is 0, then the power FETs
turn off automatically. If the µCFET bit is 1, then the external
µC must control the power FETs.
• A charge overcurrent condition exists when the voltage across
the external sense resistor exceeds the charge overcurrent
threshold, set by the charge overcurrent threshold bits
[OCC2:OCC0], for an overcurrent time delay, set by the
discharge overcurrent time out bits [OCCTB:OCCT0]. This
condition sets the COC bit high. The CH_PRSNT bit is also set
high at this time. If the µCFET bit is 0, then the power FETs turn
FN7626.2
December 5, 2012
ISL94203
off automatically. If the µCFET bit is 1, then the external µC
must control the power FETs.
• A discharge short circuit condition exists when the voltage
across the external sense resistor exceeds the discharge short
circuit threshold, set by the discharge short circuit threshold
bits [SCD2:SCD0], for an overcurrent time delay, set by the
discharge short circuit time out bits [SCDTB:SCDT0]. This
condition sets the DSC bit high. The LD_PRSNT bit is also set
high at this time. The power FETs turn off automatically in a
short circuit condition, regardless of the condition of the µCFET
bit.
If the µCFET bit is 0, the device automatically re-enables the power
FETs by setting the DFET and CFET (or PCFET) bits to “1” (assuming
all other conditions are within normal ranges). If the µCFET bit is 1,
then the µC must turn on the power FETs.
An external microcontroller can override the automatic charger
monitoring of the device. It does this by taking control of the load
monitor circuit (set the µCCMON bit = “1”) and periodically
pulsing the CMON_EN bit. When the microcontroller detects that
CH_PRSNT=”0”, the µC sets the CLR_CERR bit to “1” (to clear the
error condition and reset the COC bit) and sets the DFET and CFET
(or PCFET) bits to “1” to turn on the power FETs.
Overcurrent and Short Circuit Response
(Discharge)
Microcontroller Overcurrent FET Control
Protection
Once the ISL94203 enters the discharge overcurrent protection or
short circuit protection mode, the ISL94203 begins a load monitor
state. In the load monitor state, the ISL94203 waits three seconds,
and then periodically checks the load by turning on the LDMON
output for 0 to 15ms every 256ms. Program the pulse duration
with the [LPW3:LPW0] bits in EEPROM.
If any of the microcontroller over-ride bits (µCSCAN, µCFET,
µCLMON, µCCMON, or µCBAL) are set to “1” and the
microcontroller does not send a valid slave byte to the ISL94203
within the watchdog time out period, then the microcontroller
control bits are all reset, the device turns off the power FETs and
the balance FETs, and the INT output provides a 1µs pulse one
time per second.
When turned on, the recovery circuit outputs a small current
(~60µA) to flow from the device and into the load. With a load
present, the voltage on the LDMON pin is low and the LD_PRSNT
bit remains set to “1”. When the load rises to a sufficiently high
resistance, the voltage on the LDMON pin rises above the LDMON
threshold and the LD_PRSNT bit is reset. When the load has been
released for a sufficiently long period of time (two successive load
sample periods) the ISL94203 recognizes that the conditions are
OK and resets the DOC or DSC bits.
If the µCFET bit is 0, then the device automatically re-enables the
power FETs by setting the DFET and CFET (or PCFET) bits to “1”
(assuming all other conditions are within normal ranges). If the
µCFET bit is 1, then the µC must turn on the power FETs.
An external microcontroller can override the automatic load
monitoring of the device. It does this by taking control of the load
monitor circuit (set the µCLMON bit = “1”) and periodically
pulsing the LMON_EN bit. When the microcontroller detects that
LD_PRSNT=”0”, the µC sets the CLR_LERR bit to “1” (to clear the
error condition and reset the DOC or DSC bit) and sets the DFET
and CFET (or PCFET) bits to “1” to turn on the power FETs.
Overcurrent Response (Charge)
Once the ISL94203 enters the charge overcurrent protection
mode, the ISL94203 begins a charger monitor state. In the
charger monitor state, the ISL94203 periodically checks the
charger connection by turning on the CHMON output for 0ms to
15ms every 256ms. Program the use duration with the
[CPW3:CP0] bits in EEPROM.
When turned on, the recovery circuit checks the voltage on the
CHMON pin. With a charger present, the voltage on the CHMON pin
is high (>9V) and the CH_PRSNT bit remains set to “1”. When the
charger connection is removed, the voltage on the CHMON pin falls
below the CHMON threshold and the CH_PRSNT bit is reset. When
the charger has been released for a sufficiently long period of time
(two successive sample periods) the ISL94203 recognizes that the
conditions are OK and clears the COC bit.
29
FN7626.2
December 5, 2012
ISL94203
NORMAL OPERATION MODE
OVERCURRENT
PROTECTION
MODE
NORMAL OPERATION MODE
SENSE
CURRENT
IOCC
tOCCT
VCHMON
CHARGER REMOVED
CHARGER STILL
CONNECTED
WHEN µCFET = “0”
SAMPLE RATE SET BY ISL94203
CHMON PIN
WHEN µCFET = “1” AND µCCMON = “1”
SAMPLE RATE SET BY MICROCONTROLLER
CMON_EN
(FROM µC)
(NOTE 15)
COC BIT
(µCFET = “0”)
(NOTE 14)
COC BIT
(µCFET = “1”)
CFET
NOTES:
14. When µCFET = “1”, COC bit is reset when the CLR_CERR is set to “1”.
15. When µCFET = “0”, COC is reset by the ISL94203 when the condition is released
FIGURE 21. CHARGE OVERCURRENT PROTECTION MODE - EVENT DIAGRAM
30
FN7626.2
December 5, 2012
ISL94203
NORMAL OPERATION MODE
O.C. PROTECTION
NORMAL
SHORT
NORMAL
BATTERY
VOLTAGE
LOAD RELEASED
LOAD NOT RELEASED
3 sec
3 sec
VLDMON
WHEN µCFET = “0”
SAMPLE RATE SET BY µC
LDMON PIN
WHEN µCFET = “1” AND µCLMON = “1”
SAMPLE RATE IS SET BY µC.
LMON_EN
(FROM µC)
NO CURRENT
FOR 2x IDLE/MODE MODE TIME +
SLEEP MODE TIME
VDSC
VOCD
SLEEP
VCS
tOCDT
VDSC
VOCD
VSS
tSC
DFET
NOTE 16
NOTE 19
NOTE 19
CFET
NOTE 16
NOTE 18
NOTE 18
PCFET
NOTE 16
NOTE 18
NOTE 18
NOTE 17
DOC
(STAND ALONE)
DSC
NOTE 17
DOC
(EXTERNAL CONTROL)
LD_PRSNT
FIGURE 22. DISCHARGE OVERCURRENT PROTECTION MODE - EVENT DIAGRAM
NOTES:
16. When µCFET = “1”, CFET, DFET, and PCFET are controlled by external µC.
When µCFET = “0”, CFET, DFET, and PCFET are controlled automatically by the ISL94203.
17. When µCFET = “1”, DOC and DSC bits are reset by setting the CLR_LERR bit.
When µCFET = “0”, DOC and DSC are reset by the ISL94203 when the condition is released.
18. PCFET turns on if any cell voltage is less than LVCHG threshold. Otherwise CFET turns on.
19. DFET does not turn on if any cell is less than the UV threshold, unless the DFODUV bit is set.
31
FN7626.2
December 5, 2012
ISL94203
Voltage, Temperature, and Current Scan
The voltage scan consists of the monitoring of the digital
representation of the current, cell voltages, temperatures, pack
voltage, and regulator voltage. This scan occurs once every
32ms, 256ms, or 512ms (depending on the mode of operation,
see Figure 23). The temperature, pack voltage, and regulator
voltage are scanned only every 4th scan. The open wire is
scanned every 32nd scan as long as the CELLF condition exists.
CURRENT/VOLTAGE MONITOR (EVERY CYCLE)
After each measurement scan, the ISL94203 performs an offset
adjustment and stores the values in RAM. After the values are
stored, the state machine executes compare operations that
determine if the pack is operating within limits. See Figure 23 for
details on the scan sequence.
During manufacture, Intersil provides calibration values in the
EEPROM for each cell voltage reading. When there is a new
conversion for a particular voltage, the calibration is applied to
the conversion.
ISL94203 CURRENT MONITORING
CURRENT SELECT/SETTLING TIME
ADC CONVERT
~500µs
ISL94203 CELL VOLTAGE MONITORING
TURN ON ADC MUX SEL SETTLING TIME ADC CONVERT
OV/UV/UVLO DETECT/FET UPDATE/ADD
OFFSETS/CB CALCULATIONS/OPEN WIRE DETECT
OPEN WIRE
1ms
~100µs
CELL1
CELL2
CELL3
CELL7
CELL8
CURRENT
CELL1
LOW POWER STATE
32ms
256ms
512ms
CURRENT/VOLTAGE/TEMPERATURE MONITOR (EVERY 4TH CYCLE)
ISL94203 TEMPERATURE MONITORING
MUX SEL SETTLING TIME ADC CONVERT
ISL94203 PACK VOLTAGE MONITORING
OV/UV/UVLO DETECT/FET UPDATE/ADD
MUX SEL SETTLING TIME ADC CONVERT
OFFSETS/CB CALCULATIONS/OPEN WIRE DETECT
TEMPERATURE CALCULATIONS
OPEN WIRE
1ms
~50µs
CELL1
CELL2
CURRENT
VBATT/16
RGO/2
xT1
xT2
iT
LOW POWER
CELL1
32ms
256ms
512ms
FIGURE 23. CELL VOLTAGE, CURRENT, TEMPERATURE SCANNING
NOTES:
20. The open wire test performed every 32 voltage scans, if CELLF = 1, just prior to the scan.
21. FETs turn off immediately if there is an error, but they do not turn on until the end of the voltage scan (at “FET update” if everything else is OK). An
exception to this is when a device wakes up when connected to a load. In this case, the FETs turn on immediately on wake-up, then a scan begins.
22. The voltage scan can be turned off by an external microcontroller by setting the µCSCAN bit. This bit is monitored by the watchdog timer, so if an
external microcontroller stops communicating with the ISL94203 for more than the WDT period, this bit is automatically reset and the scan resumes.
32
FN7626.2
December 5, 2012
ISL94203
Cell Voltage Monitoring
The circuit that monitors the input cell voltage multiples the cell
voltage by 3/8. The ADC converts this voltage to a digital value,
using a 1.8V internal reference. The ADC produces a calibrated
14-bit value, but only 12 bits are stored in the cell registers (see
Figure 24.)
In manufacturing, each cell voltage is calibrated at 3.6V per cell
and at +25°C. This calibrated value is used for all subsequent
voltage threshold comparisons.
The ISL94203 has two different overvoltage and undervoltage
level comparisons, OVLO/UVLO and OV/UV. While both use the
ADC converter output values and a digital comparator, the
responses are different. The OVLO and UVLO levels are meant to
be secondary thresholds above and below the OV and UV
thresholds.
UVLO AND OVLO
OVLO and UVLO, because they provide a secondary safety
condition, can cause the pack to shut down, either permanently,
as is the case of an OVLO when the PSD pin connects to an
external fuse; or severely, as is the case of an UVLO when the
device powers down and requires connection to a charger to
recover.
The OVLO condition can be over-ridden by setting the OVLO
threshold to FFFH or by an external µC setting the µCSCAN bit to
over-ride the internal automatic scan, then turning on the CFET.
However, if the µC takes permanent control of the scan, the µC
needs to take over the scan for all cells and all control functions,
including comparisons of the cell voltage to OV and UV
thresholds, managing time delays, and controlling all cell
balance functions.
The UVLO response can be over-ridden by setting the UVLO
threshold to 0V. The device can respond to the UVLO condition by
entering the power down mode (set UVLOPD in EEPROM to “1”)
or by turning off the FETs and setting the UVLO bit
(UVLOPD = “0”).
When the UVLOPD bit is set to “1” (indicating that the ISL94203
should power down during a UVLO condition) and the µCFET bit is
set to “1” (indicating that the µC is in control of the FETs), the
automatic UVLO control forces a power-down condition,
over-riding the µC FET control.
The UVLO and OVLO detection both have delays of 5 sample
cycles (typically 160ms) to prevent noise generated entry into the
mode.
OVLO and UVLO values are each set by 12-bit values in EEPROM.
OVLO has a recovery threshold of OVR and UVLO has a recovery
threshold of UVR (if the response over-rides have been set.) If the
response over-rides are not set, then the recovery thresholds are
usually irrelevant, for example when the UVLO forces the device
into a power down condition or the OVLO condition caused a PSD
controlled fuse to blow.
UV, OV, AND SLEEP
UV, OV, and SLP thresholds are set by individual 12-bit values.
UV and OV recovery thresholds are set by individual 12-bit values.
The voltage protection scan occurs once every 32ms in normal
operation. If there has been no activity (no charge or discharge
current) detected in a programmable period of 1 to 16 minutes,
then the scan occurs every 256ms (IDLE Mode). If no charge or
discharge condition has been detected in IDLE mode for a the
programmable period, then the scan occurs every 512ms.
If an overvoltage, undervoltage, or sleep condition is detected
and is pending, the scan rate remains unchanged. It can take
longer to detect the fault condition in IDLE or DOZE modes. The
scan rate is determined by the mode of operation and the mode
of operation is determined solely by the time since pack
charge/discharge current was detected.
VC8
VOLTAGE
BUFFER
14-BIT ADC OUTPUT
14-BIT VALUE
RAM REGISTER
ADDRESS: [ABh:AAh]
VC7
1.8V
INPUT
MUX/
LEVEL
SHIFTER
(x 3/8)
VC1
CELL VOLTAGE
14-BIT
ADC
VSS
12-BIT VALUE
RAM REGISTER ADDRESS: [91h:90h] + 2(n-1);
(n = CELL NUMBER)
S
12
VOLTAGE
BUFFER
VC0
DIGITAL CAL EEPROM
TRIM ADDRESS
[AO3:AO0]
VOLTAGE SELECT BITS
FIGURE 24. BLOCK DIAGRAM OF CELL VOLTAGE CAPTURE
33
FN7626.2
December 5, 2012
ISL94203
During a scan, each cell is monitored for overvoltage,
undervoltage, and sleep voltage. The voltage will also be
converted to an ADC value and be stored in memory.
If, during the scan, a voltage is outside the set limit, then a timer
starts. There is one timer for all of the cells. If the condition
remains on any cell or combination of cells for the duration of the
time period, an error condition exists. This sets the appropriate
flag, and notifies the protection circuitry to take action (if
automatic action is enabled).
The time out delays for OV, UV, and SLEEP are each 12-bit values
stored in EEPROM (see Table 7).
TABLE 7. OV, UV, SLEEP DELAY TIMES
SCALE VALUE
DELAY (10-bit VALUE)
00
0 to 1024µs
01
0 to 1024ms
10
0 to 1024sec
11
0 to 1024min
Overvoltage Detection/Response
The device needs to monitor the voltage on each battery cell
(VCn). If for any cell, [VCn - VC(n-1)] > VOV for a time exceeding tOV,
the device sets an OV flag. Then (if µCFET = 0), the ISL94203
turns the charge FET OFF, by setting the CFET bit to “0”. Once the
OV flag is set the pack has entered Over-charge protection mode.
The status of the discharge FET remains unaffected.
The charge FET remains off until the voltage on the overcharged
cell drops back below a recovery level, VOVR, for a recovery time
period, tOVR. The tOVR time equals the tOV time.
Note: The detection timer and recovery timer are asynchronous
to the voltage threshold. As a result, a setting of 1s can result in a
delay time of 1s to 2s, depending on when the OV/OVR is
detected. For a setting of 1000ms, the detection time will be
within 1ms.
The device further continues to monitor the battery cell voltages,
and is released from overcharge protection mode when [VCn VC(n-1)]< VOVR for more than the overcharge release time, for all
cells.
The control logic for overvoltage, undervoltage, and sleep
conditions is shown in Table 7 and Figures 25 and 26.
When the Device is released from over-charge protection mode,
the charge FET is automatically switched ON (if µCFET = 0). When
the device returns from overcharge protection mode, the status
of the discharge FET remains unaffected.
During charge, if the voltage on any cell exceeds an end of
charge threshold (EOCS) then an EOCHG bit is set and the EOC
NORMAL OPERATION MODE
NORMAL
OPERATION
MODE
OVERCHARGE
PROTECTION MODE
OVERVOLTAGE LOCK-OUT
PROTECTION MODE
VOVLO
VOV
VEOC
tOV
VOVR
VCn
tOVR
PACK
CFLG RESET
CHARGE
CURRENT
DFLG SET
DFET
DISCHARGE
DFLG RESET
CFODOV FLAG = “1” ALLOWS
CFET TO TURN ON DURING OV, IF DISCHARGING
CFET
EOC PIN
EOCHG BIT
OV BIT
SD PIN
PSD PIN
OVLO BIT
FIGURE 25. OVERVOLTAGE PROTECTION MODE-EVENT DIAGRAM
34
FN7626.2
December 5, 2012
ISL94203
VC
VUVR
VUV
VLVCH
VSL
tUV +3s
VUVLO
tUV
tUV +3s
tUV
tSL
CHARGE?
IPACK
DISCHARGE
DISCHARGE
SAMPLING FOR LOAD RELEASE
(µCLMON PULSES)
LMON_EN BIT
(LOOKING FOR TOOL TRIGGER RELEASE)
(FROM µC)
MICROCONTROLLER ONLY.
(µCLMON BIT = “1”)
LOAD RELEASED
LDMON PIN
VLDMON
(STARTS LOOKING FOR CHARGER/LOAD CONNECT)
CMON_EN BIT
VWKUPC
WAKE UP
CHARGE
CONNECT
CHMON PIN
VWKUPL
LD_PRSNT BIT
DFET REMAINS SET
IF UVLOPD = “0”
AND µCFET = 1
DFET ON IF CHARGING
AND DFODUV BIT IS SET
DFET BIT
DFET ON IF CHARGING
AND DFODUV BIT IS SET
CFET BIT
IF PCFETE SET, PCFET
TURNS ON HERE, NOT CFT
PCFET BIT
IN_SLP BIT
UVLO BIT
OVERDISCHARGE
PROTECTION MODE
OVERDISCHARGE
PROTECTION MODE
SLEEP
UV BIT
(µCFET =0”)
UV BIT
(µCFET =1”)
UVLO SET IF UVLOPD = “0”.
If UVLOPD = “1” AND
µCFET = 0 OR 1, DEVICE
POWERS DOWN
RESET WHEN MICROCONTROLLER WRITES CLR_LERR BIT = “1”
FIGURE 26. UNDERVOLTAGE PROTECTION MODE-EVENT DIAGRAM
output is pulled low. The EOCHG bit and the EOC output resume
normal conditions when the voltage on all cells drops back below
the [EOCS - 117mV] threshold.
There is also an overvoltage lock-out. When this level is reached,
an OVLO bit is set, the PSD output is set and the charge FET or
precharge FET is immediately turned off (by setting the CFET or
PCFET bit to “0”). The PSD output can be used to blow a fuse to
protect the cells in the pack.
If, during an OV condition, the µCFET bit is set to “1”, the
microcontroller must control both turn off and turn on of the
charge and precharge power FETs. This does not apply to the
OVLO condition.
The device includes an option to turn the charge FET back on in
an overvoltage condition, if there is discharge current flowing out
of the pack. This option is set by the CFODOV (CFET ON During
Overvoltage) Flag stored in EEPROM. Then, if the discharge
35
current stops and there is still an over-charge condition on the
cell, the device again disables the charge FET.
Undervoltage Detection/Response
If VCn < VUV, for a time exceeding tUVT, the cells are said to be in
a over discharge (undervoltage) state. In this condition, the
ISL94203 sets a UV bit. If the µCFET bit is set to “0”, the
ISL94203 also switches the discharge FET OFF (by setting the
DFET bit = “0”).
While any cell voltage is less than a low voltage charge threshold,
and if the PCFETE bit is set, the PCFET output is turned on instead
of the CFET output. This enables a pre-charge condition to limit
the charge current to undervoltage cells.
From the undervoltage mode, if the cells recover to above a VUVR
level for a time exceeding tUVT plus three seconds, the ISL94203
pulses the LDMON output once every 256ms and looks for the
absence of a load. The pulses are of programmable duration
FN7626.2
December 5, 2012
ISL94203
(0ms to 15ms) using the [LPW3:LPW0] bits. During the pulse
period, a small current (~60µA) is output into the load. If there is
no load, then the LDMON voltage will be higher than the recovery
threshold of 0.6V. When the load has been removed, and the
cells are above the undervoltage recovery level, the ISL94203
clears the UV bit and (if µCFET = 0) turns on the discharge FET
and resumes normal operation.
Note: The tUV detection timer and tUVR recovery timer are
asynchronous to the voltage threshold. As a result, a setting of 1s
can result in a delay time of 1s to 2s (and a recovery time of 3s to
4s), depending on when the UV/UVR is detected. For a setting of
1000ms, the detection time will be within 1ms.
If any of the cells drop below a sleep threshold (VCn < VSLP) for a
period of time (tSLT), the device sets the SLEEP bit and
(if µCFET = 0) the ISL94203 turns off the both FETs (DFET and
CFET = “0”) and puts the pack into a sleep mode by setting the
SLEEP bit to “1”. If the µCFET bit is set, the device does not go to
sleep.
There is also an undervoltage lock-out condition. This is detected
by comparing the cell voltages to a programmable UVLO
threshold. When any cell voltage drops below the UVLO
threshold, and remains below the threshold for 5 voltage scan
periods (~160ms), a UVLO bit is set, and the SD output pin goes
active. If UVLOPD = 0 and µCFET = 0, the DFET is also turned off.
If UVLOPD = 1, then the ISL94203 goes into a power-down state.
If the µCFET bit is set to “1”, the microcontroller must both turn
off and turn on the discharge power FETs and control the sleep
and power-down conditions.
The device includes an option to turn the discharge FET back on,
in an undervoltage condition, if there is a charge current flowing
into the pack. This option is set by the DFODUV (DFET ON During
Undervoltage) Flag stored in EEPROM. Then, if the charge current
stops and there is still an undervoltage condition on the cell, the
device again disables the discharge FET.
Temperature Monitoring/Response
As part of the normal voltage scan, the ISL94203 monitors both
the temperature of the device and the temperature of two
external temperature sensors. External temperature 2 can be
used to monitor the temperature of the FETs, instead of the cells,
by setting the xT2M bit to “1”.
The temperature voltages have two gain settings (the same gain
for all temperature inputs). For external temperatures, a TGain
bit = 0, sets the gain to 2x (full scale input voltage = 0.9V). A
TGain bit = 1 and sets the gain to 1x (full scale input
voltage = 1.8V). See Figure 26.
The default temperature gain setting is x2, so the temperature
monitoring circuit of Figure 26A is preferred. This configuration
has other advantages. The temperature response is more linear
and covers a wider temperature range before nearing the limits
of the ADC reading.
The internal temperature reading converts from voltage to
temperature using Equations 1 and 2:
intTemp ( mV ) × 1000
----------------------------------------------- – 273.15 = ICTemp ( ° C )
TGain = 0
0.92635
(EQ. 1)
intTemp ( mV ) × 1000
----------------------------------------------- – 273.15 = ICTemp ( ° C )
TGain = 1
1.8527
(EQ. 2)
If the temperature of the IC (Internal Temp) goes above a
programmed over-temperature threshold, then the ISL94203
sets an over-temp flag (IOT), prevents cell balancing and turns off
the FETs.
OVER-TEMP
If the temperature of either of the external temperature sensors
(xT1 or xT2), as determined by an external resistor and
thermistor, goes below any of the thresholds (Charge, discharge,
and cell balance as set by internal EEPROM values), indicating an
over-temperature condition, the ISL94203 sets the
corresponding over-temp flag.
If the automatic responses are enabled (µCFET = 0); then if the
charge over-temp (COT) or discharge over-temp flag (DOT) flag is
set, the corresponding charge or discharge FET is turned off. If
the Cell balance over-temp flag (CBOT) is set, the device turns off
the balancing outputs and prevents cell balancing while the
condition exists.
If the automatic responses are disabled (µCFET = 1) then the
ISL94203 only sets the flags and an external microcontroller
responds to the condition.
TEMPO PIN
TEMPO PIN
22kΩ
82.5kΩ
22kΩ
xT1 PIN
xT1 PIN
xT2 PIN
xT2 PIN
+80°C = 0.153V
+50°C = 0.295V
+25°C = 0.463V
0°C = 0.710V
-40°C = 0.755V
10kΩ
10kΩ
THERMISTORS: 10k,
MuRata XH103F
FIGURE 27A. TGAIN = 0 (GAIN = 2)
82.5kΩ
+80°C = 0.050V
+50°C = 0.120V
+25°C = 0.270V
0°C = 0.620V
-40°C = 1.758V
FIGURE 26A. TGAIN = 1 (GAIN = 1)
FIGURE 26. EXTERNAL TEMPERATURE CIRCUITS
36
FN7626.2
December 5, 2012
CHARGE SHUTDOWN
TURN OFF CFET
DISCHARGE SHUTDOWN
TURN OFF DFET
µCFET = 0
µCFET = 1
BALANCE SHUTDOWN
TURN OFF BALANCING
µCFET = 0
µCFET = 1
37
CHARGE OVER-TEMP
SET COT BIT
BALANCE PERMITTED
ALLOW DFET TO
TURN ON
ALLOW CFET TO
TURN ON
CELL BALANCE
OVER-TEMP OK
SET CBOT BIT = 0
DISCHARGE
OVER-TEMP OK
SET DOT BIT = 0
CHARGE
OVER-TEMP OK
SET COT BIT = 0
µCFET = 0
µCFET = 1
DISCHARGE OVER-TEMP
SET DOT BIT
CELL BALANCE OVER-TEMP
SET CBOT BIT
XT2M = 0
xT2<DOTS or
xT1<DOTS
XT2M = 0
xT1<CBOTS
xT1>CBOTR
xT2 OT
xT2<COTS or
xT1<COTS
xT2 OTR
XT2M = 1
XT2M = 1
xT2<CBOTS
xT2>CBOTR
xT2>DOTR or
xT1>DOTR
xT2>COTR or
xT1>COTR
xT2<DUTR OR
xT1<DUTR
xT2<CUTR OR
xT1<CUTR
SAMPLE MODE
xT2>CBUTS
xT2<CBUTR
XT2M = 1
xT2>DUTS OR
xT1>DUTS
xT1>CBUTS
xT2 UT
XT2M=0
CHARGE UNDER TEMP
SET CUT BIT = 1
µCFET = 1
µCFET = 1
µCFET = 0
CHARGE SHUTDOWN
TURN OFF CFET
DISCHARGE UNDERTEMP
SET DUT BIT = 1
CELL BALANCE UNDERTEMP
SET CBUT BIT = 1
XT2M = 1
xT2 UTR
xT1<CBUTR
XT2M=0
CELL BALANCE
UNDER TEMP OK
SET CBUT BIT = 0
DISCHARGE
UNDER TEMP OK
SET DUT BI T= 0
CHARGE
UNDER TEMP OK
SET CUT BIT = 0
ALLOW DFET TO
TURN ON
ALLOW CFET TO
TURN ON
µCFET = 1
µCFET = 0
DISCHARGE SHUTDOWN
TURN OFF DFET
µCFET = 0
BALANCE SHUT DOWN
TURN OFF BALANCING
BALANCE PERMITTED
FIGURE 28. TEMPERATURE MANAGEMENT STATE MACHINE
ISL94203
xT2>CUTS OR
xT1>CUTS
FN7626.2
December 5, 2012
ISL94203
An exception to the above occurs if the xT2 sensor is configured
as a FET temperature indicator (XT2M = “1”). In this case, the xT2
is not compared to the cell balance temperature thresholds, it is
used only for power FET control.
TABLE 8. µC CONTROLLED MEASUREMENT OF INDIVIDUAL VOLTAGES
STEP
OPERATION
NUMBER
I2C CYCLES
TIME
TIME @400kHz
I2C CLK (ea.) (CUMULATIVE)
(µs)
(µs)
UNDER-TEMP
1
Set µCSCAN bit
29
72.5
72.5
If the temperature of either of the external temperature sensors
(xT1 or xT2), as determined by an external resistor and
thermistor, goes above any of the thresholds (Charge, discharge,
and cell balance as set by internal EEPROM values), indicating an
under-temperature condition, the ISL94203 sets the
corresponding under-temp flag.
2
Set voltage and
start ADC
29
72.5
145
3
Wait for ADC
complete
N/A
110
255
4
Read register AB
29
72.5
327.5
5
Read register AA
29
72.5
410
If the xT1 automatic responses are enabled (µCFET = 0); then if
the charge under temp (CUT) or discharge under temp flag (DUT)
flag is set the corresponding charge or discharge FET is turned
off. If the Cell balance under-temp flag (CBUT) is set, the device
turns off cell balancing outputs and prevents cell balancing.
6
Clear µCSCAN bit
29
100
472.5
If the xT2 automatic responses are disabled (µCFET = 1) then the
ISL94203 only sets the flags and an external microcontroller
responds to the condition.
An exception to the above occurs if the xT2 sensor is configured
as a FET temperature indicator (XT2M = “1”). In this case, the xT2
is not compared to the cell balance temperature thresholds. It is
used only for power FET control).
For both xT1 and xT2, when the temperature drops back within a
normal operating range, the over or under temperature condition
is reset.
Microcontroller Read of Voltages
An external microcontroller can read the value of any of the
internally monitored voltages independently of the normal
voltage scan. To do this requires that the µC first set the µCSCAN
bit. This stops the internal scan and starts the watchdog timer. If
the µC maintains this state, then communication must continue
and the µC must manage all voltage and current pack control
operations as well as implement the cell balance algorithms.
However, if the µCSCAN bit remains set for a short period of time,
the device continues to monitor voltages and control the pack
operation.
Once the µCSCAN bit is set, the external µC writes to register 85H
to select the desired voltage and to start the ADC conversion (set
the ADCSTRT bit to 1 to start an ADC conversion). Once the
conversion is complete, the results are read from the ADC
registers [ADCD:ADC0]. The result is a 14-bit value. The ADC
conversion takes about 100µs, or the µC can poll the I2C link
waiting for an ACK to indicate that the ADC conversion is
complete.
If the µCSCAN bit is set when the ISL94203 internal scan is
scheduled, then the internal scan pauses until the µCSCAN bit is
cleared and the internal scan occurs immediately.
Reading an ADC value from the µC requires the following
sequence (and time) to complete:
38
To sample more than one time (for averaging,) repeat steps 2
through 5 as many times as desired. However, if this is a
continuous operation, care must be taken to monitor other pack
functions or to pause long enough for the ISL94203 internal
operations to collect data to control the pack. A burst of five
measurements takes about 1.8ms.
Voltage Conversions
To convert from the digital value stored in the register to a “real
world” voltage, the following conversion equations should be
used.
The term “HEXvalue10” means the Binary to Decimal conversion
of the register value.
CELL VOLTAGES
HEXvalue 10 × 1.8 × 8
Cell Voltage = -----------------------------------------------------------4095 × 3
(EQ. 3)
The cell voltage conversion equation is also used to set the
voltage thresholds.
PACK CURRENT
Pack Current =
HEXvalue 10 × 1.8
--------------------------------------------------------4095 × Gain × SenseR
(EQ. 4)
Gain is the gain setting in register 85H, set by the [CG1:CG0] bits.
Sense R is the sense resistor value in Ohms.
This pack current reading is valid only when the current direction
indicators show that there is a charge or discharge current. If the
current is too low for the indicators to show current flowing, then
use the 14-bit value to estimate the current. See “14-bit Register”
on page 39.
TEMPERATURE
HEXvalue 10 × 1.8
(EQ. 5)
-------------------------------------------------4095
Equation 5 converts the register value to a voltage, but the
temperature then is converted to a temperature depending on
the external arrangement of thermistor and resistors. See
Section , “Temperature Monitoring/Response,” on page 36.
Temperature =
FN7626.2
December 5, 2012
ISL94203
14-BIT REGISTER
If HEXvalue10 is greater than or equal to 8191, then
( HEXvalue 10 – 16384 ) × 1.8
14-bit value = --------------------------------------------------------------------------8191
(EQ. 6)
• Discharge short circuit FET control. The external µC cannot
over-ride the turn off of the FETs during the short circuit.
If HEXvalue10 is less than 8191, then
HEXvalue 10 × 1.8
14-bit value = -------------------------------------------------
(EQ. 7)
8191
Once the voltage value is obtained, if the measurement is a cell
voltage, then the value should be multiplied by 8/3. A
temperature value is used “as-is”, but the voltage value is
converted to temperature by including the external temperature
circuits into the conversion.
To determine pack current from this 14-bit value requires the
following computations.
First, if both current direction flags show zero current, then the
external controller must apply an offset. Measure the 14-bit
voltage when there is a pack current of 0. Then subtract this
offset from the 14-bit current sense measurement value and
take the absolute value of the result. If either of the current
direction flags indicate a current, then do not subtract the offset
value, but use the 14-bit value directly. In either case, divide the
14-bit voltage value by the current sense gain and the current
sense resistor to arrive at the pack current.
Microcontroller FET Control
The external microcontroller can override the device control of the
FETs. With the µCFET bit set to “1”, the external microcontroller can
turn the FETs on or off under all conditions except the following:
• If there is a discharge short circuit condition, the device turns
the FETs off. The external microcontroller is responsible for
turning the FETs back on once the short circuit condition
clears.
• If there is an internal over-temperature condition, the device turns
the FETs off. The external microcontroller is responsible for
turning the FETs back on once the temperature returns to within
normal operating limits.
• If there is an Overvoltage Lock Out condition, the device turns the
charge or pre-charge FETs off. The external microcontroller is
responsible for turning the FETs back on, once the OVLO condition
clears. This assumes that the PSD output has not blown a fuse to
disable the pack.
• If there is an open wire detection, the device turns the FETs off.
The external microcontroller is responsible for turning the FET
back on. This assumes that the open wire did not cause the PSD
output to blow a fuse to disable the pack.
• If the FETSOFF input is HIGH, the FETs turn off and remain off.
The external µC is responsible for turning the FETs on once the
FETSOFF condition clears.
• If there is a sleep condition, the device turns the FETs off. On
wake up, the microcontroller is responsible for turning on the
FETs.
39
The microcontroller can also control the FETs by setting the
µCSCAN bit. However, this also stops the scan, requiring the
microcontroller to manage the scan, voltage comparisons, FET
control, and cell balance. While the µCSCAN bit is set to “1”, the
only operations controlled by the device are:
• FETSOFF external control. The FETSOFF pin has priority on
control of the FETs, even when the microcontroller is managing
the scan.
• In all other cases, the microcontroller must manage the FET
control, because it is also managing the voltage scan and all
comparisons.
Cell Balance
At the same rate as the scan of the cell voltages, if cell balancing
is on, the system checks for proper cell balance conditions. The
ISL94203 prevents cell balancing if proper temperature, current,
and voltage conditions are not met. The cells only balance during
a CBON time period. When the CBOFF timer is running, the cell
balance is off. Three additional bits determine whether the
balancing happens only during charge, only during discharge,
during both charge and discharge, during the end of charge
condition, or not at any time.
• The cell balance circuit depends on the 14-bit ADC converter
built into the device and the results of the cell voltage scan
(after calibration).
• The ADC converter loads a set of registers with each cell
voltage during every cell voltage measurement.
• At the end of the cell voltage measurement scan, the
ISL94203 updates the minimum (CELMIN) and maximum
(CELMAX) cell voltages.
• After calculating the CELMIN and CELMAX values, all of the cell
voltages are compared with the CELMIN value. When any of
the cells exceed CELMIN by CBDL (the minimum CB delta
voltage), a flag is set in RAM indicating that the cell needs
balancing (this is the CBnON bit).
• If any of the cells exceed the lowest cell by CBDU (maximum
CB delta voltage) then a flag is set indicating that a Cell
voltage failure occurred (CELLF).
• When the CELLF flag indicates that there is too great a cell to
cell differential, the balancing is turned off.
• If CELMAX is below CBUV (all the cell voltages are too low for
balancing) then the CBUV bit is set and there will be no cell
balancing. Cell balance does not start again until the CBMIN
value rises above (CBUV + 117mV). When this happens, the
ISL94203 clears the CBUV bit.
• If the CELMIN voltage is greater than the CBOV level (all the cell
voltages are too high for balancing) then the CBOV bit is set and
there will be no cell balancing. Cell balancing does not start again
until the CBMAX value drops below [CBOV - 117mV]. When this
happens, the ISL94203 clears the CBOV bit.
• A register in EEPROM (CELLS) identifies the number of cells
that are supposed to be present so only the cells present are
FN7626.2
December 5, 2012
ISL94203
used for the cell balance operation. Note: This is also used in
the cell voltage scan and open wire detect operation.
• There are no limits to the number of cells that can be balanced
at any one time, because the balancing is done external to the
device.
• The cell balance block updates at the start of the cell balance
ON period to determine if balancing is needed and that the
right cells are being balanced. The cells selected at this time
will be balanced for the duration of the cell balance period.
• The cell balance is disabled if any external temperature is out
of a programmed range set by CBUTS (cell balance under
temperature) and CBOTS (cell balance over-temperature).
• The cell balance operation can be disabled by setting the cell
balance during charge (CBDC), the cell balance during
discharge (CBDD), and the cell balance during end-of-charge
(CB_EOC) bits to zero. See Table 9 on page 40.
• Cell balancing turns off when set to balance in the charge
mode and there is no charging current detected (see CB_EOC
exception below).
• Cell balancing turns off when set to balance in the discharge
mode and there is no discharge current detected (see CB_EOC
exception below).
• If cell balancing is set to operate during both charge and
discharge, then ISL94203 balances while there is charge
current or discharge current, but does not balance when no
current flow is detected (all other limiting factors continue to
apply). See CB_EOC exception in the following.
• The CB_EOC bit provides an exception to the cell balance
current direction limit. When the CB_EOC bit is set, balancing
occurs while an end of charge condition exists (EOC bit = 1),
regardless of current flow. This allows the ISL94203 to “drain”
high voltage cells when the charge is complete. This speeds
the balancing of the pack, especially when there is a large
capacity differential between cells. Once the end of charge
condition clears, the cell balance operation returns to normal
programming.
TABLE 9. CELL BALANCE TRUTH TABLE (SEE FIGURE 29)
CB_EOC
bit
EOC
Pin
0
1
CBDC
CHING
CBDD
DCHING
ENABLE
x
1
0
0
0
0
0
0
1
x
1
0
0
0
1
0
0
1
x
1
0
0
1
0
0
0
1
x
1
0
0
1
1
1
0
1
x
1
0
1
0
0
0
0
1
x
1
0
1
0
1
0
0
1
x
1
0
1
1
0
0
0
1
x
1
0
1
1
1
0
0
1
x
1
1
0
0
0
0
0
1
x
1
1
0
0
1
0
0
1
x
1
1
0
1
0
0
0
1
x
1
1
0
1
1
1
0
1
x
1
1
1
0
0
1
0
1
x
1
1
1
0
1
0
0
1
x
1
1
1
1
0
1
0
1
x
1
1
1
1
1
0
1
0
x
x
x
x
1
• Balance is disabled by asserting the FETSOFF external pin
• The cell balance outputs are on only while the cell balance on
timer is counting down. This is a 12-bit timer. The cell balance
outputs are all off while the cell balance off timer is counting
down. This is also a 12-bit timer. The timer values are set as in
Table 10.
TABLE 10. CBON AND CBOFF TIMES
SCALE VALUE
TIME (10-BIT VALUE)
00
0 to 1024µs
01
0 to 1024ms
10
0 to 1024s
11
0 to 1024min
Cell Balance in Cascade Mode
When two ISL94203 devices are cascaded, both devices should
have the CASC bit set to “1”.
When cascaded, the lower of the two devices will have an ADDR
that is HIGH or set to “1”. The device with ADDR = 1, being on the
bottom of the stack, does not monitor the current or drive the
power FETs. Instead, they are turned off to save power
consumption.
40
FN7626.2
December 5, 2012
ISL94203
CB OFF TIMER IS
COUNTING
CBOV BIT
CELL8 VOLTAGE - CELLMIN >
CBMINDV OR [CB8ON]
CB8 DRIVER
CELL7 VOLTAGE - CELLMIN >
CBMINDV OR [CB7ON]
CB7 DRIVER
CELL6 VOLTAGE - CELLMIN >
CBMINDV OR [CB6ON]
CB6 DRIVER
CELL5 VOLTAGE - CELLMIN >
CBMINDV OR [CB5ON]
CB5 DRIVER
CELL4 VOLTAGE - CELLMIN >
CBMINDV OR [CB4ON]
CB4 DRIVER
CELL3 VOLTAGE - CELLMIN >
CBMINDV OR [CB3ON]
CB3 DRIVER
CELL2 VOLTAGE - CELLMIN >
CBMINDV OR [CB2ON]
CB2 DRIVER
CELL1 VOLTAGE - CELLMIN >
CBMINDV OR [CB1ON]
CB1 DRIVER
CBERR
CBUV BIT
CBOT BIT
CBUT BIT
ENABLE
OPEN BIT
CELLF BIT
CASC
SD PIN
FETSOFF PIN
1
EOC
CB_EOC
6
CBDC BIT
2
CHING BIT
CBDD
4
DCHING BIT
3
5
FIGURE 29. CELL BALANCE OPERATION
When CASC = 1, the ISL94203 does not use the current
detection as part of the control algorithm for cell balancing. If all
other conditions are within limits, balancing proceeds without a
detection of current. As such, balancing may happen all of the
time, requiring the use of an external microcontroller to manage
the algorithm. The reason for this is that there is no facility for
the two cascaded devices to automatically know the cell voltages
on the other device. While one device might be balancing all cells
to a voltage of 3V, the other might be balancing toward a voltage
of 3.2V. To simplify the microcontroller design, all scanning and
protection functions operate normally. The external
microcontroller needs to scan the voltages and monitor status
bits, then make decisions based on the available information
and control the cell balance FETs. Since balancing is unrestricted,
the µC needs only to set the uC_Does_CellBalance state to stop
balancing while the upper device detects no current.
With the cell balance outputs specified, the microcontroller sets
the CBAL_ON bit. This turns on the cell balance output control
circuit.
Cell Balance FET Drive
The cell balance FETs are driven by a current source or sink of
25µA. The gate voltage on the externals FET is set by the gate to
source resistor. This resistor should be set such that the gate
voltage does not exceed 9V. An external 9V zener diode across
the gate to source resistor can help to prevent overvoltage
conditions on the cell balance pin.
The cell balance circuit connection is shown in Figure 30.
µC Control of Cell Balance FETs
To control the cell balance FETs, the external microcontroller first
needs to set the µCCBAL bit (non-cascaded) to turn off the
automatic cell balance operation. In a cascaded configuration,
the external microcontroller needs to set the CASC bit on the
lower device. This turns off the detection of current. The external
microcontroller also needs to use the µCCBAL bit to over-ride the
automatic cell balance operation.
To turn on a cell balance FET, the µC needs to turn on the cell
balance output FET using the Cell Balance Control Register 84H).
In this register, each bit corresponds to a specific cell balance
output.
41
FN7626.2
December 5, 2012
ISL94203
1kΩ
VC8
22nF
10kΩ
CB8
39Ω
39Ω
39Ω
39Ω
10V
4M
VC5
22nF
10kΩ
CB5
316kΩ
1kΩ
VC4
22nF
10kΩ
CB4
316kΩ
1kΩ
VC3
22nF
10kΩ
CB3
316kΩ
1kΩ
VC2
22nF
10kΩ
CB2
316kΩ
1kΩ
VC1
22nF
10kΩ
CB1
316kΩ
1kΩ
VC0
CB4ON
CB3ON
CB2ON
10V
10V
10V
10V
10V
CB1ON
4M
4M
4M
4M
4M
VSS
CB8ON
CB7ON
25µA
22nF
25µA
VC6
CB6
CB5ON
25µA
39Ω
CB7
25µA
316kΩ
1kΩ
39Ω
4M
VC7
25µA
22nF
10kΩ
10V
ENABLE
25µA
316kΩ
1kΩ
39Ω
4M
25µA
22nF
10kΩ
10V
CBAL_ON
25µA
316kΩ
39Ω
1kΩ
ISL94203
CB6ON
VSS
FIGURE 30. CELL BALANCE DRIVE CIRCUITS AND CELL CONNECTION OPTIONS
Watchdog Timer
The I2C watchdog timer prevents an external microcontroller
from initiating an action that it cannot undo through the I2C port,
which can result in poor or unexpected operation of the pack.
The watchdog timer is normally inactive when operating the
device in a stand-alone operation. When the pack is expected to
have a µC along with the ISL94203, the WDT is activated by
setting any of the following bits:
µCSCAN, µCCMON, µCLMON, µCCBAL, µCFET, EEEN.
When active (an external µC is assumed to be connected), the
absence of I2C communications for the watchdog time-out
42
period causes a time-out event. The ISL94203 needs to see a
start bit and a valid slave byte to restart the timer.
The watchdog time-out signal turns off the cell balance and
power FET outputs, resets the serial interface, and pulses the INT
output once per second in an attempt to get the microcontroller
to respond. If the INT is unsuccessful in re-starting the
communication interface, the part operates normally, except the
power FETs and cell balance FETs are forced off. The ISL94203
remains in this condition until I2C communications resumes.
When I2C communication resumes, the µCSCAN, µCCMON,
µCLMON, µCFET, and EEEN bits are automatically cleared and
the µCCBAL bit remains set. The power FETs and cell balance
FETs turn on, if conditions allow.
FN7626.2
December 5, 2012
ISL94203
Power FET Drive
The ISL94203 drives the power FETs gates with a voltage higher
than the supply voltage by using external capacitors as part of a
charge pump. The capacitors connect (as shown in Figure 2) and
are nominally 4.7nF. The charge pump applies approximately
(VDD *2) voltage to the gate, although the voltage is clamped at
VDD + 16V.
The Power FET turn-on times are limited by the capacitance of
the power FET and the current supplied by the charge pump. The
power FET turn-off times are limited by the capacitance of the
power FET and the pull-down current of the ISL94203. The
ISL94203 provides a pull-down current for up to 300µs. This
should be long enough to discharge any FET capacitance.
The table below shows typical turn on and turn off times for the
ISL94203 under specific conditions.
TABLE 11. POWER FET GATE CONTROL (TYPICAL)
PARAMETER
CONDITIONS
Power FET Gate Turn DFET, CFET, PCFET
on current
Charge pump caps = 4.7nF
Power FET Gate Turn 10% to 90% of final voltage
on Time
VDD = 28V;
DFET, CFET = IRF1404
PCFET = FDD8451
TYPICAL
5mA, 50µs
pulses,
32kHz
frequency
An input pin (FETSOFF), when pulled high, turns off the power
FETs and the cell balance FETs, regardless of any other condition.
Higher Voltage Microcontrollers
When using a microcontroller powered by 3.3V or 5V, the design
can include pull-up resistors to the microcontroller supply on the
communication link and the open drain SD and EOC pins (instead
of pull-up resistors to RGO.)
The INT pin is a CMOS output with a maximum voltage of
RGO+0.5V. It is OK to connect this directly to a microcontroller as
long as the microcontroller pin does not have a pull up to the
3.3/5V supply. If it does, then a series resistor is recommended.
The FETSOFF input on the ISL94203 is also limited to RGO+0.5V.
This is limited by an input ESD structure that clamps the voltage.
The connection from the µC to this pin should include a series
resistor to limit any current resulting from the clamp.
An example of this connection is shown in Figure 31.
µCONTROLLER
ISL94203
3.3/5V
160µs
160µs
Power FET Gate Turn CFET, CFET, PCFET
off Current
20mA
Power FET Gate Turn Pulse Duration
off Pulse Width
300µs
Power FET Gate Fall 90% to 10% of final voltage
Time
VDD = 28V;
DFET: IRF1404
CFET: IRF1404
PCFET: FDD8451
greater than a specified limit (CELLF flag), or if there is an open
wire condition. This pin can be used for blowing a fuse in the
pack or as an interrupt to an external µC.
SD
EOC
INT
In_EOC
In_INT
*
SCL
SDAI
SDAO
FETSOFF
6µs
6µs
2µs
In_SD
SCL
SDA
10k
Out_FETSOFF
* Resistor needed only if µC has a pull-up on the In_INT pin
FIGURE 31. CONNECTION OF HIGHER VOLTAGE MICROCONTROLLER
General I/Os
There is an open drain output (SD) that is pulled up to RGO (using
an external resistor) and indicates if there are any error
conditions, such as overvoltage, undervoltage, over-temperature,
open input, and overcurrent. The output goes active (LOW) when
there is any cell or pack failure condition. The output returns
HIGH when all error conditions clear.
There is an open drain output (EOC) that is pulled up to RGO
(using an external resistor) and indicates that the cells have
reached an end of conversion state. The output goes active
(LOW) when all cell voltages are above a threshold specified by a
12-bit value in EEPROM. The output returns HIGH, when all cells
are below the EOC threshold.
Factory programmable options offer inverse polarity of SD or
EOC. Please contact Automotive Marketing if there is interest in
either of these options.
The PSD pin goes active high, when any cell voltage reaches the
OVLO threshold (OVLO flag). Optionally, PSD also goes high if
there is a voltage differential between any two cells that is
43
Packs with Fewer than 8 Cells
See Section , “Pack Configuration,” on page 21 for help when
using fewer than 8 cells. This section presents options for
minimum number of components. However, when using the
ISL94203EVAL1Z evaluation board with fewer than 8 cells, it is
not necessary to remove components from the PCB. Simply tie
the unused connections together, as shown in Figure 32. This
normally requires only a different cable.
EEPROM
The ISL94203 contains an EEPROM array for storing the device
configuration parameters, the device calibration values, and
some user available registers. Access to the EEPROM is through
the I2C port of the device. Memory is organized in a memory map
as described in “Registers: Summary (EEPROM)” on page 50,
“Registers: Summary (RAM)” on page 50, “Registers: Detailed
(EEPROM)” on page 51, and “Registers: Detailed (RAM)” on
page 58.
FN7626.2
December 5, 2012
ISL94203
8 CELLS
6 CELLS
7 CELLS
VC8
VC8
VC8
CB8
CB8
CB8
VC7
VC7
VC7
CB7
CB7
CB7
VC6
VC6
VC6
CB6
CB6
CB6
VC5
VC5
VC5
CB5
CB5
CB5
VC4
VC4
VC4
CB4
CB4
CB4
VC3
VC3
VC3
CB3
CB3
CB3
VC2
VC2
VC2
CB2
CB2
CB2
VC1
VC1
VC1
CB1
CB1
CB1
VC0
VSS
VC0
VSS
VC0
VSS
4 CELLS
5 CELLS
3 CELLS
VC8
VC8
VC8
CB8
CB8
CB8
VC7
VC7
VC7
CB7
CB7
CB7
VC6
VC6
VC6
CB6
CB6
CB6
VC5
VC5
VC5
CB5
CB5
CB5
VC4
VC4
VC4
CB4
CB4
CB4
VC3
VC3
VC3
CB3
CB3
CB3
VC2
VC2
VC2
CB2
CB2
CB2
VC1
VC1
VC1
CB1
CB1
CB1
VC0
VSS
VC0
VSS
VC0
VSS
FIGURE 32. BATTERY CONNECTION OPTIONS USING THE ISL94203EVAL1Z BOARD
When the device powers up, the ISL94203 transfers the contents
of the configuration EEPROM memory areas to RAM (Note: the
user EEPROM has no associated RAM). An external
microcontroller can read the contents of the Configuration RAM
or the contents of the EEPROM. Prior to reading the EEPROM, set
the EEEN bit to “1”. This enables access to the EEPROM area. If
EEEN is “0”, then a read or write occurs in the shadow RAM area.
The content of the Shadow Ram determines the operation of the
device.
Reading from the RAM or EEPROM can be done using a byte or
page read. See:
• “Current Address Read” on page 48,
• “Random Read” on page 48,
• “Sequential Read” on page 48, and
• “EEPROM Read” on page 49.
• “Register Protection” on page 49
Writing to the Configuration or User EEPROM must use a Page
Write operation. Each Page is four bytes in length and pages
begin at address 0.
44
FN7626.2
December 5, 2012
ISL94203
See:
Start Condition
• “Page Write” on page 46
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The device
continuously monitors the SDA and SCL lines for the start
condition and will not respond to any command until this
condition has been met (see Figure 34).
• “Register Protection” on page 49
The EEPROM contains an error detection and correction
mechanism. When reading a value from the EEPROM, the device
checks the data value for an error.
If there are no errors, then the EEPROM value is valid and the
ECC_USED and ECC_FAIL bits are set to “0”. If there is a 1-bit
error, the ISL94203 corrects the error and sets the ECC_USED bit.
This is a valid operation, and value read from the EEPROM is
correct. During an EEPROM read, if there is an error consisting of
two or more bits, the ISL94203 sets the ECC_FAIL bit
(ECC_USED = 0). This read contains invalid data.
The error correction is also active during the initial power-on
recall of the EEPROM values to the shadow RAM. The circuit
corrects for any one-bit errors. Two-bit errors are not corrected
and the contents of the shadow RAM maintain the previous
value.
Internally, the Power-On Recall circuit uses the ECC_USED and
ECC_FAIL bits to determine there is a proper recall before
allowing the device operation to start. However, an external µC
cannot use these bits to detect the validity of the shadow RAM on
power-up or determine the use of the error correction
mechanism, because the bits automatically reset on the next
valid read.
Serial Interface
• The ISL94203 uses a standard I2C interface, except the design
separates the SDA input and output (SDAI and SDAO)
• Separate SDAI and SDAO lines can be tied together and
operate as a typical I2C bus
• Interface speed is 400kHz, maximum
• A separate pin is provided to select the slave address of device.
This allows two devices to be cascaded
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter, and the receiving device as the receiver. The device
controlling the transfer is called the master and the device being
controlled is called the slave. The master always initiates data
transfers, and provides the clock for both transmit and receive
operations. Therefore, the ISL94203 devices operate as slaves in
all applications.
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is HIGH. The
stop condition is also used to place the device into the Standby
power mode after a read sequence. A stop condition is only
issued after the transmitting device has released the bus (see
Figure 34).
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either master
or slave, releases the bus after transmitting eight bits. During the
ninth clock cycle, the receiver pulls the SDA line LOW to
acknowledge that it received the eight bits of data (see
Figure 35).
The device responds with an acknowledge after recognition of a
start condition and the correct slave byte. If a write operation is
selected, the device responds with an acknowledge after the
receipt of each subsequent eight bits. The device acknowledges
all incoming data and address bytes, except for the slave byte
when the contents do not match the device’s internal slave
address.
In the read mode, the device transmits eight bits of data,
releases the SDA line, then monitor the line for an acknowledge.
If an acknowledge is detected and no stop condition is generated
by the master, the device will continue to transmit data. The
device terminates further data transmissions if an acknowledge
is not detected. The master must then issue a stop condition to
return the device to Standby mode and place the device into a
known state.
SCL
SDA
DATA
STABLE
DATA
CHANGE
DATA
STABLE
FIGURE 33. VALID DATA CHANGES ON I2C BUS
When sending or receiving data, the convention is the most
significant bit (MSB) is sent first. Therefore, the first address bit
sent is Bit 7.
Clock and Data
Data states on the SDA line can change only while SCL is LOW.
SDA state changes during SCL HIGH are reserved for indicating
start and stop conditions (see Figure 33).
45
FN7626.2
December 5, 2012
ISL94203
WATCHDOG
TIMER
RESET
SIGNALS
FROM THE
MASTER
SCL
SDA
START
SLAVE
BYTE
BYTE
ADDRESS
S
T
O
P
DATA
STOP
SDA BUS
1
8
0 1 0 1 0 0 0 0
SIGNALS
FROM THE
SLAVE
FIGURE 34. I2C START AND STOP BITS
SCL FROM
MASTER
S
T
A
R
T
9
A
C
K
A
C
K
A
C
K
ISL94203: SLAVE BYTE = 50H (ADDR = 0)
ISL94203: SLAVE BYTE = 52H (ADDR = 1)
DATA OUTPUT
FROM
TRANSMITTER
FIGURE 36. BYTE WRITE SEQUENCE
DATA OUTPUT
FROM RECEIVER
PAGE WRITE
START
ACKNOWLEDGE
FIGURE 35. ACKNOWLEDGE RESPONSE FROM RECEIVER
Write Operations
BYTE WRITE
For a byte write operation, the device requires the Slave Address
Byte and a Word Address Byte. This gives the master access to
any one of the words in the array. After receipt of the Word
Address Byte, the device responds with an acknowledge, and
awaits the next eight bits of data. After receiving the 8 bits of the
Data Byte, the device again responds with an acknowledge. The
master then terminates the transfer by generating a stop
condition, at which time the device begins the internal write cycle
to the nonvolatile memory. During this internal write cycle, the
device inputs are disabled, so the device will not respond to any
requests from the master. The SDA output is at high impedance.
See Figure 36.
A page write operation is initiated in the same manner as the
byte write operation; but instead of terminating the write cycle
after the first data byte is transferred, the master can transmit an
unlimited number of 8-bit bytes. After the receipt of each byte,
the device will respond with an acknowledge, and the address is
internally incremented by one. The page address remains
constant. When the counter reaches the end of the page, it “rolls
over” and goes back to ‘0’ on the same page. This means that
the master can write 4 bytes to the page starting at any location
on that page. If the master begins writing at location 2, and loads
4 bytes, then the first 2 bytes are written to locations 2 and 3,
and the last 2 bytes are written to locations 0 and 1. Afterwards,
the address counter would point to location 2 of the page that
was just written. If the master supplies more than 4 bytes of
data, then new data overwrites the previous data, one byte at a
time. See Figure 37.
Do not write to addresses 58H through 7FH or locations higher
than address ABH, since these addresses access registers that
are reserved. Writing to these locations can result in unexpected
device operation.
A write to a protected block of memory suppresses the
acknowledge bit.
When writing to the EEPROM, write to all addresses of a page
without an intermediate read operation, or use a page write
command. Each page is 4 bytes long, starting at address 0.
ADDRESS = 0
DATA BYTE 3
ADDRESS = 1
DATA BYTE 4
ADDRESS = 2
DATA BYTE 1
ADDRESS = 3
DATA BYTE 2
ADDRESS POINTER STARTS AND ENDS HERE
FIGURE 37. WRITING 4 BYTES TO A 4-BYTE PAGE STARTING AT LOCATION 2
46
FN7626.2
December 5, 2012
ISL94203
SIGNALS FROM
THE MASTER
WATCHDOG TIMER RESET
SIGNALS FROM
THE SLAVE
SDA BUS
S
T
A
R
T
SLAVE
BYTE
REGISTER
ADDRESS
S
T
O
P
DATA(n)
DATA(1)
01010000
A
C
K
A
C
K
A
C
K
A
C
K
ISL94203: SLAVE BYTE = 50H (ADDR = 0)
ISL94203: SLAVE BYTE = 52H (ADDR = 1)
FIGURE 38. PAGE WRITE SEQUENCE
47
FN7626.2
December 5, 2012
ISL94203
SIGNALS FROM
THE MASTER
WATCHDOG TIMER RESET
SLAVE
BYTE
S
T
A
R
T
REGISTER
ADDRESS
01010000
SIGNALS FROM
THE SLAVE
SDA BUS
S
T
A
R
T
N
A
C
K
SLAVE
BYTE
S
T
O
P
01010001
A
C
K
A
C
K
A
C
K
DATA
A
C
K
ISL94203: SLAVE BYTE = 50H (ADDR = 0)
ISL94203: SLAVE BYTE = 52H (ADDR = 1)
FIGURE 39. RANDOM READ SEQUENCE
WATCHDOG TIMER RESET
N
A
C
K
SLAVE
BYTE
S
T
O
P
1
A
C
K
DATA 1
A
C
K
DATA 2
A
C
K
DATA (n-1)
A
C
K
DATA (n)
ISL94203: SLAVE BYTE = 50H (ADDR = 0)
ISL94203: SLAVE BYTE = 52H (ADDR = 1)
FIGURE 40. SEQUENTIAL READ SEQUENCE
Read Operations
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of the Slave
Address Byte is set to one. There are three basic read operations:
Current Address Reads, Random Reads, and Sequential Reads.
CURRENT ADDRESS READ
Internally the device contains an address counter that maintains
the address of the last word read incremented by one. Therefore,
if the last read was to address n, the next read operation would
access data from address n+1. On power-up, the address of the
address counter is undefined, requiring a read or write operation
for initialization. See Figure 41.
Upon receipt of the Slave Address Byte with the R/W bit set to
one, the device issues an acknowledge and then transmits the
eight bits of the Data Byte. The master terminates the read
operation when it does not respond with an acknowledge during
the ninth clock and then issues a stop condition.
It should be noted that the ninth clock cycle of the read operation
is not a “don’t care.” To terminate a read operation, the master
must either issue a stop condition during the ninth cycle or hold
SDA HIGH during the ninth clock cycle and then issue a stop
condition.
RANDOM READ
Random read operation allows the master to access any memory
location in the array. Prior to issuing the Slave Address Byte with
48
the R/W bit set to one, the master must first perform a “dummy”
write operation. The master issues the start condition and the
Slave Address Byte, receives an acknowledge, then issues the
Word Address Bytes. After acknowledging receipts of the Word
Address Bytes, the master immediately issues another start
condition and the Slave Address Byte with the R/W bit set to one.
This is followed by an acknowledge from the device and then by
the eight bit word. The master terminates the read operation by
not responding with an acknowledge and then issuing a stop
condition (see Figure 39).
SEQUENTIAL READ
Sequential reads can be initiated as either a current address
read or random address read. The first Data Byte is transmitted
as with the other modes; however, the master now responds with
an acknowledge, indicating it requires additional data. The
device continues to output data for each acknowledge received.
The master terminates the read operation by not responding with
an acknowledge and then issuing a stop condition.
The data output is sequential, with the data from address n
followed by the data from address n + 1. The address counter for
read operations increments through all page and column
addresses, allowing the entire memory contents to be serially
read during one operation. At the end of the address space the
counter “rolls over” to address 0000H and the device continues
to output data for each acknowledge received. See Figure 40 for
the acknowledge and data transfer sequence.
FN7626.2
December 5, 2012
ISL94203
SIGNALS FROM
THE MASTER
WATCHDOG TIMER RESET
SIGNALS FROM
THE SLAVE
SDA BUS
S
T
A
R
T
N
A
C
K
SLAVE
BYTE
S
T
O
P
01010001
A
C
K
DATA
A
C
K
ISL94203: SLAVE BYTE = 50H (ADDR = 0)
ISL94203: SLAVE BYTE = 52H (ADDR = 1)
FIGURE 41. CURRENT ADDRESS READ SEQUENCE
EEPROM READ
The ISL94203 has a special requirement when reading the
EEPROM. An EEPROM read operation from the first byte of a four
byte page (locations 0H, 4H, 8H, etc.) initiates a recall of the
EEPROM page. This recall takes more than 200µs, so the first
byte may not be ready in time for a standard I2C response. It is
necessary to either read this first byte of every page two times, or
add a loop awaiting an ACK before proceeding to the next byte in
the read operation. Adding the wait for ACK works for all read
operations, so is the preferred method.
The enable byte is encoded, so that a value of ‘0’ in the EEPROM
Enable register (89H) enables access to the shadow memory
(RAM), a value of ‘1’ allows access to the EEPROM.
After a read or write of the EEPROM, the microcontroller should
reset the EEPROM Enable register value back to zero to prevent
inadvertent writes to the EEPROM and to turn off the EEPROM
block to reduce current consumption. If the microcontroller fails
to reset the EEPROM bit, and communications to the chip stops,
then the Watchdog timer will reset the EEPROM select bit.
Register Protection
The entire EEPROM memory is write protected on initial power-up
and during normal operation. An enable byte allows writing to
various areas of the memory array.
49
FN7626.2
December 5, 2012
ISL94203
Registers: Summary (EEPROM)
TABLE 12. EEPROM REGISTER SUMMARY
EEPROM (CONFIGURED AS 32 4-BYTE PAGES)
PAGE
ADDR
0x
1x
2x
3x
4x
5x
0
0
Overvoltage Level
Overvoltage Delay
Timer
Min CB Delta
Charge Over-Temp
Level
Internal Over-Temp
Level
User EEPROM
Overvoltage
recovery
Undervoltage Delay
Timer
Max CB Delta
Charge Over-Temp
Recovery
Internal Over-Temp
Recovery
Undervoltage Level
Open Wire Timing
Undervoltage
Recovery
Discharge
overcurrent timeout
Settings, Discharge
Setting
Cell Balance Off
Time
OVLO Threshold
Charge overcurrent
Timeout Settings,
Charge overcurrent
Setting
Min CB Temp Level
Short Circuit
Timeout Settings/
Recovery Settings,
Short Circuit Setting
EOC Voltage Level
Low Voltage Charge
Level
1
2
3
1
4
5
6
7
2
8
9
UVLO Threshold
A
B
3
C
Cell Balance On time Charge Under-Temp
Level
F
Charge Under-Temp Sleep Delay Timer/
Recovery
Watchdog Timer
Discharge
Over-Temp Level
Sleep Mode Timer
Min CB Temp
Recovery
Discharge
Over-Temp Recovery
Features 1
Min CB Volts
Max CB Temp Level
Discharge UnderTemp Level
Reserved
Max CB Volts
Max CB Temp
Recovery
Discharge UnderTemp Recovery
D
E
Sleep Voltage
Reserved
CELLS Config
Features 2
Registers: Summary (RAM)
TABLE 13. RAM REGISTER SUMMARY
RAM
PAGE
ADDR
8x
9x
Ax
0
0
Status1
CELL1 Voltage
iT Voltage
1
Status2
2
Status3
CELL2 Voltage
xT1 Voltage
3
Status4
4
Cell Balance
CELL3 Voltage
xT2 Voltage
5
Analog Out
6
FET Cntl/Override Control Bits
CELL4 Voltage
VBATT/16 Voltage
7
Override Control Bits
8
Force Ops
CELL5 Voltage
VRGO/2 Voltage
9
EE Write Enable
A
CELLMIN Voltage
CELL6 Voltage
14-bit ADC Voltage
1
2
B
50
FN7626.2
December 5, 2012
ISL94203
TABLE 13. RAM REGISTER SUMMARY (Continued)
RAM
PAGE
ADDR
8x
9x
Ax
3
C
CELLMAX Voltage
CELL7 Voltage
Reserved
ISense Voltage
CELL8 Voltage
D
E
F
Registers: Detailed (EEPROM)
TABLE 14. EEPROM REGISTER DETAIL
BIT/
ADDR
00
01
F
7
E
6
D
5
C
4
B
3
A
2
9
1
CPW3
CPW2
CPW1
OVLB
OVLA
OVL9
LPW2
LPW1
OVL6
OVL5
2
1E2A
OVL4
OVL3
1
0
(V):
OVL2
OVL1
4.25
OVL0
4095 × 3
OVRA
OVR9
OVR8
OVR7
Default (Hex): 0DD4
OVR6
UVLB
UVLA
UVL9
UVL8
UVL7
LPW0
OVR5
OVR4
OVR3
Default (Hex):
UVL6
UVL5
(V):
OVR2
18FF
UVL4
UVL3
OVR1
(V):
UVL2
UVL1
4.15
OVR0
2.7
UVL0
HEXvalue 10 × 1.8 × 8
Threshold = ------------------------------------------------------------
4095 × 3
Undervoltage Recovery
If all cells rise above this overvoltage recovery level (and there is no load), the
discharge FET is turned on.
UVRB
UVRA
UVR9
UVR8
UVR7
Overvoltage Lock-out Threshold
If any cell voltage is above this threshold for five successive scans, then the
device is in an overvoltage lock out condition. In this condition, the Charge FET
is turned off, the cell balance FETs are turned off, the OVLO bit is set, and the PSD
output is set to active.
Reserved
3
HEXvalue 10 × 1.8 × 8
0000 = 0 ms to
1111 = 15ms; Default = 1ms
Reserved
4
Default (Hex):
Undervoltage Threshold
If any cell voltage is below this threshold voltage for an undervoltage delay time,
the discharge FET is turned off.
LPW3
0A
0B
OVL7
5
Threshold = ------------------------------------------------------------
OVRB
Load Detect Pulse Width
These bits set the duration of the
charger monitor pulse width.
08
09
6
Overvoltage Recovery
If all cells fall below this overvoltage recovery level, the charge FET is turned on.
Reserved
06
07
OVL8
CPW0
0000 = 0ms to
1111 = 15ms; Default = 1ms
04
05
7
Overvoltage Threshold
If any cell voltage is above this threshold voltage for an overvoltage delay time,
the charge FET is turned off.
Charge Detect Pulse Width
These bits set the duration of the
charger monitor pulse width.
02
03
8
0
Default (Hex):
UVR6
UVR5
UVR4
Default (Hex):
09FF
UVR3
0E7F
V):
UVR2
UVR1
(V):
3.0
UVR0
4.35
OVLOB OVLOA OVLO9 OVLO8 OVLO7 OVLO6 OVLO5 OVLO4 OVLO3 OVLO2 OVLO1 OVLO0
Undervoltage Lock-out Threshold
If any cell voltage is below this threshold for five successive scans, then the
device is in an undervoltage lock-out condition. In this condition, the Discharge
FET is turned off and the UVLO bit is set. The device also powers down (unless
overridden).
Reserved
Default (Hex): 0600A
(V):
1.8
UVLOB UVLOA UVLO9 UVLO8 UVLO7 UVLO6 UVLO5 UVLO4 UVLO3 UVLO2 UVLO1 UVLO0
51
FN7626.2
December 5, 2012
ISL94203
TABLE 14. EEPROM REGISTER DETAIL (Continued)
BIT/
ADDR
0C
0D
F
7
E
6
D
5
C
4
EOCB
9
1
8
0
7
6
EOCA
EOC9
EOC8
EOC7
LVCHB
LVCHA
LVCH9
LVCH8
LVCH7
EOC6
LVCH6
0DFF
EOC3
LVCH5
LVCH4
LVCH3
1
(V):
EOC2
EOC1
(V):
LVCH2
LVCH1
(sec):
0
4.2
EOC0
2.3
LVCH0
1
0 to 1024
Undervoltage Delay Time Out
This value sets the time that is required for any cell to be below the undervoltage
threshold before an undervoltage condition is detected.
Default (Hex): 0801
(sec):
1
UVDTB UVDTA UVDT9 UVDT8 UVDT7 UVDT6 UVDT5 UVDT4 UVDT3 UVDT2 UVDT1 UVDT0
00 = µs
01 = ms
10 = sec
11 = min
0 to 1024
Open Wire Timing (OWT)
This value sets the width of the open wire test pulse for each cell input.
Reserved
OWT
9
OWT
8
Default (Hex):
OWT
7
0=
µs
1 = ms
16
17
EOC4
2
OVDTB OVDTA OVDT9 OVDT8 OVDT7 OVDT6 OVDT5 OVDT4 OVDT3 OVDT2 OVDT1 OVDT0
Reserved
14
15
EOC5
3
Default (Hex): 0801
00 = µs
01 = ms
10 = sec
11 = min
12
13
4
Default (Hex): 07AA
Overvoltage Delay Time Out
This value sets the time that is required for any cell to be above the overvoltage
threshold before an overvoltage condition is detected.
Reserved
5
Default (Hex):
Low Voltage Charge Level
If the voltage on any cell is less than this level, then the PCFET output turns on
instead of the PC output. To disable this function, set the value to zero or set the
PCFETE bit to 0.
Reserved
10
11
A
2
End-of-Charge (EOC) Threshold
If any cell exceeds this level, then the EOC output and the EOC bit are set.
Reserved
0E
0F
B
3
Discharge Overcurrent Time Out/Threshold
Time Out
A discharge overcurrent needs to remain for this time period prior to entering a
discharge overcurrent condition. This is an 12-bit value: Lower 10 bits sets the
time. Upper bits sets the time base.
OWT
6
OWT
5
OWT
4
0214
OWT
3
(ms):
OWT
2
OWT
1
20
OWT
0
0 to 512
Default (Hex): 44A0
(ms):
(mV):
160
32
Threshold
This value sets the voltage across
current sense resistor that creates
a discharge overcurrent condition.
OCD2
OCD1
OCD0
000 = 4mV
001 = 8mV
010 = 16mV
011 = 24mV
100 = 32mV
101 = 48mV
110 = 64mV
111 = 96mV
OCDTB OCDTA OCDT9 OCDT8 OCDT7 OCDT6 OCDT5 OCDT4 OCDT3 OCDT2 OCDT1 OCDT0
00 = µs
01 = ms
10 = sec
11 = min
52
0 to 1024
FN7626.2
December 5, 2012
ISL94203
TABLE 14. EEPROM REGISTER DETAIL (Continued)
BIT/
ADDR
18
19
F
7
E
6
D
5
C
4
B
3
A
2
9
1
8
0
7
6
Charge Overcurrent Time Out/Threshold
Time Out
A charge overcurrent needs to remain for this time period prior to entering a
charge overcurrent condition. This is an 12-bit value: Lower 10 bits sets the time.
Upper bits set the time base.
5
4
3
2
Default (Hex): 44A0
1
(ms):
(mV):
0
160
8
Threshold
This value sets the voltage across
current sense resistor that creates
a charge overcurrent condition
OCC2
OCC1
OCC0
000 = 1mV
001 = 2mV
010 = 4mV
011 = 6mV
100 = 8mV
101 = 12mV
110 = 16mV
111 = 24mV
1A
1B
OCCTB OCCTA OCCT9 OCCT8 OCCT7 OCCT6 OCCT5 OCCT4 OCCT3 OCCT2 OCCT1 OCCT0
00 = µs
01 = ms
10 = sec
11 = min
0 to 1024
Discharge Short Circuit Time Out/Threshold
Time Out
A short circuit current needs to remain for this time period prior to entering a
short circuit condition. This is an 12 bit value:
Lower 10 bits sets the time. Upper bits set the time base
Default (Hex): 60C8
(µs):
(mV):
200
128
Threshold
This value sets the voltage across
current sense resistor that creates
a short circuit condition
SCD2
SCD1
SCD0
000 = 16mV
001 = 24mV
010 = 32mV
011 = 48mV
100 = 64mV
101 = 96mV
110 = 128mV
111 = 256mV
1C
1D
CBVLB
SCT8
SCT7
SCT6
CBVLA
SCT5
SCT4
SCT3
SCT2
SCT1
SCT0
0 to 1024
CBVL9
Default (Hex): 0A55
CBVL8
CBVL7
Cell Balance Maximum Voltage (CBMAX)
If any cell is greater than this voltage, then cell balance stops.
CBVL6
CBVL5
CBVL4
CBVL3
Default (Hex): 0D70
(V):
CBVL2
CBVL1
(V):
3.1
CBVL0
4.0
CBVUB CBVUA CBVU9 CBVU8 CBVU7 CBVU6 CBVU5 CBVU4 CBVU3 CBVU2 CBVU1 CBVU0
Cell Balance Minimum Differential Voltage (CBMINDV)
If the difference between the voltage on CELLN and the lowest voltage cell is less
than this voltage, then cell balance for CELLN stops.
Reserved
22
23
SCT9
Cell Balance Minimum Voltage (CBMIN)
If any cell is less than this voltage, then cell balance stops.
Reserved
20
21
SCTA
00 = µs
01 = ms
10 = sec
11 = min
Reserved
1E
1F
SCTB
Default (Hex):
0010
(mV):
20
CBDLB CBDLA CBDL9 CBDL8 CBDL7 CBDL6 CBDL5 CBDL4 CBDL3 CBDL2 CBDL1 CBDL0
Cell Balance Maximum Differential Voltage (CBMAXDV)
If the difference between the voltage on CELLN and the lowest voltage cell is
greater than this voltage, then cell balance for CELLN stops and the CELLF flag
is set.
Reserved
Default (Hex): 01AB
(mV):
500
CBDUB CBDUA CBDU9 CBDU8 CBDU7 CBDU6 CBDU5 CBDU4 CBDU3 CBDU2 CBDU1 CBDU0
53
FN7626.2
December 5, 2012
ISL94203
TABLE 14. EEPROM REGISTER DETAIL (Continued)
BIT/
ADDR
24
25
F
7
E
6
D
5
C
4
B
3
A
2
9
1
8
0
7
Cell Balance On Time (CBON)
Cell balance is on for this set amount of time, unless another condition indicates
that there should be no cell balance. This is a 12-bit value: Lower 10 bits sets the
time. Upper 2 bits set the time base.
Reserved
Cell Balance Off Time (CBOFF)
Cell balance is off for the set amount of time. This is a 12-bit value: Lower 10 bits
sets the time. Upper 2 bits set the time base.
Reserved
Cell Balance Minimum Temperature Limit (CBUTS)
If the external 1 temperature, or the external 2 temperature (XT2M = 0) is
greater than this voltage, then cell balance stops. The voltage is based on
recommended external components (see Figure 26 on page 36).
Reserved
2A
2B
Cell Balance Minimum Temperature Recovery Level (CBUTR)
If the external 1 temperature, and the external 2 temperature (XT2M = 0) all
recover and fall below this voltage, then cell balance can resume (all other
conditions OK) .The voltage is based on recommended external components
(see Figure 26 on page 36).
Default (Hex): 0802
2
1
(sec):
0
2
0 to 1024
Default (Hex): 0802
(sec):
2
0 to 1024
Default (Hex):
0BF2
(V): 1.344
(°C): -10
Default (Hex): 0A93
(V):
(°C):
1.19
+5
CBUTR CBUTR CBUTR CBUTR CBUTR CBUTR CBUTR CBUTR CBUTR CBUTR CBUTR CBUTR
B
A
9
8
7
6
5
4
3
2
1
0
Cell Balance Maximum Temperature Limit (CBOTS)
If the external 1 temperature, or the external 2 temperature (XT2M = 0) is less
than this voltage, then cell balance stops. The voltage is based on recommended
external components (see Figure 26 on page 36).
Reserved
2E
2F
3
CBUTS CBUTS CBUTS CBUTS CBUTS CBUTS CBUTS CBUTS CBUTS CBUTS CBUTS CBUTS
B
A
9
8
7
6
5
4
3
2
1
0
Reserved
2C
2D
4
CBOFT CBOFT CBOFT CBOFT CBOFT CBOFT CBOFT CBOFT CBOFT CBOFT CBOFT CBOFT
B
A
9
8
7
6
5
4
3
2
1
0
00 = µs
01 = ms
10 = sec
11 = min
28
29
5
CBONT CBONT CBONT CBONT CBONT CBONT CBONT CBONT CBONT CBONT CBONT CBONT
B
A
9
8
7
6
5
4
3
2
1
0
00 = µs
01 = ms
10 = sec
11 = min
26
27
6
Default (Hex): 04B6
(V): 0.530
(°C): +55
CBOTS CBOTS CBOTS CBOTS CBOTS CBOTS CBOTS CBOTS CBOTS CBOTS CBOTS CBOTS
B
A
9
8
7
6
5
4
3
2
1
0
Cell Balance Maximum Temperature Recovery Level (CBOTR)
If the external 1 temperature, and the external 2 temperature (XT2M = 0) all
recover and rise above this voltage, then cell balance can resume (all other
conditions OK) .The voltage is based on recommended external components
(see Figure 26 on page 36).
Reserved
Default (Hex):
053E
(V): 0.590
(°C): +50
CBOTR CBOTR CBOTR CBOTR CBOTR CBOTR CBOTR CBOTR CBOTR CBOTR CBOTR CBOTR
B
A
9
8
7
6
5
4
3
2
1
0
For All Temperature Limits, TGain bit = 0, Temperature Gain = 2
30
31
Charge Over-Temperature Voltage
If external 1 temperature or the external 2 temperature is less than this voltage,
then the charge FET is turned off and the COT bit is set. The voltage is based on
recommended external components (see Figure 26 on page 36).
Reserved
Default (Hex): 04B6
(mV): 0.530
(°C): +55
COTSB COTSA COTS9 COTS8 COTS7 COTS6 COTS5 COTS4 COTS3 COTS2 COTS1 COTS0
54
FN7626.2
December 5, 2012
ISL94203
TABLE 14. EEPROM REGISTER DETAIL (Continued)
BIT/
ADDR
32
33
F
7
E
6
D
5
C
4
3
2
053E
1
0
(mV): 0.590
(°C): +50
Default (Hex):
0BF2
(mV): 1.344
(°C): -10
Default (Hex): 0A93
(mV): 1.190
(°C):
+5
Default (Hex):
4B6
(mV): 0.530
(°C): +55
DOTSB DOTSA DOTS9 DOTS8 DOTS7 DOTS6 DOTS5 DOTS4 DOTS3 DOTS2 DOTS1 DOTS0
Discharge Over-Temperature Recovery Voltage
If external 1 temperature or the external 2 temperature rise above this setting,
then the discharge FET is turned on and the DOT bit is reset (unless over-rides
are in place). The voltage is based on recommended external components (see
Figure 26 on page 36).
Default (Hex):
053E
(mV): 0.590
(°C): +50
DOTRB DOTRA DOTR9 DOTR8 DOTR7 DOTR6 DOTR5 DOTR4 DOTR3 DOTR2 DOTR1 DOTR0
Discharge Under-Temperature Voltage
If external 1 temperature or the external 2 temperature is greater than this
voltage, then the discharge FET is turned off and the DUT bit is set. The voltage
is based on recommended external components (see Figure 26 on page 36).
Default (Hex):
0BF2
(mV): 1.344
(°C): -10
DUTSB DUTSA DUTS9 DUTS8 DUTS7 DUTS6 DUTS5 DUTS4 DUTS3 DUTS2 DUTS1 DUTS0
Discharge Under-Temperature Recovery Voltage
If external 1 temperature or the external 2 temperature fall below this setting,
then the discharge FET is turned on and the DUT bit is reset (unless over-rides are
in place). The voltage is based on recommended external components (see
Figure 26 on page 36).
Default (Hex): 0A93
(mV): 1.190
(°C):
+5
DUTRB DUTRA DUTR9 DUTR8 DUTR7 DUTR6 DUTR5 DUTR4 DUTR3 DUTR2 DUTR1 DUTR0
Internal Over-Temperature Voltage
If the internal temperature is greater than this voltage, then all FETs are turned
off and the IOT bit is set.
Reserved
42
43
4
Default (Hex):
Discharge Over-Temperature Voltage
If external 1 temperature or the external 2 temperature is less than this voltage,
then the discharge FET is turned off and the DOT bit is set. The voltage is based
on recommended external components (see Figure 26 on page 36).
Reserved
40
41
5
CUTRB CUTRA CUTR9 CUTR8 CUTR7 CUTR6 CUTR5 CUTR4 CUTR3 CUTR2 CUTR1 CUTR0
Reserved
3E
3F
6
Charge Under Temperature Recovery Voltage
If external 1 temperature or the external 2 temperature fall below this setting,
then the charge FET is turned on and the CUT bit is reset (unless over-rides are
in place). The voltage is based on recommended external components (see
Figure 26 on page 36).
Reserved
3C
3D
7
CUTSB CUTSA CUTS9 CUTS8 CUTS7 CUTS6 CUTS5 CUTS4 CUTS3 CUTS2 CUTS1 CUTS0
Reserved
3A
3B
8
0
Charge Under Temperature Voltage
If external 1 temperature or the external 2 temperature is greater than this
voltage, then the charge FET is turned off and the CUT bit is set. The voltage is
based on recommended external components (see Figure 26 on page 36).
Reserved
38
39
9
1
COTRB COTRA COTR9 COTR8 COTR7 COTR6 COTR5 COTR4 COTR3 COTR2 COTR1 COTR0
Reserved
36
37
A
2
Charge Over-Temperature Recovery Voltage
If external 1 temperature or the external 2 temperature rise above this setting,
then the charge FET is turned on and the COT bit is reset (unless overrides are in
place). The voltage is based on recommended external components (see
Figure 26 on page 36).
Reserved
34
35
B
3
IOTS
B
IOTS
A
IOTS 9
IOTS 8
IOTS 7
Internal Over-Temperature Recovery Voltage
When the internal temperature voltage drops below this level, then the FETs can
be turned on again and the IOT bit is reset on the next µC read.
Reserved
IOTR
B
55
IOTR
A
Default (Hex): 67CH
IOTS 6
IOTS 5
IOTS 4
IOTS 3
Default (Hex): 621H
(mV): 0.73
(°C): +115
IOTS 2
IOTS 1
(mV):
(°C):
IOTS 0
0.69
+95
IOTR 9 IOTR 8 IOTR 7 IOTR 6 IOTR 5 IOTR 4 IOTR 3 IOTR 2 IOTR 1 IOTR 0
FN7626.2
December 5, 2012
ISL94203
TABLE 14. EEPROM REGISTER DETAIL (Continued)
BIT/
ADDR
44
45
F
7
E
6
D
5
C
4
A
2
9
1
8
0
7
6
Sleep Level Voltage
If any cell voltage is below this threshold voltage for a sleep delay time, the
device goes into the sleep mode.
Reserved
46
47
B
3
SLLB
SLLA
SLL 9
SLL 8
SLL 7
5
4
3
2
Default (Hex): 06AA
SLL 6
Sleep Delay Timer/Watchdog Timer
Sleep Delay
This value sets the time that is required for any cell to be below the sleep voltage
threshold before the device enters the sleep mode. Lower 10 bits sets the time.
Upper 1 bit sets the time base.
SLL 5
SLL 4
Default (Hex):
1
(V):
SLL 3
SLL 2
FC0F
Sleep
WDT
SLT3
SLT2
83FF
Idle/
Doze:
Sleep
Mode
SLL 1
(sec)
(sec)
0
2.0
SLL 0
1
31
Watchdog Timer (WDT)
Time allowed the microcontroller between
I2C slave byte writes to the ISL94203 after
setting any over-ride bit.
WDT4
WDT3
WDT2
WDT1
WDT0
0 to 31 seconds
48
49
SLTA
SLT9
SLT8
SLT7
SLT6
SLT5
00 = us
01 = ms
10 = sec
11 = min
SLT4
SLT1
SLT0
0 to 511
Sleep Mode Timer/Cell Configuration
Mode Timer
Time required to enter sleep mode from the DOZE mode when no current is
detected.
Default (Hex):
(min)
(min)
Cells
16
240
3
Cell Configuration
Only these combinations are acceptable. Any other combination will
prevent any FET from turning on.
CELL8
CELL7
CELL6
CELL5
CELL4
CELL3
CELL2
87654321
NUMBER OF CELLS
10000011
3 Cells connected
11000011
4 Cells connected
11000111
5 Cells connected
11100111
6 Cells connected
11101111
7 Cells connected
11111111
8 Cells connected
56
CELL1
MOD7
MOD6
MOD5
MOD4
MOD3
MOD2
MOD1
MOD0
IDLE and DOZE Mode:
[MOD3:0] = 0 to 16 Minutes
SLEEP Mode
[MOD7:0] = 0 to 240 Minutes
Example:
Value = 0101 1010
IDLE/DOZE = 10 minutes
SLEEP = 90 minutes
FN7626.2
December 5, 2012
ISL94203
TABLE 15. EEPROM REGISTER DETAIL (FEATURE CONTROLS)
BIT/
ADDR
4A
7
CFPSD
CELLF PSD
6
Reserved
1=
Activates PSD
output when a
“Cell Fail”
condition
occurs.
0=
Does NOT
activate PSD
output when a
cell fails
condition
occurs.
4B
CBDD
CB during
Discharge
1=
Do balance
during discharge
0=
No balance
during discharge
When both
CBDD and CBDC
equal “0”, cell
balance is
turned off.
5
4
3
2
1
0
XT2M
xTemp 2 mode
control
TGain
External Temp
Gain
CASC
Two devices
cascaded
PCFETE
Precharge FET
enable
DOWD
Disable Open
wire scan
OWPSD
Open wire PSD
1=
xT2 monitors
FET temp. Cell
balance outputs
are not shut off
when xT2
temperature
exceeds Cell
Balance limits
0=
xT2 monitors
cell temp.
(Normal
operation.)
1=
Gain of iT, xT1,
and xT2 inputs is
1x.
0=
Gain of iT, xT1,
and xT2 inputs is
2x.
1=
The device is
cascaded with
another device.
As such, the cell
balance function
is disabled.
0=
There is only one
device in the
system.
1=
Precharge FET
output turns on
instead of the
CFET output
when any of the
cell voltages are
below the under
the LVCHG
threshold.
0=
Precharge FET is
not used
1=
Disable the
input open wire
detection scan
0=
Enable the input
open wire
detection scan
UVLOPD
Enable UVLO
power-down
Reserved
Reserved
CBDC
CB during
Charge
DFODUV
CFODOV
DFET on during CFET on during
UV (charging) OV (discharging)
1=
Do balance
during charge
1=
Keep CFET on
while the pack is
discharging, reg
ar de ss of the
cell voltage. This
minimizes CFET
power
dissipation
during OV, when
the pack is
discharging
0=
Normal CFET
operation.
1=
Keep DFET on
while the pack is
charging,
regardless of the
0=
cell voltage. This
No balance
minimizes DFET
during charge
power
dissipation
When both
CBDD and CBDC during UV, when
the pack is
equal “0”, cell
charging
balance is
0=
turned off.
Normal DFET
operation.
1=
The device
powers down
when detecting
an UVLO
condition.
0=
When a UVLO
condition is
detected, the
device remains
powered.
4C
4F
Reserved
50
57
User EEPROM
Available to the user (Note: There is no shadow memory associated with these registers).
57
1=
Responds
automatically to
the input Open
Wire condition
AND sets PSD.
0=
Responds
automatically to
the input Open
Wire condition
and DOES NOT
set PSD.
CB_EOC
Enable CBAL
during EOC
1=
Cell balance
occurs during
EOC condition
regardless of
current
direction.
0=
Cell balance
turns off during
EOC if there is no
current flowing.
FN7626.2
December 5, 2012
ISL94203
Registers: Detailed (RAM)
TABLE 16. RAM REGISTER DETAIL (STATUS AND CONTROL)
BIT/
ADDR
7
6
5
4
3
2
1
0
80
(Read
only)
CUT
Charge under
temp
COT
Charge
over-temp
DUT
Discharge
under-temp
DOT
Discharge overtemp
UVLO
Undervoltage
lock-out
UV
Undervoltage
OVLO
Overvoltage
lock-out
OV
Overvoltage
These
bits are
set and
reset by
the
device.
An external
thermistor
shows the temp
is lower than the
min charge
temp limit.
An external
thermistor
shows the temp
is higher than
the max charge
temp limit.
An external
thermistor
shows the temp
is lower than the
min discharge
temp limit.
An external
thermistor
shows the temp
is higher than
the max
discharge temp
limit.
At least one cell is
below the
undervoltage
lock-out
threshold.
At least one cell
has an
undervoltage
condition.
At least one cell
is above the
overvoltage
lock-out
threshold.
At least one cell
has an
overvoltage
condition.
81
(Read
only)
EOCHG
End of charge
Reserved
OPEN
Open wire
CELLF
Cell Fail
DSC
Discharge short
circuit
DOC
Discharge
overcurrent
COC
Charge
overcurrent
IOT
Internal
over-temp
These End of charge
bits are voltage reached.
set and
reset by
the
device
82
(Read
only)
LVCHG
Low voltage
charge
These
bits are
set and
reset by
the
device
At least one cell
voltage < LVCHG
threshold. If set,
PCFET turns on
instead of CFET.
83
(Read
only)
Reserved
Reserved
IN_SLEEP
In sleep mode
No scans. RGO
remains on,
VREF off.
Monitors for a
charger or load
connection.
These
bits are
set and
reset by
the
device
84
(R/W)
An open input
circuit is
detected.
Indicates that
there is more
than the
maximum
allowable
voltage
difference
between cells.
ECC_FAIL
EEPROM Error
Correct Fail
ECC_USED
EEPROM Error
Correct
EEPROM error
correction
failed. Two bits
failed, error not
corrected.
Previous value
retained.
EEPROM error
correction used.
One bit failed,
bit error
corrected.
IN_DOZE
In doze mode
IN_IDLE
In Idle mode
Scans every
512ms.
Scans every
256ms
Short circuit
Excessive
current detected. Charge current
detected.
Excessive
discharge
current
detected.
The internal
sensor indicates
an overtemperature
condition.
DCHING
Discharging
CHING
Charging
CH_PRSNT
Chrgr present
LD_PRSNT
Load present
Indicates that a
discharge current
is detected.
Charge current is
flowing out of the
pack.
Indicates that a
charge current is
detected.
Charge current
is flowing into
the pack.
Set to “1” during
COC, while
charger is
attached.
(CHMON >
threshold.)
If µCLMON = “0”,
bit resets
automatically. If
µCLMON = “1”,
bit resets by µC
read of register.
Set to “1” during
DOC or DSC,
while load
attached.
(LDMON <
threshold.)
If µCCMON =
“0”, bit resets
automatically. If
µCCMON = “1”,
bit resets by µC
read of register.
CBUV
Cell balance
undervoltage
CBOV
Cell balance
overvoltage
CBUT
Cell balance
under temp
CBOT
Cell balance
over-temp
All cell voltages <
the minimum
allowable cell
balance voltage
threshold.
All cell voltages
> the maximum
allowable cell
balance voltage
threshold.
xT1 or xT2
indicates temp <
allowable cell
balance low
temperature
threshold
xT1 or xT2
indicates temp >
allowable cell
balance high
temperature
threshold
CB4ON
CB3ON
CB2ON
CB1ON
Cell balance FET control bits
These bits control the cell balance when the external controller overrides the internal cell balance operation.
CB8ON
CB7ON
CB6ON
CB5ON
If µCCBAL=1, CBAL_ON=1, and CBnON bit = 1 the cell balance FET is on.
If µCCBAL=0, CBAL_ON=0, or CBnON bit = 0 the cell balance FET is off.
58
FN7626.2
December 5, 2012
ISL94203
TABLE 16. RAM REGISTER DETAIL (STATUS AND CONTROL) (Continued)
BIT/
ADDR
85
(R/W)
7
6
5
4
3
2
1
0
AO3
AO2
AO1
AO0
Analog MUX control bits
Voltage monitored by ADC when microcontroller overrides the internal
scan operation.
Current Gain Setting
Current gain set when current is monitored by ADC. Only used when
microcontroller overrides the internal scan.
ADC Conversion Start
Reserved
ADCSTRT
CG1
Ext µC sets this
bit to 1 to start a
conversion
86
(R/W)
CLR_LERR
Clear load error
1 = Resets load
monitor error
condition.
This bit is
automatically
cleared.
Only active when
µCCMON = 1
87
(R/W)
Reserved
LMON_EN
Load monitor
enable
Reserved
CLR_ERR
Clear charge
error
1 = Load
monitor on
0 = Load
monitor off
1 = Resets
charge monitor
error condition.
This bit is
automatically
cleared.
Only active when Only active when
µCCMON = 1
µCLMON = 1
µCFET
µC does FET
control
1 = FETs
controlled by
external µC.
0 = Norm
automatic FET
control (29), (32)
88
(R/W)
CG1 0
00
01
10
11
µCCBAL
µC does cell
balance
1 = internal
balance
disabled. µC
manages cell
balance
0=internal
balance
enabled. (29)
Reserved
Reserved
CG0
Gain
x50
x5
x500
x500
CMON_EN
Charge monitor
enable
AO3 2 1 0
0000
0001
0010
0011
0100
0101
0110
0111
PSD
Pack shut down
1 = PSD on
1 = Charger
0 = PSD off
monitor on
0 = Charger
monitor off. Only
active when
µCCMON = 1
µCLMON
µC does load
monitor
1 = Load
monitor on
0 = Load
monitor off
(29)
Reserved
µCCMON
µC does charger
mon
1 = charge
monitor on
0 = charge
monitor off
(29)
PDWN
Power-down
1 = Power-down
the device.
0 = Normal
operation
89
(R/W)
OFF
VC1
VC2
VC3
VC4
VC5
VC6
VC7
PCFET
Pre-charge FET
1 = PCFET on
0 = PCFET off
Bit = 0 if DOC or
DSC, unless the
automatic
response is
disabled by
µCFET bit. (26)
µCSCAN
µC does scan
AO3 2 1 0
1000
1001
1010
1011
1100
1101
1110
1111
CFET
Charge FET
1 = CFET on
0 = CFET off
Bit = 0 if COC,
unless the
automatic
response is
disabled by
µCFET bit. (26)
VC8
Pack current
VBAT/16
RGO/2
xT1
xT2
iT
OFF
DFET
Discharge FET
1 = DFET on
0 = DFET off
Bit = 0 if DOC or
DSC unless the
automatic
response is
disabled by
µCFET bit. (26)
OW_STRT
CBAL_ON
Open wire start Cell balance On
1 = No auto
scan. System
controlled by µC.
0 = Normal scan
(29), (3131)
1 = Does one
open wire scan
(bit auto reset to
0)
0 = No scan Only
active if DOWD =
1 or µCSCAN = 1
SLEEP
Set Sleep
DOZE
Set Doze
1 = Put device
into sleep mode.
0 = Normal
operation
1 = Put device
into Doze mode.
0 = Normal
operation
1= (CBnON =1)
outputs ON
0= Cell bal
outputs OFF
Only active if
µCCBAL= 1.
IDLE
Set Idle
1 = Put device
into Idle
mode 0 =
Normal
operation.
EEPROM Enable
EEEN
Reserved. These bits should be zero.
59
0 = RAM access
1 = EEPROM
access
FN7626.2
December 5, 2012
ISL94203
TABLE 17. RAM REGISTER DETAIL (MONITORED VOLTAGES)
BIT/
ADDR
8A
8B
F
7
E
6
D
5
A
2
9
1
8
0
7
6
5
4
3
2
1
0
HEXvalue 10 × 1.8 × 8
-----------------------------------------------------------4095 × 3
CELLMI CELLMI CELLMI CELLMI CELLMI CELLMI CELLMI CELLMI CELLMI CELLMI CELLMI CELLMI
NB
NA
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
Cell Maximum Voltage
This is the voltage of the cell with the maximum voltage.
Reserved
8E
8F
B
3
Cell Minimum Voltage
This is the voltage of the cell with the minimum voltage.
Reserved
8C
8D
C
4
HEXvalue 10 × 1.8 × 8
-----------------------------------------------------------4095 × 3
CELLM CELLM CELLM CELLM CELLM CELLM CELLM CELLM CELLM CELLM CELLM CELLM
AXB
AXA
AX9
AX8
AX7
AX6
AX5
AX4
AX3
AX2
AX1
AX0
Pack Current
This is the current flowing into or out of the pack.
HEXvalue 10 × 1.8
--------------------------------------------------------4095 × Gain × SenseR
Polarity
identified by CHING and DCHING bits.
Reserved
90
91
ISNS6
CELL1
B
CELL1
A
CELL1
9
CELL1
8
CELL1
7
CELL1
6
60
ISNS4
ISNS3
ISNS2
ISNS1
ISNS0
CELL1
5
CELL1
4
CELL1
3
CELL1
2
CELL1
1
CELL1
0
CELL2
2
CELL2
1
CELL2
0
CELL3
2
CELL3
1
CELL3
0
CELL4
2
CELL4
1
CELL4
0
CELL5
2
CELL5
1
CELL5
0
CELL6
2
CELL6
1
CELL6
0
HEXvalue 10 × 1.8 × 8
-----------------------------------------------------------4095 × 3
CELL2
B
CELL2
A
CELL2
9
CELL2
8
CELL2
7
CELL2
6
CELL2
5
CELL2
4
CELL2
3
HEXvalue 10 × 1.8 × 8
-----------------------------------------------------------4095 × 3
CELL3
B
CELL3
A
CELL3
9
CELL3
8
CELL3
7
CELL3
6
CELL3
5
CELL3
4
CELL3
3
HEXvalue 10 × 1.8 × 8
-----------------------------------------------------------4095 × 3
CELL4
B
CELL4
A
CELL4
9
CELL4
8
CELL4
7
CELL4
6
CELL4
5
CELL4
4
CELL4
3
HEXvalue 10 × 1.8 × 8
-----------------------------------------------------------4095 × 3
CELL5
B
CELL5
A
CELL5
9
CELL5
8
CELL5
7
CELL5
6
Cell 6 Voltage
This is the voltage of CELL6.
Reserved
ISNS5
HEXvalue 10 × 1.8 × 8
-----------------------------------------------------------4095 × 3
Cell 5 Voltage
This is the voltage of CELL5.
Reserved
9A
9B
ISNS7
Cell 4 Voltage
This is the voltage of CELL4.
Reserved
98
99
ISNS8
Cell 3 Voltage
This is the voltage of CELL3.
Reserved
96
97
ISNS9
Cell 2 Voltage
This is the voltage of CELL2.
Reserved
94
95
ISNSA
Cell 1 Voltage
This is the voltage of CELL1.
Reserved
92
93
ISNSB
CELL5
5
CELL5
4
CELL5
3
HEXvalue 10 × 1.8 × 8
-----------------------------------------------------------4095 × 3
CELL6
B
CELL6
A
CELL6
9
CELL6
8
CELL6
7
CELL6
6
CELL6
5
CELL6
4
CELL6
3
FN7626.2
December 5, 2012
ISL94203
TABLE 17. RAM REGISTER DETAIL (MONITORED VOLTAGES) (Continued)
BIT/
ADDR
9C
9D
F
7
E
6
D
5
6
5
CELL7
B
CELL7
A
61
3
2
1
0
CELL7
9
CELL7
8
CELL7
7
CELL7
6
CELL7 CELL74 CELL7
5
3
CELL7
2
CELL7
1
CELL7
0
CELL8
2
CELL8
1
CELL8
0
iT2
iT1
iT0
xT12
xT11
xT10
xT22
xT21
xT20
VB2
VB1
VB0
HEXvalue 10 × 1.8 × 8
-----------------------------------------------------------4095 × 3
CELL8
B
CELL8
A
iTB
iTA
xT1B
xT1A
xT2B
xT2A
CELL8
9
CELL8
8
CELL8
7
CELL8
6
iT9
iT8
iT7
xT19
xT18
xT17
xT29
xT28
xT27
CELL8
5
CELL8
4
CELL8
3
HEXvalue 10 × 1.8
-------------------------------------------------4095
iT6
iT5
iT4
iT3
HEXvalue 10 × 1.8
-------------------------------------------------4095
xT16
xT15
xT14
xT13
HEXvalue 10 × 1.8
-------------------------------------------------4095
xT26
xT25
xT24
xT23
HEXvalue 10 × 1.8 × 32
-------------------------------------------------------------4095
VBB
VBA
VRGO Voltage
This is the voltage of ISL94203 2.5V regulator.
Reserved
4
HEXvalue 10 × 1.8 × 8
-----------------------------------------------------------4095 × 3
VBATT Voltage
This is the voltage of Pack.
Reserved
A8
A9
7
External 2 Temperature
This is the voltage reported by an external thermistor divider on the xT2 pin.
Reserved
A6
A7
8
0
External 1 Temperature
This is the voltage reported by an external thermistor divider on the xT1 pin.
Reserved
A4
A5
9
1
Internal Temperature
This is the voltage reported by the ISL94203 internal temperature sensor.
Reserved
A2
A3
A
2
Cell 8 Voltage
This is the voltage of CELL8.
Reserved
A0
A1
B
3
Cell 7 Voltage
This is the voltage of CELL7.
Reserved
9E
9F
C
4
RGOB
RGOA
VB9
VB8
VB7
VB6
VB5
VB4
VB3
HEXvalue 10 × 1.8 × 2
-----------------------------------------------------------4095
RGO 9 RGO 8 RGO 7 RGO 6 RGO 5 RGO 4 RGO 3 RGO 2 RGO 1 RGO 0
FN7626.2
December 5, 2012
ISL94203
TABLE 17. RAM REGISTER DETAIL (MONITORED VOLTAGES) (Continued)
BIT/
ADDR
AA
AB
F
7
E
6
D
5
C
4
B
3
A
2
9
1
8
0
7
6
5
4
3
2
1
0
14-bit ADC Voltage
( HEXvalue 10 – 16384 ) × 1.8
This is the calibrated voltage out of the ISL94203 ADC. In normal scan mode,
if…HEXvalue 10 ≥ 8191 → ----------------------------------------------------------------------------------------this value is not usable, because it cannot be associated with a specific
8191
monitored voltage. However, when the µC takes over the scan operations, this
value can be useful. This is a 2’s complement number.
HEXvalue10 × 1.8
else → -------------------------------------------8191
Reserved
ADC
D
ADC
C
ADC
B
ADC
A
ADC
9
ADC
8
ADC
7
ADC
6
ADC
5
ADC
4
ADC
3
ADC
2
ADC
1
ADC
0
NOTES:
23. A “1” written to a control or configuration bit causes the action to be taken. A “1” read from a status bit indicates that the condition exists.
24. “Reserved” indicates that the bit or register is reserved for future expansion. When writing to RAM addresses, write a reserved bit with the value “0”.
Do not write to reserved registers at addresses 4CH through 4FH, 58H through 7FH, or ACH through FFH. Ignore reserved bits that are returned in
a read operation.
25. The IN_SLEEP bit is cleared on initial power up, by the CHMON pin going high or by the LDMON pin going low.
26. When the automatic responses are enabled, these bits are automatically set and reset by hardware when any conditions indicate. When automatic
responses are over-ridden, an external microcontroller I2C write operation controls the respective FET and a read of the register returns the current
state of the FET drive output circuit (though not the actual voltage at the output pin).
27. Setting EEEN to 0 prior to a read or write to the EEPROM area results in a read or write to the shadow memory. Setting EEEN to “1” prior to a read
or write from the EEPROM area results in a read or write from the non-volatile array locations.
28. Writes to EEPROM registers require that the EEEN bit be set to “1” and all other bits in EEPROM enable register set to “0” prior to the write operation.
29. This bit is reset when the Watchdog timer is active and expires.
30. The memory is configured as 8 pages of 16 bytes. The I2C can perform a “page write” to write all values on one page in a single cycle.
31. Setting this bit to “1” disables all internal voltage and temperature scans. When set to “1”, the external µC needs to process all overvoltage,
undervoltage, over-temp, under temp, and all cell balance operations.
32. Short Circuit, Open Wire, Internal Over Temperature, OVLO, and UVLO faults, plus Sleep and FETSOFF conditions over-ride the µCFET control bit and
automatically force the appropriate power FETs off.
PC Board Layout
QFN Package
The AC performance of this circuit depends greatly on the care
taken in designing the PC board. The following are
recommendations to achieve optimum high performance from
your PC board.
The QFN Package Requires Additional PCB Layout Rules or the
Thermal Pad. The thermal pad is electrically connected to VSS
supply through the high resistance IC substrate. The thermal pad
provides heat sinking for the IC. In normal operation, the device
should generate little heat, so thermal pad design and layout are
not too important. However, if the design uses the RGO pin to
supply power to external components, then the IC can experience
some internal power dissipation. In this case, careful layout of
the thermal pad and the use of thermal vias to direct the heat
away from the IC is an important consideration. Besides heat
dissipation, the thermal pad also provides noise reduction by
providing a ground plane under the IC.
• The use of low inductance components, such as chip resistors
and chip capacitors, is strongly recommended.
• Minimize signal trace lengths. This is especially true for the
CS1, CS2, and VC0-VC8 inputs. Trace inductance and
capacitance can easily affect circuit performance. Vias in the
signal lines add inductance at high frequency and should be
avoided.
• Match channel-channel analog I/O trace lengths and layout
symmetry. This is especially true for the CS1 and CS2 lines,
since their inputs are normally very low voltage.
Circuit Diagrams
• Maximize use of AC de-coupled PCB layers. All signal I/O lines
should be routed over continuous ground planes (i.e. no split
planes or PCB gaps under these lines). Avoid vias in the signal
I/O lines.
The “BLOCK DIAGRAM” on page 5 shows a simple application
diagram with 8 cells in series and two cells in parallel (8S2P).
Simple Stand Alone
• When testing use good quality connectors and cables,
matching cable types and keeping cable lengths to a
minimum.
62
FN7626.2
December 5, 2012
ISL94203
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Revision.
DATE
REVISION
December 5, 2012
FN7626.2
CHANGE
Initial Release.
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the fastest growing markets within the industrial and infrastructure,
personal computing and high-end consumer markets. For more information about Intersil or to find out how to become a member of
our winning team, visit our website and career page at www.intersil.com.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page.
Also, please check the product information page to ensure that you have the most updated datasheet: ISL94203
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
Reliability reports are available from our website at: http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
63
FN7626.2
December 5, 2012
ISL94203
Package Outline Drawing
L48.6x6
48 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 4/07
4X 4.4
6.00
44X 0.40
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
48
37
1
6.00
36
4 .40 ± 0.15
25
12
0.15
(4X)
13
24
0.10 M C A B
0.05 M C
TOP VIEW
48X 0.45 ± 0.10
4 48X 0.20
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
BASE PLANE
MAX 0.80
(
SEATING PLANE
0.08 C
( 44 X 0 . 40 )
( 5. 75 TYP )
C
SIDE VIEW
4. 40 )
C
0 . 2 REF
5
( 48X 0 . 20 )
0 . 00 MIN.
0 . 05 MAX.
( 48X 0 . 65 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
64
FN7626.2
December 5, 2012