AN1568 - Intersil

Application Note 1568
ISL97676IRZ-EVAL Quick Start Guide
FIGURE 1. ISL97676 EVALUATION BOARD
This quick start guide pertains to the ISL97676IRZ-EVAL.
This board comes populated with 72 LED’s in a 6P12S
configuration to simplify evaluation and testing.
1. Apply input voltage to the VIN and GND post on the
top left corner of the evaluation board.
2. Apply a 100% duty-cycle PWM signal to PWM (J13)
and GND post.
3. Insert WR jumper.
4. To power-up the evaluation board in 6P12S
configuration, make sure jumpers JP8-14 are
inserted.
5. To power-up in 6P10S configuration, jumpers JP15-20
should be inserted.
6. Jumper JP5 should be inserted in the lower position.
See Figure 1.
11.Switches SW1 and SW2 are used to program the
switching frequency and enable the equal phase
shift feature per Table 1. For additional information,
please consult the ISL97676 data sheet.
TABLE 1.
SW2
SW1
Up
Up
Up
Down
FSW = 1.2MHz, Equal Phase Shift Enabled
Down FSW = 570kHz, No Phase Shift
Up
FSW = 1.2MHz, No Phase Shift
Down Down FSW = 570kHz, Equal Phase Shift Enabled
12.After following Steps 1 through 9, all 72 LEDs should
light up at 100% duty-cycle or full brightness.
7. Jumper J12 should be inserted in the top position.
See Figure 1.
13.Jumper JP1 can be inserted if the external fault
MOSFET Q1 is not used. See data sheet for
additional information.
8. LED current can be programmed by connecting a
current meter across J8 and varying R12.
14.Jumpers JP4, JP3, JP30 and the 10-pin white
connector in the bottom left are not used.
ILED = 724/R12
The measured current divided by 6 is the LED current per
channel. For example, 120mA measured current will
correspond to 20mA/channel.
The ISL97676 evaluation board schematic and top and
bottom silkscreen layers are shown in Figures 2 through 4.
9. Floating jumper JP7 will provide direct PWM mode
such that the dimming frequency follows the input
PWM signal without frequency modulation. See
ISL97676 data sheet for more details (FN7600).
Note that equal phase shift feature is disabled in this
mode.
10. Inserting JP7 allows the dimming frequency to be
programmed with a resistor, R12 to GND. The
dimming frequency is calculated by Equation 1:
FPWM = 6.67 × 10^7 ⁄ RFPWM
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1
(EQ. 1)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Application Note 1568
J14
Vout
JP8
JP1
J4
LX
C2
16
C18
FAULT
OVP
Vlogic
14
C11
360nF
U1
VIN
PGND
JP15
LED2
LED26
JP16
LED25
LED27
JP17
LED28
JP12
LED52
JP18
LED51
JP13
JP14
LED53
JP19
LED78
JP20
LED54
LED77
SDA J10
2
EN
1
SCL J11
J12
2
20
PWM
1
3
PWM
J13
1
2
SPDT
3
2
SPDT
3
SW1
SW2
R6
3
2
150K
3
1
JP5
R5
R9
100K
18
10k
C4
3.3nF
JP7
3
1.2MHZ _ No Phase Shift
3
1
600KHZ _ No Phase Shift
1
1
600KHZ _ with Phase Shift
3
3
1.2MHZ _ with Phase Shift
R17
Open
R13
5K
50K
R12
4
FB3
FB4
LED55
LED76
LED4
LED23
LED30
LED49
LED56
LED75
LED5
LED22
LED31
LED48
LED57
LED74
LED6
LED21
LED32
LED47
LED58
LED73
10
LED7
LED20
LED33
LED46
LED59
LED72
8
LED8
LED19
LED34
LED45
LED60
LED71
LED9
LED18
LED35
LED44
LED61
LED70
LED10
LED17
LED36
LED43
LED62
LED69
LED11
LED16
LED37
LED42
LED63
LED68
LED12
LED15
LED38
LED41
LED64
LED67
LED66
FB5
TP5
FB5
7
FB6
TP6
ISET
GND
6
9
R16
Open
J7
J7
LED50
FB4
TP4
FB6
J6
J6
LED29
FB3
TP3
RFPWM/Direct PWM
J5
J5
LED24
C17
C16
C15
C14
C13
11
R10
2K
13
R11
1M
COMP
C5
390pf
SW2
1
FSW
FB2
TP2
FB2
LED3
4.7nF
FPO
4.7nF
5
4.7nF
J3
FAULT
12
4.7nF
R4
Open
JP4
FB1
C12
C3
1uF/50V
R8
4.7K
R15
10K
FB1
TP1
VDDIO
ISL97676
R7
4.7K
Position Selecting
R14
358K
JP11
15
4.7nF
19
4.7nF
17
J2 (VLogic)
1
SW1
C10
JP10
LX
C1
JP9
LED1
100pF/50V
FDMA530PZ
JP3
R18
100
4.7uF/50V
C9
10uF/50V
JP30
D1
SS25
12
Open
SDA
EN
1
2
3
4
5
6
7
8
9
10
HEADER10(FMale)
HDR1
SCL
0.1uF/50V
3
10uH
4.7uF/50V
C8
J1(Vin)
WR
L1
4.7uF/50V
C6
1
2
5
6
4.7uF/50V
C7
Q1
4
VIN= 4.75 ~26V
J8
J8
LED13
LED14
LED39
LED40
LED65
JP25
JP26
JP27
JP28
JP29
JP21
JP22
JP23
JP24
J9
J9
Title
Size:
FIGURE 2. ISL97676 EVALUATION BOARD SCHEMATIC
Revision:
B
Date:
8-13-2009
Sheet
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the
reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
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Application Note 1568
FIGURE 3. EVALUATION BOARD TOP LAYER
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Application Note 1568
FIGURE 4. EVALUATION BOARD BOTTOM LAYER
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