Using the X80070 in an Advanced TCA Application ® Application Note December 1, 2004 AN180.0.0 Author: Carlos Martinez Introduction This application note describes one possible implementation of an Advanced TCA (PICMG 3.x) power supply control. This particular implementation shows the power on control of one -48 to 12V, 144W DC-DC power supply, with a number of circuits included to meet the requirements of the PICMG3.x specification. Some of the key elements in the application are: • Use of an X80070 hotswap controller This device provides a controlled delay on the main FET turn on, changeable FET gate currents to control the FET slew rate, and a PWRGD output that turns on the DC-DC converter only after the main FET is on. • Input protection To conform to the ATCA specification, this section includes the required fusing and filtering at the main power connector. • DC-DC converter The chosen DC-DC converter supplies 12A of output current at 12V. The circuit includes filtering at the input of the supply and enough capacitance to power the board for 5ms during an input short circuit, a PICMG3.x requirement. • Precharge circuits This block is optional, but uses the Early -48V connections of the ATCA backplane to precharge the bulk capacitance of the DC-DC converter. This will minimize the surge current through the main power FET. • Discharge circuits This block will likely be requires in all systems for safety reasons. It discharges the bulk capacitors when the board is removed from the system. This application example includes a number of external circuits that provide additional circuit protection and additional features. In an actual implementation, some changes may be required, especially in choice of filters, in order to optimize the power supply performance. X80070 Hotswap Control The X80070 device is a hot swap controller that allows a board to be safely inserted and removed from a live backplane without turning off the main power supply. During insertion, the gate of an external power MOSFET is clamped low to suppress contact bounce. The under-voltage/over-voltage circuits and the power on reset circuitry suppress the gate turn on until the mechanical bounce has ended. The X80070 turns on the gate with a user set slew rate to limit the inrush current. The X80070 1 incorporates an electronic circuit breaker set by a 20mΩ sense resistor. After the load is successfully charged, the PWRGD signal is asserted; indicating that the device is ready to power sequence the DC-DC power brick. At all times, the X80070 monitors for undervoltage, overvoltage, and overcurrent conditions. If any fault occurs, the gate will be immediately shut off and the PWRGD will be returned to the inactive state. The X80070 contains factory programmable overvoltage, undervoltage and overcurrent detection levels and programmable hardshort retry and gate control slew rates. Board Schematic and Layout For the full schematic, see the separate file: ATCA X80070 Schematic.PDF. X80070 Hot Swap Circuit Power Supply The X80070 receives power on the VDD pin. The design shows the required 12V supply being generated by a resistor and a 12V zener diode controlling the base of a pass transistor. The transistor must be able to handle more than 80V and more than 0.7W of power dissipation (at 80V). The circuit uses an MJD340 transistor that is rated at 300V and 15W. In the circuit, the voltage is dropped from 48V to 12 V through the 0.25W, 27kΩ resistor R3 to provide 1.3mA for the base drive and for zener regulation. The chosen zener regulates well with 1mA of current. The 12V regulator needs to provide an estimated 6.5mA typical continuous current (10mA peak). The X80070 requires 2.5mA during normal operation and the isolation circuits (described below) require 4.5mA. This results in maximum continuous power dissipation of 0.36W across the transistor at -48V. Part of the 12V current goes to powering an ADuM1401 isolation circuit from Analog Devices. This device requires a 5V supply at a maximum 2.4mA. The 5V is supplied by a 5V regulator on the X80070, with an emitter follower providing the needed current. X80070 Overvoltage/Undervoltage Circuits The undervoltage/overvoltage is provided by a resistor divider between the -48V and -48V return leads. The resistors in this divider are selected so the Overvoltage (OV) setting is 74.9V, the primary Undervoltage (UV1) setting is 42.4V and the secondary Undervoltage (UV2) setting is 33.2V. The resistors can be changed to change these thresholds, but the ratio of the OV and UV remain fixed by the internal levels. These internal thresholds can be set by Intersil during manufacture, if other OV and UV levels are needed. Contact Intersil for more information about this procedure. Application Note 180 In the X80070 the active undervoltage detector is selected by the BATT-ON pin. If BATT-ON is LOW (or unconnected) then the higher undervoltage level is set (42.4V). If BATT-ON is pulled HIGH, then the lower undervoltage level is set (33.2V). Since the chosen DC-DC converter provides full power down to 35V, it is not desired to turn off the FET above this threshold. As such, the BATT-ON pin is tied HIGH in this application. This circuit also contains a 6.2V zener diode to protect the device from high voltage transients through the mains and a capacitor to limit any false overvoltage and undervoltage conditions due to input voltage transients. According to the ATCA specifications, the system must not respond to OV transients shorter than 10ms at 75V. This assumes an input voltage rise time of 10V/ms. The size of a capacitor was determined by simulation. The simulation and results are in the appendices. Another consequence of the overvoltage test is the generation of a very large current through the bulk capacitor when the input voltage goes from 48 to 72V. Without correction, the X80070 will turn off the FET due to this large current. To deal with this, a current limiter is placed on the main FET. This requires a 100mΩ resistor in line with the main power FET. An NPN transistor monitors the voltage across this resistor. When the current reaches 7.7A, the transistor begins to turn on. This pulls down on the FET gate to partially turn it off. If the current remains at a level greater than 5.5A for more than 10ms, the X80070 turns off the FET, which shuts down the board. X80070 Hotswap and Support Circuits The primary components in the hotswap circuit are the FET and the sense resistor. The FET in this application is an IRFS23N15D from International Rectifier. The data sheet for this device is available on the CDROM or from the web site www.irf.com. This FET was chosen to provide the 8A peak, and maximum 5.1A continuous current. The sense resistor value is 10mΩ. This resistor sets the overcurrent condition at 5Am, since the X80070 overcurrent threshold is 50mV. An optional resistor divider in this circuit allows the over current level to be trimmed, to set the over current level to 5.5A, for example. FET feedback components (C3 and R6) provide compensation for the FET during turn on. The value of the resistance is not critical. The board default is 4.7kΩ. The capacitor value depends on the load capacitance and the desired maximum surge current. A rough calculation for the value of C3 is: I GATE × C LOAD C3 = -----------------------------------------I INRUSH Assuming a gate current of 70µA a maximum surge current of 8A, and a 2200µF load capacitance, C3 is calculated to be 2 19nF and chosen as 22nF. If the surge current is too high, the gate current can be set to 10µA or 50µA by controlling the IGQ0 and IGQ1 pins of the X80070. When power is first applied to the system, the FET tries to turn on due to its internal gate to drain capacitance (Cgd) and the feedback capacitor C3. The X80070 device, when powered, pulls the gate output low to prevent the gate voltage from rising and keep the FET from turning on. However, unless VDD powers up very quickly, there will be a brief period of time during initial application of power when the X80070 circuits cannot hold the gate low. The use of an external capacitor (C5) prevents this. Capacitors C3 and C5 form a voltage divider to prevent the gate voltage from rising above the FET turn on threshold before the X80070 can hold the gate low. Use the following formula for choosing C5. V1 – V2 C5 = --------------------- C3 V2 Where: V1 = Maximum input voltage, V2 = FET threshold Voltage, C5 = Gate capacitor, C3 = Feedback capacitor. In a system where VDD rises very fast, a smaller value of C5 may suffice as the X80070 will control voltage at the gate before the voltage can rise to the FET turn on threshold. The application assumes that the input voltage rises only to 20V before the X80000 sees operational voltage on VDD . So C5 is chosen to be 100nF. If C3 is used then the series resistor, R6, is required to prevent high frequency oscillations. The values of C3 and C5 can be reduced by using the optional pre-charge circuit described below. This circuit gradually charges the bulk capacitor, partially or completely, before the X80070 turns on the FET. This reduces or eliminates the surge current and gives more flexibility in the choice of these components. X80070 Reset Input The X80070 device has an MR input pin that signals a “Hot side” reset. Pulling this input LOW tells the device to terminate a hotswap operation that results in the Main FET gate going LOW. This turns off the FET. This application has three board power management mechanisms for controlling this input pin. First, the IPMI circuit has control of this pin through an isolated interface. The system can hold off the application of power to the board until authorized by the shelf manager. Then it can specify a “Soft-Insert” to set the MR pin HIGH and turn on the FET. Before board extraction, the IPMI controller can specify a “Soft-extract” to bring the MR pin LOW and turn off the FET. If this function is not needed, then the two shutdown control FETs (Q5 and Q6), the resistor (R23) and the isolation circuit (part of U3) can be removed. AN180.0.0 December 1, 2004 Application Note 180 Second, assuming that there is no IPMI control and there is a precharge circuit, the MR pin on the X80070 is pulled up with a 100K resistor and has a 10µF capacitor to VEE. This one second (1s) time constant gives the precharge circuit time to work. Third, without using the precharge circuit (and with or without the remote IPMI control, the capacitor can be removed and the X80070 internal 50ms delay holds off the hotswap operation until the contact bounce on insertion has decayed. X80070 DC-DC Converter Interface Circuits. The X80070 powers up one DC/DC converter. Typically this has a 12V or 5V output that is distributed to other DC-DC converters providing a variety of voltage sources. The DC-DC converter specified in this application is a SynQor 144W, 12V module. The DC-DC converter is controlled by the PWRGD signal. Prior to the main power control FET turning on the PWRGD signal is HIGH. When it is HIGH, the optical isolator is turned on with about 1.5mA of current. This turns on the optoisolator transistor. This pulls the ON/OFF pin LOW and the DC-DC converter output is off. As the main power control FET turns on, the voltage on gate pin gradually increases, until it is equal to VDD, when the FET is fully turned on. When the voltage on the Gate pin exceeds VDD-1V, the PWRGD signal goes LOW. When it goes LOW, the FET turns off the optical isolator, which allows the ON/OFF input to be pulled HIGH, turning on the DC-DC output. PWRGD is also optionally available to the IPMI controller through the ADuM1401 isolation device. To meet noise requirements of the ATCA specification, a filter is placed between the FET switch and the DC-DC converter. Also, in order to meet the requirements that the board maintain operation in the event of a 5ms loss of input power, a 2200µF capacitor is placed at the DC-DC converter input. The size of this capacitor can be reduced to 47µF if the secondary of the DC-DC converter can maintain power for the 5ms period. A combination of capacitors on the input and output can be used. This application assumes that additional capacitance on the output of the DC-DC converter cannot be added. The calculation for the input capacitor is: dV i = C ------dt Where: i = maximum DC-DC input current (5A) dV = change in voltage from 43V (minimum board voltage) to 31V (minimum DC-DC converter turn off voltage) dT = time required to hold output (5ms) Therefore: C = 2083µF (Use 2200µF) 3 IPMI Interface This interface to the IPMI controller is optional, but if used, it needs to be isolated. This can be done with optoisolator components, but in this application, an Analog Devices ADuM1401 was used. This device takes less current than optical isolators, so it simplifies the power requirements on the -48V side, while providing 2500VRMS isolation. It is also much faster in responding to signals than optically coupled components at the same current. In this application, the circuit provides three optically isolated control signals. These are Manual Reset (MR), PWRGD and FAR. The MR signal controls Soft Insert and Soft Extract operations. The PWRGD signal provides an output monitor of the FET status, and the FAR output indicates to the IPMI controller if there was a retry during turn-on of the main FET. X80070 Options There are a number of hardware options on the X80070. These are controlled by the connections on the device. If none of the options are needed, the pins are tied to VEE or left floating. Table 1 describes each connection. TABLE 1. X80000 CONFIGURATION NAME BATTON IGQ1 IGQ0 DESCRIPTION No connect or connect to VEE: Undervoltage threshold = UV1. Connect to VRGO: Undervoltage threshold = UV2. Quick select of gate current. IGQ1 IGQ0 0 0 50µA gate current 0 1 10µA gate current 1 0 70µA gate current 1 1 150µA gate current Input Components To meet ATCA requirements, each power supply connection must have a fuse and a filter. The fuses on the return lines and the main -48V lines are Littlefuse devices rated at 250V and 7A. Fuses for the Early voltage and enable pins are rated at 250V and 200mA. The filters chosen for the main power handling pins were surface mount Pi filters from Spectrum. These are rated at 200V and 10A. The capacitance value was 4000pF, but others are available. Also, Spectrum has smaller 100V/10A Pi filters that were selected for the early and enable pins. Depending on the filtering needs, feed through filters can be used instead of the Pi filters. Also each input requires a blocking diode. The main power lines use high voltage shottkey devices capable of handling 100V and 5A of current. For the early and enable lines, smaller blocking diodes are used. AN180.0.0 December 1, 2004 Application Note 180 Precharge Circuit The ATCA circuit schematic and simulations include the optional precharge control. It is not necessary for the operation of the power supply, but it does have some advantages. With this circuit, the initial insertion surge current is very low. This reduces stress on the high voltage circuits and minimizes the disruption to the -48V backplane. The X80070 is a good choice when using this circuit, because the gate output can turn off the precharge circuit when it turns on the main FET. This reduces the precharge load during normal operation. Without the precharge circuit, the system powers up as normal, but with a higher surge current. The X80070 helps here as well, because the main FET turn on time can be controlled by the X80070 selectable gate current. This allows a wide range of turn on surge currents, though typically this would be in the 1-7A range. If the surge current is higher than desired even after selecting a smaller gate current, then the feedback capacitor can be increased to reduce the surge. required by the test. V2 simulates the X80070 gate output. In the initial turn on test, it is delayed (as would the X80070 gate output be delayed) by about 1s. In the OV transient test, this voltage is left on. V3 simulates the board being removed from the system. After the circuit has been operating for about 1s, this supply turns off to mimic the removal of the board. The load resistor (R3) is 10K in the power up/power down tests, because in these cases, there should be little load. During the OV transient test, the normal operating current is assumed to be 3.3A. As such, R3 is 14Ω. In the simulation, specific part numbers chosen for components such as FETs, diodes and transistors do not exactly match those chosen for the schematic, but do have similar characteristics. The precharge circuit works by turning on an FET as power turns on. This FET charges the capacitor through a 50Ω/2W resistor. The resistor wattage can be reduced using derating curves, based on the precharge duration. A zener diode limits the voltage for protection. When the X80070 main FET gate control output turns on, the precharge FET turns off, effectively taking this circuit out of operation. Discharge Circuit As part of the ATCA specification, the bulk capacitor needs to be discharged, for safety reasons, when the board is removed from the system. This is accomplished by using a third small FET. This FET is turned off while the board is plugged in and both the -48V Return and -48V pins are connected. When the board is removed, the discharge circuit is powered by the bulk capacitor and the FET is allowed to turn on. The FET remains on until the voltage on the capacitor has dropped too low to keep it on. This is about 10V across the capacitor. The discharge current is limited by a 50Ω resistance. Summary This application shows a relatively complete hotswap implementation. Much of the circuitry has been built and tested, and the remainder has been simulated to verify proper operation. Individual hotswap applications will no doubt require some changes to achieve desired functionality. Once a final design is settled on, the areas that will likely deserve special attention are board layout and noise suppression and testing. Appendix 1 Simulation This simulation uses a spice simulator. V1 is the main supply source. It is turned on or off, or raised to OV conditions as 4 AN180.0.0 December 1, 2004 gate Application Note 180 V2 UV/OV R1 182000 1µ V1 Rser=0 V3 C5 .1µ R2 10000 C4 PULSE(12 0 1.6 0 0 4) 4.75K R9 100 C2 C3 2N2222 Q2 D2 R6 Rser=3000 BZX84C6V2L C1 -48RTN D3 MBR20100CT R3 10000 2200µ 0.022µ 2.2µ SUD40N10-25 M4 D1 MBR20100CT R4 R5 10K R7 .01 .10 -48SW sense R8100K .1µ C9 M1 SUD40N10-25 D6 MBR20100CT R10 200K gate3 R15 200K R12 M3 1500 R11 100 .tran 0 4 0 1e-3 Si4982DY C8 gate2 R17 50 R14 50 D5 0.002µ .1µ BZX84C12L M2 20K C7 Si4982DY BZX84C12L D4 Q1 2N2222 100 .01µ C6 R13 R16 200K R18 FIGURE 1. OV/UV SURGE PLUS POWERUP PRECHARGE AND DISCHARGE SIMULATION CIRCUIT 5 AN180.0.0 December 1, 2004 Application Note 180 MBR20100CT V2 R6 4.7K 12 D2 1µ V1 R9 100 C5 .1µ C3 2N2222 Q2 C1 BZX84C6V2L R2 10000 C4 0.022µ C2 2200µ R3 14 2.7µ R4 MBR20100CT .01 .10 -48sw D1 R5 10K R7 M1 sense R8 100K SUD40N10-25 PULSE (48 75 0 3e-3 3e-3 10e-3 100e-3 1) R1 182000 gate D3 UV/OV -48rtn . MBR20100CT R1 182000 gate UV/OV D3 -48rtn FIGURE 2. 48V to -74V VOLTAGE TRANSIENT SIMULATION CIRCUIT V2 R6 4.75K 1µ V1 D2 R9 100 C5 .1µ 2N2222 Q2 C1 BZX84C6V2L R2 10000 C3 0.022µ C2 2200µ R3 14 C4 2.7µ sense R8 100K D1 R4 MBR20100CT .01 R5 10K R7 .10 M1 SUD40N10-25 -48sw PULSE (48 0 0 0 0 5e-3 100e-3 1) 12 .tran 0 100e-3 0 1e-3 FIGURE 3. -48V to 0V VOLTAGE DROP-OUT SIMULATION CIRCUIT 6 AN180.0.0 December 1, 2004 Application Note 180 V(-48rtn) 50V V(-48sw) V(gate2) V(gate3) I(R14) I(R7) I(R17) Precharge current limited to about 190mA. Discharge Current less than 190mA I(R17) Discharge Current 45V V(-48SW) I(R14) Precharge Current 40V 180mA V(gate3) Input Surge Current limited to about 190mA V(-48sw), V(gate2) On board removal, 2200uF bulk capacitance discharges to less than 12V in 1s. I(R7) Input Surge Current 35V 200mA 160mA 140mA 30V 120mA 25V 100mA 20V 80mA V(gate3) 15V 60mA V(gate2) 10V 40mA 5V 20mA 0mA 0V Capacitor precharges for about 1s A shorter precharge period increases surge current I(R7) A longer precharge period decreases surge current I(R7) -5V 0.0s 0.4s 0.8s 1.2s 1.6s 2.0s 2.4s 2.8s 3.2s 3.6s -20mA 4.0s FIGURE 4. POWER UP AND DE-INSERTION PLOT 7 AN180.0.0 December 1, 2004 Application Note 180 V(-48rtn) V(uv/ov)*10 V(sense)*1000 I(R7) 8.0A 75V Load Current limited to 7.7A 70V 7.2A 65V 6.4A V(-48rtn) Load Voltage 60V 5.6A I(R7) Load Current 55V 4.8A Current sense voltage does not exceed 50mV OC limit 50V 4.0A 45V 3.2A Normal Load current = 3.3A 40V 2.4A 35V 1.6A V(UV/OV) voltage does not exceed 3.9V OV limit 0.8A 30V V(sense)*1000 25V 0.0A V(UV/OV)*10 20V 0ms 10ms 20ms 30ms 40ms 50ms 60ms 70ms 80ms 90ms -0.8A 100ms FIGURE 5. OV TRANSIENT TEST PLOT 8 AN180.0.0 December 1, 2004 Application Note 180 V(-48rtn) V(uv/ov)*10 V(n001) V(sense)*1000 I(R7) 51V 8.0A Load current limited to 7.7A 48V 7.2A V(n001) Input Voltage V(-48Vrtn) Load Voltage 45V 6.4A 42V 5.6A 39V 4.8A Load Voltage stays above 35V so DC-DC retains enough voltage to operate 36V 4.0A I(R7) Load current 33V 3.2A Load current voltage stays below 50mV so X80070 does not turn off FET V(sense)*1000 load current voltage 30V 2.4A 27V 1.6A V(UV/OV)*10 Input Voltage 24V 0.8A Input voltage monitor stays above 1.78V so X80070 does not turn off FET 21V 18V 0ms 0.0A -0.8A 10ms 20ms 30ms 40ms 50ms 60ms 70ms 80ms 90ms FIGURE 6. UV VOLTAGE DROP OUT TEST PLOT 9 AN180.0.0 December 1, 2004 Application Note 180 Appendix 2 Bill of Materials PART TYPE DESIGNATOR DESCRIPTION PART NUMBER 1µF C1 Capacitor * 2200µF 100V C2 Capacitor Panasonic: ECO-S2AP222BA 0.022µF C3 Capacitor * 2.7µF C4 Capacitor * 0.1µF C5 Capacitor * 0.002µF C6 Capacitor * 0.1µF C7 Capacitor * 0.01µF C8 Capacitor * 0.1µF C9 Capacitor * 0.01µF C10 Capacitor * 0.01µF C11 Capacitor * 0.01µF C12 Capacitor * 0.01µF C13 Capacitor * 0.01µF C14 Capacitor * MBRM5100 D1 Schottky Diode Diodes: MBRM5100 6.2V D2 Zener Diode Fairchild: BZX84C6V2 MBRM5100 D3 Schottky Diode Diodes: MBRM5100 12V D4 Zener Diode Fairchild: BZX84C12 12V D5 Zener Diode Fairchild: BZX84C12 MBRM5100 D6 Schottky Diode Diodes: MBRM5100 MBRM5100 D7 Schottky Diode Diodes: MBRM5100 BAS21 D8 Diode Fairchild: BAS21 BAS21 D9 Diode Fairchild: BAS21 BAS21 D10 Diode Fairchild: BAS21 BAS21 D11 Diode Fairchild: BAS21 4.7V D12 Zener Diode Fairchild: BZX84C4V7 12V D13 Zener Diode Fairchild: BZX84C12 7A F1 Fuse Littlefuse: 326007 7A F2 Fuse Littlefuse: 326007 7A F3 Fuse Littlefuse: 326007 Fuse 7A F4 FILTER F5 Spectrum Control: PSM1-402P-10T Littlefuse: 326007 FILTER F6 Spectrum Control: PSM4-402P-10T FILTER F7 Spectrum Control: SSM1-402E-10T FILTER F8 Spectrum Control: SSM1-402E-10T FILTER F9 Spectrum Control: PSM4-402P-10T FILTER F10 Spectrum Control: PSM4-402P-10T FILTER F11 Spectrum Control: SSM1-402E-10T FILTER F12 200mA F13 Fuse Littlefuse: 326200 200mA F14 Fuse Littlefuse: 326200 200mA F15 Fuse Littlefuse: 326200 10 Spectrum Control: SSM1-402E-10T AN180.0.0 December 1, 2004 Application Note 180 Appendix 2 Bill of Materials (Continued) PART TYPE DESIGNATOR FLTR100V10 F16 DESCRIPTION PART NUMBER 200mA F17 IRFS23N15D M1 * IRFR120N/SM_2 M2 * IRFR120N/SM_2 M3 * DC-DC CONVERTER M4 SynQor: PQ120QTA12 2N2222 Q1 * Fuse Littlefuse: 326200 NPN Transistor * 2N2222 Q2 NPN Transistor * MJD340 Q3 NPN Transistor * 2N3904 Q4 NPN Transistor * 2N7002 Q5 * 2N7002 Q6 * 2N7002 Q7 * 182K 1% R1 * 10K 1% R2 * 27K R3 * 10m 1W R4 * 10K R5 * 4.7K R6 * 0.1 4W R7 * 100K R8 * 100 R9 * 200K R10 * 100 R11 * 1.5K R12 * 20K R13 * 50 2W R14 * 200K R15 * 100K R16 * 50 2W R17 * 27K R18 * 100K R19 * 100K R20 * 100K R21 * 5.1K R22 * 10K R23 * 100 R24 * X80070Q20 U1 * TLP124B U2 * ADUM1401 U3 * 11 AN180.0.0 December 1, 2004 Application Schematic -48V_RTN Q4 2N3904 RGO M4 In Out 2 7A MBRM5100 VDD X80070Q20 13 NA1 12 NA1 Out 2 200mA F14 Enable_B 27K 20 7 100K 16 3 4 14 6 BAS21 F8 1 In FILTER Out D9 R23 10K 2 200mA C10 FAR PWRGD C1 1uF FAR 0.1uF 0.01uF 4 3 Q7 2N7002 17 PWRGD ON/OFF C11 .01uF C5 1 2 C3 R6 6.2V 4.7K 0.1uF 22nF F16 FLTR100V10 4 I+ O+ 3 OI- -48V_SW 5 10K 1% D12 12V -V +Vout +sense Trim -sense -Vout C13 1 2 15 D2 R2 10uF 2N7002 BATTON NA2 NA2 NA2 VEE D13 Q6 BAS21 MR VUV/OV SENSE In Delay 1s 8 7 6 5 4 +Vout +Sense Trim -Sense -Vout 5.1K U2 TLP124B R21 GATE 1 D8 2 9 F13 Enable_A FILTER 3 R22 19 18 IGQ0 IGQ1 R18 F7 DC-DC CONVERTER +Vin R19 R20 U1 5 C9 G 1 R3 R1 27K D6 FILTER 8 12 VRTN_B X80070 has OV set to 74.9V and UV set to 33.2V MBRM5100 F6 2&4 F2 100K 7A 100K Out 2 1 In D3 FILTER VRGO VRTN_A F5 1 182K 1% F1 C2 2200uF 100V 1 Q3 MJD340 C4 2.7uF M1 R9 R8 100K 2N7002 F3 -48_A F9 1 In Out F4 -48_B R4 2 1 In Out U3 2 7A RGO Current Limit = 7A Q2 2N2222 MBRM5100 PWRGD FAR R15 200K 2&4 R10 200K Discharge Circuit Discharge to 4V in less than 1s M3 R24 100 1 3 R16 100K IRFR120N/SM_2 SHDN R11 100 D5 Pre-charge circuit Charge to 48V in about 1s 12V R12 R17 C8 10nF 1.5K D4 Q1 2N2222 12V F11 1 In FILTER Out D10 C7 BAS21 0.1uF 2 1 F15 Early_A 200mA C6 2nF F17 Early_B 200mA Chassis Ground F12 1 In D11 FILTER Out 2 BAS21 R14 50 2W 3 2&4 M2 IRFR120N/SM_2 50 2W R13 20K C14 0.01uF C12 0.01uF 0.1 4W Max current = 5.5A 10ms O.C. delay from 3.3A to 5.5A D7 FILTER Chassis ground R7 10m 1W MBRM5100 F10 3 R5 10K D1 FILTER 7A 1 100 SHDN 1 2 3 4 5 6 7 8 ADUM1401 16 15 14 13 12 11 10 9 VDD1VDD2 GND1GND2 VIA VOA VIB VOB VIC VOC VOD VID VE1 VE2 GND1GND2 IPMI Positive supply PWRGD OUT FAR OUT Remote Shutdown IPMI neg supply Connect to IPMI positive supply to turn off power Application Note 180 Q5 IRFS23N15D 4.7V AN180.0.0 December 1, 2004 Application Note 180 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 AN180.0.0 December 1, 2004